JP4557469B2 - Photoelectric conversion device and solid-state imaging system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a photoelectric conversion device. , And And Solid imaging Regarding systems, in particular, photoelectric conversion devices such as digital cameras , And And Solid imaging It is about the system.
[0002]
[Prior art]
Conventionally, as a solid-state imaging device, a CCD imaging device is often used because of its good S / N ratio. However, on the other hand, so-called amplification type solid-state imaging devices have also been developed, which have advantages such as ease of use and low power consumption.
[0003]
An amplification type solid-state imaging device converts an optical signal into an electric signal by a photoelectric conversion element such as a photodiode, and guides the electric signal to a control electrode of the transistor, thereby generating an amplified signal based on the electric signal from the main electrode of the transistor. SIT image sensor using SIT as an amplifying transistor (A. Yusa, J. Nishizawa et al., "SIT image sensor: Design consideration and characteristics," IEEE trans. Vol. ED-33, pp.735-742, June 1986), BASIS using bipolar transistors (N. Tanaka et al., "A 310K pixel bipolar imager (BASIS)," IEEE Trans. Electron Devices, vol.35, pp. 646- 652, may 1990), CMD using a JFET with a depleted control electrode (Nakamura et al. “Gate storage type MOS phototransistor image sensor”, TV Society, 41, 11, pp.1075-1082 Nov., 1987), CMOS sensor using MOS transistor (SKMendis, SEKemeny and ERFossum, “A 128 × 128 CMOS active image sensor for highly integrated imaging systems,” in IEDM Tech. Dig., 1993, pp. 583-586.
[0004]
In particular, the CMOS sensor is well matched with the CMOS process, and the peripheral CMOS circuit can be made on-chip. However, a drawback common to these amplifying solid-state imaging devices is that the output offset of the amplifying transistor provided in each pixel is different for each pixel, so that fixed pattern noise (FPN) is carried as an image sensor signal. It is. Conventionally, various signal readout circuits have been devised to eliminate this FPN, but here, typical examples of CMOS sensors will be described below.
[0005]
FIG. 8 is a circuit diagram showing a conventional CMOS image sensor. In FIG. 8, 1 is a pixel, 2 is a photodiode that converts an optical signal into an electrical signal and stores it, 4 is a transfer MOS transistor that transfers an electrical signal stored in the photodiode 2, and 3 is transferred from the photodiode 2 An amplifying MOS transistor for amplifying the optical signal 5 is a resetting MOS transistor for resetting the gate electrode potential of the amplifying MOS transistor 3, and 6 is a drain electrode for the resetting MOS transistor 5 and a drain electrode for the amplifying MOS transistor 3. A power supply potential supply line that is connected and supplies a power supply potential to the pixel 1 side, 7 is a selection switch MOS transistor that selects the output source pixel 1 of the amplified signal based on the electric signal, and 8 is a signal output line that transmits the amplified signal, Reference numeral 9 denotes a constant current supply MOS transistor for supplying a constant current to the vertical output line 8.
[0006]
Further, 10 is a reset control line for controlling the gate potential of the reset MOS transistor 5, 11 is a transfer control line for controlling the gate potential of the transfer MOS transistor 4, and 12 is the gate potential of the selection MOS transistor 7. A selection control line 13 for controlling the constant voltage supply line 13 is a constant potential supply line for supplying a constant potential to the gate of the MOS transistor 9 so as to operate in a saturation region such that the MOS transistor 9 becomes a constant current supply source. .
[0007]
Further, 14 is a pulse terminal for supplying a reset pulse to the reset control line 11, 15 is a pulse terminal for supplying a transfer pulse to the transfer control line 10, and 16 is for supplying a selection pulse to the selection control line 12. Pulse terminal, 17 is a vertical scanning circuit for sequentially selecting and scanning the rows of pixels 1 in a matrix arrangement, 18-1 and 18-2 are first and second row selection output lines of the vertical scanning circuit, and 19 is a reset control line. 10 is a switching MOS transistor for guiding a pulse from the pulse terminal 15, 20 is a switching MOS transistor for guiding a pulse from the pulse terminal 14 to the transfer control line 11, and 21 is a pulse guiding the pulse from the pulse terminal 16 to the selection control line 12. This is a switching MOS transistor.
[0008]
Furthermore, 22 is a readout circuit for reading a signal from the pixel 1, 23 is a capacitor for holding the reset signal output of the pixel 1, 24 is a capacitor for holding the optical signal output of the pixel 1, and 25 is the vertical output line 8 and the capacitor 23. Switch MOS transistor for controlling the conduction between the vertical output line 8 and the capacitor 24, and switching MOS transistors 37 and 38 for applying pulses to the gates of the switching MOS transistors 25 and 26, respectively. The pulse supply terminal 27 is a horizontal output line through which a noise signal held in the capacitor 23 is transmitted, 28 is an optical signal transmission optical signal held in the capacitor 24, and 29 is a conduction between the capacitor 23 and the horizontal output line 27. A switching MOS transistor 30 for controlling the switching, and a switching MOS transistor 30 for controlling the conduction between the capacitor 24 and the signal output line 28.
[0009]
Further, 31 is a horizontal output line reset MOS transistor for resetting the potential of the horizontal output line 27, 32 is a horizontal output line reset MOS transistor for resetting the potential of the horizontal output line 28, and 33 is a horizontal output line reset MOS transistor 31. , 32 is a power supply terminal for supplying a reset potential, 34 is a horizontal scanning circuit for sequentially selecting capacitors 23, 24 provided for each column of the pixel 1 in the matrix arrangement, and 35-1, 35-2 are switches. Connected to the MOS transistors 29 and 30, 36 is a pulse supply terminal for applying a pulse to the gates of the horizontal output line reset MOS transistors 31 and 32, and 39 is the difference between the potential of the horizontal output line 27 and the potential of the signal output line 28. A differential amplifier 40 that amplifies and outputs a voltage component is an output terminal of a differential amplifier 39.
[0010]
FIG. 8 shows the pixel 1 in 2 rows and 2 columns for the sake of simplicity, but the number of matrices actually depends on the application.
[0011]
FIG. 9 is a timing chart showing the operation of FIG. It is assumed that all the MOS transistors shown in FIG. 8 are N-type, and are turned on when the gate potential is high and turned off when low. First, when the pulse signal applied to the first row selection output line 18-1 is switched to the high level by the vertical scanning circuit 17, the operation of the pixels 1 in the first row becomes possible. When the pulse signal applied to the pulse terminal 16 switches to a high level, the source of the amplifying MOS transistor 3 of the pixel 1 and the constant current supply MOS transistor 9 are connected, and the signal from the pixel 1 side is the vertical output line. 8 can be output.
[0012]
By setting the pulse signal applied to the pulse terminal 15 to the high level, the reset MOS transistor 5 is turned on, and the gate portion of the amplification MOS transistor 3 is reset to the reset potential.
[0013]
Next, the pulse applied to the pulse supply terminal 37 is switched to a high level, and the output signal of the pixel 1 is read out and stored in the capacitor 23 through the MOS transistor 25.
[0014]
Next, by setting the pulse applied to the pulse terminal 14 to the high level, the optical signal generated by the photodiode 2 is transferred to the gate of the MOS transistor 3 through the transfer MOS transistor 4.
[0015]
Here, a noise signal generated when the potential of the pixel 1 is reset is superimposed on the optical signal transferred to the gate of the MOS transistor 3.
[0016]
Subsequently, when a high level pulse is applied to the pulse supply terminal 38, an amplified signal based on the optical signal on which the noise signal is superimposed is accumulated in the capacitor 24 through the MOS transistor 26.
[0017]
When the horizontal scanning circuit 34 is driven, the pulse signals output to the first column selection output line 35-1 and the second column selection output line 35-2 are sequentially set to the high level and accumulated in the capacitors 23 and 24. These signals are output to the horizontal output lines 27 and 28 through the MOS transistors 29 and 30, respectively.
[0018]
Before the high-level pulse is output to the first column selection output line 35-1 and the second column selection output line 35-2, the pulse applied to the pulse supply terminal 36 is set to the high level, and the horizontal output line It is necessary to reset the potentials of the horizontal output lines 27 and 28 through the reset MOS transistors 31 and 32.
[0019]
The signals guided to the horizontal output lines 27 and 28 are input to the differential amplifier 39, the difference is taken, and an amplified signal based on the optical signal is output from the output terminal 40.
[0020]
Similarly, when signals are read out from the pixels 1 in the second row, an amplified signal based on the optical signal is output from the output terminal 40.
[0021]
[Problems to be solved by the invention]
However, the conventional technique has the following problems. That is, since the gain of the signal input to the differential amplifier is slightly different as will be described below, noise cannot be completely removed.
[0022]
If the capacitors 23 and 24 are CTN and CTS, respectively, and the capacitors of the horizontal output lines 27 and 28 are CHN and CHS, respectively, the gain up to the differential amplifier 39 is
CTN / (CTN + CHN)
CTS / (CTS + CHS)
It is.
[0023]
In the design phase,
CTN = CTS
CHN = CHS
As a result, it is difficult to make the two output paths completely congruent, and the actual process steps may deviate from the design. The two paths have slightly different gains.
[0024]
For the reasons described above, the remaining removal of the variation in the noise signal of the pixel appears as so-called fixed pattern noise (FPN), and the S / N ratio of the pixel is not sufficiently increased.
[0025]
Further, the gain of the signal output up to the differential amplifier 39 is reduced. That is, the signal voltage input to the differential amplifier is relative to the pixel output voltage.
CTS / (CTS + CHS) <1
The gain is smaller.
[0026]
On the other hand, the differential amplifier 39 always generates some random noise. Further, thermal noise due to the parasitic capacitances of the storage capacitors 23 and 24 and the horizontal output lines 27 and 28 reaching the differential amplifier 39 occurs. As a result, the S / N ratio of the sensor relating to random noise falls.
[0027]
Accordingly, an object of the present invention is to improve the S / N ratio by reducing FPN.
[0028]
Another object of the present invention is to improve the S / N ratio by reducing random noise.
[0029]
[Means for Solving the Problems]
The photoelectric conversion device of the present invention is a plurality of pixels arranged in a matrix, each pixel being transferred by a photoelectric conversion unit, a transfer unit that transfers charges generated by the photoelectric conversion unit, and a transfer unit A pixel amplifying unit that outputs a pixel signal based on the generated charge; a pixel reset unit that initializes an input of the pixel amplifying unit; and an input of the pixel amplifying unit included in the pixel signal A clamp circuit that reduces a noise component generated when initializing the signal, an amplifier that is provided corresponding to the column of pixels and that amplifies the pixel signal in which the noise component is reduced by the clamp circuit, and the amplifier An offset removal circuit provided in a subsequent stage to remove the offset of the amplifier; Applying means for applying a clamp potential to the input terminal of the amplifier when a noise signal generated when resetting the potential of the pixel is output from the pixel; Including The clamp circuit has a clamp capacitor for clamping the output from the pixel and a switch element for clamping the input potential of the amplifier, and the amplifier sets a gain whose absolute value is larger than 1. One end of the clamp capacitor is connected to the input terminal of the amplifier It is characterized by that.
The solid-state imaging system according to the present invention includes the photoelectric conversion device.
[0033]
DETAILED DESCRIPTION OF THE INVENTION
(Embodiment 1)
FIG. 1 is an equivalent circuit diagram of the solid-state imaging device according to the first embodiment of the present invention. In FIG. 1, 1 is a pixel, 2 is a photodiode that converts an optical signal into an electrical signal and stores it, 4 is a transfer MOS transistor that transfers an electrical signal stored in the photodiode 2, and 3 is transferred from the photodiode 2 An amplifying MOS transistor for amplifying the electric signal, 5 is a resetting MOS transistor for resetting the potential of the gate electrode of the amplifying MOS transistor 3, and 6 is a drain electrode of the resetting MOS transistor 5 and a drain of the amplifying MOS transistor 3. A power supply potential supply line that is connected to the electrode and supplies a power supply potential to the pixel 1, 7 is a selection switch MOS transistor that selects a pixel from which an amplified signal is output based on an electrical signal, 8 is a vertical output line that transmits the amplified signal, Reference numeral 9 denotes a constant current supply MOS transistor for supplying a constant current to the vertical output line 8. .
[0034]
Further, 10 is a reset control line for controlling the gate potential of the reset MOS transistor 5, 11 is a transfer control line for controlling the gate potential of the transfer MOS transistor 4, and 12 is the gate potential of the selection MOS transistor 7. A selection control line 13 for controlling the constant voltage supply line 13 is a constant potential supply line for supplying a constant potential to the gate of the MOS transistor 9 so as to operate in a saturation region such that the MOS transistor 9 becomes a constant current supply source. .
[0035]
Further, 14 is a pulse terminal for supplying a reset pulse to the reset control line 11, 15 is a pulse terminal for supplying a transfer pulse to the transfer control line 10, and 16 is for supplying a selection pulse to the selection control line 12. A pulse terminal, 17 is a vertical scanning circuit for sequentially selecting and scanning the rows of the pixels 1, 18-1 and 18-2 are first and second row selection output lines of the vertical scanning circuit 17, and 19 is a pulse terminal for the reset control line 10. 15 is a switch MOS transistor that guides a pulse from the pulse terminal 16 to the transfer control line 11, and 21 is a switch MOS transistor that guides a pulse from the pulse terminal 16 to the selection control line 12. It is a MOS transistor.
[0036]
41 is a gain amplifier for amplifying each signal from the pixel 1 in each column, 42 is a clamp capacitor for clamping the output from the pixel 1, 43 is a MOS switch for clamping the input potential of the gain amplifier 41, Reference numeral 44 is a clamp potential supply terminal, and 45 is a supply terminal for supplying a switch pulse to the gate of the clamp switch 43.
[0037]
Furthermore, 22 is a readout circuit (removal circuit) that reads a signal from the pixel 1, 23 is a capacitor that holds the offset of the gain amplifier 41 when outputting a signal based on a noise signal generated when the potential of the pixel 1 is reset, and 24 A capacitor for holding the offset of the gain amplifier 41 and the output of the gain amplifier 41, 25 is a switching MOS transistor for controlling conduction between the vertical output line 8 and the capacitor 23, and 26 is for controlling conduction between the vertical output line 8 and the capacitor 24. Switch MOS transistors 37 and 38 for supplying pulses to the gates of the switch MOS transistors 25 and 26, 27 a horizontal output line for transmitting a signal held in the capacitor 23, and 28 a capacitor 24 A horizontal output line 29 for transmitting the signal held in the capacitor 23 is a switch for controlling the conduction between the capacitor 23 and the horizontal output line 27. Pitch MOS transistor, 30 is a MOS transistor for a switch for controlling conduction between the capacitor 24 and the signal output line 28.
[0038]
Further, 31 is a horizontal output line reset MOS transistor for resetting the potential of the horizontal output line 27, 32 is a horizontal output line reset MOS transistor for resetting the potential of the horizontal output line 28, and 33 is a horizontal output line reset MOS transistor 31. , 32 is a power supply terminal for supplying a reset potential, 34 is a horizontal scanning circuit for sequentially selecting capacitors 23, 24, 35-1, 35-2 are switch MOS transistors 29, 30 from the horizontal scanning circuit 34. The first and second column selection output lines for transmitting signals, 36 is a pulse supply terminal for applying a pulse to the gates of the horizontal output line reset MOS transistors 31 and 32, and 39 is the potential of the horizontal output line 27 and the signal output line 28. A differential amplifier 40 that amplifies and outputs a voltage difference between the first and second potentials, and 40 is an output terminal of the differential amplifier 39.
[0039]
Although FIG. 1 shows a state in which the pixels 1 are arranged in 2 rows and 2 columns for the sake of simplicity, the number of pixels 1 is actually a number corresponding to the application. The pixels 1 are not limited to the matrix arrangement, but may be arranged in a delta shape or a honeycomb shape.
[0040]
FIG. 2 is an equivalent circuit diagram of the gain amplifier 41 of FIG. In FIG. 2, 46 is a differential input stage, 47 is a non-inverting input section, 48 is an inverting input section, 49 is a constant current supply MOS transistor, 50 is a source follower which is an output stage, 51 is an output section, and 52 is A MOS transistor for supplying a constant current, 53 is a connection for connecting the output section of the differential input stage 46 and the input section of the source follower 50, 54 is a MOS transistor for connecting the output section 51 and the inverting input section 48, and 55 is One electrode is connected to the inverting input unit 48 and the other electrode is connected to ground or a fixed potential. 56 is connected to the inverting input unit 48 and the other electrode is connected to the output unit 51. , 57 is a terminal for supplying a constant potential to the gates of the MOS transistors 49 and 52, and 58 is a terminal for applying a control pulse to the gate of the MOS transistor 54.
[0041]
The gain amplifier 41 is designed so that the offset variation is smaller than the reset variation of the pixel 1, and the configuration is as shown in FIG. 2 if the absolute value of the gain is larger than 1. For example, the differential input stage may be configured using another transistor, or an emitter follower may be used instead of the source follower.
[0042]
Regarding the offset, since the restrictions on the layout of the gain amplifier 41 are generally much more lenient than the restrictions on the layout of the pixel 1, it is possible to design the offset variation to be small.
[0043]
Further, by making the gain of the gain amplifier 41 larger than 1, the signal output from the pixel 1 is finally multiplied by the gain. Therefore, even if the noise of the differential amplifier 39 and the thermal noise caused by the capacitors 23 and 24 are not changed, the S / N ratio regarding random noise is improved.
[0044]
Incidentally, the gain amplifier 41 shown in FIG. 2 can be operated with a constant current whose operation does not depend on the magnitude of the signal voltage. Further, as will be described later, the gain can be easily set only by changing the capacitance division ratio of the capacitors 55 and 56, and the capacitance division ratio is less susceptible to manufacturing variations and is generally formed stably. There is an advantage that it is easy to obtain.
[0045]
When the current of the gain amplifier 41 depends on the signal voltage, the amount of voltage drop caused by the resistance of the ground line and the power supply line supplied to the gain amplifier 41 varies, so the offset levels in the capacitors 23 and 24 are different, and the difference is different. Since it varies depending on the signal amount, the offset removal rate decreases and the S / N ratio with respect to the FPN decreases. However, the gain amplifier 41 has an advantage that such a decrease in the S / N ratio can be prevented.
[0046]
FIG. 3 is a timing chart showing the operation of FIG. Note that the MOS transistors shown in FIG. 1 are all N-type, and are described as being on when the gate potential is high and off when low.
[0047]
First, when the pulse signal applied to the first row selection output line 18-1 is switched to the high level by the vertical scanning circuit 17, the operation of the pixels 1 in the first row becomes possible. When the pulse signal applied to the pulse terminal 16 switches to a high level, the source of the amplifying MOS transistor 3 of the pixel 1 and the constant current supply MOS transistor 9 are connected, and the signal from the pixel 1 side is the vertical output line. 8 can be output.
[0048]
By setting the pulse signal applied to the pulse terminal 15 to the high level, the reset MOS transistor 5 is turned on, and the gate portion of the amplification MOS transistor 3 is reset to the reset potential.
[0049]
Next, the pulse applied from the supply terminal 45 to the gate of the MOS transistor 43 is switched to a high level, the pulse applied to the pulse supply terminal 37 is switched to a high level, and the input potential of the gain amplifier 41 is changed. Clamp potential.
[0050]
Here, the input part and the output part of the gain amplifier 41 are the non-inverting input part 47 and the output part 51 of FIG. 2, respectively.
[0051]
When the MOS switch 54 is on, the gain amplifier 41 operates as a voltage follower, and the inverting input unit 48 is initialized. Therefore, by applying a pulse synchronized with the pulse applied to the supply terminal 45 to the supply terminal 58, the potential of the output unit 51 is added to the potential of the non-inverting input unit 47 and the offset voltage of the gain amplifier 41 is added. The offset of the gain amplifier 41 is accumulated in the capacitor 23.
[0052]
Next, by setting the pulse applied to the pulse terminal 14 to the high level, the optical signal generated by the photodiode 2 is transferred to the gate of the MOS transistor 3 through the transfer MOS transistor 4.
[0053]
Here, a noise signal generated when the potential of the pixel 1 is reset is superimposed on the optical signal transferred to the gate of the MOS transistor 3.
[0054]
Subsequently, when a high-level pulse is applied to the pulse supply terminal 38, an amplification signal based on the optical signal on which the noise signal is superimposed is input to the gain amplifier 41. At this time, since the MOS switch 54 is off, this input signal operates as a voltage feedback operational amplifier (op-amp) and is amplified to a gain multiplied by the capacitance division ratio of the capacitors 55 and 56.
[0055]
Therefore, the capacitor 24 stores a signal in which the offset level of the gain amplifier 41 is superimposed on the output signal of the gain amplifier. Incidentally, if the values of the capacitors 55 and 56 are C1 and C2, respectively, (C1 + C2) / C2 becomes a gain.
[0056]
When the horizontal scanning circuit 34 is driven, the pulse signals output to the first column selection output line 35-1 and the second column selection output line 35-2 are sequentially set to the high level and accumulated in the capacitors 23 and 24. These signals are output to the horizontal output lines 27 and 28 through the MOS transistors 29 and 30, respectively.
[0057]
Before the high-level pulse is output to the first column selection output line 35-1 and the second column selection output line 35-2, the pulse applied to the pulse supply terminal 36 is set to the high level, and the horizontal output line It is necessary to reset the potentials of the horizontal output lines 27 and 28 through the reset MOS transistors 31 and 32.
[0058]
The signals guided to the horizontal output lines 27 and 28 are input to the differential amplifier 39, the difference is taken, and an amplified signal based on the optical signal is output from the output terminal 40.
[0059]
Similarly, when signals are read out from the pixels 1 in the second row, an amplified signal based on the optical signal is output from the output terminal 40.
[0060]
In this way, when clamping is performed by the MOS switch 43 during the output period of the noise signal of the pixel 1 and the input potential of the gain amplifier 41 is set to the clamp potential, the offset of the gain amplifier 41 is removed by the differential amplifier 39 and finally. Can obtain a sensor signal with small offset variation.
[0061]
(Embodiment 2)
FIG. 4 is an equivalent circuit diagram of the solid-state imaging device according to the second embodiment of the present invention. In FIG. 4, 59 is a readout circuit (removing means) including a clamp circuit, 60 is a capacitor for holding the clamped signal, 61 is a switching MOS transistor for controlling conduction between the clamp capacitor 42 and the capacitor 60, 62 Is a horizontal output line for outputting a signal held in the capacitor 60, 65 is a MOS transistor for resetting the potential of the horizontal output line 62, 66 is an amplifier for amplifying a signal transmitted through the horizontal output line 62, and 67 is an amplifier 66 Output terminal. In FIG. 4, the same parts as those in FIG.
[0062]
FIG. 5 is a timing chart showing the operation of FIG. It is assumed that all the MOS transistors shown in FIG. 4 are N-type, and are turned on when the gate potential is high and turned off when low.
[0063]
First, when the pulse signal applied to the first row selection output line 18-1 is switched to the high level by the vertical scanning circuit 17, the operation of the pixels 1 in the first row becomes possible. When the pulse signal applied to the pulse terminal 16 switches to a high level, the source of the amplifying MOS transistor 3 of the pixel 1 and the constant current supply MOS transistor 9 are connected, and the signal from the pixel 1 side is the vertical output line. 8 can be output.
[0064]
By setting the pulse signal applied to the pulse terminal 15 to the high level, the reset MOS transistor 5 is turned on, and the gate portion of the amplification MOS transistor 3 is reset to the reset potential.
[0065]
Then, an amplified signal based on a noise signal generated at the time of reset is output from the pixel 1 to the vertical output line 8, and this amplified signal is amplified by the gain amplifier 41.
[0066]
Thereafter, when the pulse signal input from the pulse input terminal 64 is set to the high level and the pulse applied to the supply terminal 45 is set to the high level, the clamp potential supplied from the clamp potential supply terminal 44 by the capacitor 60 Become.
[0067]
Next, by setting the pulse applied to the pulse terminal 14 to the high level, the optical signal generated by the photodiode 2 is transferred to the gate of the MOS transistor 3 through the transfer MOS transistor 4.
[0068]
Then, the gate of the MOS transistor 3 is turned on, and an amplified signal based on the optical signal on which the noise signal is superimposed is output from the pixel 1 and input to the gain amplifier 41.
[0069]
As a result, the capacitor 60 is in a state where the clamp potential is added to the potential based on the output signal of the gain amplifier 41. At this time, the pulse signal applied to the pulse input terminal 64 is returned to the low level. The signal accumulated in the capacitor 60 becomes a signal that does not include the noise signal of the pixel 1 and the offset of the gain amplifier 41 by the clamping operation.
[0070]
Thereafter, when the horizontal scanning circuit 34 is driven, the pulse signals output to the first column selection output line 35-1 and the second column selection output line 35-2 are sequentially set to the high level, and each column of the pixel 1 The signal stored in the capacitor 60 is guided to the horizontal output line 62 through the MOS transistor 63, respectively.
[0071]
Before the pulse signals output to the first column selection output line 35-1 and the second column selection output line 35-2 are sequentially switched to a high level, the potential of the horizontal output line 62 is reset as in the first embodiment. It is necessary to keep it. The signal output guided to the horizontal output line 62 is input to the amplifier 66, and an amplified signal based on the optical signal is output from the output terminal 67.
[0072]
Similarly, when signals are read out from the pixels 1 in the second row, an amplified signal based on the optical signal is output from the output terminal 67.
[0073]
The voltage of the signal from the pixel 1 is subjected to a capacitance division between the clamp capacitor 42 and the storage capacitor 60, a capacitance division between the capacitor 60 and the signal output line 62, and two capacitance divisions. Since the gain is multiplied by 41, the signal voltage when input to the amplifier 66 does not drop greatly.
[0074]
On the other hand, the noise signal variation of the pixel 1 and the offset variation of the gain amplifier 41 are eliminated by the clamp circuit, so that the S / N ratio is high for both FPN and random noise.
[0075]
In addition, since the input portion capacitance of the gain amplifier 41 in the present embodiment is sufficiently small, the signal output from the arbitrary pixel 1 may actually charge up only the capacitance of the vertical output line 8, and the pixel output Can be speeded up.
[0076]
(Embodiment 3)
FIG. 6 is an equivalent circuit diagram of the solid-state imaging device according to the third embodiment of the present invention. The operation of the solid-state imaging device shown in FIG. 6 is the same as the operation of the solid-state imaging device of FIG. However, since the solid-state imaging device of this embodiment does not include a clamp circuit, a signal based on the noise signal of the pixel 1 is accumulated in the storage capacitor 23 in addition to the offset of the gain amplifier 41, and the gain is stored in the storage capacitor 24. In addition to the offset of the amplifier 41 and the output signal of the gain amplifier 41, a signal based on the noise signal of the pixel 1 is accumulated.
[0077]
For this reason, the output terminal 40 of the amplifier 39 has, as fixed pattern noise, residual removal of the variation between the signal based on the noise signal of the pixel 1 and the offset of the gain amplifier 41, but the variation in the offset of the gain amplifier 41 is small. So there is no problem.
[0078]
Further, since the gain amplifier 41 performs signal amplification with a gain larger than 1, the S / N ratio of the present embodiment relating to FPN is improved, and the S / N ratio relating to random noise is also gained by the gain amplifier 41. It improves by being doubled.
[0079]
Further, as in the second embodiment, the output from the pixel 1 is actually only required to charge up the parasitic capacitance of the vertical output line 8, and the pixel output can be speeded up.
[0080]
As described above, in each embodiment, the case where the signal amplification is performed by the MOS transistor in the pixel 1 has been described as an example. However, the signal amplification may be performed by another transistor.
[0081]
(Embodiment 4)
FIG. 7 is a block diagram showing a structural configuration of an imaging system according to Embodiment 4 of the present invention. In FIG. 7, 1051 is a barrier that serves as a lens switch and a main switch, 1052 is a lens that forms an optical image of a subject on the solid-state imaging device 1054 described in Embodiments 1 to 3, and 1053 is an amount of light that has passed through the lens 1052. A variable aperture, 1054 is a solid-state image sensor for capturing the subject imaged by the lens 1052 as an image signal, and 1055 performs various corrections, clamps, and the like on the image signal output from the solid-state image sensor 1054. An imaging signal processing circuit, 1056 is an A / D converter that performs analog-digital conversion of an image signal output from the solid-state imaging device 1054, and 1057 performs various corrections on the image data output from the A / D converter 1056. A signal processing unit 1058 for compressing data, a solid-state imaging device 1054, and an imaging signal processing circuit 1 55, A / D converter 1056, timing generation unit for outputting various timing signals to the signal processing unit 1057, 1059 is a general control / computation unit for controlling various operations and the entire still video camera, and 1060 temporarily stores image data. A memory unit for storage, 1061 is a recording medium control interface (I / F) unit for performing recording or reading on a recording medium, and 1062 is a removable recording such as a semiconductor memory for recording or reading image data. A medium 1063 is an external interface (I / F) unit for communicating with an external computer or the like.
[0082]
Next, the operation of the still video camera at the time of shooting in the above configuration will be described. When the barrier 1051 is opened, the main power supply is turned on, the control system power supply is turned on, and the power supply of the imaging system circuit such as the A / D converter 1056 is turned on.
[0083]
Then, in order to control the exposure amount, the overall control / arithmetic unit 1059 opens the aperture 1053, and the signal output from the solid-state imaging device 1054 passes through the imaging signal processing circuit 1055 to the A / D converter 1056. Is output.
[0084]
The A / D converter 1056 A / D converts the signal and outputs it to the signal processing unit 1057. The signal processing unit 1057 performs exposure calculation by the overall control / calculation unit 1059 based on the data.
[0085]
The brightness is determined based on the result of the photometry, and the overall control / calculation unit 1059 controls the aperture according to the result.
[0086]
Next, based on the signal output from the solid-state image sensor 1054, the high-frequency component is extracted and the distance to the subject is calculated by the overall control / calculation unit 1059. Thereafter, the lens 1052 is driven to determine whether or not it is in focus. When it is determined that the lens is not in focus, the lens 1052 is driven again to perform distance measurement.
[0087]
Then, after the in-focus state is confirmed, the main exposure starts. When the exposure is completed, the image signal output from the solid-state imaging device 1054 is corrected and the like in the imaging signal processing circuit 1055, further A / D converted by the A / D converter 1056, and totally controlled through the signal processing unit 1057. Accumulated in the memory unit 1060 by the operation 1059.
[0088]
Thereafter, the data stored in the memory unit 1060 is recorded on a removable recording medium 1062 such as a semiconductor memory through the recording medium control I / F unit 1061 under the control of the overall control / arithmetic unit 1059. Further, the image may be processed by directly inputting to a computer or the like through the external I / F unit 1063.
[0089]
【The invention's effect】
As described above, according to the present invention, FPN and random noise can be reduced, and the S / N ratio can be improved.
[Brief description of the drawings]
FIG. 1 is an equivalent circuit diagram of a solid-state imaging device according to a first embodiment of the present invention.
FIG. 2 is an equivalent circuit diagram of the gain amplifier 41 of FIG.
FIG. 3 is a timing chart showing the operation of FIG. 1;
FIG. 4 is an equivalent circuit diagram of a solid-state imaging apparatus according to Embodiment 2 of the present invention.
FIG. 5 is a timing chart showing the operation of FIG. 4;
FIG. 6 is an equivalent circuit diagram of the solid-state imaging device according to the third embodiment of the present invention.
FIG. 7 is a block diagram illustrating a schematic configuration of a solid-state imaging system according to a fourth embodiment of the present invention.
FIG. 8 is a circuit diagram showing a conventional CMOS image sensor.
9 is a timing chart showing the operation of FIG.
[Explanation of symbols]
1 pixel
2 Photodiode
3 MOS transistor
4 Transfer MOS switch
5 Reset MOS switch
6 Power supply potential supply line
7 MOS switch for selection switch
8 Vertical output line
9 Constant current supply MOS transistor
10 Reset control line
11 Transfer control line
12 Selection control line
13 Constant potential supply line
14-16 pulse terminal
17 Vertical scanning circuit
18-1 First row selection output line
18-2 Second row selection output line
19-21 MOS transistor for switch
22 Read circuit
23,24 capacity
25,26 MOS transistor for switch
27, 28, 62 Horizontal output line
30 MOS transistor for switch
31, 32 Horizontal output line reset MOS transistor
33 Power supply terminal
34 Horizontal scanning circuit
35-1 First column selection output line
35-2 Second column selection output line
36-38 pulse supply terminal
39 Differential Amplifier
40 output terminals
41, 66 gain amplifier
42 Clamping capacity
43 MOS transistor
44 Clamp potential supply terminal
45 Supply terminal
46 Differential input stage
47 Non-inverting input
48 Inverting input section
49 MOS transistor
50 Source follower
51 Output section
52 MOS transistor
53 Connection
54 MOS transistor
55,56 capacity
57, 58 terminals

Claims (3)

A plurality of pixels arranged in a matrix, each pixel having a photoelectric conversion unit, a transfer unit that transfers charges generated by the photoelectric conversion unit, and a pixel signal based on the charges transferred by the transfer unit A plurality of pixels having a pixel amplifying unit for output and a pixel reset unit for initializing an input of the pixel amplifying unit;
A clamp circuit for reducing a noise component generated when initializing an input of the pixel amplifier included in the pixel signal;
An amplifier that is provided corresponding to the column of pixels and that amplifies the pixel signal in which the noise component is reduced by the clamp circuit;
An offset removal circuit that is provided in a subsequent stage of the amplifier and removes the offset of the amplifier;
See containing and a applying means for applying a clamping voltage to an input terminal of the amplifier when it is a noise signal generated when resetting the potential of the pixel output from the pixel,
The clamp circuit includes a clamp capacitor for clamping an output from the pixel, and a switch element for clamping an input potential of the amplifier.
The amplifier is capable of setting a gain whose absolute value is greater than 1.
One end of the clamp capacitor is connected to an input terminal of the amplifier . The photoelectric conversion apparatus according to claim 1, wherein the amplifier includes a differential amplification unit. A solid-state imaging system comprising: a photoelectric conversion device according to claim 1 or 2.

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