JP4552595B2 - Electro-optical device, image signal processing method thereof, and electronic apparatus - Google Patents

Description

  The present invention relates to a technique for preventing deterioration in display quality caused by sampling a data signal at a delayed timing.

  In recent years, a projector that forms a reduced image by a display panel such as a liquid crystal and enlarges and projects the reduced image on a screen, a wall surface, or the like by an optical system is becoming popular. The projector does not have a function of creating an image by itself, and is supplied with image data (also referred to as video data or video signal) from a host device such as a personal computer or a TV tuner. This image data specifies the gradation (brightness) of the pixels, and is supplied in the form of vertical scanning and horizontal scanning of the pixels arranged in a matrix, so that the panel used in the projector is also this It is appropriate to drive according to the format. For this reason, in the panel used for the projector, the scanning lines are selected in a predetermined order, while the data lines are sequentially selected over a period (one horizontal scanning period) in which one row of scanning lines is selected, and the image signal A dot sequential method is generally used in which a data signal supplied to a line is sampled on a selected data line. Here, the data signal is a signal obtained by converting image data so as to be suitable for driving a liquid crystal.

  Recently, a method called phase expansion driving has been devised in order to cope with high definition of a display image such as high-definition. In this phase expansion drive method, in one horizontal scanning period, a predetermined number of data lines, for example, six lines are collectively selected as a block and simultaneously selected, and pixels corresponding to the intersection of the selected scanning line and the selected data line are selected. The image signal is expanded six times with respect to the time axis and sampled on each of the six data lines corresponding to the selected block. There is no difference in that the data signal is sampled on the data line in either the point sequential method or the phase expansion drive method.

Here, the data line is configured to be selected by a sampling signal (pulse). Specifically, a sampling switch is provided between the image signal line and each data line, and the data signal is sampled on the data line when the sampling switch is turned on according to the sampling signal. .
On the other hand, in the panel itself, since transistors, various wirings, and the like are formed on a substrate such as glass, capacitance or the like is parasitic on various signal lines including the image signal lines, and signal delay is likely to occur. For this reason, a state in which the sampling signal is delayed with respect to the supply timing of the image signal may also occur. When this state occurs, a data signal to be sampled on a certain data line is not correctly sampled, so that a so-called ghost is generated and display quality is deteriorated. Therefore, in recent years, a technique has been proposed in which the degree of ghost is predicted from the change in the data signal, and the data signal is corrected so as to cancel it (see Patent Document 1).
Japanese Patent Laid-Open No. 2001-337641

However, the amount of delay in various signal lines varies depending on the environment such as individual differences and temperature, so it is not uniform. Therefore, the amount of correction that cancels ghosts should be determined appropriately only from the change in the data signal. The problem of being unable to do so occurred.
The present invention has been made in view of the above-described circumstances, and an object of the present invention is to provide a correction amount for canceling a ghost even if the delay amount of various signal lines changes due to an environment such as individual difference or temperature. It is an object of the present invention to provide an electro-optical device, an image processing method for the electro-optical device, and an electronic apparatus that can be appropriately obtained.

To achieve the above object, the present invention is provided corresponding to each intersection of a plurality of scanning lines and a plurality of data lines, and is sampled on the data lines when the scanning lines and the data lines are selected. A pixel having a gradation corresponding to a data signal, a scanning line driving circuit for selecting the scanning line, and a shift register for sequentially generating a pulse signal for selecting the data line over a period in which the scanning line is selected And a logic circuit that generates a sampling signal from the pulse signals respectively generated by the shift register, and a sampling circuit that samples a data signal supplied via an image signal line on the data line according to the sampling signal An image signal processing method of an electro-optical device, wherein the sample for a data signal supplied via the image signal line Detecting a delay amount of the ring signal, converts the image data serial specifying a gradation of a plurality of pixels in parallel the image data distributed to a plurality of channels, each said channel, the image data distributed, A change between the distributed image data and the next distributed image data is obtained, and the change is multiplied by a coefficient corresponding to the detection result of the delay amount to calculate a correction value. It said image data corrected by the correction value, the pre Kiho Tadashisa image data, converts the data signal and supplying the image signal lines. According to this method, the correction amount of the image data is controlled according to the detected delay amount of the sampling signal, so that it is difficult to receive changes such as individual differences and environmental temperature. The delay amount of the sampling signal here may be detected either directly or indirectly.

In the present invention, it is preferable to increase the coefficient as the detected delay amount increases, and it is also preferable to increase the coefficient with the passage of time from the initial period in which the scanning line is selected.
Further, in the present invention, the data lines are divided into a plurality of blocks, the image signal lines are the same number as the blocks, and a plurality of data lines of the same block are selected substantially simultaneously by the sampling signal. It is also preferable to sample image signals supplied to different image signal lines.
In addition to the image processing method of the electro-optical device, the present invention can be conceptualized as the electro-optical device itself. In addition, since the electronic apparatus according to the present invention includes the electro-optical device, it is possible to prevent the display quality from being deteriorated as a result of the ghost being canceled without being affected by individual differences or environmental temperature.

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram illustrating the overall configuration of the electro-optical device according to the present embodiment.
As shown in this figure, the electro-optical device 10 is roughly divided into a processing circuit 50 and a panel 100. Among these, the processing circuit 50 is a circuit module formed on a printed board, and is connected to the panel 100 by an FPC (Flexible Printed Circuit) board or the like.
The processing circuit 50 includes a data signal supply circuit 300, a scan control circuit 212, and a data conversion circuit 214. Of these, the data signal supply circuit 300 further includes an S / P conversion circuit 310, a correction circuit group 320, and a D / A. A conversion circuit group 330 and an amplification / inversion circuit 340 are included.
Among these, the S / P conversion circuit 310 synchronizes with the vertical scanning signal Vs, the horizontal scanning signal Hs, and the dot clock signal DCLK, and distributes digital image data Vid supplied from a host device (not shown) to six channels. At the same time, the image data is expanded six times on the time axis (also referred to as phase expansion or serial-parallel conversion) and output as image data Vd1d to Vd6d. For convenience of explanation, the image data Vd1d to Vd6d may be referred to as channels 1 to 6, respectively.

Here, the image data Vid is data that designates the brightness of the pixel by a gradation value in the horizontal effective display period, and designates the pixel to the lowest gradation (black) in the horizontal blanking period. Note that the reason why a pixel is designated as the lowest gradation in the horizontal blanking period is mainly because the pixel does not contribute to display even if it is supplied to the pixel due to timing shift or the like. The reason why the image data Vid is converted from serial to parallel is to secure a sample and hold time and a charge / discharge time by increasing a time during which a data signal is applied in a sampling switch described later.
The correction circuit group 320 is an aggregate of correction circuits 3200 provided for each channel. The correction circuit group 320 corrects the image data Vd1d to Vd6 according to the change in the gradation value, and outputs the corrected image data Vd1e to Vd6e. Is. The detailed configuration of the correction circuit 3200 will be described later.

The D / A conversion circuit group 330 is an aggregate of D / A converters provided for each channel, and converts the corrected image data Vd1e to Vd6e into analog signals having voltages corresponding to the respective gradation values. To do.
The amplifying / inverting circuit 340 performs normal rotation or polarity inversion on the analog-converted signal with reference to the voltage Vc as will be described later, and supplies the signal to the panel 100 as data signals Vid1 to Vid6.
Regarding polarity inversion, there are various modes such as (a) every scanning line, (b) every data signal, (c) every pixel, and (d) every surface (frame). In this embodiment, (a) ) It is assumed that the polarity is inverted for each scanning line. However, the present invention is not limited to this.
The voltage Vc is the amplitude center voltage of the image signal as shown in FIG. In the present embodiment, for convenience, the higher voltage than the amplitude center voltage Vc is referred to as positive polarity, and the lower voltage is referred to as negative polarity. In this embodiment, the image data Vid is converted to analog after serial-parallel conversion, but of course, analog conversion may be performed before serial-parallel conversion.

Here, for convenience of description, the configuration of the panel 100 will be described. The panel 100 forms a predetermined image by an electro-optic change, and FIG. 2 is a block diagram showing an electrical configuration of the panel 100. FIG. 3 is a diagram illustrating a detailed configuration of the pixels of the panel 100.
As shown in FIG. 2, in the panel 100, a plurality of scanning lines 112 extend in the horizontal direction (X direction), while a plurality of data lines 114 extend in the vertical direction (Y direction) in the drawing. Has been. A pixel 110 is provided so as to correspond to each of the intersections of the scanning lines 112 and the data lines 114, thereby forming a display area 100a.
In this embodiment, the number of scanning lines 112 (the number of rows) is “m”, the number of data lines (the number of columns) is “6n” (a multiple of 6), and the pixels 110 are m rows × 6n columns. It is assumed that the arrangement is arranged in a matrix.

The six image signal lines 171 are supplied with data signals Vid1 to Vid6 from the amplification / inversion circuit 340, respectively.
One end of each data line 114 is provided with a sampling switch 150 for sampling the data signals Vid1 to Vid6 supplied to the image signal line 171 to the data line 114, respectively. In this embodiment, each sampling switch 150 is an n-channel thin film transistor (hereinafter referred to as TFT), and its drain is connected to the data line 114, while its gate has six data. The line 114 is commonly connected as one unit.

  Here, the data line 114 to which the gates of the sampling switches 150 are commonly connected is considered as one block. Considering such a block, the sampling switch 150 having a drain connected to one end of the data line 114 in the j-th column from the left in FIG. 2 has a remainder obtained by dividing j by 6 as “1”. If there is, its source is connected to the image signal line 171 to which the data signal Vid1 is supplied. Similarly, each of the sampling switches 150 whose drains are connected to the data lines 114 whose remainders obtained by dividing j by 6 are “2”, “3”, “4”, “5”, “0” Are connected to image signal lines 171 to which data signals Vid2 to Vid6 are supplied, respectively. For example, in FIG. 2, the source of the sampling switch 150 whose drain is connected to the data line 114 in the eleventh column from the left in FIG. 2 has a remainder of “5” obtained by dividing “11” by 6; It is connected to the supplied image signal line 171. Note that “j” here is for generalizing the data line 114 and is a positive integer satisfying 1 ≦ j ≦ 6n.

  As shown in FIG. 5, the scanning line driving circuit 130 takes in the transfer start pulse DY supplied at the beginning of the vertical effective display period at the timing when the level of the clock signal CLY changes (rises or falls) and sequentially. The signals are shifted and exclusively output sequentially as scanning signals G1, G2,..., Gm that become H level only during the horizontal scanning period (1H). Note that the details of the scanning line driving circuit 130 are not directly related to the present invention, and thus are omitted.

The block selection circuit 140 includes a shift register 142 and an AND circuit 144. Among these, as shown in FIG. 6, the shift register 142 takes in the transfer start pulse DX supplied at the beginning of the horizontal effective display period at the timing when the level of the clock signal CLX transitions and sequentially shifts the signal Sa1. , Sa2, Sa3,..., Sa (n-1), San.
The AND circuit 144 is provided in each output stage of the shift register 142, obtains a logical product signal of the signal from the output stage and the signal Ma / Enb supplied from one end of the pulse signal line 143, and each sample signal Output as S1, S2, S3,..., Sn.
Here, as shown in FIG. 6, the signal Ma / Enb is a signal that becomes the monitor pulse Ma in the horizontal blanking period and becomes the enable pulse Enb in the horizontal effective display period. Among these, the enable pulse Enb is generated by the scanning control circuit 212 so that the pulse width at which it becomes H level is narrower than the half cycle of the clock signal CLX.
Therefore, in the horizontal effective display period, the signals Sa1, Sa2,..., Sa (n−1), San from the shift register 142 are narrowed by the enable pulse Enb, and the sampling signals S1, S2, S3,. , Sn are output.

These sampling signals S1, S2, S3,..., Sn are commonly supplied to the gates of the sampling switches corresponding to the data lines 114 that are blocked in FIG. For example, since the second block from the left corresponds to the data lines 114 in the seventh column to the twelfth column, the sampling signal S2 is commonly used for the gates of the sampling switches 150 corresponding to these data lines 114. Supplied.
Note that the TFT constituting the sampling switch 150 is an n-channel type in this embodiment, but it may be a p-channel type or a complementary type combining both channels.

In the present embodiment, the monitor signal line 173 is provided so as to be adjacent to and substantially parallel to the image signal line 171 to which the data signals Vid1 to Vid6 are respectively supplied. The monitor signal line 173 is desirably formed under the same conditions (material, length, width, etc.) as the image signal line 171.
As will be described later, a reference pulse Ref is supplied to one end which is an input end of the monitor signal line 173, while the other end is connected to the phase difference detection circuit 180. The phase difference detection circuit 180 includes an AND circuit 182 and a TFT 184. Of these, the AND circuit 182 has the same circuit configuration as that of the AND circuit 144, and the TFT 184 has the same circuit configuration as that of the sampling switch 150.
Specifically, one of the input ends of the AND circuit 182 is connected to the opposite end (termination) side of the input side of the pulse signal line 143, while the other input end of the AND circuit 182 is connected to the horizontal blanking line. A signal Br which is at an H level only during the period is supplied. Similarly to the sampling switch 150, the TFT 184 is an n-channel TFT, its gate is connected to the output terminal of the AND circuit 182, its source is connected to the other end of the monitor signal line 173, and its drain is monitored. The signal Det is fed back to the processing circuit 50.

Next, the pixel 110 will be described.
As shown in FIG. 3, in the pixel 110, the source of the n-channel TFT 116 is connected to the data line 114, the drain is connected to the pixel electrode 118, and the gate is connected to the scanning line 112. Yes.
Further, the counter electrode 108 is provided in common to all the pixels so as to face the pixel electrode 118, and is maintained at a constant voltage LCcom. A liquid crystal layer 105 is sandwiched between the pixel electrode 118 and the counter electrode 108. Therefore, a liquid crystal capacitor composed of the pixel electrode 118, the counter electrode 108, and the liquid crystal layer 105 is formed for each pixel.

Although not shown in particular, each opposing surface of both substrates is provided with an alignment film that has been rubbed so that the major axis direction of the liquid crystal molecules is continuously twisted, for example, by about 90 degrees between the two substrates. A polarizer corresponding to the orientation direction is provided on each back side of the substrate.
If the voltage effective value applied to the liquid crystal layer 105 is zero, the light passing between the pixel electrode 118 and the counter electrode 108 rotates about 90 degrees along the twist of the liquid crystal molecules, while the voltage effective value As is increased, the liquid crystal molecules are tilted in the direction of the electric field, and as a result, their optical rotation disappears. For this reason, for example, in a transmission type, when polarizers whose polarization axes are orthogonal to each other according to the alignment direction are arranged on the incident side and the back side, if the voltage effective value is close to zero, the light transmittance is While the maximum is white display, the amount of transmitted light decreases as the effective voltage value increases, and finally black display with the minimum transmittance is obtained (normally white mode).
In addition, a storage capacitor 109 is formed for each pixel in order to make it difficult for charge to leak in the liquid crystal capacitor. One end of the storage capacitor 109 is connected to the pixel electrode 118 (the drain of the TFT 116), while the other end is commonly grounded across all pixels.
Note that the TFT 116 in the pixel 110 is formed by a manufacturing process common to the scanning line driving circuit 130, the shift register 142, the AND circuit 144, and the constituent elements of the sampling switch 150, and contributes to downsizing and cost reduction of the entire device. is doing.

The description returns to FIG. 1 again. The scanning control circuit 212 generates a transfer start pulse DX and a clock signal CLX from the vertical scanning signal Vs, the horizontal scanning signal Hs, and the dot clock signal DCLK supplied from the host device, and controls the horizontal scanning by the block selection circuit 140. At the same time, a transfer start pulse DY and a clock signal CLY are generated to control vertical scanning by the scanning line driving circuit 130.
Further, as shown in FIG. 6, the scanning control circuit 212 synchronizes the reference pulse Ref having a pulse width that is a half value of the clock signal CLX with the period in which the clock signal CLX is at the H level in the horizontal blanking period. One shot is generated and supplied to the monitor signal line 173 of the panel 100.
Further, as shown in FIG. 6, the scan control circuit 212 becomes L level in a transitional period including the timing at which the logic level of the clock signal CLX transitions in the horizontal effective display period, and in other periods, that is, A signal that becomes H level while the logic level of the clock signal CLX is stable is generated as the enable signal Enb, and the supply path of the enable signal Enb is the same with the reference pulse Ref generated during the horizontal blanking period as the monitor pulse Ma. That is, the monitor pulse Ma and the enable signal Enb are combined and supplied to the pulse signal line 143 of the panel 100 as the signal Ma / Enb.

Note that the scan control circuit 212 also controls the phase expansion operation and the polarity inversion operation in the data signal supply circuit 300 in accordance with the control of the vertical scan and the horizontal scan.
As described above, the scanning control circuit 212 controls the vertical scanning and the horizontal scanning of the panel 100. However, the scanning control circuit 212 does not perform real-time control at the timing coincident with the image data Vid supplied from the host apparatus, but 6 for the image data Vid. Control is performed at a timing delayed by the amount of pixels. As will be described later, in this embodiment, the reason is that in the correction circuit group 320, the image data Vd1e to Vd6e are output at a timing delayed from the image data Vd1d to Vd6d by 6 pixels of the image data Vid. Therefore, it is necessary to synchronize with this output timing.

  The data conversion circuit 214 calculates data dθ indicating the delay amount of the sampling signals S1, S2, S3,..., Sn with respect to the data signals Vid1 to Vid6 from the pulse state of the monitor signal Det supplied from the panel 100, Each correction circuit 3200 is supplied.

Next, details of the correction circuit group 320 (correction circuit 3200) will be described with reference to FIG. As described above, the correction circuit group 320 includes the correction circuit 3200 for each channel, and the correction circuits have the same configuration. Therefore, the correction circuit 3200 will be described by taking an example of correcting the channel 1, that is, the image data Vd 1 d.
In FIG. 4, the image data Vd1d phase-expanded by the S / P conversion circuit 310 is supplied to the addition circuit (+) of the delay circuit 3202 and the adder 3204, respectively.

Among these, the delay circuit 3202 is a period corresponding to the expansion of the time axis in phase expansion, that is, a period from input of image data Vd1d of a certain pixel subjected to phase expansion to input of image data of the next pixel. In this embodiment, the input data is delayed for a period corresponding to six pixels of the image data Vid before phase expansion, in other words, for a period corresponding to a half cycle of the clock signal CLX. The image data delayed by the delay circuit 3202 is supplied to the subtraction input terminal (−) of the adder 3204 and the addition input terminal (+) of the adder 3210, respectively.
The adder 3204 subtracts the image data Vd1d delayed by the delay circuit 3202 from the image data Vd1d converted by the S / P conversion circuit 310. Therefore, when the gradation value indicated by the delayed image data is b and the gradation value indicated by the next supplied image data is a, the calculation result by the adder 3204 is obtained from the delayed image data. This indicates the change (a−b) in the gradation value when changing to the next supplied image data.

On the other hand, the conversion table 3208 is for converting the data dθ calculated by the data conversion circuit 214 (see FIG. 1) to the coefficient k _1, for the conversion characteristics is predetermined so as follows. That is, as the conversion characteristics of the conversion table 3208, the sampling signals S1, S2, S3 the data d [theta], ..., when the delay amount of Sn is zero, coefficient _{k 1} is zero, the delay amount increases, The characteristic is set so that the coefficient k ₁ gradually increases. In the embodiment, the linear characteristic is used. However, since it is actually determined experimentally, a curved characteristic such as a quadratic function may be used.
The multiplier 3208 multiplies the calculation result by the adder 3204 by the coefficient k ₁ and supplies the result to the subtraction input terminal (−) of the adder 3210 as correction data. The adder 3210 subtracts the correction data from the delayed image data and outputs the result as corrected image data Vd1e. Here, since the multiplication result of the multiplier 3208 is indicated by k ₁ (ab), the corrected image data Vd1e is indicated by b−k ₁ (ab) in terms of gradation values. become.
Although channel 1 has been described here, correction circuits 3200 for channels 2 to 6 have the same configuration. For this reason, each of the corrected image data Vd1e to Vd6e is obtained by subtracting a correction value corresponding to a change with respect to the previous gradation value from the gradation value indicated by the image data.

Next, the operation of the electro-optical device will be described. First, it is assumed that the enable pulse Enb is not delayed with respect to the clock signal CLX.
Regarding the display operation of the electro-optical device, FIG. 5 is a timing chart for explaining vertical scanning, FIG. 6 is a timing chart for explaining horizontal scanning, and FIG. 7 shows a continuous horizontal scanning period. It is a figure which shows the example of the voltage waveform of the data signal supplied.
At the beginning of the vertical effective display period, the transfer start pulse DY is supplied to the scanning line driving circuit 130. By this supply, as shown in FIG. 5, the scanning signals G1, G2, G3,..., Gm sequentially become H level exclusively and are output to the scanning lines 112, respectively. Attention is paid to the horizontal scanning period in which G1 is at the H level. In this horizontal scanning period, positive writing is performed.

The horizontal scanning period is divided into a horizontal blanking period and a subsequent horizontal display period. In the horizontal effective display period, the image data Vid supplied in synchronization with the horizontal scanning is first distributed to 6 channels by the S / P conversion circuit 310 and expanded six times with respect to the time axis. Secondly, the distributed and expanded image data Vd1d to Vd1d are corrected to Vd1e to Vd1e by the correction circuit 3200, respectively, and thirdly converted to analog signals by the D / A conversion circuit group 330, and fourth. Further, the amplifying / inverting circuit 340 performs normal rotation with respect to the voltage Vc in correspondence with positive writing and outputs the result. For this reason, the voltages of the data signals Vid1 to Vid6 by the amplifying / inverting circuit 340 become higher than the voltage Vc as the pixels are darkened.
If the enable pulse Enb is not delayed with respect to the clock signal CLX, the delay amount of the sampling pulses S1, S2, S3,..., Sn is zero, so that the correction amount of the correction circuit 3200 is also zero. Therefore, no correction is made in this state.

On the other hand, in the horizontal effective display period in which the scanning signal G1 is at the H level, as shown in FIG. 6, the shift register 142 captures the transfer start pulse DX by the clock signal CLX and sequentially shifts the signals Sa1, Sa2, Sa3,..., San are sequentially at the H level.
Here, since it is assumed that the enable pulse Enb is not delayed with respect to the clock signal CLX, the enable pulse Enb is as shown in FIG. Therefore, the signals Sa1, Sa2, Sa3,..., San have their pulse widths that become H level reduced by the enable pulse Enb, respectively, so that the sampling signals S1, S2, S3,. Is output.

Now, in the horizontal effective scanning period in which the scanning signal G1 becomes H level, when the sampling signal S1 becomes H level, the six data lines 114 belonging to the first block from the left correspond to the data signals Vid1 to Vid6. Each thing to be sampled is sampled. The sampled data signals Vid1 to Vid6 are the pixels of the crossing lines of the scanning lines 112 in the first row counted from the top in FIG. 2 and the six data lines 114 (1st to 6th columns counted from the left). Each is applied to the pixel electrode 118.
Thereafter, when the sampling signal S2 becomes H level, the data signals Vid1 to Vid6 are sampled on the six data lines 114 belonging to the second block, respectively, and these data signals Vid1 to Vid6 are 1 This is applied to the pixel electrode 118 of the pixel that intersects the scanning line 112 in the row and the six data lines 114 (seventh to twelfth columns from the left).

  In the same manner, when the sampling signals S3, S4,..., Sn sequentially become H level, the data signals Vid1 to 6 are applied to the six data lines 114 belonging to the third, fourth,. Corresponding ones of Vid6 are sampled, and these data signals Vid1 to Vid6 are applied to the scanning electrodes 112 in the first row and the pixel electrodes 118 of the pixels that intersect the six data lines 114, respectively. . As a result, writing to all the pixels in the first row is completed.

Subsequently, a period during which the scanning signal G2 is at the H level will be described. In this embodiment, as described above, polarity inversion is performed in units of scanning lines, and thus negative polarity writing is performed in this horizontal effective display period.
On the other hand, the image data Vid designates the blackening of the pixel in the horizontal blanking period, but the data signals Vid1 to Vid6 are as shown in FIG. At the approximate center timing of the horizontal blanking period, when applied to the pixel electrode 118 of the pixel 110, the pixel is made the black of the lowest gradation from the positive voltage Vb (+) that makes the pixel the black of the lowest gradation. It switches to the negative polarity voltage Vb (-).
In addition, referring to the relationship between the voltages in FIG. 7, when the voltages Vw (−) and Vg (−) are applied to the pixel electrode 118 in the pixel 110, the pixels are set to the highest gradation white and intermediate gradation, respectively. It is a negative polarity voltage which makes it gray. On the other hand, Vw (+) and Vg (+) are positive voltages that, when applied to the electrode 118 in the pixel 110, cause the pixel to have the highest gradation white and the intermediate gradation gray, respectively. Vc (−) and Vg (−) are symmetrical with respect to Vc. As for the voltage relationship between the scanning signals G1, G2, G3,..., Gm, the L level is lower than the voltage Vb (−), and the H level of the scanning signal is higher than the voltage Vb (+).

  The operation in the horizontal effective display period in which the scanning signal G2 is at the H level is the same as the horizontal effective display period in which the scanning signal G1 is at the H level, and the sampling signals S1, S2, S3,. Thus, writing to all the pixels in the second row is completed. However, since the horizontal effective display period in which the scanning signal G2 is at the H level is negative writing, the amplifying / inverting circuit 340 distributes the signal that is distributed to 6 channels and expanded 6 times with respect to the time axis. Corresponding to negative polarity writing, the voltage Vc is inverted and output. For this reason, as shown in FIG. 7, the voltages of the data signals Vid1 to Vid6 become lower than the voltage Vc as the pixel is darkened.

In the same manner, the scanning signals G3, G4,..., Gm become H level, and writing is performed on the pixels in the third row, fourth row,. As a result, the positive polarity writing is performed for the pixels in the odd-numbered rows, and the negative polarity writing is performed for the pixels in the even-numbered rows. In this one vertical scanning period, the first to m-th rows are performed. Writing is completed over all the pixels in the row.
Note that the data signals Vid to Vid6 are supplied from the voltage Vb (+) when shifting from the horizontal effective display period of positive polarity writing to the horizontal effective display period of negative polarity writing at substantially the center timing of the horizontal blanking period. When shifting from the horizontal effective display period for negative polarity writing to the horizontal effective display period for positive polarity writing, the voltage Vb (−) is switched to the voltage Vb (+).
Further, similar writing is performed in the next one vertical scanning period, but at this time, the writing polarity with respect to the pixels in each row is switched. That is, in the next one vertical scanning period, the negative polarity writing is performed on the pixels in the odd-numbered rows, while the positive polarity writing is performed on the pixels in the even-numbered rows.
In this way, since the writing polarity for the pixels is switched every vertical scanning period, a direct current component is not applied to the liquid crystal layer 105, and deterioration of the liquid crystal layer 105 is prevented.

By the way, various signals such as the data signals Vid1 to Vid6 and the signal Ma / Enb are output from the processing circuit 50 at the same timing. Various signals are supplied from the processing circuit 50 to the panel 100 via the FPC board. Although there are differences in the copper foil pattern and the like, timing deviations caused by different paths are not a problem in the FPC board. it is conceivable that.
However, in the panel 100, since the wiring and the like are formed on the glass substrate, the resistivity and the parasitic capacitance are larger than those of the FPC substrate. Further, in the panel 100, the signal Ma / Enb and the data signals Vid1 to Vid6 have different supply paths.
For this reason, even if the timing coincides at the time of input in panel 100, a phase difference tends to occur in enable pulse Enb included in signal Ma / Enb with respect to the supply timing of data signals Vid1 to Vid6 in panel 100. Occurs.

If the phase of the enable pulse Enb is delayed with respect to the supply timing of the data signals Vid1 to Vid6 inside the panel 100 as shown in FIG. 8B, the sampling signals S1, S2, S3,. Since the timing of becoming the H level is also delayed, after the data signal corresponding to the original pixel is sampled on the data line 114, the data signal corresponding to a different pixel is sampled. For this reason, the display quality is significantly lowered.
For example, as shown in the figure, it is assumed that the sampling signals Si, S (i + 1) are delayed in the case of being indicated by the data signal Vid1 of the pixel having the gradation value a following the pixel having the gradation value b. To do. In this case, only the data signal Vid1 of the gradation value b should be sampled on the {6 (i−1) +1} th data line 114 counting from the left, but the sampling signal Si is delayed. Therefore, after sampling the data signal Vid of the gradation value a, the data signal Vid1 of the next gradation value a is also sampled, and the voltage of the data signal written to the pixel changes.
In FIG. 8A, the supply timing of the enable pulse Enb matches the supply timing of the data signals Vid1 to Vid6, and the sampling signals Si, S (i + 1), S (i + 2),. It is a figure which shows the ideal state which has not generate | occur | produced. Further, “i” here is a sign for generally describing the sampling signal, and is a positive integer satisfying 1 ≦ i ≦ n.

Therefore, in the embodiment, the phase difference detection circuit 180 detects how much the enable pulse Enb is out of phase with the supply timing of the data signals Vid1 to Vid6 in the panel 100, and the phase difference (delay amount) is data. A configuration is employed in which conversion is performed by the conversion circuit 214 and the image data Vid1 to Vid6 are corrected according to the delay amount for each channel.
Incidentally, the rise and fall timings of the enable pulse Enb do not coincide with the clock signal CLX, and the data signals Vid1 to Vid6 are also analog signals. For this reason, it is difficult to directly detect the phase shift of the enable pulse Enb with respect to the supply timing of the data signals Vid1 to Vid6.
Therefore, in the present embodiment, in the horizontal blanking period that does not contribute to display, the reference pulse Ref for half a period is synchronized with the clock signal CLX, and the monitor pulse Ma is supplied to the pulse signal line 143 to which the enable pulse Enb is supplied. And the same reference pulse Ref is also supplied to the monitor signal line 173 adjacent to the image signal line 171, and the phase difference between the monitor pulse Ma and the reference pulse Ref is detected inside the panel 100 to obtain a data signal. The phase shift of the enable pulse Enb with respect to the supply timings of Vid1 to Vid6 is indirectly detected.

  The details of this configuration will be described. When the reference pulse Ref is supplied to one input side end of the monitor signal line 173, the source of the TFT 184 which is the other end of the monitor signal line 173 has the same level as the data signals Vid1 to Vid6. There is a delay. When the monitor pulse Ma is supplied to one end of the pulse signal line 143 on the input side, one of the input ends of the AND circuit 182 that is the other end of the pulse signal line 143 has a delay comparable to that of the enable pulse Enb. Arise. Therefore, the phase difference of the enable pulse Enb with respect to the supply timing of the data signals Vid1 to Vid6 is detected by determining how much the monitor pulse Ma is shifted in the panel 100 with respect to the reference pulse Ref as follows. be able to.

For example, as shown in FIG. 9A, when the reference pulse Ref and the monitor pulse Ma coincide with each other at the input time of the panel 100, if the delay degree in the panel 100 is the same, the source of the TFT 184 The reference pulse Ref ′ that has reached 1 and the monitor pulse Ma ′ that has reached one of the input ends of the AND circuit 182 are both delayed in common by the time d ₃ . For this reason, the detection signal Det immediately after being output to the drain of the TFT 184 is delayed with respect to the reference pulse Ref and has the same pulse width (half cycle of the clock signal CLX).
The detection signal Det is fed back to the adjustment control circuit 230 in the processing circuit 50. However, at the time when the data conversion circuit 214 receives the signal (the signal Det ′ in FIG. 9), the detection signal Det is more than the waveform immediately after being output to the drain of the TFT 184. Further, it is delayed by time d ₄ . However, the pulse width is received by the data conversion circuit 214 in a stored state regardless of the delay. For this reason, the data conversion circuit 214 changes the signal Det ′ to the H level when the time (d ₃ + d ₄ ) elapses after the reference pulse Ref is sent to the panel 100, and the signal Det ′ (the H level). If the pulse width is equal to the pulse width of the reference pulse Ref (half cycle of the clock signal CLX), the enable pulse Enb is not out of phase (delayed) with respect to the data signals Vid1 to Vid6 in the panel 100. No).
Note that the times d ₃ and d ₄ are values inherent to the panel and are values that do not vary depending on the environment or the like. Therefore, the delay time is experimentally obtained and stored, and the data conversion circuit 214 stores it at the time of determination. A configuration using values may be used.
In addition, as described above, when the scanning control circuit 212 notifies that the reference pulse Ref has been output, the data conversion circuit 214 changes the state of the signal Det ′ from time (d ₃ + d ₄ ) after receiving the notification. Judgment can be made at the time.

On the other hand, if the enable pulse Enb is delayed in phase with respect to the data signals Vid1 to Vid6 in the panel 100, the monitor pulse Ma ′ further increases with respect to the reference pulse Ref ′ as shown in FIG. 9B. Delay. For this reason, the front end portion of the pulse width at which the detection signal Det immediately after being output to the drain of the TFT 184 becomes H level is shorter than the reference pulse Ref ′ by the delayed monitor pulse Ma ′. Thereafter, the detection signal Det is delayed by time d ₄ and received by the data conversion circuit 214 in a state where the pulse width is preserved. For this reason, if the signal Det ′ is at the L level when the time (d ₃ + d ₄ ) has elapsed since the reference pulse Ref was sent to the panel 100, the data conversion circuit 214 has the phase of the enable pulse Enb in the panel 100. Can be determined to be delayed with respect to the data signals Vid1 to Vid6. Further, the data conversion circuit 214 determines the delay amount of the enable pulse Enb depending on how much the pulse width is shorter than the pulse width of the reference pulse Ref when the signal Det ′ becomes H level after that time. That is, the delay amount of the sampling signals S1, S2, S3,..., Sn can be obtained.
In this way, the data conversion circuit 214 determines the delay amount of the sampling signals S1, S2, S3,..., Sn with respect to the data signals Vid1 to Vid6 from the signal Det ′ indicating the phase difference between the reference pulse Ref and the monitor pulse Ma. It is obtained indirectly and supplied to the correction circuit 3200 provided for each channel as data dθ indicating the delay amount.

On the other hand, the deterioration of the display quality caused by the delay of the sampling signals S1, S2, S3,..., Sn with respect to the data signals Vid1 to Vid6 is caused in different pixels after the data signal corresponding to the original pixel is sampled as described above. This is due to the corresponding data signal being sampled. The “different pixel” here refers to a pixel corresponding to a data line corresponding to the same image signal line 171 among data lines belonging to the next selected block, and this is a phase expansion of image data. If this is the case, it is nothing but the next pixel in the same channel. That is, when attention is paid to a certain pixel, the target pixel is affected by a change in image data (data signal) of a pixel to be supplied next. Further, as the delay amount of the sampling signals S1, S2, S3,..., Sn increases, the degree of influence of the next pixel also increases.
Here, as described above, the correction circuit 3200 subtracts the correction value corresponding to the change with respect to the previous gradation value from the gradation value indicated by the image data Vd1d to Vd6d, respectively, to obtain the image data. Output as Vd1e to Vd6e. During this correction coefficient k ₁ is set to the characteristic, such as increased as the delay amount indicated by the data dθ increases.
Therefore, in the correction circuit 3200, when attention is paid to a certain pixel, the gradation value b of the pixel of interest is canceled by a value corresponding to the change (ab) leading to the gradation value a of the next pixel. In addition, the correction is made by subtracting {k ₁ (ab)} in advance. At the time of this correction, the coefficient k ₁ also increases as the delay amount indicated by the data dθ increases, so that it is affected by the next pixel depending on the delay amount of the sampling signals S1, S2, S3,. The point where the degree changes is also taken into consideration.

  Therefore, according to the present embodiment, even if the sampling signals S1, S2, S3,..., Sn are delayed with respect to the data signals Vid1 to Vid6, the image data Vd1d to Vd6d ( Since the data signals Vid1 to Vid6) are corrected, it is possible to appropriately cope with environmental changes such as individual differences and temperature.

In the above-described embodiment, the correction amount is determined based on the change in the gradation value and the delay amount. However, although the degree of ghost is small in the initial period of the horizontal scanning period, it is toward the later stage of the horizontal scanning period. Tend to grow gradually. Therefore, as shown in FIG. 10, the output side of the conversion table 3208 and the input side of the multiplier 3208, with interposing a multiplier 3210 supplies the coefficients k _2, from the initial period to the final period of the horizontal scanning period toward, it may be configured and supplied so as to increase the coefficient k ₂ gradually.
In the embodiment, only the configuration for correcting the image data is used. However, the enable signal Enb, the clock signal CLX (transfer start pulse DX), and the data are arranged in a direction to eliminate the phase difference of the enable pulse Enb with respect to the data signals Vid1 to Vid6. A configuration in which the supply timing of any of the signals Vid1 to Vid6 is appropriately adjusted may be combined.

In the embodiment, the detection monitor pulse Ma is included in the signal Ma / Enb, but the transfer start pulse DX may be supplied to the monitor signal line 173 as the monitor pulse Ma. However, when substituting with the transfer start pulse DX, it is necessary to change the configuration so that a certain amount of time is required after the transfer start pulse DX is supplied until the enable pulse Enb is supplied.
Further, instead of indirectly detecting the shift amount of the enable pulse Enb with respect to the data signals Vid1 to Vid6, for example, a detection dummy signal is inserted into the data signals Vid1 to Vid6 in the blanking period, and synchronized with the dummy signal. The detection enable pulse may be generated, and the dummy signal for detection and the detection enable pulse may be supplied to the panel 100 to directly detect the delay in the panel 100.

In the above-described embodiment, the image data Vid is expanded into the image data Vd1d to Vd6d of 6 channels. However, the number of channels to be expanded is not limited to “6”. Further, the configuration is not limited to the phase expansion, and a dot sequential method may be used. Furthermore, the present invention can be applied even if the sampling signal is not narrowed by the enable pulse Enb.
On the other hand, in the above-described embodiment, the data signal supply circuit 300 processes the digital image signal Vid. However, the data signal supply circuit 300 may be configured to process an analog image signal. Further, in the data signal supply circuit 300, the analog conversion is performed after the S / P expansion. However, if the final output is the same analog signal, the S / P expansion may be performed after the analog conversion. .

Furthermore, in the above-described embodiment, the description has been given of the normally white mode in which white display is performed when the effective voltage value between the counter electrode 108 and the pixel electrode 118 is small. However, the normally black mode in which black display is performed may be used. good.
In the above-described embodiment, the TN type is used as the liquid crystal. However, a bistable type having a memory property such as a BTN (Bi-stable Twisted Nematic) type or a ferroelectric type, a polymer dispersed type, or a molecular length A dye (guest) having anisotropy in the absorption of visible light in the axial direction and the minor axis direction is dissolved in a liquid crystal (host) having a certain molecular arrangement, and the dye molecule is arranged in parallel with the liquid crystal molecule (GH) A guest-host type liquid crystal may be used.
In addition, the liquid crystal molecules are arranged in a vertical direction with respect to both substrates when no voltage is applied, while the liquid crystal molecules are arranged in a horizontal direction with respect to both substrates when a voltage is applied. The liquid crystal molecules are aligned in the horizontal direction with respect to both substrates when no voltage is applied, while the liquid crystal molecules are aligned in the vertical direction with respect to both substrates when a voltage is applied. It is good also as a structure. As described above, the present invention can be applied to various liquid crystal and alignment methods.
Although the liquid crystal device has been described above, in the present invention, for example, an EL (Electronic Luminescence) element, an electron emission element, an electric emission element, and the like can be used as long as image data (video signal) is supplied via the image signal line 171. The present invention can also be applied to an apparatus using an electrophoretic element, a digital mirror element, or a plasma display.

<Electronic equipment>
Next, a projector using the panel 100 described above as a light valve will be described as an example of an electronic apparatus using the electro-optical device according to the embodiment described above.
FIG. 11 is a plan view showing the configuration of the projector. As shown in this figure, a projector 2100 is provided with a lamp unit 2102 composed of a white light source such as a halogen lamp. The projection light emitted from the lamp unit 2102 is separated into three primary colors of R (red), G (green), and B (blue) by three mirrors 2106 and two dichroic mirrors 2108 arranged inside. Are guided to the light valves 100R, 100G and 100B corresponding to the respective primary colors. Note that B light has a longer optical path than other R and G colors, and therefore, in order to prevent the loss, B light passes through a relay lens system 2121 including an incident lens 2122, a relay lens 2123, and an exit lens 2124. Led.

Here, the configuration of the light valves 100R, 100G, and 100B is the same as that of the panel 100 in the above-described embodiment, and image signals corresponding to the R, G, and B colors supplied from the processing circuit (not shown in FIG. 11). Are driven respectively.
The lights modulated by the light valves 100R, 100G, and 100B are incident on the dichroic prism 2112 from three directions. In the dichroic prism 2112, the R and B light beams are refracted at 90 degrees, while the G light beam travels straight. Therefore, after the images of the respective colors are combined, a color image is projected onto the screen 2120 by the projection lens 2114.

  Since light corresponding to the primary colors R, G, and B is incident on the light valves 100R, 100G, and 100B by the dichroic mirror 2108, it is not necessary to provide a color filter. In addition, the transmission images of the light valves 100R and 100B are projected after being reflected by the dichroic prism 2112, whereas the transmission image of the light valve 100G is projected as it is, so the horizontal scanning direction by the light valves 100R and 100B is The left-right reversed image is displayed in the direction opposite to the horizontal scanning direction by the light valve 100G.

  In addition to the electronic device described with reference to FIG. 11, the direct view type, for example, a mobile phone, personal computer, television, video camera monitor, car navigation device, pager, electronic notebook, calculator, word processor , Workstations, videophones, POS terminals, digital still cameras, devices equipped with touch panels, and the like. Needless to say, the electro-optical device according to the present invention is applicable to these various electronic devices.

1 is a block diagram illustrating a configuration of an electro-optical device according to an embodiment of the invention. FIG. It is a figure which shows the structure of the panel in the same electro-optical apparatus. It is a figure which shows the structure of the pixel in the panel. It is a figure which shows the structure of the correction circuit for 1 channel in the same electro-optical apparatus. 6 is a timing chart for explaining a display operation of the electro-optical device. 6 is a timing chart for explaining a display operation of the electro-optical device. FIG. 6 is a diagram for explaining a display operation of the electro-optical device. FIG. 6 is a diagram for explaining a delay of a sampling signal in the same electro-optical device. FIG. 6 is a diagram for explaining a relationship between an enable pulse and a detection pulse in the same electro-optical device. It is a figure which shows another structure of the correction circuit in the same electro-optical apparatus. FIG. 3 is a diagram illustrating a configuration of a projector as an example of an electronic apparatus to which the electro-optical device is applied.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 100 ... Panel, 130 ... Scan line drive circuit, 142 ... Shift register, 143 ... Pulse signal line, 144 ... AND circuit, 150 ... Sampling switch, 171 ... Image signal line, 173 ... Monitor signal line, 212 ... Scan control circuit, 214 ... Data conversion circuit, 2100 ... Projector

Claims (6)

A pixel which is provided corresponding to each intersection of the plurality of scanning lines and the plurality of data lines, and has a gradation corresponding to the data signal sampled on the data line when the scanning line and the data line are selected; ,
A scanning line driving circuit for selecting the scanning line;
A shift register that sequentially generates a pulse signal for selecting the data line over a period in which the scanning line is selected;
A logic circuit for generating a sampling signal from the pulse signals respectively generated by the shift register;
A sampling circuit that samples a data signal supplied via an image signal line on the data line in accordance with the sampling signal;
Detecting a delay amount of the sampling signal with respect to a data signal supplied via the image signal line;
Serial image data designating the gradations of a plurality of pixels is converted into parallel image data and distributed to a plurality of channels. For each channel, the distributed image data and the distributed image data are next. together determine the amount of change between the distributed image data, to the change amount, is calculated as a correction value by multiplying a coefficient corresponding to the detection result of the delay, the picture Zode over data by the correction value To correct
Before Kiho Tadashisa the image data, the image signal processing method for an electro-optical device, characterized in that by converting the data signal supplied to the image signal lines. The image signal processing method of the electro-optical device according to claim 1, wherein the coefficient is increased as the detected delay amount increases. The image signal processing method for an electro-optical device according to claim 1, wherein the coefficient is increased as time elapses from an initial period in which the scanning line is selected. The data lines are divided into blocks, and the image signal lines are the same number as the blocks,
A plurality of data lines of the same block are selected substantially simultaneously by the sampling signal,
The image signal processing method for an electro-optical device according to claim 1, wherein image signals supplied to different image signal lines are sampled. A pixel which is provided corresponding to each intersection of the plurality of scanning lines and the plurality of data lines, and has a gradation corresponding to the data signal sampled on the data line when the scanning line and the data line are selected; ,
A scanning line driving circuit for selecting the scanning line;
A shift register that generates a pulse signal for selecting the data line over a period in which the scan line is selected;
A logic circuit for generating a sampling signal from the pulse signals respectively generated by the shift register;
A sampling circuit for sampling a data signal supplied via an image signal line on the data line according to the sampling signal;
A detection circuit for detecting a delay amount of the sampling signal with respect to a data signal supplied via the image signal line;
A conversion circuit that converts serial image data specifying gradations of a plurality of pixels into parallel image data and distributes the image data to a plurality of channels;
For each channel, a change between the distributed image data and the image data distributed next to the distributed image data is obtained, and the change is determined in accordance with the detection result of the delay amount. A correction circuit that multiplies a coefficient to calculate a correction value and corrects the image data by the correction value;
An electro-optical device comprising: a data signal supply circuit that converts the image data corrected by the correction circuit into the data signal and supplies the data signal to the image signal line.   An electronic apparatus comprising the electro-optical device according to claim 5.

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