JP4551588B2 - Imaging apparatus and imaging system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an image pickup apparatus and an image pickup system, and more particularly to an image pickup apparatus and an image pickup system that can output by adding outputs from two or more pixels.
[0002]
[Prior art]
In addition to the standard operation of reading all pixels, some imaging devices are required to have a method capable of reading at a high frame rate (speed) even when the resolution is reduced. In this case, there is a method of scanning by thinning out pixels, but in this case, information on the skipped pixels is discarded, which is disadvantageous in terms of sensitivity. Therefore, a method has been proposed in which outputs from pixels are added in an imaging region and read out as an addition signal, and a signal is read out at a high frame rate.
[0003]
FIG. 13 is a schematic configuration diagram illustrating an example of an addition method between pixels in the imaging region of the imaging apparatus. In the imaging device shown in FIG. 13, an addition switch is arranged between arranged pixels (in the figure, one pixel is indicated by ■), and a decoder (indicated by □ in the figure) is used to control each addition switch. Is provided for each addition switch. Further, in order to control each decoder, a plurality of control lines CL are extended in the imaging apparatus, and each addition switch is individually turned on / off by controlling each decoder in the addition mode of the imaging apparatus.
[0004]
[Problems to be solved by the invention]
However, providing an addition switch as shown in FIG. 13 between each pixel and providing a switch control means such as a decoder or a control line for each addition switch causes an increase in the area occupied by the imaging region. Become.
[0005]
[Means for Solving the Problems]
The imaging apparatus of the present invention includes a plurality of arranged pixels,
First switch means for commonly connecting the predetermined number of pixels to add and read signals of the predetermined number of pixels of the plurality of pixels;
A second for commonly connecting the plurality of first pixel groups in order to add and read signals of the plurality of first pixel groups each including the predetermined number of pixels and the first switch means. Switch means,
Control means for controlling on or off of the first switch means and for controlling on or off of the second switch means;
Have
When the second pixel group includes the plurality of first pixel groups and the second switch means,
The control means turns off the first and second switch means when reading signals from the plurality of pixels, respectively, and adds the signals in the first pixel group when reading signals. When the first switch means is turned on and the second switch means is turned off, and the signals in the second pixel group are added and read, the first and second switch means are turned on. It is characterized by controlling.
[0006]
The imaging system of the present invention is characterized by comprising an imaging apparatus of the present invention, a signal processing circuit for processing signals from the image pickup device.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0008]
(First embodiment)
FIG. 1 is a schematic configuration diagram showing a first embodiment of an imaging apparatus of the present invention. Here, 8 × 8 pixels are shown. A11 to A88 denote pixels, S1 to S8 denote control lines for controlling the addition switch (SW), CL denotes a plurality of addition mode control lines, and 11 to 18 denote decoders. 2A to 2C are configuration diagrams showing the configuration of one pixel. 3A to 3D are conceptual diagrams showing a 4-pixel addition state, a 16-pixel addition state, a 64-pixel addition state, and a 256-pixel addition state, respectively.
[0009]
As shown in FIG. 3A, in the case of 4-pixel addition, the control lines S1, S3, S5, and S7 shown in FIG. Pixels are connected in common on a pixel basis. For example, in the area A shown in FIG. 3A, the pixels A11, A12, A21, and A22 are connected in common and signals are added.
[0010]
As shown in FIG. 3B, in the case of 16 pixel addition, the control lines S1, S2, S3, S5, S6, and S7 shown in FIG. Thus, the pixels are commonly connected in units of 16 pixels. For example, in the area B shown in FIG. 3B, the pixels A11 to A14, A21 to A24, A32 to A34, and A41 to A44 are connected in common and the signals are added.
[0011]
As shown in FIG. 3 (c), in the case of 64 pixel addition, the control lines S1 to S7 and S9 to S15 (S9 to S15 are not shown) shown in FIG. The switch is turned on, and the pixels are commonly connected in units of 64 pixels. For example, in the area C shown in FIG. 3C, the pixels A11 to A88 are connected in common and signals are added.
[0012]
As shown in FIG. 3D, in the case of 256 pixel addition, the control lines S1 to S15 and S17 to S1 (S9 to S17 are not shown) shown in FIG. The switch is turned on and the pixels are connected in common in units of 256 pixels.
[0013]
In this embodiment, if the area A shown in FIG. 3A is a first pixel group (four pixels and three addition switches), the second pixel group is shown in FIG. The region B shown and the third pixel group are the region C shown in FIG. If the area B shown in FIG. 3B is the first pixel group (16 pixels and 15 addition switches), the second pixel group is the area C shown in FIG. .
[0014]
The above-described addition method will be described with reference to FIGS. 4A to 4D. In the case of 4-pixel addition, as shown in FIG. Are added using three addition switches. The addition pixel unit here is the addition region A. Next, in the case of 16 pixel addition, as shown in FIG. 4B, the four addition regions A to which four pixels are added are added using three addition switches. The addition pixel unit here is the addition region B. Next, in the case of 64 pixel addition, as shown in FIG. 4C, the four addition regions B to which 16 pixels are added are added using three addition switches.
The addition pixel unit here is the addition region C. Next, in the case of 256 pixel addition, as shown in FIG. 4D, the four addition regions C to which 64 pixels are added are added using three addition switches. The addition pixel unit here is the addition region D. As can be understood from FIGS. 4A to 4D, in this embodiment, four pixels or addition regions are connected by turning on three addition switches.
[0015]
Next, the configuration of one pixel will be described with reference to FIGS. As shown in FIG. 2A, the cathode side of the photodiode PD is connected to the first amplifier Amp1, and the switch constituting the sample hold circuit is connected to the output side of the first amplifier Amp1 (this switch is a sample / hold signal). (A sampling switch controlled by (S / H).), A capacitor C is connected, and the capacitor C is connected to the second amplifier Amp2. The output of the second amplifier Amp2 is output to the vertical output line SL via a switch controlled by the control signal G. For example, as shown in FIG. 2B, the first amplifier Amp1 includes a source follower circuit including a MOS transistor M1 and a current source I1. For example, as shown in FIG. 2C, the second amplifier Amp2 and the switch (selection switch) are connected to the MOS transistor M2 and its drain side (controlled by the control signal G applied to the control line GL). ) It is composed of a MOS transistor M3. The addition of pixels is performed by connecting the capacitances C of the pixels with an addition switch (SW). The charges accumulated in the capacitance C are added, and in other words, the average value of the potential can be output. it can.
[0016]
The pixel addition reading operation has been described above, but the operation of reading the output from all the pixels can be performed by turning off all the addition switches.
[0017]
(Second Embodiment)
In the first embodiment described above, the case where the decoder for controlling the addition switch for adding the pixels is provided separately from the scanning circuit for reading the signal from the pixel is shown. In the present embodiment, an example will be described in which an addition switch for adding pixels is controlled using a signal from a scanning circuit such as a shift register for reading a signal from the pixel.
[0018]
FIG. 5 is a schematic configuration diagram showing a second embodiment of the imaging apparatus of the present invention. In FIG. 5, Sw1 to Sw8 are signals for controlling the addition switches, and G1 to G8 are signals for performing control to output signals from the pixel groups arranged in one direction, respectively. Each of the signals G1 to G8 is applied to, for example, the control line GL shown in FIG. FIG. 6 is a diagram showing a circuit for outputting a signal for controlling the addition switch and the pixel selection switch. FIG. 7 is a diagram showing a logical operation circuit and its truth table.
[0019]
8 is a timing chart in the all-pixel readout mode, FIG. 9 is a timing chart in the 4-pixel addition mode, FIG. 10 is a timing chart in the 16-pixel addition mode, and FIG. 11 is in the 64-pixel addition mode. It is a timing chart.
[0020]
As shown in FIG. 6, a circuit for outputting a signal for controlling the addition switch and the pixel selection switch includes a shift register for outputting signals Q1 to Q8 and a logical operation circuit. The logic operation circuit is composed of the logic gate 1 shown in FIG. 7A and the logic gate (AND gate) shown in FIG. 7B, and the input sides of the logic gates 1 and 2 output the shift register signals Q1 to Q8, respectively. The control signals G1 to G8 are output from the output side of the logic gate 1, and the control signals Sw1 to Sw8 are output from the output side of the logic gate 2. OE is a signal for controlling on / off of the output of the shift register.
[0021]
In the all-pixel readout mode shown in FIG. 8, since the clock CLK is operated with only one pulse when SIN is at a high level, the control signals G1 to G8 are sequentially increased in accordance with the signals Q1 to Q8 output from the shift register. Since the control signals Sw1 to Sw8 are all held at a low level and all the addition switches are turned off, a signal is output from each pixel to the vertical output line for each pixel row.
[0022]
In the 4-pixel addition mode shown in FIG. 9, since two pulses of the clock CLK are input when SIN is at a high level, two shift pulses are generated inside the shift register. Two pulses of signals Q1 and Q2, Q3 and Q4,... Are simultaneously output from the shift register, and the control signals G2, G4, G6, and G8 are at a high level according to this pulse, and the control signals Sw1, Sw3, Sw5, and Sw7 are output. Becomes a high level, and the addition switches controlled by the control signals Sw1, Sw3, Sw5, and Sw7 are turned on, so that the four-pixel addition process as shown in FIG. 3A is performed. For example, FIG. ) Of pixels in the area A is output.
[0023]
In the 16-pixel addition mode shown in FIG. 10, since four pulses of the clock CLK are input when SIN is at a high level, four shift pulses are generated inside the shift register. From the shift register, signals Q1 to Q4 and Q5 to Q8 and 4 pulses are simultaneously output. In accordance with this pulse, the control signals G4 and G8 are at a high level, the control signals Sw1 to Sw3 and Sw5 to Sw7 are at a high level, and the control signal Sw1 Since the addition switches controlled by -Sw3 and Sw5-Sw7 are turned on, a 16-pixel addition process as shown in FIG. 3B is performed, for example, the pixels in the region B in FIG. The addition (average) value is output.
[0024]
In the 64-pixel addition mode shown in FIG. 11, since eight pulses of the clock CLK are input when SIN is at a high level, eight shift pulses are generated inside the shift register. Eight pulses of signals Q1 to Q8 are simultaneously output from the shift register, and in accordance with this pulse, the control signal G8 becomes high level, the control signals Sw1 to Sw7 become high level, and the addition switch controlled by the control signals Sw1 to Sw7 is turned on. Therefore, the 64 pixel addition process as shown in FIG. 3C is performed, and for example, the addition (average) value of the pixels in the region C in FIG. 3C is output.
[0025]
In the embodiment described above, the first pixel group is configured and arranged by 4 (a = 4) pixels arranged and 3 (a-1 = 3) first switch means. 4 (b = 4) first pixel groups and 3 (b-1 = 3) second switch means constitute a second pixel group and are arranged 4 (c = 4) Taking as an example the case where the third pixel group is composed of the second pixel group and 3 (b−1 = 3) third switch means, 4-pixel addition, 16-pixel addition, and 64-pixel addition However, the number of pixels or pixel groups is not limited to four, and may be two, three, five or more pixels or pixel groups.
[0026]
Next, an imaging system using the imaging device will be described. Based on FIG. 12, an embodiment when the imaging apparatus of the present invention is applied to a still camera will be described in detail.
[0027]
FIG. 12 is a block diagram showing a case where the imaging apparatus of the present invention is applied to a “still video camera”.
[0028]
In FIG. 12, 101 is a barrier that serves as a lens switch and a main switch, 102 is a lens that forms an optical image of a subject on an image sensor (imaging device) 104, and 103 is a diaphragm for varying the amount of light that passes through the lens 102. , 104 is an image sensor for capturing the subject imaged by the lens 102 as an image signal, 106 is an A / D converter that performs analog-digital conversion of the image signal output from the image sensor 104, and 107 is an A / D converter. A signal processing unit 108 performs various corrections on the image data output from the converter 106 and compresses the data. The image processing unit 108 includes an image sensor 104, an image signal processing circuit 105, an A / D converter 106, and a signal processing unit 107. Timing generator for outputting timing signals, 109 is an overall control / arithmetic unit for controlling various calculations and the entire still video camera 110 is a memory unit for temporarily storing image data, 111 is an interface unit for performing recording or reading on a recording medium, and 112 is a removable recording such as a semiconductor memory for recording or reading image data. A medium 113 is an interface unit for communicating with an external computer or the like.
[0029]
Next, the operation of the still video camera at the time of shooting in the above configuration will be described.
[0030]
When the barrier 101 is opened, the main power supply is turned on, the control system power supply is turned on, and the power supply of the imaging system circuit such as the A / D converter 106 is turned on.
[0031]
Then, in order to control the exposure amount, the overall control / arithmetic unit 109 opens the aperture 103, and the signal output from the image sensor 104 is converted by the A / D converter 106 and then input to the signal processing unit 107. Is done. Based on this data, exposure calculation is performed by the overall control / calculation unit 109.
[0032]
The brightness is determined based on the result of the photometry, and the overall control / calculation unit 109 controls the aperture according to the result.
[0033]
Next, based on the signal output from the image sensor 104, the high-frequency component is extracted and the distance to the subject is calculated by the overall control / calculation unit 109. Thereafter, the lens is driven to determine whether or not it is in focus. If it is determined that the lens is not in focus, the lens is driven again to perform distance measurement.
[0034]
Then, after the in-focus state is confirmed, the main exposure starts. When the exposure ends, the image signal output from the image sensor 104 is A / D converted by the A / D converter 106, passes through the signal processing unit 107, and is written in the memory unit by the overall control / calculation 109. Thereafter, the data stored in the memory unit 110 is recorded on a removable recording medium 112 such as a semiconductor memory through the recording medium control I / F unit under the control of the overall control / arithmetic unit 109. Alternatively, the image may be processed by directly entering a computer or the like through the external I / F unit 113.
[0035]
【The invention's effect】
As described above, according to the present invention, the area occupied by the imaging region can be reduced.
[Brief description of the drawings]
FIG. 1 is a schematic configuration diagram showing a first embodiment of an image sensor of the present invention.
FIGS. 2A to 2C are configuration diagrams showing the configuration of one pixel.
FIGS. 3A to 3D are conceptual diagrams showing a 4-pixel addition state, a 16-pixel addition state, a 64-pixel addition state, and a 256-pixel addition state, respectively.
FIGS. 4A to 4D are explanatory diagrams for explaining an addition method. FIG.
FIG. 5 is a schematic configuration diagram showing a second embodiment of the image sensor of the present invention.
FIG. 6 is a diagram illustrating a circuit for outputting a signal for controlling an addition switch and a pixel selection switch.
FIG. 7 is a diagram showing a logical operation circuit and its truth table.
FIG. 8 is a timing chart in the all-pixel readout mode.
FIG. 9 is a timing chart in the case of a 4-pixel addition mode.
FIG. 10 is a timing chart in the case of 16-pixel addition mode.
FIG. 11 is a timing chart in the case of a 64-pixel addition mode.
FIG. 12 is a block diagram showing a case where the imaging apparatus of the present invention is applied to a still video camera.
FIG. 13 is a schematic configuration diagram illustrating an example of an addition method between pixels in an imaging region of an imaging element.
[Explanation of symbols]
A11 to A88 Pixels S1 to S8 Addition switch (SW) control line CL Multiple addition mode control lines

Claims (9)

A plurality of arranged pixels;
First switch means for commonly connecting the predetermined number of pixels to add and read signals of the predetermined number of pixels of the plurality of pixels;
A second for commonly connecting the plurality of first pixel groups in order to add and read signals of the plurality of first pixel groups each including the predetermined number of pixels and the first switch means. Switch means,
Control means for controlling on or off of the first switch means and for controlling on or off of the second switch means;
Have
When the second pixel group includes the plurality of first pixel groups and the second switch means,
The control means turns off the first and second switch means when reading signals from the plurality of pixels, respectively, and adds the signals in the first pixel group when reading signals. When the first switch means is turned on and the second switch means is turned off, and the signals in the second pixel group are added and read, the first and second switch means are turned on. An imaging device characterized by controlling. 2. The imaging apparatus according to claim 1, wherein pixels included in the first pixel group are connected in common by a number of the first switch means that is one less than the predetermined number. The plurality of first pixel groups included in the second pixel group are shared by the number of the second switch means which is one less than the number of the first pixel groups included in the second pixel group. The imaging device according to claim 1, wherein the imaging device is connected to the imaging device. 4. The pixel according to claim 1, wherein the pixel includes a photodiode and a capacitor for storing a signal from the photodiode, and the first and second switch means are means for controlling connection between the capacitors. The imaging device according to item. A third switch means for commonly connecting the plurality of second pixel groups for adding and reading signals of the plurality of second pixel groups;
When the third pixel group includes the plurality of second pixel groups and the third switch means,
The control means turns on the third switch means or turns on the first, second and third switch means when adding and reading the signals in the third pixel group. The imaging apparatus according to claim 1, further comprising controlling off. A plurality of the second pixel groups included in the third pixel group are shared by the number of the third switch means which is one less than the number of the second pixel groups included in the third pixel group. The imaging device according to claim 5, wherein the imaging device is connected to the imaging device. The imaging apparatus according to claim 5, wherein the third switch unit is a unit that controls connection between the capacitors. The imaging apparatus according to claim 5, further comprising a plurality of control lines connected to any one of the first, second, and third switch means. Imaging system comprising: the imaging apparatus according to any one of claims 1 to 8, and a signal processing circuit for processing signals from the image pickup device.

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