JP4547726B2 - Liquid crystal display device, driving method thereof, and liquid crystal display system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a liquid crystal display device, a driving method thereof, and a liquid crystal display system, and more particularly, to a dot sequential driving type active matrix liquid crystal display device, a driving method thereof, and a liquid crystal display system using the liquid crystal display device.
[0002]
[Prior art]
In an active matrix liquid crystal display device, a thin film transistor (TFT) is usually used as a switching element for each pixel. An example of the configuration of this active matrix TFT liquid crystal display device is shown in FIG. Here, for the sake of simplicity, the case of a pixel array of 4 rows and 4 columns is shown as an example.
[0003]
In FIG. 7, pixels 101 are arranged in a matrix at intersections of the gate lines Vg1 to Vg4 and the signal lines sig1 to sig4. The pixel 101 includes a thin film transistor TFT having a gate electrode connected to the gate lines Vg1 to Vg4 and a source electrode (or drain electrode) to the signal lines sig1 to sig4, and a drain electrode (or source electrode) of the thin film transistor TFT. And a storage capacitor Cs to which one electrode is connected. Here, the liquid crystal cell LC is omitted for simplification of the drawing. The pixel electrode of the liquid crystal cell LC is connected to the drain electrode of the thin film transistor TFT.
[0004]
In this pixel structure, the counter electrode of the liquid crystal cell LC (not shown) and the other electrode of the storage capacitor Cs are connected to the Cs line 102 in common between the pixels. A predetermined DC voltage is applied as a common voltage Vcom to the counter electrode of the liquid crystal cell LC (not shown) and the other electrode of the storage capacitor Cs via the Cs line 102.
[0005]
The scan driver 103 performs a process of sequentially scanning the gate lines Vg1 to Vg4 every one vertical period (one field period) to select the pixels 101 in units of rows. On the other hand, the source driver 104 sequentially samples, for example, video signals video1 and video2 input in two systems every one horizontal period (1H), and writes the pixel signals 101 in the row selected by the scan driver 103. .
[0006]
In the source driver 104, specifically, sampling switches sw1 to sw4 are alternately arranged between the signal lines sig1 to sig4 of the pixel portion and the input signal lines 105-2 and 105-1 of the video signals video2 and 1, respectively. The sampling switches sw1 to sw4 are paired in pairs so that they are sequentially turned on in response to sampling pulses Vh1 and Vh2 sequentially output from the transfer stages 106-1 and 106-2 of the shift register. It has become.
[0007]
In the active matrix TFT liquid crystal display device having the above-described configuration, a dot sequential driving method is known in which each pixel is sequentially driven in units of pixels for each line (one row). When performing this dot-sequential driving, in the 1H inversion driving method, the sampling switches sw1 to sw4 are turned on dot-sequentially by sampling pulses Vh1 and Vh2 in the horizontal 1 line, and as shown in FIG. video1 and video2 have the same polarity) are written to each pixel 101 via each signal line sig1 to sig4. As a result, as shown in FIG. 9, video signals having the same polarity (+/−) are written to adjacent left and right pixels.
[0008]
By the way, the resistance component RCs exists between the left and right pixels adjacent to each other in the Cs line 102, and further, the parasitic capacitance c1 exists between the Cs line 102 and the signal lines sig1 to sig4. Since the differentiation circuit is formed by the holding capacitor Cs and the parasitic capacitance c1, when the video signals video1 and video2 are written, the video signal video1, video1 is supplied to the Cs line 102 and the gate lines Vg1 to Vg4 via the holding capacitor Cs and the parasitic capacitance c1. 2 will jump in.
[0009]
As a result, as shown in FIG. 8, the potential VCs of the Cs line 102 fluctuates in the direction of the same polarity as the video signals video1 and video2 (ΔVCs). Therefore, the horizontal crosstalk shown in FIG. (Simply abbreviated) or shading failure, and the image quality is greatly impaired. In FIG. 10, if the portion indicated by the black area is the actual image 111 that is actually displayed, a false image (portion indicated by the dotted area) 112 is generated in the horizontal direction of the actual image 111 due to the horizontal crosstalk.
[0010]
Further, while the pixel 101 holds the pixel information for one field period, the potential Vsig of the signal lines sig1 to sig4 fluctuates every 1H (ΔVsig). Here, in the case of the 1H inversion driving method, since the polarities of the video signals written to the adjacent left and right pixels are the same, the potential fluctuation ΔVsig of the signal lines sig1 to sig4 increases.
[0011]
In each pixel 101, parasitic capacitance is also present between the source / drain electrodes of the thin film transistor TFT and each of the signal lines sig1 to sig4. Therefore, the fluctuation ΔVsig of the potential of the signal lines sig1 to sig4 is equal to that of the thin film transistor TFT. Since it jumps into the pixel by source / drain coupling, vertical crosstalk (hereinafter, abbreviated as vertical crosstalk) becomes prominent, which causes image quality defects as with horizontal crosstalk.
[0012]
  As a driving method that does not cause the potential fluctuation ΔVCs of the Cs line 102 and the potential fluctuation ΔVsig of the signal lines sig1 to sig4, there is a dot inversion driving method. In the case of this dot inversion driving method, the two video signals video1 and video2 are input with opposite polarities (however, as in the case of the 1H inversion driving method, each polarity of the video signals video1 and video2 having the opposite polarity is every 1H. To reverse). Accordingly, when the switches sw1 and sw2 are turned on in response to the sampling pulse Vh1, the video signal video1 and the video signal video2 are simultaneously written with opposite polarities as shown in FIG.ΔVsigIs canceled between adjacent pixels, the problem of poor image quality does not occur as in the case of the 1H inversion driving method.
[0013]
[Problems to be solved by the invention]
  However, in the case of the above-described dot inversion driving method, as apparent from FIG. 12, the video signals video1 and video2 written to the adjacent left and right pixels have different polarities, and therefore are affected by the electric field of the adjacent pixels. Become. Then, as shown in FIG. 13, a domain (light leakage region) 122 is generated at the corner of the opening 121.AndSince this portion cannot be used as the opening 121, the light shielding portion 123 must be used. Therefore, the aperture ratio of the pixel is lowered and the transmittance is lowered, so that the contrast is lowered and the image quality is deteriorated.
[0014]
The present invention has been made in view of the above problems, and its object is to provide a liquid crystal capable of improving image quality defects such as lateral crosstalk and in-plane shading without reducing the aperture ratio of the pixels. It is an object to provide a display device, a driving method thereof, and a liquid crystal display system.
[0015]
[Means for Solving the Problems]
  In order to achieve the above object, in the present invention,
  A plurality of signal lines wired for each column with respect to an array of pixels arranged in a matrix and meandering wiring between two pixels above and below the pixel array, and odd numbers with respect to the pixels above and below the two lines In driving a liquid crystal display device having a plurality of gate lines alternately connected in columns and even columns,
  While sequentially selecting the plurality of gate lines,
  The polarity is reversed every horizontal period andInput video signals of opposite polarities to each other, and this reverse polarity video signalTo the pixels connected to the sequentially selected gate lines through the signal lines in units of two adjacent columns,
  In the pixel array after the video signal is written, the polarities of the pixels are the same in adjacent left and right pixels, and are opposite in the upper and lower pixels.
[0016]
By inputting video signals having opposite polarities to each other and applying video signals having opposite polarities to adjacent signal lines, the same driving as in the dot inversion driving method is performed. At this time, in the pixel arrangement after the video signal is written, the video signal is written by driving so that the polarities of the pixels are the same in the adjacent left and right pixels and reverse in the upper and lower pixels. As in the case of the 1H inversion driving method, the subsequent pixel arrangement has the same polarity in the adjacent left and right pixels.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0018]
FIG. 1 is a circuit diagram showing a configuration example of an active matrix liquid crystal display device according to an embodiment of the present invention. Here, for the sake of simplicity, the case of a pixel array of 6 rows and 4 columns is shown as an example. Note that the first and sixth rows are arranged every other column in the pixel, and have a dummy pixel arrangement in which a black signal is written without writing a video signal.
[0019]
In FIG. 1, pixels 11 for 6 rows × 4 columns are arranged in a matrix. However, only odd columns of pixels are arranged as dummy pixels for the first row, and only even columns of pixels are arranged as dummy pixels for the sixth row. Each of the pixels 11 includes a thin film transistor TFT that is a pixel transistor, and a storage capacitor Cs in which one electrode is connected to a drain electrode (or a source electrode) of the thin film transistor TFT. Here, the liquid crystal cell LC is omitted for simplification of the drawing. The pixel electrode of the liquid crystal cell LC is connected to the drain electrode of the thin film transistor TFT.
[0020]
For each of the pixels 11, signal lines sig1 to sig4 are wired along the column direction for each column. On the other hand, the gate lines Vg <b> 1 to Vg <b> 5 are arranged in a meandering manner between the pixels 11 and 11 of different lines, for example, upper and lower two lines (upper and lower two lines), not along the row direction for each row. That is, the gate line Vg1 is wired to each pixel in the first row, first column, the second row, second column, the first row, third column, and the second row, fourth column. The gate line Vg2 is wired to each pixel in the second row, the first column, the third row, the second column, the second row, the third column, and the third row, the fourth column. The gate lines Vg3, Vg4, and Vg5 are also meandered in the same manner.
[0021]
In each of the pixels 11, the source electrode (or drain electrode) of the thin film transistor TFT is connected to each of the corresponding signal lines sig 1 to sig 4, and the counter electrode of the liquid crystal cell LC (not shown) and the other electrode of the storage capacitor Cs are The pixels are connected to the Cs line 12 in common among the pixels. Here, as is apparent from FIG. 1, the Cs lines 12 are wired in a matrix. A predetermined DC voltage is supplied as a common voltage Vcom to the counter electrode of the liquid crystal cell LC (not shown) and the other electrode of the storage capacitor Cs via the Cs line 12.
[0022]
The connection relation to the gate lines Vg1 to Vg5 is as follows. That is, for the odd columns (1 column, 3 columns), the gate electrode of the thin film transistor TFT of each pixel is connected to the gate lines Vg1 to Vg5 of the corresponding row for each row (1st to 5th rows), and even columns With regard to (two columns, four columns), the gates of the thin film transistors TFT of the respective pixels are connected to the gate lines Vg1 to Vg5 in the row one row for each row (second row to sixth row).
[0023]
In the pixel portion configured as described above, one end of each of the gate lines Vg1 to Vg5 is connected to an output end of each row of the scan driver 14 which is a vertical drive circuit disposed on the left side of the pixel portion, for example. The scan driver 13 sequentially scans the gate lines Vg1 to Vg5 every one vertical period (one field period), and selects each of the pixels 11 alternately connected to the gate lines Vg1 to Vg5 between the upper and lower lines. I do.
[0024]
That is, when a scan pulse is applied from the scan driver 13 to the gate line Vg1, each pixel in the first row, first column, the second row, the second column, the first row, the third column, and the second row, the fourth column is selected. The When a scanning pulse is applied to the gate line Vg2, each pixel in the second row, first column, the third row, second column, the second row, third column, and the third row, fourth column is selected. Similarly, when a scanning pulse is applied to the gate lines Vg3, Vg4, and Vg5, pixels are alternately selected between the upper and lower lines.
[0025]
For example, a source driver 14 that is a horizontal drive circuit is disposed on the upper side of the pixel portion. For example, the source driver 14 sequentially samples the video signals video1 and video2 input in two systems for every 1H, and performs a process of writing to each pixel 11 selected by the scan driver 13. As the two systems of video signals video1 and video2, as in the case of the dot inversion driving method, video signals having opposite polarities and input to each other are input every 1H.
[0026]
The source driver 14 sequentially performs a shift operation in response to the horizontal start pulse Hst and outputs sampling pulses Vh1 and Vh2, and each signal line sig1 of the pixel unit. To sig4 and sampling signal sw1 to sw4 connected alternately to the input signal lines 16-2 and 16-1 of the video signals video2 and 1, respectively.
[0027]
In the source driver 14, two sampling switches sw1 to sw4 are paired (sw1 and sw2, sw3 and sw4), and sampling pulses are sequentially output from the transfer stages 15-1 and 15-2 of the shift register. By sequentially performing an ON operation in response to Vh1 and Vh2, video signals video2 and 1 of two systems having opposite polarities are written to each signal line sig1 to sig4 in units of two columns (two pixels). .
[0028]
Next, driving of the dot matrix driving type active matrix TFT liquid crystal display device having the above configuration will be described with reference to the timing chart of FIG. Note that in the pixel array of 6 rows × 4 columns, the address of each pixel is given as shown in FIG. Here, d represents a dummy pixel.
[0029]
First, when a scan pulse is output from the scan driver 13 to the gate line Vg1 in the first first line, the scan pulse is transmitted through the gate line Vg1 to the pixels d-1, 1-2, d-3, 1-4. Since these are applied to the gate electrodes of the thin film transistors TFT, the pixels d-1, 1-2, d-3, and 1-4 are turned on.
[0030]
Here, as in the case of the dot inversion driving method, the video signals video 1 and video 2 having opposite polarities are input through the input signal lines 16-1 and 16-2, while each transfer stage of the shift register is performed in the source driver 16. Sampling pulses Vh1 and Vh2 are output in order from 15-1 and 15-2, so that sampling switches sw1 and sw2 and sw3 and sw4 are sequentially turned on.
[0031]
Then, video signals video2 and 1 having opposite polarities are first supplied to the signal lines sig1 and sig2 through the sampling switches sw1 and sw2. Thus, the video signal video2 having a negative polarity (denoted as “−” in FIG. 3) is written into the pixel d−1, and the video signal video1 having a positive polarity (denoted as “+” in FIG. 3) is written into the pixel 1-2. Will be. However, a black signal is input as the video signal video2 at this time, and the black signal is written to the dummy pixel d-1.
[0032]
Subsequently, the video signals video2 and 1 are given to the signal lines sig3 and sig4 through the sampling switches sw3 and sw4. As a result, the negative video signal video2 is written in the pixel d-3, and the positive video signal video1 is written in the pixel 1-4. Also at this time, when the black signal is input as the video signal video2, the black signal is written to the dummy pixel d-3.
[0033]
Next, when a scan pulse is output from the scan driver 13 to the gate line Vg2 in the second line, the scan pulse is transmitted through the gate line Vg2 to the pixels 1-1, 2-2, 1-3, 2-4. Since these are applied to the gate electrode of each thin film transistor TFT, the pixels 1-1, 2-2, 1-3, and 2-4 are turned on.
[0034]
In the second line, the polarities of the video signals video1 and video2 are inverted. That is, in the first line, the video signal video1 is positive and the video signal video2 is negative. In the second line, the video signal video1 is negative and the video signal video2 is positive. In the source driver 16, the sampling pulses Vh1 and Vh2 are sequentially output again from the transfer stages 15-1 and 15-2 of the shift register, so that the sampling switches sw1 and sw2 and sw3 and sw4 are sequentially turned on in pairs. It becomes.
[0035]
Then, video signals video2 and 1 having opposite polarities are first supplied to the signal lines sig1 and sig2 through the sampling switches sw1 and sw2. As a result, the video signal video2 having a positive polarity is written in the pixel 1-1, and the video signal video1 having a negative polarity is written in the pixel 2-2. Subsequently, the video signals video2 and 1 are given to the signal lines sig3 and sig4 through the sampling switches sw3 and sw4. As a result, the video signal video2 having a positive polarity is written in the pixel 1-3, and the video signal video1 having a negative polarity is written in the pixel 2-4.
[0036]
Thereafter, the video signals video2 and 1 having opposite polarities are input with the polarity inverted every 1H, while the above-described operation is repeated so that the scan driver 13 scans in the vertical direction (row direction) and the source driver 14. Scanning in the horizontal direction (column direction) is performed. In the case of scanning with respect to the gate line Vg5, a black signal is input as the video signal video1, and the black signal is written to the dummy pixels d-2 and d-4.
[0037]
As described above, in the active matrix TFT liquid crystal display device, for example, two video signals video1 and video2 are input with opposite polarities, while the opposite polarity video signals video1 and video2 are input on different lines (in this example, up and down). 2 lines) pixels are written simultaneously, and in the pixel arrangement after writing, the polarity of the pixels is the same polarity in the adjacent left and right pixels and the opposite polarity in the upper and lower pixels as shown in FIG. -Line inversion drive is performed.
[0038]
As is apparent from the timing chart of FIG. 2, the dot-line inversion drive sequentially outputs sampling pulses Vh1 and Vh2, and when the sampling switches sw1 and sw2 and sw3 and sw4 are sequentially turned on, the dot inversion drive method Similarly to the case, since video signals video2 and 1 having opposite polarities are given to the signal lines sig1 and sig2, and sig3 and sig4, image quality defects such as horizontal crosstalk, in-plane shading, and vertical crosstalk can be improved. .
[0039]
That is, due to the presence of the resistance component RCs in the Cs line 12, the video signals video1 and video2 are passed through the parasitic capacitance c1 and the holding capacitance Cs that exist between the signal lines sig1 to 4 and the Cs line 12. Since jumping into the Cs line 12 can be canceled by applying video signals video 1 and video 2 having opposite polarities to adjacent signal lines, the potential VCs of the Cs line 12 does not fluctuate, and thus the occurrence of lateral crosstalk is suppressed. Or shading defects can be eliminated.
[0040]
Further, due to the parasitic capacitance existing between the source / drain electrodes of the thin film transistor TFT and each of the signal lines sig1 to sig4, the potential fluctuation ΔVsig for each 1H of the signal lines sig1 to sig4 is the source / drain of the thin film transistor TFT. Since jumping into a pixel by coupling can be canceled by applying video signals video1 and video2 having opposite polarities to adjacent signal lines, occurrence of vertical crosstalk can be suppressed. As a result, the video signals video1 and video2 can be written at a sufficient level, so that the contrast can be improved.
[0041]
Further, the video signals video1 and video2 having opposite polarities are not written to the pixels in one horizontal line as in the case of the dot inversion driving method, but between different horizontal lines (in this example, the upper and lower two lines). By performing every other pixel (every other column), the polarity of the pixel array becomes the same in the adjacent pixels on the left and right as in the case of the 1H inversion driving method, as is apparent from FIG. A domain (see FIG. 13) which is a problem in the case of the inversion driving method does not occur. Thereby, it is not necessary to reduce the aperture ratio of the pixel.
[0042]
In the above-described embodiment, two video signals video1 and video2 are input as video signals. However, the number of inputs is not limited to two, and may be 2n (n is an integer). Further, the video signals video1 and video2 having opposite polarities are simultaneously written to the upper and lower two lines of pixels. However, the upper and lower two lines are not necessarily required. In short, the polarities of the pixels are adjacent in the pixel array after the writing. It is only necessary to simultaneously write to pixels on different horizontal lines so that the left and right pixels have the same polarity and the upper and lower pixels have the opposite polarity.
[0043]
In the above-described embodiment, an analog video signal is input, and the case where it is applied to a liquid crystal display device equipped with an analog interface driving circuit that samples and drives each pixel dot-sequentially has been described. The same applies to a liquid crystal display device equipped with a digital interface drive circuit that takes a signal as input and converts it into an analog video signal, samples the analog video signal, and drives each pixel dot-sequentially Is possible.
[0044]
Next, a liquid crystal display system according to the present invention using the active matrix TFT liquid crystal display device of the dot sequential driving system having the above-described configuration will be described.
[0045]
FIG. 4 is a block diagram showing an example of the configuration of the liquid crystal display system according to the present invention. The liquid crystal display system includes a delay processing circuit 21, a DA converter 22, a liquid crystal panel signal driver 23, a liquid crystal panel 24, and a liquid crystal panel timing generator 25. The liquid crystal panel 24 is a dot-line according to the present invention described above. The active matrix TFT liquid crystal display device of the inversion driving method is used.
[0046]
The delay processing circuit 21 receives an odd pixel digital video signal and an even pixel digital video signal as two inputs, and delays one of the digital video signals by a time corresponding to one line for output. The DA converter 22 DA-converts an odd pixel digital video signal and an even pixel digital video signal each having a time lag corresponding to one line, and outputs a liquid crystal as an odd pixel analog video signal and an even pixel analog video signal. The signal is supplied to the panel signal driver 23.
[0047]
The liquid crystal panel signal driver 23 performs display driving for each pixel of the liquid crystal panel 24 based on the analog video signal of the odd pixels and the analog video signal of the even pixels having a time shift corresponding to one line. The liquid crystal panel 24 performs control such as horizontal scanning and vertical scanning based on various timing signals such as horizontal / vertical start pulses and horizontal / vertical clocks supplied from the liquid crystal panel timing generator 25, and outputs a video signal to each pixel. Is supposed to write.
[0048]
Here, the case where the dot matrix driving type active matrix TFT liquid crystal display device shown in FIG. 1, that is, the dot-line inversion driving type active matrix TFT liquid crystal display device shown in FIG. When writing a video signal to each pixel in the first row excluding the dummy pixel array (pixels 1-1, 1-2, 1-3, 1-4 in FIG. 3), these pixels 1-1, 1 The meandering gate lines Vg1 and Vg2 are connected to -2, 1-3, and 1-4, but it is necessary to write video signals for the same 1H period.
[0049]
However, as apparent from the above-described operation description, the odd-numbered pixel 1 is obtained by connecting the gate lines Vg1 and Vg2 meandered to the pixels 1-1, 1-2, 1-3, and 1-4. The video signals after one line are written to the even pixels 1-2 and 1-4 in -1 and 1-3. Therefore, in the case of this example, the delay processing circuit 21 delays the video signal of the even-numbered pixels by the time corresponding to one line from the video signal of the odd-numbered pixels, whereby each of the pixels 1-1 and 1 in the first row. The same 1H period video signal can be written to 1-2, 1-3 and 1-4.
[0050]
FIG. 5 is a block diagram illustrating an example of a specific configuration of the delay processing circuit 21. The delay processing circuit 21 according to this example takes an odd-pixel digital video signal and an even-pixel digital video signal as two inputs, and outputs an odd-pixel digital video signal from the output end a side according to the scan direction control signal. Select whether to output the digital video signal of the even pixel from the output end b side, or to output the digital video signal of the odd pixel from the output end b side, and to output the digital video signal of the even pixel from the output end a side. And a one-line delay element 32 that delays the video signal output from the output terminal a of the selector 31 by a time corresponding to one line.
[0051]
In the case of the above example, the selector 31 outputs an even pixel digital video signal from the output end a side, and outputs an odd pixel digital video signal from the output end b side. At this time, the digital video signal of the even pixel is output via the one-line delay element 32, and the digital video signal of the odd pixel is directly output without passing through the one-line delay element 32.
[0052]
However, whether the digital video signal of even pixels or the digital video signal of odd pixels is delayed depends on the structural layout of the liquid crystal panel 24 and the horizontal and vertical scanning directions. Therefore, the selector 31 performs switching according to the scanning direction. When the scanning direction is opposite to the above example, the selector 31 outputs the odd-pixel digital video signal from the output terminal a side and outputs the even-pixel digital video signal from the output terminal b side. Become. As the one-line delay element 32, a line memory or the like is used.
[0053]
FIG. 6 shows a timing relationship between the digital video signal of the odd pixel and the digital video signal of the even pixel when the digital video signal of the odd pixel is delayed. Here, n means the number of vertical lines, and m means the number of horizontal pixels. From the timing chart of FIG. 6, a signal of n-1 vertical lines is output as a digital video signal of odd pixels, a signal of n vertical lines is output as a digital video signal of even pixels, and a digital video signal of odd pixels is an even pixel. It can be seen that the digital video signal is delayed by a time corresponding to one line.
[0054]
In this way, an active matrix TFT liquid crystal display device driven by dot-line inversion, that is, for example, two video signals of opposite polarity video 1 and video 2 are simultaneously written to pixels of different horizontal lines, and the pixels in the pixel array after writing Even in the case of a liquid crystal display device of a driving method in which the polarities of adjacent left and right pixels are the same polarity and the upper and lower pixels are opposite polarities, a signal delayed by a time corresponding to one line Since it is possible to select whether to use a video signal or an odd pixel digital video signal in accordance with the scanning direction, it is possible to easily cope with a change in the scanning direction.
[0055]
In this example, the delay element 32 has one line because it is applied to an example of a liquid crystal display device that is configured to simultaneously write video signals video 1 and video 2 having opposite polarities to pixels in two upper and lower lines (two upper and lower lines). The delay element 32 is delayed for a considerable time. However, when applied to a liquid crystal display device configured to write simultaneously to pixels on different lines separated by two lines or more, the delay element 32 delays the time corresponding to the number of separated lines. You can do that.
[0056]
【The invention's effect】
As described above, according to the present invention, in a sequentially driven active matrix liquid crystal display device, video signals having opposite polarities are simultaneously written to pixels on different lines, and the polarities of the pixels in the pixel array after writing are written. Are set to have the same polarity in the adjacent left and right pixels, and in the opposite polarity in the upper and lower pixels, as in the case of the dot inversion driving method, video signals having opposite polarities are given to the adjacent signal lines. In addition, as in the case of the 1H inversion driving method, the polarity of the pixel array after writing the video signal is the same in the left and right adjacent pixels, so that the horizontal crosstalk is not reduced without reducing the pixel aperture ratio. And poor image quality such as in-plane shading.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a configuration example of an active matrix TFT liquid crystal display device according to an embodiment of the present invention.
FIG. 2 is a waveform diagram for explaining the operation of dot-line inversion driving.
FIG. 3 is a diagram illustrating an address of each pixel and a polarity of a video signal written to each pixel in the case of dot-line inversion driving.
FIG. 4 is a block diagram showing an example of a configuration of a liquid crystal display system according to the present invention.
FIG. 5 is a block diagram illustrating an example of a specific configuration of a delay processing circuit.
FIG. 6 is a timing chart showing a relationship between an odd pixel digital video signal and an even pixel digital video signal when an odd pixel digital video signal is delayed;
FIG. 7 is a configuration diagram illustrating a conventional example of an active matrix liquid crystal display device.
FIG. 8 is a waveform diagram for explaining the operation of 1H inversion driving.
FIG. 9 is a diagram illustrating the polarity of a video signal written to each pixel by 1H inversion driving.
FIG. 10 is a diagram for explaining the cause of occurrence of lateral crosstalk.
FIG. 11 is a waveform diagram for explaining the operation of dot inversion driving.
FIG. 12 is a diagram illustrating the polarity of a video signal written to each pixel by dot inversion driving.
FIG. 13 is a diagram illustrating how a pixel domain is generated during dot inversion driving.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 11 ... Pixel, 12 ... Cs line, 13 ... Scan driver, 14 ... Source driver, 21 ... Delay processing circuit, 24 ... Liquid crystal panel, 31 ... Selector, 32 ... 1 line delay element, sw1-sw4 ... Sampling switch

Claims (6)

A plurality of signal lines wired for each column with respect to an array of pixels arranged in a matrix;
A plurality of gate lines that meander between the upper and lower two lines of the pixel array and are alternately connected in odd and even columns to the upper and lower two lines of pixels;
A vertical driving circuit for sequentially selecting the plurality of gate lines;
A 2n (n is an integer) video signal whose polarity is inverted every horizontal period is input, and the 2n video signals having the opposite polarity are input through the signal line in units of two adjacent columns. A liquid crystal display device comprising: a horizontal drive circuit that simultaneously writes in a pixel connected to a gate line selected by a vertical drive circuit. The liquid crystal display device according to claim 1, wherein connection lines for commonly connecting the electrodes of the storage capacitors of the pixels arranged in a matrix are arranged in a matrix. A plurality of signal lines wired for each column with respect to an array of pixels arranged in a matrix;
Driving a liquid crystal display device having a plurality of gate lines that meander between two upper and lower lines of the pixel array and are alternately connected in odd and even columns to the upper and lower two lines of pixels. Hitting
While sequentially selecting the plurality of gate lines,
A 2n (n is an integer) video signal whose polarity is inverted every horizontal period is input, and the 2n video signals having the opposite polarity are input through the signal line in units of two adjacent columns. A method for driving a liquid crystal display device in which data is simultaneously written to pixels connected to sequentially selected gate lines. Liquid crystal display means adopting a driving method of sequentially driving each pixel arranged in a matrix for each line in units of pixels;
A delay processing means for inputting the video signals of the pixels in the odd columns and the video signals of the pixels in the even columns by shifting the time by a time corresponding to a predetermined number of lines;
Driving means for driving the liquid crystal display device based on the video signals of the odd-numbered columns of pixels and the video signals of the even-numbered columns of pixels that have passed through the delay processing means;
The liquid crystal display means includes
A plurality of signal lines wired for each column to the pixel array;
A plurality of gate lines that meander between the upper and lower two lines of the pixel array and are alternately connected in odd and even columns to the upper and lower two lines of pixels;
A vertical driving circuit for sequentially selecting the plurality of gate lines;
A 2n (n is an integer) video signal whose polarity is inverted every horizontal period is input, and the 2n video signals having the opposite polarity are input through the signal line in units of two adjacent columns. A liquid crystal display system comprising: a horizontal drive circuit for simultaneously writing to pixels connected to a gate line selected by a vertical drive circuit. The liquid crystal display system according to claim 4, wherein the liquid crystal display means includes a connection line that is wired in a matrix and connects the electrodes of the storage capacitors of the pixels in common between the pixels. The delay processing means has two inputs, a delay means having a time corresponding to the predetermined number of lines as a delay time, and a video signal of the pixels in the odd columns and a video signal of the pixels in the even columns, and scan direction control The liquid crystal display system according to claim 4, further comprising a selection unit that selects one of the two inputs in accordance with a signal and supplies the selected one to the delay unit.

Images