JP4531667B2 - Clock recovery circuit - Google Patents

Description

  The present invention relates to a clock recovery circuit that recovers a clock signal synchronized with an input data signal.

  FIG. 3 is a circuit diagram showing a conventional clock recovery circuit (see, for example, Non-Patent Document 1). In this clock recovery circuit, a voltage controlled oscillator circuit VCO (Voltage Controlled Oscillator), a phase comparison circuit PFD (Phase Frequency Detector), and a PLL (Phase Locked Loop) consisting of a charge pump and filter, the frequency synchronized with the reference clock. Send a signal. Then, using this signal, the input data signal Data_in is passed through the two voltage controlled oscillation circuits VCO and ORed to generate a reproduction clock signal Clock_out synchronized with the input data signal Data_in. Further, using the reproduction clock signal Clock_out, the D-type flip-flop circuit DFF is used to identify and reproduce the input data signal Data_in to generate a reproduction data signal Data_out.

High-Speed Burst-Mode Packet-Capable Optical Receiver and Instataneous Clock Recovery for Optical Bus Operation (1994.2 IEEE J of LIGHTWAVE TECHNOLOGY), Fig. 4

  However, since the conventional clock recovery circuit has separate functions for frequency synchronization and phase synchronization, it is suitable for high-speed response (high-speed synchronization), but has a problem that the circuit scale is large and it is not suitable for high-speed operation. In addition, when the number of bits having the same sign of the input data signal Data_in is increased, the recovered clock signal Clock_out is changed from the phase synchronization state to the automatic oscillation state of the voltage controlled oscillation circuit.

  The present invention has been made in order to solve the above-described problems, and an object of the present invention is to provide a clock that is small in circuit size and capable of high-speed operation without impairing high-speed response (high-speed synchronization) and is less likely to cause bit errors. A reproduction circuit is obtained.

  A clock recovery circuit according to the present invention includes a gate circuit for detecting an edge of a pulse of an input data signal, a voltage controlled oscillation circuit having a ring oscillator function based on the edge detected by the gate circuit, and an output of the voltage controlled oscillation circuit A band pass filter for suppressing phase noise of the signal. Other features of the present invention will become apparent below.

  According to the present invention, it is possible to obtain a clock recovery circuit that has a small circuit scale and can be operated at high speed without impairing high-speed response (high-speed synchronization) and hardly causes bit errors.

  FIG. 1 is a circuit diagram showing a clock recovery circuit according to an embodiment of the present invention. This clock recovery circuit includes a gate circuit Gating for detecting the edge of the pulse of the input data signal Data_in, a voltage controlled oscillation circuit VCO having a ring oscillator function based on the edge detected by the gate circuit Gating, and a voltage controlled oscillation circuit VCO. A band-pass filter BPF (band-pass filter) that suppresses phase noise of the output signal of the output signal, and a D-type flip-flop circuit DFF that identifies and reproduces the input data signal Data_in by the reproduction clock signal Clock_out and generates the reproduction data signal Data_out Have. That is, the gate circuit Gating is inserted in the previous stage of the voltage controlled oscillation circuit VCO, and the band pass filter BPF is inserted in the subsequent stage.

  By inserting the bandpass filter BPF, the frequency lock range is expanded with almost no loss of high-speed response, eliminating the need for a voltage-controlled oscillation circuit VCO for frequency synchronization, reducing the circuit scale, and suitable for high-speed operation. ing. Further, it is not necessary to supply a reference clock. In the conventional clock recovery circuit, two voltage controlled oscillation circuits VCO are used and ORed. However, in this embodiment, since the gate circuit Gating is adopted, only one voltage controlled oscillation circuit VCO is used. Good.

  FIG. 2 is a timing chart of the clock recovery circuit shown in FIG. When the same sign bit continues in the input data signal Data_in, the output of the gate circuit Gating (point A) continues to be in a high state. For this reason, the clock jitter gradually increases at the output (point B) of the voltage controlled oscillation circuit VCO. However, by providing the band pass filter BPF, it is possible to maintain the phase state of the recovered clock signal Clock_out even when the number of bits of the same sign is increased, and it is difficult to cause a bit error, and jitter of the recovered clock signal Clock_out is reduced. Can be reduced.

  One of the parameters of the bandpass filter BPF is a Q value. The higher the Q value, the longer the synchronization time of the clock recovery circuit, but the same symbol continuity tolerance increases. Therefore, the Q value of the band pass filter BPF is set so as to satisfy the desired synchronization time and the desired continuity tolerance of the same sign. For example, if the input signal is 10 Gb / s, the request for “high-speed synchronization” is 1 ns (10 bits) or less, and the required value of “allowable same sign continuous bit length” is 7 ns (70 bits) or more, Set to 10.

1 is a circuit diagram showing a clock recovery circuit according to an embodiment of the present invention. 2 is a timing chart of the clock recovery circuit shown in FIG. It is a circuit diagram which shows the conventional clock reproduction circuit.

Explanation of symbols

BPF band pass filter
Gating gate circuit
VCO voltage controlled oscillator

Claims (2)

A gate circuit for detecting the edge of the pulse of the input data signal;
A voltage controlled oscillation circuit having a ring oscillator function based on an edge detected by a gate circuit;
A clock recovery circuit comprising: a band-pass filter that suppresses phase noise of an output signal of the voltage controlled oscillation circuit.   The clock recovery circuit according to claim 1, wherein the band-pass filter has a Q value satisfying a desired synchronization time and a desired same-symbol continuity tolerance.

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