JP4515878B2 - Flash memory and writing / verifying method thereof - Google Patents

Description

  BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically rewritable nonvolatile semiconductor memory device and a writing / verifying method thereof, and, for example, to a technique for speeding up writing and verifying in a whole chip (or system) in a large-capacity flash memory. .

  As the capacity of the nonvolatile semiconductor memory device increases, the number of memory cells connected to the bit line increases, and as the chip size decreases, the pitch between the bit lines also decreases. The capacity in between has been increasing. For this reason, an increase in the load capacity of the bit line increases the charge / discharge time of the bit line, leading to an increase in the write time.

  In addition, in general, in a nonvolatile semiconductor memory device, it is necessary to verify whether or not sufficient writing has been performed after data writing, so that the writing time is further increased. For example, writing to a NAND flash memory is performed by applying a high voltage to the control gate of a cell transistor serving as a memory cell and changing (shifting) the threshold voltage of the cell transistor. Thereafter, verification is performed to monitor the amount of change in the threshold voltage of the cell transistor, and it is confirmed whether or not the amount of shift in the threshold voltage of the cell transistor is sufficient. For this reason, the number of times of writing and verifying (applying a high voltage to the control gate of the cell transistor / monitoring the threshold voltage of the cell transistor) is increasing (for example, see Patent Document 1).

  For this reason, the writing time of the entire system (for example, a system that writes a large amount of data in a NAND flash memory such as a digital camera) is lengthened.

However, in the market, there is a strong demand for writing a large amount of data, such as writing moving image data, and it is desired to increase writing speed and verify speed of the entire system.
JP-A-8-87895

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a flash memory and a writing / verifying method thereof capable of increasing the writing and verifying speed.

According to one aspect of the present invention, a memory cell array in which memory cells are arranged in a matrix, and one end of bit lines in the memory cell array are connected to write data to the memory cell and to verify the written data. A verify circuit, a switch element that divides the bit line into a plurality of parts, and the write / verify circuit and the switch element are controlled, and a memory cell at an address to be written is on the write / verify circuit side from the switch element. Occasionally, the switching element is turned off to write and verify, when the memory cell address to be the writing is on the side away from the write-verify circuit from the switching element, it turns off the switching element , The memory address of the address to be written After saving by changing the most significant address of the block address write data to memory cells of the write-verify circuit side in, writing by turning on the switching element when the write-verify circuit is not operating There is provided a flash memory including a control circuit for performing control for writing the saved data into a memory cell at a target address.

Further, according to one aspect of the present invention, the first step of determining whether or not the memory cell at the address to be written is on the write / verify circuit side in the memory cell array, and the write operation in the first step When it is determined that the memory cell at the target address is on the write / verify circuit side in the memory cell array, the bit line is divided into a plurality of pieces and data is written to the selected memory cell in the memory cell array, When it is determined that the second step of verifying and the memory cell at the address to be written in the first step are on the side away from the write / verify circuit in the memory cell array, a plurality of bit lines are provided. divided into blocks in the memory cell of the address to be write A third step of saving the data to the write-verify circuit of the memory cells in said memory cell array by changing the most significant address of the dress, when the write-verify circuit is not operating, divided the bit A flash memory writing / verifying method comprising: a fourth step of connecting a line and writing the data saved in the third step into a memory cell to be written.

According to the present invention, it is possible to obtain a flash memory and a writing / verifying method thereof capable of increasing the writing and verifying speed.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram showing a schematic configuration of a main part related to a write and verify operation of a NAND flash memory, for explaining a nonvolatile semiconductor memory device and a write / verify method thereof according to an embodiment of the present invention. It is.

  As shown in FIG. 1, the NAND flash memory includes a memory cell array 11, a command input buffer 12, a control circuit 13, an address input buffer 14, a row decoder 15, a column decoder 16, a write / verify circuit 17, a data output buffer 18, and the like. ing. When a command CMD is input to the command input buffer 12, the control circuit 13 decodes the command, and the control circuit 13 controls the address input buffer 14, the row decoder 15, the write / verify circuit 17 and the like according to the command CMD. Of the address signal ADD input to the address input buffer 14, the row address signal is supplied to the row decoder 15 and decoded, and the column address signal is supplied to the column decoder 16 and decoded. A memory cell (cell transistor) in the memory cell array 11 is selected by the row decoder 15 and the column decoder 16. Data read from the selected memory cell is amplified by a sense amplifier in the write / verify circuit 17 and read out to the outside via the data output buffer 18. When data is written to the memory cell, the write / verify circuit 17 verifies whether the write is sufficient, in other words, whether the shift amount of the threshold voltage of the cell transistor is sufficient.

  In the memory cell array 11, NAND strings are arranged in a matrix as shown in FIG. NAND strings arranged in the same row constitute one block, and here, the memory cell array 11 is composed of 1024 blocks Block0 to Block1023. Word lines WL0-31_ * (* is 0 to 1023) and select gate lines SGD and SGS are commonly connected to the NAND strings in the respective blocks Block0 to Block1023. Here, as shown in FIGS. 3A and 3B, an example is shown in which the current paths of 32 cell transistors CT0_ * to CT31_ * are connected in series in each NAND string, and the cell transistors CT0_ * A current path of the selection gate transistor ST1 is connected between the source and the source line CELSRC, and a current path of the selection gate transistor ST2 is connected between the drain of the cell transistor CT31_ * and the bit line BL. The select gate transistors ST1 in the NAND strings arranged in the same row are commonly connected to the select gate line SGS, and the control gates of the cell transistors CT0_ * to CT31_ * are commonly connected to the word lines WL0_ * to WL31_ *. ST2 is commonly connected to the select gate line SGD.

  On the other hand, NAND strings arranged in the same column are connected to bit lines BL0 to BL2047 for each column. Current paths of MOS transistors Q0 to Q2047 functioning as switching elements that divide the bit lines BL0 to BL2047 into a plurality of bits are connected to the bit lines BL0 to BL2047 in the central portion (between Block511 and Block512) of the memory cell array 11. ing. The gates of these MOS transistors Q0 to Q2047 are supplied with a control signal CS from the control circuit 13 and are turned on / off. When the MOS transistors Q0 to Q2047 are in the ON state, the bit lines BL0 to BL2047 are continuous. When one bit line BLi (i = 0 to 2047) is selected, 1024 NANDs are selected on the selected bit line BLi. The string is connected. On the other hand, in the off state, the bit lines BL0 to BL2047 are divided into two, and 512 NAND strings are connected to the selected bit line BLi. That is, the memory cell array 11 is divided into two blocks, Block 0 to Block 511 and Block 512 to Block 1023, by the MOS transistors Q0 to Q2047. Write / verify circuits 17-0 to 17-2047 are connected to one ends of the bit lines BL0 to BL2047, respectively.

  In the configuration as described above, when a command CMD is input to the command input buffer 12 and a write operation is instructed, the write operation is performed as shown in the flowchart of FIG. 4 based on the address signal ADD input to the address input buffer 14. It is determined whether the address to be subjected to is a memory cell in the block Block 0 to Block 511 or a memory cell in the block Block 512 to Block 1023 in the memory cell array 11. In other words, it is determined whether or not the MOS transistor Q0-Q2047 is at a position closer to or farther from the write / verify circuit 17 (STEP 1).

  In this STEP1, the word line WL1_1 in the block Block1 is selected, for example, as shown in FIG. 2, in which the memory cell at the address to be written is in a position close to the write / verify circuit 17 (in the block Block0 to Block511). In some cases, the control signal CS is set to the ground potential VSS level, the MOS transistors MOS transistors Q0 to Q2047 are turned off, the bit lines BL0 to BL2047 are divided into two, and data is written to the memory cell selected by the word line WL1_1 for verification. (STEP 2). In this case, since the bit line capacitance is halved, the charge / discharge time of the bit line can be substantially halved, and the time required for the write and verify operations can be shortened.

  In contrast, for example, as shown in FIG. 5, the word line WL1_512 in the block Block 512 is located at a position far from the write / verify circuit 17 (in the block Block 512 to Block 1023). When selected, the control signal CS is set to the ground potential VSS level, the MOS transistors MOS transistors Q0 to Q2047 are turned off, and the bit lines BL0 to BL2047 are divided into two, for example, the highest address of the block address is changed. Data is saved in the memory cell at the address (STEP 3). In FIG. 5, data is saved in the memory cell selected by the word line WL1_0.

  In order to speed up the write operation, it is important to perform the save operation earlier (reducing the number of write operations). For this reason, it is preferable to reduce the number of times of writing by performing a binary operation and increasing the write voltage (at some sacrifice of the threshold voltage control of the cell transistor).

  After that, as shown in FIG. 6, when the write / verify circuit 17 is not used, the control signal CS is set to the power supply voltage VDD level and the MOS transistors MOS transistors Q0 to Q2047 are turned on to save the saved data. Is written in a manner such as page copy to the memory cell of the correct address to be written (STEP 3).

  For example, the following timings (a) to (d) can be considered as the timing for writing to the correct address.

(A) At the time of writing to another plane (b) In the case of a two-chip configuration, when another chip is accessed (c) At the time of input / output (serial read / data load) (d) Free time of controller It is possible to shorten the writing time of the entire system by writing data to the regular address in the idle time that does not control the writing time of the system.

  In the above embodiment, the case where the bit line is divided into two and the charge / discharge time of the bit line is halved has been described as an example. However, if the bit line is divided into n, the charge / discharge of the bit line is similarly performed. The time can be reduced to 1 / n, and the write and verify operations can be speeded up.

  As described above, in a nonvolatile semiconductor memory device having a large bit line load capacity such as a NAND flash memory, when a memory cell closer to the write / verify circuit is selected at the time of writing, the bit line is divided. Writing and verifying speed can be increased by reducing the bit line capacitance and writing. On the other hand, when a memory cell far from the write / verify circuit is selected, data is first saved at high speed to the memory cell closer to the write / verify circuit, and then this write is performed when the write / verify circuit is not used. -Operate the verify circuit to write (copy) data to the memory cell at the normal address.

  In this way, the bit line load capacity is reduced and saved in the memory cell closer to the write / verify circuit, and written back to the memory cell at the correct address in the idle time, so that the charge / discharge time of the bit line during writing is reduced. In addition, the charge / discharge time of the bit line during verification can be shortened. By performing the timing to write back to the regular address during other operations (while writing to other addresses, in the case of a multi-chip configuration, during the period when other chips are operating, during data input / output) (System) Overall writing and verifying speed can be increased.

  Although the present invention has been described above using the embodiment, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention in the implementation stage. Further, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent elements are deleted from all the constituent elements shown in the embodiment, at least one of the problems described in the column of the problem to be solved by the invention can be solved, and is described in the column of the effect of the invention. When at least one of the effects obtained is obtained, a configuration in which this configuration requirement is deleted can be extracted as an invention.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram illustrating a schematic configuration of a main part related to a write and verify operation of a NAND flash memory for explaining a nonvolatile semiconductor memory device and a write / verify method thereof according to an embodiment of the present invention; FIG. 2 is a block diagram showing a configuration example of a memory cell array and a write / verify circuit in the circuit shown in FIG. 1. FIG. 3 is a symbol diagram of the NAND string in FIG. 2 and a circuit diagram illustrating a specific configuration example. 10 is a flowchart for explaining a writing / verifying method. FIG. 5 is a block diagram for explaining a write verify operation. FIG. 5 is a block diagram for explaining a write verify operation.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Memory cell array, 12 ... Command input buffer, 13 ... Control circuit, 14 ... Address input buffer, 15 ... Row decoder, 16 ... Column decoder, 17, 17-0 to 17-2047 ... Write / verify circuit, 18 ... Data Input / output buffer, Block 0 to Block 1023... Block, Q0 to Q2047... MOS transistor (switch element), CS... Control signal, BL0 to BL2047... Bit line, WL0-31_ *. * To CT31_ *: cell transistors, ST1, ST2: selection gate transistors, CELSRC: source lines.

Claims (4)

A memory cell array in which memory cells are arranged in a matrix;
A write / verify circuit that is connected to one end of a bit line in the memory cell array, writes data to the memory cell, and verifies the written data;
A switch element for dividing the bit line into a plurality of parts;
The write / verify circuit and the switch element are controlled, and when the memory cell at the address to be written is on the write / verify circuit side from the switch element, the switch element is turned off to perform writing and verification, When the memory cell at the address to be written is on the side farther from the write / verify circuit than the switch element, the switch element is turned off , and the most significant block address in the memory cell at the address to be written to After changing the address and writing and saving data in the memory cell on the write / verify circuit side, when the write / verify circuit is not operating, the switch element is turned on and the address of the write target Write the saved data to the memory cell Flash memory characterized by comprising a control circuit for writing control. A first step of determining whether or not a memory cell at an address to be written is on the write / verify circuit side in the memory cell array;
When it is determined in the first step that the memory cell of the address to be written is on the write / verify circuit side in the memory cell array, the bit line is divided into a plurality and selected in the memory cell array. A second step of writing and verifying data in the memory cell,
When it is determined that the memory cell at the address to be written in the first step is on the side away from the write / verify circuit in the memory cell array, the bit line is divided into a plurality of A third step of changing the highest address of the block address in the memory cell at the address to save the data in the memory cell on the write / verify circuit side in the memory cell array;
A fourth step of connecting the divided bit lines and writing the data saved in the third step to a memory cell to be written when the write / verify circuit is not operating. A flash memory write / verify method characterized by the above. 3. The flash memory write / verify method according to claim 2 , wherein the operation of saving data in the third step is a binary write operation. The write voltage when the third saving data in step claim 2 or 3 write-verify method of the flash memory, wherein the higher than the write voltage in the normal write operation.

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