JP4515525B2 - Semiconductor device - Google Patents

Description

  The present invention provides a peripheral drive circuit, a control circuit, an MPU (Micro Processing Unit) and an image processing circuit on the same substrate in an active matrix drive liquid crystal display device driven by a TFT (Thin Film Transistor). The present invention relates to a semiconductor substrate used for a display device such as an integrated high-performance liquid crystal display device or an OLED (Organic Light Emitting Diode: organic EL) display device, a semiconductor device, and a manufacturing method thereof.

  In particular, system-on-panel technology that significantly improves circuit performance with a single crystal thin film device, and a manufacturing method thereof, a device structure used in manufacturing the semiconductor device, and a single crystal device and non-single crystal Si, In particular, the present invention relates to a manufacturing technique for coexisting with polycrystalline Si.

  A thin film transistor (hereinafter referred to as “TFT (Thin Film Transistor)”) of amorphous Si (hereinafter abbreviated as “a-Si”) or polycrystalline Si (hereinafter abbreviated as “Poly-Si”) on a glass substrate. ") Is formed as a switching element of a pixel, and a liquid crystal display device performing so-called active matrix driving for driving a liquid crystal display panel, an organic EL panel, or the like has been put into practical use and has been produced in large numbers.

  In particular, Poly-Si, which has a high mobility and operates at high speed, has recently been able to be integrated on a glass substrate by utilizing the features of the high mobility and provided on a glass substrate. Has been done.

  However, in a display device such as a liquid crystal display device that performs so-called active matrix driving and an OLED (Organic Light Emitting Diode: organic EL) display device using a large glass substrate, a non-single crystal Si, particularly poly, is used as a transistor of a driver IC. In the case of using -Si, there is a problem that characteristic variations caused by crystal grain boundaries peculiar to poly-Si and that it is extremely difficult to obtain a high-quality gate insulating film, and there is a limit to integration of advanced systems. Therefore, from the viewpoint of display quality (uniformity), a device with higher performance and less characteristic variation is required.

  In particular, in the direct integration and systemization of highly integrated semiconductor devices on display substrates, microfabrication corresponding to high-speed performance and integration density, device performance (mobility, threshold controllability, transfer characteristics) In order to achieve true system integration in systems used in drivers such as image processors and timing controllers that require higher performance, either device performance or integration density is required. Is insufficient.

  Therefore, it is extremely difficult to realize both a pixel TFT and a higher performance / high density driver IC for driving the pixel TFT directly on a display substrate such as a large glass substrate.

  Therefore, as an approach to solving this problem, there is a technique in which a single-crystal Si driver IC is mounted (assembled) on an LSI (Large Scale Integrated circuit) using COG (Chip On Glass). In this COG, an LSI formed of single crystal Si is assembled on a display substrate by flip chip mounting using an anisotropic conductive film or the like.

  In these ordinary LSIs, MOS (Metal Oxide Semiconductor) transistors are formed of bulk single crystal Si, and therefore, it is required to operate each transistor independently. Therefore, ion implantation such as doping of the channel stop 101 and the multiwell 102 is performed as shown in FIG. 13 in order to isolate and independence of individual transistors (element isolation) or to prevent latch-up by the parasitic bipolar transistor. Is called. However, with the miniaturization of transistors, a region for element isolation has become a problem. Therefore, in order to reduce the area for element isolation, a technique such as a retrograde well (reverse impurity concentration gradient well) structure is used. However, the process is complicated by requiring many ion implantations. Therefore, there were problems of cost increase and yield decrease. Further, a process such as a bump forming process is necessary, and the manufacturing process is long, which causes a decrease in yield.

  Further, there is a restriction that a display device such as a liquid crystal display device or an OLED display device cannot assemble a driver IC unless it is completed as a panel. For this reason, there are problems that the degree of freedom in manufacturing is small and the process is complicated, the degree of freedom in the manufacturing process is small and complicated, and the distribution / manufacturing efficiency is low, resulting in high cost and low yield.

  On the other hand, there is a solution to this problem by device transfer (device transfer). This device transfer is a technique in which a device made of single crystal Si is formed on an insulator, the device is bonded to a glass substrate serving as a display panel, and then the insulator is detached. A structure in which a device made of single crystal Si is formed on the insulator is referred to as an SOI (Silicon On Insulator) structure.

  As for this device transfer (device transfer), for example, there is a method (Kopin) for forming a separate thin film by etching an oxide film under single crystal Si in the SOI structure. Specific prior art documents include, for example, Patent Document 1 and Non-Patent Documents 1 and 2.

  Patent Document 1 discloses that a display panel of an active matrix liquid crystal display device is produced using a semiconductor device in which a single crystal Si thin film transistor previously produced using an adhesive is transferred onto a glass substrate. .

  As other prior arts related to the present invention, there are Patent Document 2 and Non-Patent Documents 3 and 4. In Patent Document 2, a step is provided in single crystal Si, and a polishing stopper having a polishing rate smaller than that of single crystal Si is formed thereon, transferred to another Si substrate, the separation surface is polished, and the polishing rate Using this difference, a technique is disclosed in which a single-crystal Si thin film is left in the form of islands by a stopper in a step recess.

JP 7-503557 A (publication date April 13, 1995) Japanese Patent Laid-Open No. 10-125880 (published on May 15, 1998)

J.P.Salerno “Single Crystal Silicon AMLCDs”, Conference Record of the 1994 International Display Research Conference (IDRC) p.39-44 (1994) Q.-Y.Tong & U.Gesele, SEMICONDUCTOR WAFER BONDING: SCIENCE AND TECHNOLOGY_, John Wiley & Sons, New York (1999) K. Warner, et.al., 2002 IEEE International SOI Conference: Oct, pp.123-125 (2002) L.P.Allen, et.al., 2002 IEEE International SOI Conference: Oct, pp.192-193 (2002)

  However, the conventional semiconductor substrate, semiconductor device, and manufacturing method thereof have the following problems.

  First, in the SOI structure, since devices are formed on a silicon (Si) wafer, the total size of all devices is limited to the silicon (Si) wafer. Therefore, since the size of the silicon (Si) wafer is limited, the length of the large glass substrate may be insufficient.

  In addition, in order to bond a single crystal Si device formed on a silicon (Si) wafer to a glass substrate with an adhesive such as an epoxy resin, a step of performing defect recovery heat treatment (annealing) after bonding, a step of forming an interlayer insulating film Alternatively, a process such as a process of forming a metal wiring cannot be added. For this reason, it is extremely difficult to connect a device formed in advance on a large glass substrate and a single crystal Si device to be transferred by mutual wiring.

Furthermore, forming a region of operation the single crystal Si devices to silicon dioxide (SiO ₂₎ solid-phase epitaxial layer is a single crystal layer of a thin film grown on the (Epitaxial film), etched separating silicon dioxide (SiO ₂₎ Since the method is a manufacturing method, there are problems (transfer process, thin film separation / holding, epi-growth) that the process becomes complicated and the yield decreases.

  The present invention has been made in view of the above problems, and its purpose is to form a non-single-crystal Si semiconductor element and a single-crystal Si semiconductor element on a large insulating substrate, and to integrate a high-performance system. When manufacturing a semiconductor device, a semiconductor capable of simplifying the manufacturing process of a single crystal Si portion and transferring the element to a fine single crystal Si semiconductor element without high precision photolithography after being transferred to a large insulating substrate It is to provide a substrate, a semiconductor device, and a manufacturing method thereof.

In order to solve the above problems, a semiconductor device of a related invention of the present invention includes an insulating substrate, a single crystal Si semiconductor element formed on a partial region of the insulating substrate, and another region of the insulating substrate. A single-crystal Si semiconductor element comprising: a gate electrode formed above the insulating substrate; and a gate insulation formed on the gate electrode. A device, an active layer made of a single crystal Si layer including a channel region, a source region, and a drain region formed on the gate insulating film, and an element isolation oxide for element isolation formed around the active layer And an interlayer insulating film formed on the active layer and the element isolation oxide film.

  According to the above invention, since the semiconductor device includes an insulating substrate and a single crystal Si semiconductor element formed on the insulating substrate, for example, an insulating substrate such as a glass plate and a single crystal Si semiconductor element Are united.

  The single crystal Si semiconductor element includes a gate electrode formed above an insulating substrate, a gate insulating film formed on the gate electrode, and a channel region, a source region, and a drain region formed on the gate insulating film. And an element isolation oxide film formed around the active layer, and an interlayer insulating film formed on the active layer and the element isolation oxide film.

  As a result, non-single-crystal Si semiconductor elements and single-crystal Si semiconductor elements are formed on a large insulating substrate, and the manufacturing process of the single-crystal Si portion is simplified when manufacturing a semiconductor device in which a high-performance system is integrated. In addition, it is possible to provide a semiconductor device capable of realizing element separation of a fine single crystal Si semiconductor element without high-precision photolithography after being transferred to a large insulating substrate.

A semiconductor device according to a related invention of the present invention is the semiconductor device described above, wherein the semiconductor device is formed on the interlayer insulating film and connected to the source region and the drain region through a connection hole provided in the interlayer insulating film. It has a wiring layer.

In order to solve the above problems, a semiconductor device of the present invention has an insulating substrate, a single crystal Si semiconductor element formed on a partial region of the insulating substrate, and another region of the insulating substrate. A semiconductor device including a formed non-single-crystal Si semiconductor element, wherein the single-crystal Si semiconductor element includes a gate electrode formed above the insulating substrate and a gate insulating film formed on the gate electrode. An active layer made of a single crystal Si layer including a channel region, a source region, and a drain region formed on the gate insulating film; and a LOCOS oxide film for element isolation formed around the active layer; A protective insulating film and an interlayer insulating film formed on the active layer and the LOCOS oxide film, an insulating film formed between the insulating substrate and the gate electrode, and a lower surface side of the insulating film Formed into At least one layer first wiring layer is formed on the interlayer insulating film, the interlayer insulating film, on the first wiring layer through a contact hole penetrating the LOCOS oxide film and the insulating film And a second wiring layer connected thereto.

  By the way, when forming a metal wiring layer, including the above-mentioned case, generally, in order to improve the integration density of an integrated circuit, it is necessary to form a plurality of wiring layers and efficiently use a space. This is because, when the element region becomes very small, as a practical problem, external extraction electrodes are densely arranged immediately above the element region, and it becomes difficult to form a wiring pattern.

  Therefore, in the semiconductor device of the present invention, at least one first wiring layer formed on the lower surface side of the insulating film and a second wiring formed on the interlayer insulating film and connected to the first wiring layer. And have a layer.

  Therefore, wiring can be efficiently routed using the space on the back side of the element region, and the integration density can be increased.

  The semiconductor device according to the present invention is characterized in that, in the semiconductor device described above, the upper surface of the active layer is located lower than the upper surface of the element molecular oxide film.

According to the present invention, the upper surface of the active layer is etched back to a position lower than the upper surface of the LOCOS oxide film by cleaving and separating the thinned single crystal Si thin film surface, thereby reducing the final device leakage current. Can be reduced.

The semiconductor device of the present invention is characterized in that, in the semiconductor device described above, an end portion of the active layer is formed so as to overlap an inclined portion of an end portion of the LOCOS oxide film.

According to the above invention, since the end portion of the active layer is formed so as to overlap the inclined portion of the end portion of the LOCOS oxide film, a device-isolated structure is realized, and the conventional island etching is performed. Si island edge defects and leakage current due to stress can be reduced.

  The semiconductor device according to the present invention is the above semiconductor device, wherein the first wiring layer is made of a material having a heat resistant temperature (melting point or reaction temperature with Si, whichever is lower) of about 500 ° C. or more. It is characterized by being.

  According to the above invention, the first wiring layer is made of a material having a heat resistant temperature (melting point or reaction temperature with Si, whichever is lower) of about 500 ° C. or higher. The wiring layer does not melt.

  The semiconductor device of the present invention is the above semiconductor device, wherein at least a part of the non-single-crystal Si semiconductor element constitutes a switching transistor of each pixel constituting a display portion, while A transistor composed of a crystalline Si semiconductor element constitutes a display drive circuit for driving a display unit or a processing circuit for outputting a predetermined signal to the display drive circuit, and serves as a constituent substrate of a display device. It is characterized by being used.

  That is, conventionally, in a display device such as a liquid crystal display device, a switching transistor of each pixel made of a non-single crystal Si semiconductor element is formed on an insulating substrate such as a glass substrate, and a wiring pattern is further formed. A display driving circuit for driving the display or a processing circuit for outputting a predetermined signal to the display driving circuit is mounted by COG or COF made of a single crystal Si semiconductor element and then connected to the wiring pattern. It was. Or it supplied from an external printed circuit board.

  However, according to the present invention, at least a part of the non-single-crystal Si semiconductor element constitutes a switching transistor of each pixel constituting the display unit, and the transistor constituted by the single-crystal Si semiconductor element is A display driving circuit for driving the display unit or a processing circuit for outputting a predetermined signal to the display driving circuit is configured.

  Therefore, after forming at least a part of the non-single-crystal Si semiconductor element and a part of the single-crystal Si semiconductor element on the insulating substrate, the wiring layers of both can be formed. As a result, a semiconductor device for forming a high-quality display device with high productivity can be provided.

  As described above, the semiconductor substrate, the semiconductor device, and the manufacturing method thereof of the present invention have an active layer including a channel region, a source region, and a drain region, and do not have a well structure and a channel stop region. A single crystal Si substrate is used. Therefore, since it is made of single crystal Si, it is possible to form a semiconductor having high performance and low device performance.

  Further, in the present invention, since there is no conventional well, channel stop, or well contact, the area of the element region can be reduced, and the integration density can be increased by miniaturization of the element region, and the integration is highly integrated. It becomes a semiconductor substrate. Furthermore, since the conventional well structure is not formed, the depth can be reduced to the extent that it is not necessary to consider the well. As a result, since the semiconductor element can be formed in a thin film, when the semiconductor device is formed, for example, coexistence with other TFTs made of polycrystalline Si, and the two are interconnected with a thin film. It becomes possible to do. Furthermore, since it can be formed into a thin film, even in an insulating substrate such as a large glass substrate, element separation of a fine single crystal Si device can be realized without high-precision photolithography. Furthermore, since a well or the like is not formed, the manufacturing process is simple.

  In the present invention, a LOCOS oxide film thicker than the gate insulating film is formed so as to surround the periphery of the active layer. Therefore, element isolation is reliably achieved by the LOCOS oxide film.

  As a result, non-single-crystal Si semiconductor elements and single-crystal Si semiconductor elements are formed on a large insulating substrate, and the manufacturing process of the single-crystal Si portion is simplified when manufacturing a semiconductor device in which a high-performance system is integrated. And an effect that it is possible to provide a semiconductor substrate, a semiconductor device, and a manufacturing method thereof that can realize element isolation of a fine single crystal Si semiconductor element without high-precision photolithography after being transferred to a large insulating substrate. Play.

It is sectional drawing which shows one form of the reference of the semiconductor substrate in the related invention of this invention. It is sectional drawing which shows the structure of the semiconductor device which formed the metal wiring layer in the semiconductor device formed using the said semiconductor substrate. (A)-(g) is sectional drawing which shows the manufacturing process of the said semiconductor substrate and semiconductor device. (A)-(e) is sectional drawing which shows the manufacturing process following FIG.3 (g) in the manufacturing process of the said semiconductor device. (A) is a top view which shows the magnitude | size of the said semiconductor device at the time of contact hole formation, (b) is a top view which shows the magnitude | size of the semiconductor device at the time of the conventional contact hole formation as a comparison. It is sectional drawing which shows the semiconductor device in which the single-crystal Si semiconductor element and the non-single-crystal Si semiconductor element coexisted on the said insulated substrate. It is a top view which shows the structure of the display apparatus containing the display part which comprised the switching transistor of each pixel by the non-single-crystal Si semiconductor element, and the processing circuit provided with the transistor comprised by the single-crystal Si semiconductor element. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates an embodiment of the present invention and is a cross-sectional view illustrating a configuration of a semiconductor device. (A)-(g) is sectional drawing which shows the manufacturing process of the said semiconductor substrate and semiconductor device. (A)-(e) is a manufacturing process of the said semiconductor device, and is sectional drawing which shows the manufacturing process following FIG.7 (g). It is sectional drawing which shows the semiconductor device of the modification of the semiconductor device shown in FIG. (A)-(i) shows the reference form of this invention, and is sectional drawing which shows the manufacturing process of a semiconductor device. It is sectional drawing which shows the conventional semiconductor device of a well structure.

[Reference form 1 ]
Before describing the present embodiment, since there is a technique proposed in an unpublished patent application by the present inventors in order to solve the conventional problems, it will be described first.

  First, there are the following problems as conventional problems.

  That is, in an SOI (Silicon On Insulator) structure, devices are formed on a silicon (Si) wafer, so the total size of all devices is limited to a silicon (Si) wafer. Therefore, since the size of the silicon (Si) wafer is limited, it is insufficient for the size of the large glass substrate.

  In addition, in order to bond a single crystal Si device formed on a silicon (Si) wafer to a glass substrate with an adhesive such as an epoxy resin, a step of performing defect recovery heat treatment (annealing) after bonding, a step of forming an interlayer insulating film Alternatively, a process such as a process of forming a metal wiring cannot be added. Therefore, it is extremely difficult to connect the device formed on the large glass substrate and the single crystal Si device to be transferred by mutual wiring.

Furthermore, forming a region of operation the single crystal Si devices to silicon dioxide (SiO ₂₎ solid-phase epitaxial layer is a single crystal layer of a thin film grown on the (Epitaxial film), etched separating silicon dioxide (SiO ₂₎ Since the method is a manufacturing method, there are problems (transfer process, thin film separation / holding, epi-growth) that the process becomes complicated and the yield decreases.

Therefore, as shown in FIGS. 9A to 9C, the present inventors formed a gate electrode 83, an impurity doped layer 84, and the like, and a gate insulating film 82 on a single crystal Si substrate 81 by microfabrication, thereby forming a transistor. After completing the main steps, a predetermined concentration of hydrogen ions is implanted to a predetermined depth to form an ion implantation portion 85, an oxide film 86 is formed on the surface, and the oxide film 86 is then subjected to CMP (Chemical Mechanical Polishing: Single crystal Si substrate 81 flattened by chemical mechanical polishing and cut into a predetermined shape, and SiO formed on the surface by plasma CVD using TEOS (Si (OC ₂ H ₅ ) ₄ : Tetra Ethyl Ortho Silicate) _Two films 87 are formed and bonded to a glass substrate 88 activated with an SC1 cleaning solution or the like.

  Next, the joined material is heat-treated to grow a platelet containing hydrogen gas from the hydrogen ion implanting portion 85, forming a separate thin film to obtain a single crystal Si device 90, as shown in FIGS. 9 (d) to 9 (i). As described above, the single crystal Si device 90 and the non-single crystal Si TFT 91 made of polycrystalline Si coexist.

  This provides a means for solving the problem that the size is conventionally limited to the Si wafer size.

Furthermore, conventional, to form a single crystal Si devices to a solid epitaxial layer on silicon dioxide (SiO _2), due to the silicon dioxide (SiO ₂₎ is a manufacturing method of etching the separation step is complicated, the yield decreases The above manufacturing method also eliminates the need for solid phase epilayer formation on silicon dioxide (SiO ₂ ), and the problem of incurring the problem of incurring (transfer process, thin film separation / holding, epi growth). SiO ₂ ) provides a solution to long-time etching separation process, complicated process, and low yield (transfer process, thin film separation / holding, epi growth).

  However, in order to achieve high integration of single crystal Si thin film transistors and to exhibit sufficient performance, further measures for the following problems are required.

  That is, in order to form a single crystal Si device on a large glass substrate, element isolation is indispensable. However, element isolation by island-shaped etching of single crystal Si in the above technique is performed by photolithography on a large glass substrate. It is virtually impossible due to restrictions.

  In addition, the single crystal Si that forms the device by being transferred to an insulating substrate such as a glass substrate is finally in a thin film state. Therefore, doping such as complex wells and channel stops required for a normal bulk single crystal Si LSI is required. However, there is a need for solution means such as element manufacturing, surface damage recovery after thinning, and a new manufacturing process or device structure including measures for short channels.

  As another technique, there is a method of implanting hydrogen ions or the like into a Si substrate on which at least a part of a single crystal Si device is fabricated, and separating the thin portions by implanting the hydrogen ions or the like. In addition to the above-mentioned problems (element isolation, recovery of Si surface damage after thinning, planarization, simplified device structure without wells, etc., and provision of the manufacturing process), this method provides element isolation (Si island with island etch) Edge defects) and the problem of insufficient stress leakage current reduction.

  The present embodiment described below solves such a problem.

[ Reference form 2 ]
A reference embodiment of the related invention of the present invention will be described below with reference to FIGS.

Note that in the semiconductor substrate and the semiconductor device described in this reference embodiment, a MOS-type non-single-crystal Si thin-film transistor and a MOS-type single-crystal Si thin-film transistor are finally formed in different regions on an insulating substrate such as a glass substrate. The semiconductor device is suitable for high performance and high functionality, and is formed on an active matrix substrate using TFT (Thin Film Transistor).

  The MOS type thin film transistor comprises an active layer, a gate electrode, a gate insulating film, and a high concentration impurity doped portion (source / drain electrode) formed on both sides of the gate, and the carrier concentration of the semiconductor layer under the gate is reduced by the gate electrode. It is a general transistor that is modulated and the current flowing between the source and the drain is controlled.

As a characteristic of the MOS type transistor, a CMOS (Complementary MOS) structure is suitable for low power consumption type logic because it consumes less power and can fully output depending on the power supply voltage. Also in the present reference, it is assumed CMOS (Complementary MOS) structure, drawing one of MOS (Metal Oxide Semiconductor) only not described.

The semiconductor substrate 10 according to this reference embodiment, as shown in FIG. 1, the channel region 17, has an active layer 6 including a source region 4 and drain region 5, the single-crystal Si substrate having no well structure and the channel stop structure A single crystal silicon (Si) wafer (hereinafter referred to as a “single crystal Si wafer”) 8, a gate insulating film 3 formed on the single crystal Si wafer 8, and a gate insulating film 3. And a LOCOS (Local Oxidation of Silicon) oxide film 7 formed on the single crystal Si wafer 8 around the active layer 6 and thicker than the gate insulating film 3. And a planarizing insulating film 1 as an insulating film formed on the gate electrode 2 and the LOCOS oxide film 7.

In the active layer 6, N ⁺ or P ⁺ impurity implanted portions are formed as the source region 4 and the drain region 5 in the element region doped with the shallow reverse conductivity type impurity for threshold control.

That is, the semiconductor substrate 10 according to this reference embodiment, the single-crystal Si wafer 8, LDD (Lightly Doped Drain) structure 4a · 5a or Pocket implantation short channel measures, or Halo implantation (doping) is performed . However, there is no other well implantation and ion implantation for channel stop, and no well contact is formed.

The oxide film 1 is made of, for example, a silicon dioxide (SiO ₂ ) film having a planarized surface, a phosphorus silicate glass (PSG) film, or a boron phosphorus silicate glass (BPSG) film. In a normal LSI, the LOCOS film is one of element isolation means. By forming a thick thermal oxide film (field oxide film) around the active layer 6, the LOCOS film is thicker than the gate electrode crossing the field portion. Since it acts as a gate insulating film and raises the threshold voltage of the parasitic transistor that can be formed here, it plays the role of partitioning the elements, and the elements can be separated.

The LOCOS oxide film 7, in this reference embodiment, has a thickness of approximately 30nm or more and approximately 200nm or less. That is, conventionally, MOSLSI (Large Scale Integrated circuit: large scale integration) in about 500nm or more, with respect to form at least 300nm or more of the LOCOS oxide film, in this reference embodiment, 1/2 to one digit thin, A LOCOS film having a thickness of about 30 nm to about 200 nm or less is grown in the field region 16. In this reference embodiment, in order to remove the Si film portion can aforementioned parasitic transistor, because in practice no parasitic transistor.

  Thereby, a thin film device coexisting with non-single crystal Si can be formed on an insulating substrate such as a large glass substrate. Further, the oxidation treatment time can be greatly shortened, and the treatment can be performed at a practical level by dry oxidation instead of wet oxidation. In particular, since the stress accompanying oxidation at the oxide film edge can be greatly relieved, a transistor with stable characteristics can be formed. Furthermore, since the oxide film can be thin, Bird's Beak can be reduced, and the element region of a fine transistor can be accurately defined.

In the semiconductor substrate 10 according to this reference embodiment, as shown in the figure, to a predetermined depth of the active layer 6 in the monocrystalline Si wafer 8, a predetermined concentration of hydrogen ions, or / and helium (He) An ion-implanted layer 9 in which inert gas ions such as ions are individually or both implanted is formed. Thereby, as will be described later, a part of the single crystal Si wafer 8 can be separated with the ion implantation layer 9 as a boundary.

On the other hand, in this reference embodiment, as shown in FIG. 2, it may be formed a metal wiring layer at least one layer on the semiconductor substrate 10.

That is, the semiconductor substrate 10 is formed on the gate electrode 2 formed on the planarization insulating film 1, the gate insulating film 3 formed on the gate electrode 2, the gate insulating film 3, and For threshold control, an active element having no well structure made of single crystal Si in which an N ⁺ or P ⁺ impurity implanted portion is formed as a source region 4 and a drain region 5 in an element region doped with a shallow reverse conductivity type impurity. Layer 6, a LOCOS oxide film 7 formed so as to surround the active layer 6, a protective insulating film and an interlayer insulating film 21 formed on the active layer 6 and the LOCOS oxide film 7, and the protective insulation Surfaces of the protective insulating film and the interlayer insulating film 21 are connected to the source region 4 and the drain region 5 through contact holes 22 and 22 as connection holes formed in the film and the interlayer insulating film 21, respectively. The metal wiring layers 23 and 23 are formed on each other.

Further, in the present reference embodiment, as shown in FIG. 2, by bonding the semiconductor substrate 10 on the insulating substrate 25 such as a glass substrate to form a semiconductor device 30. That is, as shown in the figure, the semiconductor device 30 includes silicon dioxide (SiO ₂ ) formed on the insulating substrate 25 by plasma CVD using TEOS (Si (OC ₂ H ₅ ) ₄ : Tetra Ethyl Ortho Silicate). ) The semiconductor device 20 is formed through the film 26.

  A method for manufacturing the semiconductor substrates 10 and 20 and the semiconductor device 30 having the above-described configuration will be described with reference to FIGS. 3A to 3G and FIGS. 4A to 4E.

First, as shown in FIG. 3A, a single crystal Si wafer 8 made of single crystal silicon (Si) is prepared, and the surface thereof is oxidized to form a thin silicon dioxide (SiO ₂ ) film 11 having a thickness of about 30 nm. . Subsequently, a silicon nitride (SiN) film 12 is deposited on the entire surface of the silicon dioxide (SiO ₂ ) film 11 by plasma CVD (Chemical Vapor Deposition), and then a portion that becomes an element region. The silicon nitride (SiN) film 12 is left, and the silicon nitride (SiN) film 12 in portions other than the element region is removed by etching.

Next, as shown in FIG. 3B, with the silicon nitride (SiN) film 12 as a mask, an oxide film made of silicon dioxide (SiO ₂ ) of about 120 nm is grown as a field oxide film by dry oxidation, and LOCOS is grown. An oxide film 7 is formed.

Next, as shown in FIG. 3C, the silicon nitride (SiN) film 12 is removed by etching, and an N channel region or a P channel is formed in the element region 13 surrounded by the LOCOS oxide film 7 which is a field oxide film. Boron (B) ions or phosphorus (P) ions are implanted to control the threshold voltage in any one of the channel regions, and the silicon dioxide (SiO ₂ ) film 11 is removed by etching. That is, if boron (B) ions are implanted into the element region 13, a P-type region is formed, and arsenic (As) ions are implanted into this P-type region to form the source region 4 and the drain region 5, as will be described later. Thus, an N-type MOS transistor can be formed. On the other hand, if phosphorus (P) ions are implanted into the element region 13, an N-type region is formed, and boron fluoride (BF ₂ ) ions are implanted into the N-type region to form the source region 4 and the drain region 5. Thus, a P-type MOS transistor can be formed. Further, in the present reference embodiment, it forms the N-type MOS transistor and the P-type MOS transistor at the same time, after completion, the CMOS transistor. The region including the channel region (the region under the gate electrode 2), the source region 4 and the drain region 5 becomes the active layer 6. The channel region under the gate electrode 2 is implanted with impurity ions for adjusting the threshold voltage.

Thereafter, as shown in FIG. 3D, 15 nm of silicon dioxide (SiO ₂ ) is grown by dry oxidation as the gate insulating film 3.

Next, as shown in FIG. 3E, a polycrystalline silicon (Si) (hereinafter abbreviated as “Poly-Si”) film having a thickness of about 300 nm is deposited on the gate insulating film 3 and is not shown. Deposit phosphorus oxychloride (POCl ₃ ) and diffuse at 800 ° C. This is patterned as the gate electrode 2, boron (B) or phosphorus (P) ions are implanted to form the LDD structures 4a and 5a, and about 300 nm of silicon dioxide (SiO ₂ ) is deposited thereon, The sidewalls 15 and 15 are formed by etching back by reactive ion etching (RIE).

Subsequently, arsenic (As) ions or boron fluoride (BF ₂ ) ions are implanted as source / drain regions, and activation annealing is performed at about 900 ° C. Thereby, the source region 4 and the drain region 5 are formed. Next, about 100 nm of silicon dioxide (SiO ₂ ) is deposited by APCVD (Atmospheric Pressure CVD), and further about 400 nm of silicon dioxide (SiO ₂ ) film is formed by PECVD (Plasma Enhanced CVD: Plasma CVD using TEOS). ) And polished by CMP (Chemical Mechanical Polishing) for about 100 nm to planarize the surface to obtain a planarized insulating film 1.

Next, as shown in FIG. 3F, for example, hydrogen (H) ions are implanted into the single crystal Si wafer 8 from above the planarization insulating film 1. Here, hydrogen (H) ions are implanted into the ion implantation layer 9 with an energy of 100 keV at a dose of 5.5 × 10 ¹⁶ cm ⁻² . Note that the hydrogen (H) ion is not necessarily limited thereto, and for example, helium (He) ion or the like can be used. Further, in the present reference embodiment, the depth of the active layer 6 made of single crystal Si of the ion implantation layer 9, and adjusting the implantation energy so as to be within the lower portion of the Si crystal of the LOCOS oxide film 7.

Thereafter, as shown in FIG. 3 (g), the above is turned over and the surface of an insulating substrate 25, which is a separately prepared insulating substrate, is formed on the surface of silicon dioxide (about 100 nm by plasma CVD using TEOS and oxygen gas. With the formation of SiO ₂ ), megasonic is superimposed on the shower of a mixed liquid of ammonia water, hydrogen peroxide water and pure water (SC1 liquid), cleaning and surface activation are performed, and the planarization insulation is performed. A marker position (not shown) on the film 1 is aligned and bonded in close contact as shown in FIG. Here, the insulating substrate 25 is bonded to the planarization insulating film 1 by van der Waals force and hydrogen bonding. Instead of the surface activation by the SC1 cleaning, the surface may be activated by exposure to oxygen plasma. In addition, although the insulating substrate 25 is described as having the same size as the semiconductor substrate 10 in FIG. 5G, in reality, it may be a large glass plate having an area larger than that of many semiconductor substrates 10. In the present reference embodiment, insulating substrate 25, for example, Corning tradename - have a glass of "Code 1737 (alkaline earth alumino borosilicate glass)".

  This is then annealed at about 250 ° C. for 2 hours to strengthen the bond. Thereafter, when heat treatment is performed at about 600 ° C. for 3 minutes, as shown in FIG. 4B, the single crystal Si wafer 8 is separated by cleaving with the ion implantation layer 9 (projection range of hydrogen ion implantation) as a boundary.

Next, as shown in FIG. 4C, about 100 nm of silicon dioxide (SiO ₂ ) is deposited on the surface after separation by plasma CVD using TEOS and oxygen gas, and reactive ion etching (RIE) is performed. Etch back. At that time, a gas in which hydrogen is mixed with carbon fluoride (CF ₄ ) is used first. After the etching of about 100 nm, the reactive ion etching (RIE) is continued by switching to a gas in which oxygen is mixed with fluorocarbon (CF ₄ ), and the single crystal Si wafer 8 on the LOCOS oxide film 7 which is a field oxide film disappears. The etching is stopped at the place. Since the end point is difficult to monitor, the etching is stopped according to the time determined from the etching rate.

Thereafter, as shown in FIG. 4D, the surface is lightly etched with buffered hydrofluoric acid (HF), the substrate temperature is raised to 380 ° C., and a silicon dioxide (SiO ₂ ) film of about 400 nm is formed by PECVD using TEOS. A protective insulating film and an interlayer insulating film 21 are deposited.

  Next, as shown in FIG. 4E, contact holes 22 and 22 as openings are formed in the protective insulating film and interlayer insulating film 21, and metal wiring material is deposited to form metal wiring layers 23 and 23. And Here, Ti / TiN / Al—Si / TiN / Ti and the total film thickness is about 400 nm. By processing this into a predetermined pattern, as shown in FIG. 2B, a semiconductor device 30 having a large number of single crystal Si TFTs on the insulating substrate 25 is completed.

  The CMOS inverter, which is a basic circuit element of the semiconductor device formed in this way, is shown as in FIG. 5A, and has a much larger area than the conventional CMOS inverter shown in FIG. It has been reduced.

As described above, the semiconductor substrate 10, 20 of this reference embodiment is a MOS transistor of the monocrystalline Si formed on the element region surrounded by a thin field oxide film. Since there is no well, the structure is simplified, yield improvement and cost reduction effects are obtained, and this does not operate by itself, but operates at high performance after being transferred to an insulating substrate 25 such as another glass substrate. In addition, the semiconductor device 30 includes a MOS type non-single crystal Si thin film transistor including a non-single crystal Si thin film made of SiO ₂ film, polycrystalline Si, and a MOS type single crystal including a single crystal Si thin film on an insulating substrate 25. Si thin film transistor and metal wiring are provided.

Further, in the present reference embodiment, surrounded by a field oxide film, for the threshold voltage determined region respectively the n-channel and p-channel, respectively implanted boron or phosphorus ions of a predetermined concentration, the gate insulating film 3, a gate electrode 2. Further, if necessary, LDD, HALO or Pocket implantation, N ⁺ and P ⁺ implantation for the source region 4 and drain region 5, a flattening film, etc. are formed, and hydrogen ions or He at a predetermined concentration and a predetermined depth are formed. Implanting ions alone or ions such as He and Ne, cutting them into a predetermined shape, and activating the surface with oxygen plasma, hydrogen peroxide, RCA1 cleaning solution (SCl), etc. The bulk single crystal S is bonded to the insulating substrate 25 on which the non-single-crystal Si TFT or a part thereof is formed, and heat-treated after bonding. The i portion is cleaved and separated by using the ion implantation layer 9 as a boundary to form a thin film. By doing so, for example, a thin film device coexisting with non-single-crystal Si is transferred onto a large glass substrate or the like.

  Next, this single crystal Si surface is etched back by RIE (Reactive Ion Etching), thinned, and etched until the Si film on the LOCOS oxide film 7 disappears. A fine transistor region is defined without alignment, and element isolation can be performed.

A silicon dioxide (SiO ₂ ) film is formed on the surface of the single crystal Si thin film that has been cleaved and separated to form a thin film by PECVD or the like using TEOS or the like. By appropriately selecting the gas composition (for example, CF ₄ and hydrogen) and performing etch back, the surface is planarized, and the leakage current of the final device can be reduced.

  By this process, regions such as wells, ion implantation such as channel stop, contacts, etc. necessary for a normal MOS LSI can be eliminated, and both the space and the process are greatly simplified.

  In this way, the film thickness of the single crystal Si thin film becomes approximately ½ or less of the total film thickness of the Si oxide film (LOCOS oxide film 7) surrounding the active layer 6, and the pattern edge of the single crystal Si thin film is active. Leakage caused by defects and stress at the Si island edge in the conventional island etch, which is formed so as to substantially overlap with the inclined portion of the Si oxide film pattern edge surrounding the layer 6 to achieve element isolation. Current.

  Further, a protective insulating film and an interlayer insulating film 21 are deposited thereon, a contact hole 22 is opened, and a metal wiring layer 23 is formed, thereby completing the device.

  Here, the protective insulating film and the interlayer insulating film 21 may be made of the same material as long as they have the functions and characteristics.

  Further, after implanting hydrogen ions or the like, a wiring and a contact are formed with a metal material having a high melting point and difficult to oxidize, a planarizing film is further deposited, and planarization suitable for bonding the insulating substrate 25 by CMP or the like. Then, bonding to an insulating substrate 25 such as a glass substrate, heat treatment, and cleaving separation of bulk Si can achieve further miniaturization and improved integration density.

Thus, in this reference embodiment of the semiconductor substrate 10 and the semiconductor device 30 and methods for their preparation, the channel region 17, has an active layer 6 including a source region 4 and drain region 5, the well structure and the channel stop region The single crystal Si wafer 8 that does not have is used.

  Therefore, since it is made of single crystal Si, it is possible to form a semiconductor having high performance and low device performance.

Further, in the present reference embodiment, a conventional well, a channel stop, since the well contact is not present, it is possible to reduce the area of the element region 13, due to the miniaturization of the element region 13, it is possible to increase the integration density, The semiconductor substrate 10 is highly integrated. Furthermore, since there is no conventional well, the depth can be reduced by the amount of no well. As a result, since the semiconductor element can be formed in a thin film, when the semiconductor device 30 is formed, for example, coexistence with other TFTs made of polycrystalline Si, and the two are interconnected with a thin film. It becomes possible to connect. Furthermore, since it can be formed into a thin film, even in an insulating substrate 25 such as a large glass substrate, element isolation of a fine single crystal Si device can be realized without high-precision photolithography. Furthermore, since a well or the like is not formed, the manufacturing process is simple.

Further, in the present reference embodiment, so as to surround the periphery of the active layer 6, a thick LOCOS oxide film 7 having a film thickness than the gate insulating film 3 is formed. Therefore, element isolation is reliably achieved by the LOCOS oxide film 7.

As a result, a non-single crystal Si semiconductor element and a single crystal Si semiconductor element are formed on a large insulating substrate 25, and a manufacturing process of a single crystal Si portion is performed when manufacturing a semiconductor device 30 in which a high performance system is integrated. The semiconductor substrate 10 capable of realizing element separation of a fine single crystal Si semiconductor element without high-precision photolithography after being transferred to a large insulating substrate 25 and a method for manufacturing the same can be provided. In the present reference embodiment, insulating substrate 25, although a large, in the present invention, the insulating substrate 25 is not necessarily large.

Further, in the present reference embodiment of the semiconductor substrate 10 and the semiconductor device 30 as well as its production method thereof, the source region 4 and drain region 5 of the active layer 6 has at least LDD structure. Therefore, the change in the concentration distribution of the impurity in the vicinity of the drain becomes gradual, and the electric field strength in the vicinity of the drain region 5 can be reduced, thereby contributing to the improvement of reliability.

Further, in the semiconductor substrate 10 and the semiconductor device 30 as well as their production method of the present reference embodiment, the upper surface of the planarization insulating film 1 is planarized. Therefore, an insulating substrate 25 such as a flat glass substrate can be bonded onto the planarizing insulating film 1.

Incidentally, in the conventional MOSLSI, about 500nm or more, while forming at least 300nm or more of the LOCOS oxide film, in this reference embodiment of the semiconductor substrate 10 and the semiconductor device 30 and methods for their preparation, an order of magnitude thinner, approximately 30nm The LOCOS oxide film 7 of approximately ½ and 200 nm or less is grown as the field region 16 as described above.

  As a result, the oxidation process time can be greatly shortened, and the process can be performed at a practical level by dry oxidation rather than wet oxidation. In particular, the stress associated with oxidation of the oxide film edge can be greatly relieved, and a transistor with stable characteristics can be obtained. Can be formed. In addition, since the oxide film can be thin, Bird's Beak can be reduced, and the element region of a fine transistor can be accurately defined.

Further, in the present reference embodiment of the semiconductor substrate 10 and the semiconductor device 30 and methods for their preparation, to a predetermined depth in the single crystal Si wafer 8, one or more selected from among hydrogen ions and inert element ion Since the ion-implanted layer 9 formed by ion implantation is formed, when the heat treatment is performed, the ion-implanted layer 9 can be cleaved and thinned. By doing so, for example, a thin film device coexisting with non-single crystal Si can be transferred onto a large insulating substrate or the like.

Further, in the present reference embodiment of the semiconductor substrate 10 and the semiconductor device 30 and methods for their preparation, the ion implantation layer 9, is formed to a predetermined depth in the single crystal Si wafer 8 below the LOCOS oxide film 7 Therefore, by etching back the surface of the single crystal Si thin film that has been cleaved and separated and thinned to the injection side surface of the LOCOS oxide film 7, the surface is flattened, and the leakage current of the final device can be reduced.

Further, in the present reference embodiment of the semiconductor substrate 10, 20 and the semiconductor device 30 and methods for their preparation, since the LOCOS oxide film 7 can be formed into a thin film can be formed by dry oxidation. Therefore, stress associated with oxidation of the oxide film edge can be greatly relieved, so that a transistor with stable characteristics can be formed.

Further, the semiconductor device 30 according to this reference embodiment includes an insulating substrate 25, because it contains a single-crystal Si semiconductor element formed on the insulating substrate 25, for example, single crystal and the insulating substrate 25 such as a glass plate The Si semiconductor element is integrated.

  The single crystal Si semiconductor element includes a gate electrode 2 formed above the insulating substrate 25, a gate insulating film 3 formed on the gate electrode 2, and a channel region 17 formed on the gate insulating film 3. , An active layer 6 composed of a single-crystal Si layer including the source region 4 and the drain region 5, a LOCOS oxide film 7 formed around the active layer 6, and a protection formed on the active layer 6 and the LOCOS oxide film 7. An insulating film and an interlayer insulating film 21 are included.

  As a result, the non-single crystal Si semiconductor element and the single crystal Si semiconductor element are formed on the large insulating substrate 25, and the manufacturing process of the single crystal Si portion is performed when manufacturing the semiconductor device 30 in which the high performance system is integrated. It is possible to provide a semiconductor device 30 which can be simplified and transferred to a large insulating substrate 25 and can realize element isolation of a fine single crystal Si semiconductor element without high-precision photolithography.

In the semiconductor device 30 according to the reference embodiment of the present invention, the source region 4 and the interlayer insulating film 21 are formed on the protective insulating film and the interlayer insulating film 21 through the contact holes 22 and 22 provided in the protective insulating film and the interlayer insulating film 21. A metal wiring layer 23 connected to the drain region 5 is included.

A method of manufacturing a semiconductor device 30 according to this reference embodiment, the semiconductor substrate 10, 20 produced by the production method of the semiconductor substrate 10, 20, and bonding on the insulating substrate 25, heat treatment is performed Then, the single crystal Si wafer 8 is divided with the ion implantation layer 9 as a boundary, and a single crystal Si substrate peeling step for peeling a part of the single crystal Si wafer 8 is performed, and the single crystal Si wafer 8 on the insulating substrate 25 is etched. A step of exposing the surface of the LOCOS oxide film 7; a step of forming a protective insulating film and an interlayer insulating film 21 on the active layer 6 and the LOCOS oxide film 7; A step of forming a metal wiring layer 23 connected to the source region 4 and the drain region 5 through the contact holes 22 and 22 formed in the protective insulating film and the interlayer insulating film 21.

  According to the above, the metal formed on the protective insulating film and the interlayer insulating film 21 and connected to the source region 4 and the drain region 5 through the contact holes 22 and 22 provided in the protective insulating film and the interlayer insulating film 21. A wiring layer 23 is provided. Therefore, the semiconductor device 30 having the metal wiring layer 23 connected to another circuit, a power source or the like by this metal wiring layer. In addition, the metal wiring layer 23 can be formed after the semiconductor substrate 10 having a non-single-crystal Si semiconductor element is bonded to the insulating substrate 25.

  As a result, the non-single crystal Si semiconductor element and the single crystal Si semiconductor element are formed on the large insulating substrate 25, and the manufacturing process of the single crystal Si portion is performed when manufacturing the semiconductor device 30 in which the high performance system is integrated. It is possible to provide a semiconductor device 30 and a method for manufacturing the same that can be simplified and can realize element isolation of a fine single crystal Si semiconductor element without high-precision photolithography after being transferred to a large insulating substrate 25.

Further, in the present reference embodiment of the semiconductor substrate 10, 20 and the semiconductor device 30 and methods for their preparation, the upper surface of the active layer 6 and is in a position lower than the upper surface of the LOCOS oxide film 7 was thinned cleavage separated By etching back the surface of the single crystal Si thin film, the leakage current of the final device can be reduced.

Further, in the present reference embodiment of the semiconductor substrate 10, 20 and the semiconductor device 30 and methods for their preparation, since the end portion of the active layer 6 is formed so as to overlap the inclined portion of the end portion of the LOCOS oxide film 7 In addition, a device-isolated structure can be realized, and the Si island edge defects and the leakage current resulting from stress in the conventional island etch can be reduced.

Further, in the semiconductor device 30 and the manufacturing method of the present reference embodiment, as shown in FIG. 6, whereas the single-crystal Si semiconductor element in a partial region of the insulating substrate 25 is formed, in another area, the non A single crystal Si semiconductor element is formed.

  Therefore, the single crystal Si semiconductor element and the non-single crystal Si semiconductor element can coexist on the insulating substrate 25.

  By the way, conventionally, in a display device such as a liquid crystal display device, a switching transistor of each pixel made of a non-single-crystal Si semiconductor element is formed on an insulating substrate 25 such as a glass substrate, and a wiring pattern is further formed. The display driving circuit for driving the unit or the processing circuit for outputting a predetermined signal to the display driving circuit is mounted by COG or COF made of a single crystal Si semiconductor element and then connected to the wiring pattern. there were.

However, according to this reference embodiment, at least a portion of the non-single-crystal Si semiconductor device, as shown in FIG. 7, is intended to constitute the switching transistor of each pixel constituting the display unit 71, also single The transistors composed of crystalline Si semiconductor elements constitute display drive circuits 72 and 73 for driving the display unit 71 or processing circuits 74 and 75 for outputting predetermined signals to the display drive circuits 72 and 73. Therefore, it is used as a constituent substrate of the display device 70.

  Therefore, after forming at least a part of the non-single-crystal Si semiconductor element and a part of the single-crystal Si semiconductor element on the insulating substrate 25, both wiring layers can be formed in common. As a result, the semiconductor device 30 for forming a high-quality display device with high productivity can be provided.

In each manufacturing method of the semiconductor device 30 of the present reference embodiment, the surface of the semiconductor substrate 10 and the insulating substrate 25, by washing with washing water containing hydrogen peroxide, or by exposure to a plasma containing oxygen After activation, a substrate bonding step is performed.

  As a result, the semiconductor substrates 10 and 20 and the insulating substrate 25 can be joined without an adhesive by van der Waals force and hydrogen bonding. This bond changes to a strong Si—O bond in the subsequent heat treatment step.

In the manufacturing method of the semiconductor device 30 of the present reference embodiment, the heat treatment in the single-crystal Si substrate peeling step, performed substantially 250 ° C. or higher and at a temperature substantially 600 ° C..

  Accordingly, the single crystal Si semiconductor element can be heated to a temperature at which, for example, hydrogen ions are separated from Si, and the bonding strength to the insulating substrate 25 can be increased, and a part of the single crystal Si wafer 8 is bordered on the ion implantation layer 9. Can be cleaved and peeled off.

[Form state of implementation]
The embodiment of the present invention will be described with reference to FIGS. 8 to 11 as follows. Note that the configuration other than those described in the present embodiment is the same as Embodiment 2 of the reference. For convenience of explanation, members having the same functions as those shown in the drawings of the reference embodiment 2 are given the same reference numerals and explanations thereof are omitted.

In the semiconductor substrate 10 and the semiconductor device 30 according to the second of said reference, as shown in FIG. 2, the metal wiring layers 23, 23 is a take-out electrode through the contact hole 22, 22 of the protective insulating film and the interlayer insulating film 21, It was directly connected to the source region 4 and the drain region 5.

  However, in the semiconductor device 50 of the present embodiment, as shown in FIG. 8, the first metal wirings 42 and 42 as the first wiring layers connected to the source region 4 and the drain region 5 are once described later. The semiconductor substrate 40 and the semiconductor device 50 are taken out to the back surface side, and the second wiring layer is formed as a second wiring layer formed on the surface of the semiconductor substrate 40 and the semiconductor device 50 again in the field region 16 around the element region 13. The difference is that the metal wiring 45 is formed.

  That is, the semiconductor substrate 40 of the present embodiment includes an insulating substrate 25 and a single crystal Si semiconductor element formed on the insulating substrate 25 as shown in FIG.

  The single crystal Si semiconductor element includes a gate electrode 2 formed above the insulating substrate 25, a gate insulating film 3 formed on the gate electrode 2, and a channel formed on the gate insulating film 3. An active layer 6 composed of a single crystal Si layer including the region 17, the source region 4 and the drain region 5, a LOCOS oxide film 7 formed around the active layer 6, and the active layer 6 and the LOCOS oxide film 7. A protective insulating film and an interlayer insulating film 21, an interlayer insulating film 43 as an insulating film formed between the insulating substrate 25 and the gate electrode 2, and a lower surface side of the interlayer insulating film 43. The first metal wirings 42 and 42 of at least one layer formed and the second metal wiring 45 formed on the protective insulating film and the interlayer insulating film 21 and connected to the first metal wirings 42 and 42 are provided. is doing.

The active layer 6 is made of a single crystal Si having a source region 4 and a drain region 5 with N ⁺ or P ⁺ impurity implanted portions in a device region doped with a shallow reverse conductivity type impurity for threshold control. The active layer 6 is not formed.

  The first metal wirings 42 and 42 are connected to the source region 4 and the drain region 5 through contact holes 41 and 41 as connection holes formed in the insulating film 1 and the gate insulating film 3, respectively. The back surface of the insulating film 1 is exposed. Further, the second metal wiring 45 is connected to the first metal wirings 42 and 42 and serves as a connection hole formed in the insulating film 1, the gate insulating film 3, the protective insulating film and the interlayer insulating film 21. It is formed on the surface of the protective insulating film and the interlayer insulating film 21 through the contact hole 44.

Further, as shown in the figure, the semiconductor device 50 is formed by forming the semiconductor substrate 40 on an insulating substrate 25 such as a glass substrate. Specifically, the semiconductor device 50 is formed on the insulating substrate 25 on a silicon dioxide (SiO ₂ ) film 26 formed by plasma CVD using TEOS.

A method for manufacturing the semiconductor substrate 40 and the semiconductor device 50 having the above-described configuration will be described with reference to FIGS. 7 (a) to 7 (g) and FIGS. 8 (a) to 8 (e). 7A to 7F are the same as the steps of FIGS. 3A to 3F in the second embodiment.

That is, as shown in FIG. 9 (a), similarly to Embodiment 2 of the reference, First, a single crystal Si wafer 8 made of single crystal silicon (Si), thin to about 30nm by oxidizing the surface A silicon dioxide (SiO ₂ ) film 11 is formed. Subsequently, a silicon nitride (SiN) film 12 is deposited on the entire surface of the silicon dioxide (SiO ₂ ) film 11 by plasma CVD (Chemical Vapor Deposition), and then a portion that becomes an element region. The silicon nitride (SiN) film 12 is left, and the silicon nitride (SiN) film 12 in portions other than the element region is removed by etching.

Next, as shown in FIG. 9B, using the silicon nitride (SiN) film 12 as a mask, an oxide film made of silicon dioxide (SiO ₂ ) of about 120 nm is grown as a field oxide film by dry oxidation, and LOCOS is grown. An oxide film 7 is formed.

Next, as shown in FIG. 9C, the silicon nitride (SiN) film 12 is removed by etching, and an N channel region or a P channel is formed in the element region 13 surrounded by the LOCOS oxide film 7 which is a field oxide film. Boron (B) ions or phosphorus (P) ions are implanted to control the threshold voltage in any one of the channel regions, and the silicon dioxide (SiO ₂ ) film 11 is removed by etching. The region including the channel region (the region under the gate electrode 2), the source region 4 and the drain region 5 becomes the active layer 6. The channel region under the gate electrode 2 is implanted with impurity ions for adjusting the threshold voltage.

Thereafter, as shown in FIG. 9D, 15 nm of silicon dioxide (SiO ₂ ) is grown as the gate insulating film 3 by dry oxidation.

Next, as shown in FIG. 9E, a polycrystalline silicon (Si) (hereinafter abbreviated as “Poly-Si”) film having a thickness of about 300 nm is deposited on the gate insulating film 3 and is not shown. Deposit phosphorus oxychloride (POCl ₃ ) and diffuse at 800 ° C. Patterning this as the gate electrode 2, implanting phosphorus (P) and boron (B) ions to form the LDD structures 4a and 5a, and HALO ion implantation of the opposite type to LDD for countermeasures against the short channel effect Then, it is deposited as about 300 nm of silicon dioxide (SiO ₂ ) from above, and etched back by reactive ion etching (RIE) to form sidewalls 15 and 15.

Subsequently, arsenic (As) ions or boron fluoride (BF ₂ ) ions are implanted as the source region 4 and the drain region 5, and activation annealing is performed at about 900 ° C. Thereby, the source region 4 and the drain region 5 are formed. Next, about 100 nm of silicon dioxide (SiO ₂ ) is deposited by APCVD (Atmospheric Pressure CVD), and further about 400 nm of silicon dioxide (SiO ₂ ) film is formed by PECVD (Plasma Enhanced CVD: Plasma CVD using TEOS). ) And polished by CMP (Chemical Mechanical Polishing) for about 100 nm to planarize the surface to obtain a planarized insulating film 1.

Next, as shown in FIG. 9F, hydrogen (H) ions are implanted into the single crystal Si wafer 8 from above the insulating film 1. Here, hydrogen (H) ions are implanted into the ion implantation layer 9 with an energy of 100 keV at a dose of 5.5 × 10 ¹⁶ cm ⁻² . In this embodiment, the depth of the ion implantation layer 9 in the active layer 6 made of single-crystal Si sets energy in the Si crystal below the Si (lower part of the LOCOS oxide film 7).

From here, it becomes a process different from the said reference form 2 .

That is, in the present embodiment, as shown in FIG. 9G, a 200 nm silicon dioxide (SiO ₂ ) film is further deposited thereon, contact holes 41 and 41 are opened, and metal wiring is formed thereon. The material is deposited to form first metal wirings 42 and 42. Here, the first metal wirings 42 and 42 have a total film thickness of about 400 nm with Ti / TiN / Ti taking into consideration the heat-resistant temperature. This is processed into a predetermined pattern.

Next, a silicon dioxide (SiO ₂ ) film having a thickness of about 400 nm is deposited thereon by PECVD using TEOS, and the portions other than the first metal wirings 42 and 42 and their surroundings are left, and reactive ion etching (RIE) is performed. ) Etch back. Further, a 500 nm silicon dioxide (SiO ₂ ) film is deposited and planarized by CMP to form an interlayer insulating film 43.

Thereafter, as shown in FIG. 10 (a), the above is cut into a predetermined shape, and about 100 nm is formed on the surface of an insulating substrate 25 made of a separately prepared glass substrate by plasma CVD using TEOS and oxygen gas. Silicon dioxide (SiO ₂ ) is formed, megasonic is superimposed on the SCl cleaning liquid shower, cleaning and surface activation are performed, and alignment with a marker (not shown) on the interlayer insulating film 43 is performed. As shown in b), they are bonded in close contact. Here, the insulating substrate 25 is bonded to the insulating film 1 by Van der Waals force and hydrogen bonding. In addition, although the insulating substrate 25 is described as being the same size as the semiconductor substrate 40 in FIG. 2B, it is actually a large glass plate corresponding to the area of many semiconductor substrates 10. In the present embodiment, the insulating substrate 25 is made of, for example, glass having a trade name “code1737 (alkaline earth-aluminoborosilicate glass)” by Corning.

  This is then annealed at about 250 ° C. for 2 hours to strengthen the bond. Thereafter, when heat treatment is performed at about 600 ° C. for 3 minutes, as shown in FIG. 10C, the ion implantation layer 9 (peak position of hydrogen ion implantation) is cleaved, and the single crystal Si wafer 8 is separated.

Next, as shown in FIG. 10D, about 100 nm of silicon dioxide (SiO ₂ ) is deposited on the separated surface by plasma CVD using TEOS and oxygen gas, and reactive ion etching (RIE) is performed. Etch back. At that time, a gas in which hydrogen is mixed with carbon fluoride (CF ₄ ) is used first. After the etching of about 100 nm, the reactive ion etching (RIE) is continued by switching to a gas in which oxygen is mixed with fluorocarbon (CF ₄ ), and the single crystal Si wafer 8 on the LOCOS oxide film 7 which is a field oxide film disappears. The etching is stopped at the place. Since the end point is difficult to monitor, the etching is stopped according to the time determined from the etching rate.

Thereafter, as shown in FIG. 10E, the surface is lightly etched with buffered hydrofluoric acid (HF), the substrate temperature is raised to 380 ° C., and the silicon dioxide (SiO ₂ ) film of about 400 nm is formed by PECVD using TEOS. To form a protective insulating film and an interlayer insulating film 21.

  Next, a contact hole 44 as a connection hole is opened in the protective insulating film and the interlayer insulating film 21, and a metal wiring material is deposited to form a second metal wiring 45. Here, Ti / TiN / Al—Si / TiN / Ti and the total film thickness is about 400 nm. By processing this into a predetermined pattern, a semiconductor device 50 having a single crystal Si semiconductor substrate 40 on an insulating substrate 25 is completed as shown in FIG.

  In the semiconductor device 50 described above, the first metal wiring 42 is directly connected to the second metal wiring 45. However, the second metal wiring 45 is not necessarily limited to this. For example, As shown in FIG. 11, the first metal wiring layer 42 may be connected to the first metal wiring layer 42 via a relay electrode made of the gate layer 2a. In this case, the second metal wiring 45 is connected to the gate layer 2a. Since the contact hole for connecting to the electrode for use can be made shallow, the yield is improved. That is, the first metal wiring 42 is connected through the contact hole to the gate, and the back surface side thereof is connected to the second metal wiring 45.

  As described above, the semiconductor substrate 50 of the present embodiment includes the insulating substrate 25 and the single crystal Si semiconductor element formed on the insulating substrate 25.

  The single crystal Si semiconductor element includes a gate electrode 2 formed above the insulating substrate 25, a gate insulating film 3 formed on the gate electrode 2, and a channel formed on the gate insulating film 3. An active layer 6 composed of a single crystal Si layer including the region 17, the source region 4 and the drain region 5, a LOCOS oxide film 7 formed around the active layer 6, and the active layer 6 and the LOCOS oxide film 7. A protective insulating film and an interlayer insulating film 21, an interlayer insulating film 43 as an insulating film formed between the insulating substrate 25 and the gate electrode 2, and a lower surface side of the interlayer insulating film 43. The first metal wirings 42 and 42 of at least one layer formed and the second metal wiring 45 formed on the protective insulating film and the interlayer insulating film 21 and connected to the first metal wirings 42 and 42 are provided. is doing.

  Therefore, the semiconductor device 50 having the second metal wiring 45 can be formed. Further, the semiconductor device 50 can be manufactured by bonding the semiconductor substrate 40 to the insulating substrate 25.

  By the way, when the first wiring layer is formed, including the above case, in general, in order to improve the integration density of the integrated circuit, it is necessary to form a plurality of wiring layers and efficiently use the space. However, this is because it becomes difficult to form a wiring pattern when the element region becomes minute.

  Therefore, in the semiconductor substrate 40 and the semiconductor device 50 according to the present embodiment, at least one layer of the first metal wirings 42 and 42 formed on the lower surface side of the planarization insulating film 1, the protective insulating film, and the interlayer insulating film 21. And a second metal wiring 45 formed on the first metal wiring and connected to the first metal wiring.

  Therefore, wiring can be efficiently routed using the space on the back side of the element region, and the integration density can be increased.

  In the semiconductor substrate 40 of the present embodiment, since the first metal wirings 42 and 42 as at least one wiring layer are formed on the planarization insulating film 1, the first metal wiring 42 is formed. 42 can be an electrode for external extraction from the source region 4 and the drain region 5. In FIG. 6, the first metal wirings 42 and 42 are one layer, but the present invention is not necessarily limited to this, and a plurality of metal wiring layers can be provided.

  In the semiconductor substrate 40, the semiconductor device 50, and the manufacturing method thereof according to the present embodiment, the first metal wirings 42 and 42 have a heat resistance temperature (melting point or reaction temperature with Si, whichever is lower) of about 500. Since it is made of a material having a temperature equal to or higher than ° C., the first metal wirings 42 and 42 are not melted in the manufacturing process.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the claims, and the technical means disclosed in different embodiments can be appropriately combined. Such embodiments are also included in the technical scope of the present invention.

  In order to solve the above problems, a semiconductor substrate of the present invention includes a single crystal Si substrate having an active layer including a channel region, a source region, and a drain region, and not having a well structure and a channel stop region, and the single crystal Si. A gate insulating film formed on the substrate, a gate electrode formed on the gate insulating film, and a film thickness larger than the gate insulating film formed on the single crystal Si substrate around the active layer A thick LOCOS oxide film, and an insulating film formed on the gate electrode and the LOCOS oxide film.

  Further, in order to solve the above problems, a method for manufacturing a semiconductor substrate according to the present invention includes a step of forming a LOCOS oxide film outside an element region in a single crystal Si substrate, and a gate insulating film in the element region in the single crystal Si substrate. Forming a gate electrode on the gate insulating film, and forming a source region, a drain region, and a channel region by selectively implanting impurities into the element region of the single crystal Si substrate. Then, an active layer including the channel region, the source region, and the drain region is formed, and an insulating film whose upper surface is flattened by CMP or the like is formed on the gate electrode, the gate insulating film, and the LOCOS oxide film. And implanting one or a plurality of ions selected from hydrogen ions and inert element ions through the planarization insulating film. Ri is characterized in that it comprises a step of forming an ion-implanted layer to a predetermined depth in the single crystal Si substrate.

  Further, in order to solve the above problems, a method for manufacturing a semiconductor substrate according to the present invention includes a step of forming a LOCOS oxide film outside an element region in a single crystal Si substrate, and a gate insulating film in the element region in the single crystal Si substrate. Forming a gate electrode on the gate insulating film, and forming a source region, a drain region, and a channel region by selectively implanting impurities into the element region of the single crystal Si substrate. Forming an active layer including the channel region, the source region, and the drain region, and forming an insulating film having a planarized upper surface on the gate electrode, the gate insulating film, and the LOCOS oxide film; By implanting one or more ions selected from hydrogen ions and inert element ions through the planarization insulating film, It is characterized by a step of forming an ion-implanted layer to a predetermined depth in the Si substrate.

  Further, in order to solve the above problems, a method for manufacturing a semiconductor substrate according to the present invention includes a step of forming a LOCOS oxide film outside an element region in a single crystal Si substrate, and a gate insulating film in the element region in the single crystal Si substrate. Forming a gate electrode on the gate insulating film, and forming a source region, a drain region, and a channel region by selectively implanting impurities into the element region of the single crystal Si substrate. Then, an active layer including the channel region, the source region, and the drain region is formed, and a first insulating film having a flat upper surface is formed on the gate electrode, the gate insulating film, and the LOCOS oxide film. And implanting one or more ions selected from hydrogen ions and inert element ions through the planarized first insulating film. The step of forming an ion implantation layer at a predetermined depth in the single crystal Si substrate and at least one layer via an interlayer insulating film formed directly or separately above the first insulating film The method includes a step of forming a first wiring layer and a step of forming a second insulating film on the first wiring layer.

  According to the above invention, the semiconductor substrate is a single crystal Si substrate having an active layer including a channel region, a source region, and a drain region, and not having a well structure and a channel stop region.

  Therefore, since it is made of single crystal Si, it is possible to form a semiconductor having high performance and low device performance.

  In the present invention, since there is no conventional well, channel stop, or well contact, the area of the element region can be reduced, and the integration density can be increased by miniaturization of the element region, thereby achieving high integration. The resulting semiconductor substrate. Furthermore, since there is no conventional well, the depth can be reduced by the amount of no well. As a result, since the semiconductor element can be formed in a thin film, when the semiconductor device is formed, for example, coexistence with other TFTs made of polycrystalline Si, and the two are interconnected with a thin film. It becomes possible to do. Furthermore, since it can be formed into a thin film, even in an insulating substrate such as a large glass substrate, element separation of a fine single crystal Si device can be realized without high-precision photolithography. Furthermore, since a well or the like is not formed, the manufacturing process is simple.

  In the present invention, a LOCOS oxide film thicker than the gate insulating film is formed so as to surround the periphery of the active layer. Therefore, element isolation is reliably achieved by the LOCOS oxide film.

  As a result, non-single-crystal Si semiconductor elements and single-crystal Si semiconductor elements are formed on a large insulating substrate, and the manufacturing process of the single-crystal Si portion is simplified when manufacturing a semiconductor device in which a high-performance system is integrated. In addition, it is possible to provide a semiconductor substrate that can realize element isolation of a fine single crystal Si semiconductor element without high-precision photolithography after being transferred to a large insulating substrate, and a manufacturing method thereof.

  The semiconductor substrate of the present invention is characterized in that, in the semiconductor substrate described above, the source region and the drain region of the active layer have an LDD structure.

  Therefore, the change in the impurity concentration distribution in the vicinity of the drain becomes gentle, the electric field strength in the vicinity of the drain region can be reduced, and the reliability can be improved.

  The semiconductor substrate of the present invention is characterized in that, in the semiconductor substrate described above, the upper surface of the insulating film is highly planarized by CMP or the like.

  Therefore, a flat insulating substrate such as a glass substrate can be bonded onto the insulating film.

  The semiconductor substrate of the present invention is characterized in that in the semiconductor substrate described above, at least one wiring layer is formed on the insulating film.

  According to the above invention, since at least one wiring layer made of, for example, metal is formed on the insulating film, the wiring layer can be connected to other circuits, power supplies, and the like.

  The semiconductor substrate of the present invention is characterized in that, in the semiconductor substrate described above, the LOCOS oxide film has a thickness of about 30 nm or more and about 200 nm or less.

  In other words, in a normal MOS LSI, a LOCOS oxide film having a thickness of about 500 nm or more and at least 300 nm or more is formed. Grow as an area.

  As a result, the oxidation process time can be greatly shortened, and the process can be carried out at a practical level by dry oxidation rather than wet oxidation. Can be formed. In addition, since the oxide film can be thin, Bird's Beak can be reduced, and the element region of a fine transistor can be accurately defined.

  The semiconductor substrate of the present invention is the above-described semiconductor substrate, wherein one or a plurality of ions selected from hydrogen ions and inert element ions are implanted to a predetermined depth in the single crystal Si substrate. The formed ion implantation layer is formed. The predetermined depth may be determined according to the target thickness of the single crystal Si substrate to be formed.

  According to the above invention, an ion implantation layer formed by implanting one or a plurality of ions selected from hydrogen ions and inert gas ions is formed at a predetermined depth in the single crystal Si substrate. Therefore, when heat treatment is performed, Si can be cleaved and separated into a thin film in the ion-implanted layer. By doing so, for example, a thin film device coexisting with non-single crystal Si can be transferred onto a large insulating substrate or the like.

  The semiconductor substrate of the present invention is characterized in that, in the semiconductor substrate described above, the ion implantation layer is formed at a predetermined depth in the single crystal Si substrate below the LOCOS oxide film. Yes.

  According to the above invention, since the ion implantation layer is formed at a predetermined depth in the single crystal Si substrate below the LOCOS oxide film, the surface of the single crystal Si thin film thinned by cleaving is thinned. By etching back to the injection side surface of the LOCOS oxide film, element isolation is achieved, and the final device leakage current can be reduced.

  The semiconductor substrate manufacturing method of the present invention is characterized in that, in the semiconductor substrate manufacturing method described above, the LOCOS oxide film is formed by dry oxidation.

  According to the above invention, since the LOCOS oxide film can be formed into a thin film, it can be formed by dry oxidation, and the stress accompanying oxidation at the end of the oxide film can be greatly relieved, so that a transistor with stable characteristics can be formed.

  In order to solve the above problems, a semiconductor device of the present invention is a semiconductor device including an insulating substrate and a single crystal Si semiconductor element formed on the insulating substrate, wherein the single crystal Si semiconductor element is A single-crystal Si including a gate electrode formed above the insulating substrate, a gate insulating film formed on the gate electrode, and a channel region, a source region, and a drain region formed on the gate insulating film. The active layer is composed of a layer, a LOCOS oxide film formed around the active layer, and an interlayer insulating film formed on the active layer and the LOCOS oxide film.

  According to the above invention, since the semiconductor device includes an insulating substrate and a single crystal Si semiconductor element formed on the insulating substrate, for example, an insulating substrate such as a glass plate and a single crystal Si semiconductor element Are united.

  The single crystal Si semiconductor element includes a gate electrode formed above an insulating substrate, a gate insulating film formed on the gate electrode, and a channel region, a source region, and a drain region formed on the gate insulating film. And an LOCOS oxide film formed around the active layer, and an interlayer insulating film formed on the active layer and the LOCOS oxide film.

  As a result, non-single crystal Si semiconductor elements and single crystal Si semiconductor elements are formed on a large insulating substrate, and the manufacturing process of the single crystal Si portion is simplified when manufacturing a semiconductor device in which a high performance system is integrated. In addition, it is possible to provide a semiconductor device capable of realizing element isolation of a fine single crystal Si semiconductor element without high-precision photolithography after being transferred to a large insulating substrate.

  According to another aspect of the present invention, there is provided a semiconductor device comprising: a wiring layer formed on the interlayer insulating film and connected to the source region and the drain region through a connection hole provided in the interlayer insulating film; It is characterized by having.

  According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: a step of bonding a semiconductor substrate manufactured by the method of manufacturing a semiconductor substrate onto an insulating substrate; The single crystal Si substrate is divided at the ion implantation layer as a boundary, a single crystal Si substrate peeling step for peeling a part of the single crystal Si substrate, and etching the single crystal Si substrate on the insulating substrate, A step of exposing a surface of the LOCOS oxide film; a step of forming a protective insulating film and an interlayer insulating film on the active layer and the LOCOS oxide film; and forming the protective insulating film and the interlayer insulating film on the interlayer insulating film. Forming a wiring layer connected to the source region and the drain region through the formed connection hole.

  According to the above invention, the wiring layer is formed on the protective insulating film and the interlayer insulating film, and connected to the source region and the drain region through the connection hole provided in the protective insulating film and the interlayer insulating film. Yes.

  Therefore, this results in a semiconductor device having a wiring layer connected to other circuits, power supplies, and the like. In addition, a wiring layer can be formed after a semiconductor substrate having a non-single-crystal Si semiconductor element is bonded to an insulating substrate and thinned.

  As a result, non-single-crystal Si semiconductor elements and single-crystal Si semiconductor elements are formed on a large insulating substrate, and the manufacturing process of the single-crystal Si portion is simplified when manufacturing a semiconductor device in which a high-performance system is integrated. In addition, it is possible to provide a semiconductor device that can realize element isolation of a fine single crystal Si semiconductor element without high-precision photolithography after being transferred to a large insulating substrate, and a method for manufacturing the same.

  In order to solve the above problems, a semiconductor device of the present invention is a semiconductor device including an insulating substrate and a single crystal Si semiconductor element formed on the insulating substrate, wherein the single crystal Si semiconductor element is A single-crystal Si including a gate electrode formed above the insulating substrate, a gate insulating film formed on the gate electrode, and a channel region, a source region, and a drain region formed on the gate insulating film. An active layer composed of layers, a LOCOS oxide film formed around the active layer, a protective insulating film and an interlayer insulating film formed on the active layer and the LOCOS oxide film, and the insulating substrate An insulating film formed between the first and second gate electrodes, at least one first wiring layer formed on a lower surface side of the insulating film, and the first wiring layer formed on the interlayer insulating film. Connected to It is characterized by having a second wiring layer.

  According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: a step of bonding a semiconductor substrate manufactured by the method of manufacturing a semiconductor substrate onto an insulating substrate; The single crystal Si substrate is divided at the ion implantation layer as a boundary, a single crystal Si substrate peeling step for peeling a part of the single crystal Si substrate, and etching the single crystal Si substrate on the insulating substrate, A step of exposing a surface of a LOCOS oxide film; a step of forming a protective insulating film and an interlayer insulating film on the active layer and the LOCOS oxide film; and the first wiring layer on the protective insulating film and the interlayer insulating film. And a step of forming a second wiring layer connected to the capacitor.

  By the way, when forming a metal wiring layer, including the above-mentioned case, generally, in order to improve the integration density of an integrated circuit, it is necessary to form a plurality of wiring layers and efficiently use a space. This is because, when the element region becomes very small, as a practical problem, external extraction electrodes are densely arranged immediately above the element region, and it becomes difficult to form a wiring pattern.

  Therefore, in the semiconductor device of the present invention, at least one first wiring layer formed on the lower surface side of the insulating film and a second wiring formed on the interlayer insulating film and connected to the first wiring layer. And have a layer.

  Therefore, wiring can be efficiently routed using the space on the back side of the element region, and the integration density can be increased.

  The semiconductor device of the present invention is characterized in that, in the semiconductor device described above, the upper surface of the active layer is located lower than the upper surface of the LOCOS oxide film.

  According to the above invention, the upper surface of the active layer is etched back to a position lower than the upper surface of the LOCOS oxide film by cleaving and separating the thinned single crystal Si thin film surface, thereby reducing the leakage current of the final device. Can be reduced.

  The semiconductor device of the present invention is characterized in that, in the semiconductor device described above, an end portion of the active layer is formed so as to overlap an inclined portion of an end portion of the LOCOS oxide film.

  According to the above invention, since the end portion of the active layer is formed so as to overlap the inclined portion of the end portion of the LOCOS oxide film, a device-isolated structure is realized, and the conventional island etching is performed. Si island edge defects and leakage current due to stress can be reduced.

  The semiconductor device according to the present invention is the above semiconductor device, wherein the first wiring layer is made of a material having a heat resistant temperature (melting point or reaction temperature with Si, whichever is lower) of about 500 ° C. or more. It is characterized by being.

  According to the above invention, the first wiring layer is made of a material having a heat resistant temperature (melting point or reaction temperature with Si, whichever is lower) of about 500 ° C. or higher. The wiring layer does not melt.

  According to another aspect of the present invention, there is provided a semiconductor device according to the above-described semiconductor device, wherein the single crystal Si semiconductor element is formed in a partial region of the insulating substrate and a non-single crystal constituting a transistor in another region. A Si semiconductor element is formed.

  Therefore, the single crystal Si semiconductor element and the non-single crystal Si semiconductor element can coexist on the insulating substrate.

  The semiconductor device of the present invention is the above semiconductor device, wherein at least a part of the non-single-crystal Si semiconductor element constitutes a switching transistor of each pixel constituting a display portion, while A transistor composed of a crystalline Si semiconductor element constitutes a display drive circuit for driving a display unit or a processing circuit for outputting a predetermined signal to the display drive circuit, and serves as a constituent substrate of a display device. It is characterized by being used.

  That is, conventionally, in a display device such as a liquid crystal display device, a switching transistor of each pixel made of a non-single crystal Si semiconductor element is formed on an insulating substrate such as a glass substrate, and a wiring pattern is further formed. A display driving circuit for driving the display or a processing circuit for outputting a predetermined signal to the display driving circuit is mounted by COG or COF made of a single crystal Si semiconductor element and then connected to the wiring pattern. It was. Or it supplied from an external printed circuit board.

  However, according to the present invention, at least a part of the non-single-crystal Si semiconductor element constitutes a switching transistor of each pixel constituting the display unit, and the transistor constituted by the single-crystal Si semiconductor element is A display driving circuit for driving the display unit or a processing circuit for outputting a predetermined signal to the display driving circuit is configured.

  Therefore, after forming at least a part of the non-single-crystal Si semiconductor element and a part of the single-crystal Si semiconductor element on the insulating substrate, the wiring layers of both can be formed. As a result, a semiconductor device for forming a high-quality display device with high productivity can be provided.

  According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device by cleaning the surfaces of the semiconductor substrate and the insulating substrate with cleaning water such as SC1 containing hydrogen peroxide water, or It is characterized in that after being activated by exposure to a plasma containing oxygen, a bonding step of the substrate is performed.

  As a result, the semiconductor substrate and the insulating substrate can be bonded to each other without an adhesive by Van der Waals force and hydrogen bonding.

  The semiconductor device manufacturing method of the present invention is characterized in that in the semiconductor device manufacturing method described above, the heat treatment in the single crystal Si substrate peeling step is performed at a temperature of about 250 ° C. or more and about 600 ° C. or less. Yes.

  According to said invention, the heat processing in a single crystal Si substrate peeling process are performed at the temperature of about 250 degreeC or more and about 600 degrees C or less.

  As a result, the single crystal Si semiconductor element can be heated to a temperature at which, for example, hydrogen ions are released from Si, and the bonding strength to the insulating substrate can be increased, and a part of the single crystal Si substrate is cleaved and separated from the ion implantation layer Can be made.

  The present invention can form two types of semiconductor devices having different characteristics on the same substrate, and can be applied to various uses such as a display device by utilizing each advantage. In particular, in an active matrix drive liquid crystal display device driven by TFTs, etc., a high-performance liquid crystal display device in which peripheral drive circuits, control circuits, MPUs (ultra-compact arithmetic processing devices) and image processing circuits are integrated on the same substrate, or The present invention can be applied to a display device such as an OLED (Organic Light Emitting Diode: organic EL) display device.

DESCRIPTION OF SYMBOLS 1 Planarization insulating film 2 Gate electrode 3 Gate insulating film 4 Source region 4a LDD structure 5 Drain region 5a LDD structure 6 Active layer [Channel region (region under gate electrode), region including source region and drain region]
7 LOCOS oxide film 8 Single crystal Si wafer (single crystal Si substrate)
9 Ion implantation layer [Ion implantation layer (peak position) formed by implantation of one or more ions selected from hydrogen ions and inert element ions]
10 semiconductor substrate 11 of silicon dioxide (SiO ₂₎ film 12 silicon nitride (SiN) film 13 element region 15 side wall 16 field region 21 the protective insulating film and the interlayer insulating film 22 contact hole (connection hole)
23 Metal wiring layer (wiring layer)
25 Insulating substrate 26 Silicon dioxide (SiO ₂ ) film 30 Semiconductor substrate 40 Semiconductor substrate 41 Contact hole 42 First metal wiring (first wiring layer)
43 Interlayer insulating film 44 Contact hole 45 Second metal wiring (second wiring layer)
DESCRIPTION OF SYMBOLS 50 Semiconductor device 70 Display apparatus 71 Display part 72 Display drive circuit 73 Display drive circuit 74 Image processing circuit (processing circuit)
75 Control circuit (processing circuit)
101 channel stop

Claims (7)

A semiconductor device comprising: an insulating substrate; a single crystal Si semiconductor element formed on a part of the insulating substrate; and a non-single crystal Si semiconductor element formed on another region of the insulating substrate. ,
The single crystal Si semiconductor element having no well structure and channel stop structure is
A gate electrode formed above the insulating substrate;
A gate insulating film formed on the gate electrode;
An active layer made of a single-crystal Si layer including a channel region, a source region, and a drain region, formed on the gate insulating film;
A LOCOS oxide film for element isolation formed around the active layer;
A first interlayer insulating film formed on the active layer and the LOCOS oxide film, and
An insulating film formed between the insulating substrate and the gate electrode;
At least one first wiring layer formed on the lower surface side of the insulating film;
A second layer formed on the first interlayer insulating film and connected to the first wiring layer through a contact hole penetrating the first interlayer insulating film, the LOCOS oxide film, and the insulating film. and the wiring layer of,
A second interlayer insulating film formed on the lower surface side of the insulating film and the first wiring layer;
A semiconductor device, wherein a lower surface side of the second interlayer insulating film is planarized, and the planarized second interlayer insulating film is bonded to the insulating substrate .   2. The semiconductor device according to claim 1, wherein the active layer has an island shape in which the LOCOS oxide film surrounds the active layer, and adjacent active layers are spatially separated from each other.   2. The semiconductor device according to claim 1, wherein the second wiring layer is connected to the first wiring layer through a relay electrode formed of a gate layer formed on the LOCOS oxide film.   4. The semiconductor device according to claim 1, wherein an upper surface of the active layer is positioned lower than an upper surface of the LOCOS oxide film.   The semiconductor device according to claim 1, wherein an end portion of the active layer is formed so as to overlap an inclined portion of an end portion of the LOCOS oxide film.   2. The semiconductor device according to claim 1, wherein the first wiring layer is made of a material having a heat resistant temperature (melting point or reaction temperature with Si, whichever is lower) of about 500 ° C. or more. At least a part of the non-single-crystal Si semiconductor element constitutes a transistor that controls display of each pixel constituting the display unit,
The transistor composed of the single crystal Si semiconductor element constitutes a display driving circuit for driving the display unit or a processing circuit for outputting a predetermined signal to the display driving circuit, and constitutes the display unit. The semiconductor device according to claim 1, wherein the semiconductor device is monolithically formed on the substrate.

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