JP4508385B2 - Timing generator and semiconductor test apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a technique for reducing the memory capacity of a timing generator in a semiconductor test apparatus (IC tester).
[0002]
[Prior art]
A semiconductor test apparatus for performing an operation test of a semiconductor integrated circuit includes a variable delay circuit for synchronously extracting signals output from external terminals (pins) of the semiconductor integrated circuit to be inspected.
[0003]
Here, the configuration of a conventional variable delay circuit will be briefly described with reference to FIG.
FIG. 2A is a circuit diagram for explaining the configuration of a conventional variable delay circuit. FIG. 2B is a circuit diagram for explaining the internal configuration of the delay unit. As shown in FIG. 2A, the conventional variable delay circuit includes n stages (n is an integer of 2 or more) of delay units 10 connected in series.
[0004]
As shown in FIG. 2B, the delay unit 10 at each stage selectively transmits a signal to the passing path 4 for passing the signal, the delay path 5 for delaying the signal, and the passing path 4 or the delay path 5. And a selector 3 that propagates to
A delay element 51 is provided in the delay path 5 of the delay unit 10 in each stage.
[0005]
As shown in FIG. 2B, the selector 3 includes an AND circuit 31 that outputs a signal to the passage path 4 and an AND circuit 32 that outputs a signal to the delay path 4. The AND circuit 31 receives a delayed signal and an inverted delay setting value. The AND circuit 32 receives a delayed signal and a delay setting value.
[0006]
The delay times of the delay elements 51 are different between the delay units 10 in order to efficiently generate a variety of delay times with a small number of stages. That is, the weighting of each delay unit 10 is varied.
[0007]
For example, the delay time of the delay element of the first-stage delay unit 10 is 1 second, and the delay times of the second, third, and fourth stages are 2 seconds, 4 seconds, and 8 seconds, respectively. In this case, a delay time of 10 seconds can be easily obtained by selecting a delay time of only the second-stage and fourth-stage delay elements according to the delay setting value.
On the other hand, if the delay time of each stage delay element is 1 second, 10 stages of delay elements are required to obtain a delay time of 10 seconds.
The rate at which the delay time increases for each stage number is referred to as an increase coefficient. In this case, the increase coefficient is “2”.
[0008]
Incidentally, an error is included in the delay time of the actual delay element. As a result, the delay time of each delay unit is not necessarily a value as designed, but is slightly deviated from the design value. For this reason, if each bit of the delay setting value indicating the delay time is simply assigned one-to-one to each delay unit 10, the actual delay amount deviates from the delay setting value.
[0009]
Therefore, in an actual timing generator, in order to obtain a desired number of delay times, the number of delay units is made larger than the minimum number necessary for design to provide redundancy. That is, the increase coefficient of the delay unit 10 is reduced to, for example, about “1.5”, and a larger number of delay units 10 are prepared than when the increase coefficient is “2”. Then, after including the error, the delay time when the delay units are combined is measured, and the combination closest to the desired delay time is selected and used from among the delay time combinations of the respective delay units.
[0010]
For this reason, the timing generator of the conventional example stores a delay time, a delay setting value indicating a combination of the delay units 10 for propagating a signal to the delay path 5 among the delay units 10, and a linearly stored in association with the delay time. A rise memory 2 is provided.
[0011]
Therefore, by inputting a delay setting value indicating a desired delay time to the linearized memory 2, in the linearized memory 2, a delay setting value indicating a combination of the delay units 10 corresponding to the delay time can be obtained. . Then, according to the delay setting value, the selector 3 can select the passing path 4 or the delay path 5 in each delay unit 10 to generate a desired delay time.
[0012]
[Problems to be solved by the invention]
By the way, when the delay setting value corresponding to the delay time is n bits, the amount of information represented by the delay setting value is 2 n (2 ^ n). For this reason, the depth of the linearized memory in which the correspondence between the delay setting value and the delay time is stored is (2 ^ n).
[0013]
Furthermore, when the delay unit 10 of the variable delay circuit 1 is provided in m stages, the delay setting value stored in the linearized memory 2 also requires m bits. Therefore, in order to store this amount of information, the memory capacity of the delay setting value for n bits in the linearized memory 2 is ((2 n) × m) bits, that is, (2 ^ n × m) bits.
[0014]
In order to provide the above-described redundancy or to improve the performance of the timing generator, the number m of delay units constituting the variable delay circuit is increased, the setting resolution is high, that is, n is increased. As a result, the depth of the linearized memory increases exponentially. As a result, it is necessary to secure a huge memory capacity in the linearized memory.
Furthermore, the size of the linearized memory is increased, and as a result, it is difficult to reduce the size of the device.
[0015]
The present invention has been made to solve the above problems, and has as its object to provide a timing generator capable of reducing the memory capacity and reducing the size of the apparatus, and a semiconductor inspection apparatus including the timing generator. To do.
[0016]
[Means for Solving the Problems]
In order to achieve this object, according to the timing generator of the present invention , a plurality of stages of delay units each having a path for passing a signal and a path for delaying the signal and generating different delay times are connected in series. A timing generator comprising: a variable delay circuit connected to each other; a delay setting value indicating a combination of delay units that generate a delay time among the delay units; and a memory that stores the delay times in association with each other, The delay part of the variable delay circuit is divided into a plurality of delay groups, and as the memory, individual divided memories divided for each delay group are provided, and each divided memory has a delay constituting a delay group corresponding to the divided memory. In this configuration, a combination of delay units that generate a delay time and a division delay setting value indicating the delay time of the delay group are stored in association with each other.
[0017]
Thus, according to the timing generator of the present invention, the variable delay circuit is divided into a plurality of delay groups (k, k is an integer of 2 or more). Each delay group is responsible for a divided delay setting value obtained by dividing the delay setting value. In this case, the total number of bits (n1, n2,..., Nk) of the divided delay setting values assigned to each delay group is the total number of delay bits (N) for the variable delay circuit as shown in the following equation (1). ).
[0018]
N = n1 + n2 + ... + nk (1)
However, N, n1, n2, ..., nk represents an integer of 2 or more.
[0019]
On the other hand, the sum of the depths of individual memories (2 ^ n1, 2 ^ n2,..., 2 ^ nk) corresponding to each delay group corresponds to all delay sections as shown in the following equation (2). It becomes shallower than the depth of memory (2 ^ N).
[0020]
(2 ^ N)> (2 ^ n1) + (2 ^ n2) + ... + (2 ^ nk) (2)
[0021]
The above equation (2) is derived from the following equations (3) and (4).
(2 ^ N) = (2 ^ n1) (2 ^ n2) (2 ^ nk) (3)
(2 ^ n1) (2 ^ n2) ... (2 ^ nk)> (2 ^ n1) + (2 ^ n2) + ... + (2 ^ nk) (4)
[0022]
Therefore, according to the present invention, the total depth of all the divided memories can be made smaller than the depth of the undivided memories. That is, the total memory capacity of all memories can be reduced. Further, since the memory capacity can be reduced, the size of the memory can be reduced. As a result, it is possible to reduce the size of the timing generator.
[0023]
In addition, according to the semiconductor test apparatus of the present invention , an operation test of this semiconductor integrated circuit including a timing generator for synchronously extracting signals output from the respective external terminals of the semiconductor integrated circuit to be inspected is performed. A semiconductor test apparatus for performing,
The timing generator has a path through which a signal passes and a path through which the signal is delayed, and includes a variable delay circuit in which multiple stages of delay units that generate different delay times are connected in series, and a delay among the delay units. A delay setting value indicating a combination of delay units that generate time and a memory that stores the delay time in association with each other, and the delay unit of the variable delay circuit is divided into a plurality of delay groups. A plurality of individual divided memories are provided, and each divided memory includes a combination of delay units that generate a delay time among delay units constituting the delay group corresponding to the divided memory, and the delay time of the delay group. Are stored in association with the division delay setting value indicating.
[0024]
Thus, according to the semiconductor test apparatus of the present invention, the total depth of all the divided memories can be made smaller than the depth of the undivided memories. That is, the total memory capacity of all memories can be reduced. Further, since the memory capacity can be reduced, the size of the memory can be reduced. As a result, it is possible to reduce the size of the timing generator. Furthermore, it is possible to reduce the size of the semiconductor test apparatus including the timing generator.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
First, the configuration of the variable delay circuit of the present embodiment will be described with reference to FIG. This variable delay circuit is provided in a semiconductor inspection apparatus (IC tester) in order to synchronously extract signals output from external terminals of the semiconductor integrated circuit to be inspected.
FIG. 1 is a circuit diagram for explaining the configuration of the timing generator of the present embodiment.
Also in the timing generator of this embodiment, the variable delay circuit 1 is connected in series with m stages (m is an integer of 2 or more) of delay units 10 between the input terminal in and the output terminal out, as in the conventional example. Provided. The delay time setting value (variable amount setting value) is n bits (n is an integer of 2 or more).
[0026]
In the present embodiment, each delay unit 10 of the variable delay circuit 1 is divided into three delay groups, a first delay group 11, a second delay group 12, and a third delay group 13. The first, second, and third delay groups 11, 12, and 13 include mw1, mw2, and mw3 delay units 10, respectively.
[0027]
Note that mW1 <m, mw2 <m, and mw3 <m. Here, m is the number of all delay parts before division. Therefore, the total number of delay units included in each divided delay group satisfies the following expression (5).
[0028]
m <(mw1 + mw2 + mw3) <3m (5)
[0029]
In addition, the first delay group 11 is responsible for w1 bits, the second delay group 12 is for w2 bits, and the third delay group 13 is for w3 bits for the delay setting value bit number n. .
The total number of bits (w1 + w2 + w3) of the divided delay setting values corresponding to each of the delay groups 11, 12 and 13 is the total number of bits (n) of the delay setting values as shown in the following equation (6). It becomes.
[0030]
n = (w1) + (w2) + (w3) (6)
[0031]
In this embodiment, the first linearized memory 21, the second linearized memory 22, and the third linearized memory 23 are individually provided for each of these three delay groups 11, 12, and 13.
[0032]
Each divided memory corresponds to a combination of delay units that generate a delay time among delay units constituting the delay group corresponding to the divided memory, and a divided delay setting value indicating the delay time of the delay group. And stored.
[0033]
That is, the first linearized memory 21 includes, for each mw1 delay unit 10 included in the first delay unit 11, a w1 bit delay setting value indicating a delay time and each of the mw1 delay units 10. Correspondence with the setting of is stored.
For this reason, the depth of the memory of the first linearized memory 21 is (2 ^ w1). The memory capacity of the first linearized memory 21 is (2 ^ w1 × mw1).
[0034]
Further, in the second linearized memory 22, for each of the mw2 delay units 10 included in the second delay unit 12, a w2 bit delay setting value indicating a delay time and each of the mw2 delay units 10 are provided. Stores correspondence with settings.
For this reason, the depth of the memory of the second linearized memory 22 is (2 ^ w2). The memory capacity of the second linearized memory 22 is (2 ^ w2 × mw2).
[0035]
Further, in the third linearized memory 23, for each of the mw3 delay units 10 included in the third delay unit 13, a w3 bit delay setting value indicating a delay time and each of the mw3 delay units 10 are provided. Stores correspondence with settings.
For this reason, the depth of the memory of the third linearized memory 23 is (2 ^ w3). The memory capacity of the third linearized memory 23 is (2 ^ w3 × mw3).
[0036]
The total memory depth of each of the linearized memories 21 to 23 is the same as that obtained when one linearized memory corresponding to the initial m stages of delay units is provided, as shown in the following equation (7). It becomes shallower than the depth of memory.
[0037]
(2 ^ n)> (2 ^ w1) + (2 ^ w2) + (2 ^ w3) (7)
[0038]
Furthermore, in this embodiment, since mw1 <m, mw2 <m, and mw3 <m, the total memory capacity of each of the linearized memories 21 to 23 is expressed by the following equation (8): This is smaller than the memory capacity when the first linearized memory corresponding to the m-stage delay unit is provided.
[0039]
(2 ^ n * m)> (2 ^ w1 * mw1) + (2 ^ w2 * mw2) + (2 ^ w3 * mw3) (8)
[0040]
Therefore, according to the present embodiment, the total memory capacity of all memories can be reduced. Further, since the memory capacity can be reduced, the size of the memory can be reduced.
[0041]
For example, when the number of bits (n) of the delay setting value is 12, the depth of the non-divided linearized memory is (2 ^ 12) = 4096.
[0042]
On the other hand, when the 12-bit setting resolution is divided into, for example, 5-bit, 4-bit, and 3-bit division delay setting values, the depth of the linearized memory divided into three is (2 ^ 5), respectively. ) = 32, (2 ^ 4) = 16 and (2 ^ 3) = 8.
[0043]
Therefore, the total depth of the linearized memory divided into three is (32 + 16 + 8 =) 56. That is, it can be seen that the value is much smaller than the memory depth 4096 in the case of non-division.
[0044]
Furthermore, if the number of delay units 10 included in each delay group 11 to 13 is made uniform, that is, if w1 = w2 = w3, then the memory of the delay groups in each delay group is made nonuniform. The depth of can be further reduced.
[0045]
For example, when twelve delay units are equally divided by four, each of the equally divided linearized memories has a depth of (2 ^ 4) = 16. Accordingly, the total depth of the equally divided linearized memory is (16 + 16 + 16 =) 48. That is, it can be seen that the depth of the memory can be further reduced as compared with the case where the number of delay parts of each delay group is not uniform.
[0046]
In the above-described embodiment, the example in which the present invention is configured under specific conditions has been described. However, the present invention can be variously modified. For example, in the above-described embodiment, an example in which three linearized memories are provided has been described, but the number of memory divisions is not limited to this.
[0047]
In the above-described embodiment, the delay units of each divided group are configured by mutually adjacent delay units. However, in the present invention, the method of dividing the delay units is not limited to this. For example, sequentially connected delay units may be included in separate divided groups.
The number of delay units included in one divided group is not particularly limited. For example, the number of delay units included in one divided group may be one.
[0048]
【The invention's effect】
As described above in detail, according to the present invention, the total depth of all divided memories can be made smaller than the depth of undivided memories. That is, the total memory capacity of all memories can be reduced. Further, since the memory capacity can be reduced, the size of the memory can be reduced. As a result, it is possible to reduce the size of the timing generator. Furthermore, it is possible to reduce the size of the semiconductor test apparatus including the timing generator.
[Brief description of the drawings]
FIG. 1 is a circuit diagram for explaining a configuration of a timing generator according to an embodiment.
FIG. 2A is a circuit diagram for explaining a configuration of a conventional timing generator, and FIG. 2B is a circuit diagram for explaining an internal configuration of a delay unit;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Variable delay circuit 2 Linearization memory 3 Selector 4 Passing path 5 Delay circuit 6 OR gate 10 Delay part 11 1st delay group 12 2nd delay group 13 3rd delay group 21 1st linearize memory 22 2nd linearize memory 23 Third linearized memory 31, 32 AND gate

Claims (2)

A variable delay circuit having a plurality of delay units connected in series, each having a path through which a signal passes and a path through which the signal is delayed, and causing different delay times;
A timing generator comprising a delay setting value indicating a combination of delay units that generate a delay time among the delay units, and a memory that stores the delay time in association with each other,
The delay units of m stages (m is an integer of 2 or more) of the variable delay circuit are divided into a plurality of delay groups, and each delay group has mw1, mw2,... MwN delay units,
As the memory having the number n of delay setting values, the delay setting values divided for each delay group are w1 bits, w2 bits,... WN bits (n = (w1) + (w2) +. )) A plurality of individual divided memories,
Each divided memory includes a combination of delay units that generate a delay time among mw1, mw2,... MwN delay units that constitute a delay group corresponding to the divided memory, and a delay of the delay group. Store the w1 bit, w2 bit,... WN bit division delay setting values indicating time in association with each other ,
A timing generator characterized in that the depth and the memory capacity of the memory and each divided memory satisfy the following two relationships .
(2 ^ n)> (2 ^ w1) + (2 ^ w2) + (2 ^ wN)
(2 ^ n * m)> (2 ^ w1 * mw1) + (2 ^ w2 * mw2) + (2 ^ wN * mwN) A semiconductor test apparatus for performing an operation test of this semiconductor integrated circuit, comprising a timing generator for synchronously extracting signals output from each external terminal of a semiconductor integrated circuit to be inspected,
The timing generator is
A variable delay circuit having a plurality of delay units connected in series, each having a path through which a signal passes and a path through which the signal is delayed, and causing different delay times;
A delay setting value indicating a combination of delay units that cause a delay time among the delay units, and a memory that stores the delay time in association with each other, and
The delay units of m stages (m is an integer of 2 or more) of the variable delay circuit are divided into a plurality of delay groups, and each delay group has mw1, mw2,... MwN delay units,
As the memory having the number n of delay setting values, the delay setting values divided for each delay group are w1 bits, w2 bits,... WN bits (n = (w1) + (w2) +. )) A plurality of individual divided memories,
Each divided memory includes a combination of delay units that generate a delay time among mw1, mw2,... MwN delay units that constitute a delay group corresponding to the divided memory, and a delay of the delay group. Store the w1 bit, w2 bit,... WN bit division delay setting values indicating time in association with each other ,
A semiconductor test apparatus characterized in that the depth and memory capacity of the memory and each divided memory satisfy the following two relationships .
(2 ^ n)> (2 ^ w1) + (2 ^ w2) + (2 ^ wN)
(2 ^ n * m)> (2 ^ w1 * mw1) + (2 ^ w2 * mw2) + (2 ^ wN * mwN)

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