JP4507676B2 - Charge removal circuit, electro-optical device and electronic apparatus - Google Patents

Description

  The present invention relates to an electro-optical device using an electro-optical material such as a liquid crystal, and more particularly to a technique for preventing application of a DC voltage to the electro-optical material.

  An electro-optical device using an electro-optical material is widely used as a display device for various electronic devices. For example, a liquid crystal device using a liquid crystal as an electro-optical material includes a pixel electrode connected to a switching element provided at the intersection of a scanning line and a data line, and a counter electrode facing each pixel electrode with the liquid crystal interposed therebetween. With this configuration, when a scanning line is selected and the switching element is in an on state, various images are displayed by applying a voltage corresponding to the display image from the data line to the pixel electrode.

In this type of electro-optical device, even after the display of an image is stopped, the charge corresponding to the content of the immediately preceding display image may remain in each pixel electrode and the counter electrode. If the DC component of the voltage continues to be applied to the liquid crystal due to this charge, the characteristics of the liquid crystal, alignment film, etc. will deteriorate, so when the image display is started after that, the image that was displayed when the display was last stopped will be A phenomenon (hereinafter referred to as “burn-in”) that appears as an afterimage superimposed on the display image. Further, deterioration of the liquid crystal or alignment film may cause a phenomenon (so-called flicker) in which the luminance of each pixel fluctuates in a short cycle and the image flickers. As a technique for preventing these problems, all scanning lines are sequentially selected when display is stopped, and an off voltage (for example, a counter electrode) is applied to the pixel electrode corresponding to the selected scanning line via a data line. Has been proposed (see, for example, Patent Document 1). According to this configuration, since the charges accumulated in each pixel electrode and the counter electrode are discharged before the display is stopped, the deterioration of the liquid crystal and the alignment film due to the application of the DC component is suppressed.
JP-A-9-269476 (paragraph 0018 and FIG. 3)

  By the way, in order to execute the off-sequence processing, it is necessary to drive the scanning lines and the data lines in the same manner as in normal image display. However, since the drive of scanning lines and data lines is generally controlled by a control device of an electronic device in which the electro-optical device is mounted, an off-sequence process is executed unless the electro-optical device is mounted in the electronic device. There are cases where it is not possible. In this case, since charges accumulated in the pixel electrodes and the counter electrode are not removed during the manufacturing process of the electro-optical device, the liquid crystal is used until the electro-optical device manufactured through the manufacturing process is mounted on the electronic apparatus. As a result, seizure may occur. The present invention has been made in view of such circumstances, and an object of the present invention is to remove the electric charge of each electrode and eliminate the need for driving scanning lines and data lines and to apply a direct current component to the electro-optical material. It is to suppress.

In order to solve this problem, a charge removal circuit according to the present invention includes a pixel electrode disposed corresponding to an intersection of a scanning line and a data line, and a counter electrode facing the pixel electrode with an electro-optic material interposed therebetween. A charge removal circuit for an electro-optical device comprising: a resistor that electrically connects the counter electrode and a ground line; and a reference signal that changes from a higher voltage to a lower voltage that is lower than the higher voltage. An input power supply line , a capacitive element for holding a voltage, switching means for conducting the data line and the ground line when an ON voltage is applied to the gate, and a gate electrode and a drain electrode are connected to the power supply line. A first transistor, a gate electrode connected to the power supply line, a source electrode connected to the source electrode of the first transistor and one end of the capacitor, and a gate transistor; A control circuit comprising a third transistor having an electrode connected to the power supply line, a drain electrode connected to the drain electrode of the second transistor and the gate of the switching means, and a source electrode connected to a ground line. When the reference signal input to the power supply line is the high voltage, the first and third transistors are turned on and the second transistor is turned off, and the power supply line and the capacitive element are connected. When the reference signal becomes the low-side voltage while conducting the voltage and holding the voltage , the first and third transistors are turned off and the second transistor is turned on, and the capacitive element the voltage held and a control circuit for applying to the gate of the switching means as the oN voltage, the resistance When the data line is connected to the ground line by the switching means, the voltage attenuation amount per unit time of the counter electrode in which the supply of the common potential is stopped is 100 kΩ or more and 500 kΩ or less. The resistance value is set to be larger than the voltage attenuation amount per unit time of the data line .

Na us, and the electro-optical material in the present invention, is a substance which changes its optical characteristics such as transmittance or luminance by the action of electrical energy, such as current or voltage. A typical example of this type of electro-optical material is a liquid crystal whose transmittance changes due to a change in orientation direction according to an applied voltage, but the electro-optical material in the present invention is not limited to this. However, since the object of the present invention is to suppress the application of a DC component to the electro-optical material, the present invention is applied to a configuration using an electro-optical material that may cause problems such as deterioration of characteristics due to the application of the DC component. Is particularly suitable .

The electro-optical device according to the present invention sandwiches the electro-optical material, a substrate for holding the electro-optical material, a pixel electrode disposed on the substrate corresponding to the intersection of the scanning line and the data line, and And a counter electrode facing the pixel electrode, and the above-described charge removal circuit disposed on the substrate.

The electro-optical device according to the present invention includes a substrate for holding an electro-optical material, and a plurality of pixel electrodes arranged on the substrate corresponding to intersections of a plurality of scanning lines and a plurality of data lines, respectively. And a counter electrode facing each of the pixel electrodes with the electro-optical material interposed therebetween, and a charge removal circuit disposed on the substrate, wherein the charge removal circuit electrically connects the counter electrode and the ground line. A resistor connected to the power supply line, a power supply line to which a reference signal that changes from a higher voltage to a lower voltage that is lower than the higher voltage is input, a capacitor that holds the voltage, and an ON voltage applied to the gate Switching means for conducting the data line and the ground line; a first transistor having a gate electrode and a drain electrode connected to the power supply line; a gate electrode connected to the power supply line; and a source electrode connected to the first transistor. A second electrode connected to one end of the source electrode and the capacitive element, and a gate electrode connected to the power supply line, and a drain electrode connected to the drain electrode of the second transistor and the gate of the switching unit, A control circuit including a third transistor having a source electrode connected to a ground line, and when the reference signal input to the power supply line is the high voltage, the first and third transistors are in an on state. In addition, when the second transistor is turned off and the power supply line and the capacitive element are made conductive to hold the voltage in the capacitive element, when the reference signal becomes the lower voltage, the first and second transistors 3 transistors are turned off and the second transistor is turned on, so that the voltage held in the capacitor element is turned on. A control circuit for applying a voltage to the gate of the switching means as a voltage, the resistance is not less than 100 kΩ and not more than 500 kΩ, and when the data line and the ground line are conducted by the switching means, a common potential is provided. The voltage attenuation amount per unit time of the counter electrode from which the power supply is stopped is set to a resistance value larger than the voltage attenuation amount per unit time of the data line.

By the way, in an electro-optical device using liquid crystal as an electro-optical material, for example, another substrate that sandwiches the electro-optical material in a gap with the substrate, and a seal for bonding the substrate and the other substrate together Material. In this configuration, it is desirable that the charge removal circuit is disposed in a region of the substrate that faces the sealing material. According to this aspect, since it is not necessary to secure an area independent of other elements (for example, a sealing material) as a space for arranging the charge removal circuit, a so-called frame area (area around the display area) is narrowed. Is particularly suitable when
In the active matrix electro-optical device, a transistor is provided which is turned on when the scanning line is selected to conduct the data line and the pixel electrode. This transistor is a switching element including a semiconductor layer, a gate electrode layer, and a wiring layer. In this configuration, it is preferable that at least one electrode constituting the capacitor is made of a conductive material common to any of the semiconductor layer, the gate electrode layer, and the wiring layer of the transistor. According to this configuration, since the capacitive element and the transistor can be formed in a common process, the manufacturing process can be simplified and the manufacturing cost can be reduced as compared with the case where each is formed in a separate process. It is done.

In the electro-optical device of the present invention, configurations, each with a plurality of charge removal circuit corresponding to one or more data lines in board, or, based on one of the charge removing circuit for all of the data lines A configuration arranged on a plate may be employed. Of these, in the former configuration, it is desirable that the plurality of charge removal circuits be arranged at substantially equal intervals along the periphery of the substrate. According to this aspect, for example, when the present invention is applied to a liquid crystal device using a liquid crystal as an electro-optic material, the alignment film on the substrate is compared with a configuration in which a plurality of charge removal circuits are unevenly distributed at specific locations. On the other hand, a uniform rubbing process can be performed. In the case where a plurality of charge removal circuits are provided, the capacitive elements of all the charge removal circuits may be integrally formed, or a separate capacitive element may be provided for each charge removal circuit.

  Specific embodiments of the present invention will be described with reference to the drawings. In the drawings shown below, the dimensions and ratios of the components are appropriately different from the actual ones in order to make the components large enough to be recognized in the drawings.

<A: Configuration of liquid crystal device>
First, a mode in which the present invention is applied to a liquid crystal device using liquid crystal as an electro-optical material will be described. FIG. 1 is a perspective view showing a configuration of a liquid crystal device according to the present embodiment, and FIG. 2 is a cross-sectional view taken along line II-II in FIG. As shown in these drawings, the liquid crystal device D includes an element substrate 10 and a counter substrate 20 that are bonded to each other with a sealant 51 so as to face each other with a certain gap therebetween. A liquid crystal 53 is sealed in a space surrounded by both substrates and the sealing material 51. The sealing material 51 is formed in a frame shape along the edge of the counter substrate 20, but a part thereof is opened to enclose the liquid crystal 53. As shown in FIG. 1, the opening is sealed with a sealing material 51a after the liquid crystal 53 is sealed.

  On the plate surface of the counter substrate 20 facing the liquid crystal 53, the counter electrode 21 is formed over substantially the entire area. The counter electrode 21 is made of a conductive material having optical transparency such as ITO (Indium Tin Oxide). 3 is a cross-sectional view taken along line III-III in FIG. 1 (that is, a cross-sectional view when the liquid crystal device D is broken along one side of the sealing material 51). As shown in FIG. 3, electrodes (hereinafter referred to as “vertical conduction electrodes”) 34 are provided at positions facing the four corners of the counter substrate 20 in the element substrate 10. The vertical conductive electrode 34 and the counter electrode 21 are electrically connected through a conductive material 52 such as a silver paste. As shown in FIG. 2, a region of the counter electrode 21 that does not overlap with the sealing material 51 is covered with an alignment film 22 that has been rubbed in a predetermined direction.

  Next, FIG. 4 is a block diagram showing the configuration of each element on the plate surface facing the liquid crystal 53 in the element substrate 10. In the figure, the area (hereinafter referred to as “sealing area”) As covered by the sealing material 51 in the element substrate 10 is hatched. As shown in FIG. 4, a plurality of scanning lines 11 extending in the X direction and a plurality extending in the Y direction so as to be orthogonal to the scanning surface 11 on the plate surface of the element substrate 10 facing the liquid crystal 53. Data lines 12 are formed. A pixel P is disposed at each intersection of the scanning line 11 and the data line 12. As shown in FIG. 5A, each pixel P includes a thin film transistor (hereinafter referred to as “TFT (Thin Film Transistor)”) 14 connected to the scanning line 11 and the data line 12, and a pixel connected to the TFT 14. Electrode 15. More specifically, each TFT 14 has a gate electrode connected to the scanning line 11, a source electrode connected to the data line 12, and a drain electrode connected to the pixel electrode 15. Each pixel electrode 15 is a substantially rectangular electrode made of a light-transmitting conductive material such as ITO. Since the liquid crystal device D has a configuration in which the liquid crystal 53 is sandwiched between the element substrate 10 and the counter substrate 20 as described above, in each pixel P, as shown in FIG. 15, the counter electrode 21, and the liquid crystal 53 sandwiched between the two electrodes form a liquid crystal capacitor 172. Hereinafter, a region in the element substrate 10 in which a plurality of pixels P are arranged in a matrix is referred to as a “display region Ad”. Further, the pixel P in the present embodiment has a storage capacitor 171. The storage capacitor 171 has one end connected to the drain electrode of the TFT 14 and the other end connected to the capacitor line 322. As shown in FIG. 2, the element substrate 10 on which these elements are formed is covered with an alignment film 18 that has been rubbed in a predetermined direction.

  FIG. 6 is an enlarged sectional view showing elements related to one pixel P in the display area Ad. In the figure, the elements constituting the storage capacitor 171 are not shown. In addition, although the elements of the seal region As are also shown in the drawing, these elements will be described later. As shown in FIG. 6, the TFT 14 branches from the scanning line 11, the semiconductor layer 141 formed of polysilicon on the element substrate 10, the gate insulating film 142 formed on the surface of the semiconductor layer 141 by heat treatment, and the scanning line 11. A gate electrode 111 which is a portion. A region of the semiconductor layer 141 that faces the gate electrode 111 with the gate insulating film 142 interposed therebetween is a channel region 141G. Further, the semiconductor layer 141 includes a source region 141S and a drain region 141D. Of these, the source region 141S is connected to the data line 12 through a contact hole 146S formed across the first interlayer insulating film 143 (a layer made of an insulator covering the gate electrode 111) and the gate insulating film 142, and the drain region 141D includes a contact hole 146D formed over the second interlayer insulating film 144 (a layer made of an insulator covering the data line 12 on the first interlayer insulating film 143), the first interlayer insulating film 143, and the gate insulating film 142. And is connected to the pixel electrode 15.

  As shown in FIG. 4, a plurality of connection terminals 31 are arranged along an edge 10 a extending in the X direction in a region of the element substrate 10 that protrudes from the counter substrate 20 (hereinafter referred to as “peripheral region”). is doing. Various signals supplied from an external circuit such as a control device (not shown) of an electronic device in which the liquid crystal device D is mounted are input to the liquid crystal device D through the connection terminal 31. A signal input to each connection terminal 31 is supplied to each part of the liquid crystal device D through the wiring 32.

  A data line driving circuit 43 is provided along the edge 10a in a region sandwiched between the array of the plurality of connection terminals 31 and the display region Ad in the peripheral region. One end of each data line 12 described above is connected to the data line driving circuit 43. Further, scanning line driving circuits 41a and 41b are provided in the peripheral area so as to sandwich the display area Ad in the X direction. Each scanning line 11 described above has one end connected to the scanning line driving circuit 41a and the other end connected to the scanning line driving circuit 41b. Under this configuration, each scanning line driving circuit 41 (41a, 41b) and data line driving circuit 43 are based on various signals such as a clock signal and a control signal supplied from the connection terminal 31 via the wiring 32. Then, an operation for displaying an image is performed. That is, each scanning line drive circuit 41 supplies each scanning line 11 with a scanning signal that sequentially becomes an active level every horizontal scanning period. When the scanning signal transitions to the active level in this way, one row of TFTs 14 connected to the scanning line 11 are turned on simultaneously. On the other hand, when any scanning line 11 is selected by the scanning line driving circuit 41 (that is, when the scanning signal supplied to any scanning line 11 becomes an active level), the data line driving circuit 43 performs this scanning. An image signal of pixels P for one row corresponding to the line 11 is supplied from each data line 12 to the pixel electrode 15 via the TFT 14. The switching elements constituting the scanning line driving circuit 41 and the data line driving circuit 43 have the same configuration as the TFT 14 shown in FIG. 6 and are formed in the same process as each TFT 14. That is, the liquid crystal device D in the present embodiment is a peripheral circuit built-in type.

  On the element substrate 10, a wiring 32 for supplying a higher voltage Vdd of the power source to each part of the liquid crystal device D such as the data line driving circuit 43 and each scanning line driving circuit 41 (41 a and 41 b) And a wiring 32 for supplying a lower voltage (ground potential) Gnd (hereinafter sometimes referred to as “ground line 325”) is formed. That is, as shown in FIG. 4, each of the ground line 325 and the power supply line 324 branches into a part extending from the connection terminal 31 to the data line driving circuit 43 and a part extending in the X direction along the edge 10a. The latter portion bends in the vicinity of the edge 10c and extends in the Y direction, passes through the scanning line driving circuit 41b, bends in the X direction, extends along the edge 10d, and is in the vicinity of the edge 10b. Then, it bends in the Y direction and reaches the scanning line driving circuit 41a. Further, each of the wirings 32 connected to each connection terminal 31 to which the common potential LCcom is supplied is routed from both sides of the data line driving circuit 43 to the upper and lower conductive electrodes 34. The four vertical conduction electrodes 34 are electrically connected to each other by a common wiring 321 formed on the element substrate 10 so as to surround the display region Ad. The common wiring 321 branches so as to partially reach the display area Ad to form a capacitance line 322.

  Further, in the area corresponding to one side of the sealing material 51 (side extending along the edge 10 d) in the sealing area As of the element substrate 10, the number of seizure preventions corresponding to the total number of the data lines 12 is prevented. A circuit (corresponding to a “charge removing circuit” according to the present invention) 60 is formed. Each image sticking prevention circuit 60 discharges the electric charge remaining in each of the liquid crystal capacitors 172 for one column connected to the data line 12 corresponding to the image sticking prevention circuit 60 when image display is stopped. It is a means for preventing. Therefore, the burn-in prevention circuit 60 is grasped as a circuit for preventing application of a DC voltage to the liquid crystal capacitor 172. These seizure prevention circuits 60 are arranged at substantially equal intervals along the edge 10 d and are covered with the sealing material 51.

  Each seizure prevention circuit 60 is connected in common to the common wiring 321. The end of each data line 12 opposite to the data line driving circuit 43 is connected to a burn-in prevention circuit 60 corresponding to the data line 12. That is, the data line 12 of the first column is connected to the first-stage seizure prevention circuit 60 from the left shown in FIG. 4, and the second-stage seizure prevention circuit 60 is connected to the data of the second column. For example, the line 12 is connected. Further, each burn-in prevention circuit 60 receives a high-side voltage Vdd and a low-side voltage Gnd via a power line 324 and a ground line 325 extending from the scanning line driving circuit 41a to the scanning line driving circuit 41b, respectively. Supplied.

  FIG. 7 is a circuit diagram showing a configuration of one seizure prevention circuit 60. As shown in the figure, the burn-in prevention circuit 60 includes a capacitive element 61, an n-channel type switching element 63, and a control circuit 65. Each transistor constituting the burn-in prevention circuit 60 has the same configuration as the TFT 14 shown in FIG. 6 and is formed in the same process as each TFT 14.

  The capacitive element 61 is a means for holding the voltage at the point P 1 in the control circuit 65, and one end is connected to the point P 1 and the other end is connected to the ground line 325. The capacitor element 61 is formed of a common material in the process of forming the TFT 14 in the manufacturing process of the liquid crystal device D. That is, as shown in FIG. 6, one electrode 611 of the capacitor element 61 is formed in the same process as the semiconductor layer 141 of the TFT 14, and the other electrode 612 is connected to the gate electrode 111 (that is, the scanning line 11) of the TFT 14. It is formed by a common process. More specifically, the semiconductor layer 141 of the TFT 14 and the electrode 611 of the capacitor element 61 are collectively formed in the patterning process of the polysilicon film formed so as to cover the element substrate 10. In the step of patterning the film of aluminum or polysilicon formed so as to cover, the gate electrode 111 and the scanning line 11 of the TFT 14 and the electrode 612 of the capacitor element 61 are collectively formed. Further, the gate insulating film 142 formed so as to cover the electrode 611 together with the semiconductor layer 141 functions as a dielectric interposed between both electrodes of the capacitor 61.

  The switching element 63 shown in FIG. 7 is means for switching conduction and non-conduction between the data line 12 and the common wiring 321 in accordance with the voltage applied to the gate electrode, and the source electrode is connected to the data line 12. The drain electrode is connected to the common wiring 321 while the gate electrode is connected to the point P 2 in the control circuit 65. The capacitance of the capacitive element 61 described above is larger than the capacitance of the switching element 63. More specifically, the capacitive element 61 has a capacitance (about 2000 pF (picofarad)) about twice that of the switching element 63.

  On the other hand, the control circuit 65 holds the voltage corresponding to the high-side voltage Vdd in the capacitor element 61 during the period when the high-side voltage Vdd is supplied via the power line 324, while the voltage of the power line 324 is This is means for applying the voltage charged in the capacitive element 61 to the gate electrode of the switching element 63 until the voltage drops from the higher voltage Vdd. The voltage applied to the power supply line 324 is maintained at the high voltage Vdd when the liquid crystal device D is performing an image display operation, and gradually when the display operation is stopped (that is, when the power is turned off). It decreases and finally coincides with the lower voltage Gnd. Therefore, the control circuit 65 can also be grasped as means for switching between charging of the capacitive element 61 and conduction of the switching element 63 based on a voltage signal whose signal level is either the high-order side voltage Vdd or the low-order side voltage Gnd.

  The control circuit 65 includes n-channel transistors Tr1 and Tr3 and a p-channel transistor Tr2. The threshold voltages Vth of these transistors Tr1 to Tr3 are substantially the same. Among these, the source electrode of the transistor Tr1 is connected to the source electrode of the transistor Tr2 at the point P1, and the drain electrode of the transistor Tr2 is connected to the drain electrode of the transistor Tr3 at the point P2. The drain electrode and gate electrode 111 of the transistor Tr1, the gate electrode 111 of the transistor Tr2, and the gate electrode 111 of the transistor Tr3 are commonly connected to the power supply line 324. The source electrode of the transistor Tr3 is connected to the ground line 325.

  With the above configuration, when the voltage of the power supply line 324 is maintained at the high voltage Vdd (for example, when the liquid crystal device D is performing a display operation), the transistors Tr1 and Tr3 are turned on. Therefore, the electrode 611 of the capacitive element 61 is electrically connected to the power supply line 324 via the point P1 and the transistor Tr1, and as a result, a voltage corresponding to the high-order side voltage Vdd is held by the capacitive element 61. At this time, since the transistor Tr2 is in the off state, the voltage at the point P2 becomes the low voltage Gnd from the ground line 325 via the transistor Tr3. Therefore, the switching element 63 maintains the OFF state, and as a result, the data line 12 and the common wiring 321 are electrically insulated.

  On the other hand, for example, when the operation of the electronic device is operated by the user to stop the display, the voltage supplied from the host device to the power supply line 324 decreases from the high voltage Vdd to the low voltage Gnd. I will do it. Here, when the voltage of the power supply line 324 falls below the threshold voltage Vth of the transistors Tr1 to Tr3, the transistors Tr1 and Tr3 are turned off and the power supply line 324 and the electrode 611 of the capacitor 61 are electrically insulated. The Further, since the transistor Tr2 is turned on at the same time, the electrode 611 of the capacitor 61 and the gate electrode of the switching element 63 are electrically connected via the transistor Tr2 and the point P2. Therefore, the voltage that has been charged in the capacitive element 61 so far is applied to the gate electrode of the switching element 63. By applying this voltage, the switching element 63 is turned on, and the data line 12 and the common wiring 321 become conductive. As a result, the data line 12 and the common wiring 321 have the same potential.

  Thus, when the data line 12 and the common wiring 321 have the same potential, the pixel electrode 15 and the counter electrode 21 that is conducted to the common wiring 321 have substantially the same potential, whereby the charge of the liquid crystal capacitor 172 is removed. Here, a TFT 14 is interposed between each pixel electrode 15 and the data line 12, and each TFT 14 is in an OFF state when the display is stopped. And the counter electrode 21 are set to substantially the same potential, the charge of the liquid crystal capacitor 172 is effectively removed. This is because the off resistance of the TFT 14 is relatively small, and the voltage of the pixel electrode 15 approaches the voltage of the data line 12 (in other words, the voltage of the counter electrode 21) in the long term.

  As described above, in this embodiment, when the voltage of the power supply line 324 is the high voltage Vdd, the voltage is held in the capacitive element 61, and the voltage of the power supply line 324 decreases as the display is stopped. Then, the data line 12 and the common wiring 321 are made conductive by the voltage stored in the capacitor element 61. Therefore, electric charges remaining in the liquid crystal capacitor 172 can be removed and burn-in can be prevented without operating the scanning line driving circuit 41 and the data line driving circuit 43.

  Further, in the present embodiment, since each seizure prevention circuit 60 is provided in the seal area As, the display area is compared with a configuration in which the space for each seizure prevention circuit 60 is secured in other areas. The area of the peripheral region (so-called frame region) can be reduced. In addition, in the present embodiment, the components of each seizure prevention circuit 60 (capacitance element 61, switching element 63, and transistors Tr1 to Tr3 constituting control circuit 65) are common to TFT 14 in display area Ad. Since it is formed in a process, the manufacturing process can be simplified and the manufacturing cost can be reduced as compared with the case where each seizure prevention circuit 60 is formed in an independent process.

<B: Modification>
Various modifications can be added to the above embodiment. Specific modifications are as follows. In addition, the structure which combined each following aspect suitably may be employ | adopted.

<B-1: Modification 1>
In the above embodiment, the configuration in which the data line 12 and the counter electrode 21 (more precisely, the common wiring 321) are made conductive by the seizure prevention circuit 60 is illustrated. However, as shown in FIG. A configuration in which the line 325 is electrically connected may be employed. However, in this configuration, in order to remove the electric charge of the liquid crystal capacitor 172 by setting the data line 12 and the counter electrode 21 to the same potential, the configuration for reducing the voltage of the counter electrode 21 to the lower voltage Gnd is the same as that of the data line 12. Is preferably provided separately. The configuration for this is arbitrary, but from the viewpoint of avoiding complication of the configuration and the manufacturing process, a configuration in which the counter electrode 21 and the ground line 325 are electrically connected by a resistor having a relatively high resistance value is desirable. More specifically, as shown in FIG. 9, a configuration in which a resistor 35 that electrically connects the common wiring 321 that conducts to the counter electrode 21 and the ground line 325 is provided on the element substrate 10 may be employed. According to this configuration, when the supply of the common potential LCcom is stopped, the voltage of the counter electrode 21 decreases to the lower voltage Gnd of the ground line 325 via the common wiring 321 and the resistor 35. Thus, in combination with the configuration in which the data line 12 is electrically connected to the ground line 325, the data line 12 and the counter electrode 21 can be set to substantially the same potential (ground voltage). However, if the configuration in which the host device lowers the potential of the counter electrode 21 from the common potential LCcom to the lower voltage Gnd is employed, the resistor 35 need not be provided.

  Incidentally, it is desirable that the resistor 35 in the configuration of FIG. 9 has a low resistance only from the viewpoint of causing the charge of the counter electrode 21 to leak after the display is stopped and the voltage of the counter electrode 21 to be quickly reduced. However, if the resistance value of the resistor 35 is too low, the through current during the display period may be excessive, which may hinder low power consumption. According to the test by the present inventor against such circumstances, if the resistance value of the resistor 35 is 100 kΩ or more, the power consumption is not a problem, and if the resistance value is 500 kΩ or less, the charge of the counter electrode 21 It has come to the knowledge that can be leaked quickly. Therefore, the resistance value of the resistor 35 is desirably 100 kΩ or more and 500 kΩ or less.

  Further, in the configuration of FIGS. 8 and 9, the rate at which the voltage of the counter electrode 21 decreases (the amount of voltage attenuation per unit time) is the data when the data line 12 is conducted to the ground line 325. It is desirable that it be greater than the rate at which the voltage on line 12 decreases. This is due to the following reason. Since the data line 12 and the counter electrode 21 are opposed to each other with the dielectric liquid crystal 53 interposed therebetween, the data line 12 and the counter electrode 21 are capacitively coupled. Under this configuration, the voltage of the data line 12 is affected by the counter electrode 21 via the coupling capacitance. Therefore, even if the data line 12 is conducted to the ground line 325 by the seizure prevention circuit 60, If the voltage is not lower than or equal to the voltage of the data line 12, the voltage of the data line 12 cannot be effectively reduced to the lower voltage Gnd. Therefore, in the configuration of FIGS. 8 and 9, the speed at which the voltage of the counter electrode 21 decreases is faster than the speed at which the voltage of the data line 12 decreases when the data line 12 is conducted to the ground line 325. Thus, it is desirable that the resistance value of the resistor 35 be determined. In this way, even if a coupling capacitor is attached to the data line 12 and the counter electrode 21, the charge of the liquid crystal capacitor 172 can be quickly removed by conducting the data line 12 to the ground line 325.

<B-2: Modification 2>
In the above embodiment, the configuration in which the burn-in prevention circuit 60 is provided for each data line 12 is illustrated, but a configuration in which one burn-in prevention circuit 60 is shared by a plurality of data lines 12 may be employed. For example, in the burn-in prevention circuit 60 shown in FIG. 10, a plurality of switching elements 63 corresponding to different data lines 12 are provided. The source electrode of each switching element 63 is connected to the data line 12 corresponding to the switching element 63. Further, the gate electrode 111 of each switching element 63 is commonly connected to the point P 2 of the control circuit 65, and the drain electrode is commonly connected to the common wiring 321. Under this configuration, when the voltage of the power supply line 324 decreases as the display is stopped, the switching elements 63 are turned on at the same time, and the data lines 12 and the common wiring 321 become conductive. . Note that the number of data lines 12 sharing one burn-in prevention circuit 60 is arbitrary. For example, one seizure prevention circuit 60 may be provided to electrically connect all the data lines 12 of the liquid crystal device D to the counter electrode 21, or all the data lines 12 are divided into a plurality of blocks. In addition, one seizure prevention circuit 60 may be provided for each block. However, when the interval between the image sticking prevention circuits 60 is widened in a configuration in which a plurality of the image sticking prevention circuits 60 are provided, there may arise a problem that uniform rubbing processing on the alignment film 18 may be hindered. This problem will be described in detail as follows.

  In the manufacturing process of the liquid crystal device D, in order to define the alignment direction of the liquid crystal 53 when no voltage is applied, the alignment film 18 provided on the element substrate 10 is rubbed as shown in FIG. Then, a rubbing process for rubbing in a predetermined direction (the direction of arrow A in the figure) is performed. When the rubbing cloth 80 comes into contact with the anti-seizure circuit 60 on the element substrate 10 during the rubbing process, the tip of the rubbing cloth 80 is slightly disturbed by the step between the surface of the element substrate 10 and the anti-seizure circuit 60. Become. For this reason, in the display area Ad, an area where the anti-seize circuit 60 is provided on the upstream side in the rubbing direction A (an area where hatching is performed in FIG. 11), and no anti-seize circuit 60 exists on the upstream side. The extent of the bristles of the rubbing cloth 80 is different from the region, and as a result, the accuracy of the rubbing process may be different. Here, when each seizure prevention circuit 60 is arranged at a relatively wide interval under the configuration in which the seizure prevention circuit 60 is provided for each of the plurality of data lines 12, the rubbing cloth having a distorted tip is used. Since the contact area is unevenly distributed in the display area Ad, the difference in display quality between this area and the other areas (that is, the area where the seizure prevention circuit 60 does not exist on the upstream side) is remarkably observed. It will be. On the other hand, according to the configuration in which the seizure prevention circuit 60 is provided at a narrow interval for each data line 12 as in the above embodiment, the region where the rubbing tip of the rubbing cloth is disturbed is distributed over the entire display region Ad. Therefore, the difference in display quality due to variation in the accuracy of the rubbing process becomes inconspicuous. Therefore, from the viewpoint of performing a uniform rubbing process on the display area Ad, an anti-seize circuit 60 is provided for each data line 12 as in the above embodiment, and the interval between the anti-seize circuits 60 is reduced. This configuration is desirable. However, if the anti-seizure circuit 60 is not provided on the upstream side in the rubbing direction A with respect to the display area Ad, the difference in the accuracy of the rubbing process due to the step between the anti-seize circuit 60 and the surface of the element substrate 10. Therefore, a configuration in which the image sticking prevention circuit 60 is provided in a region other than the region upstream of the rubbing direction A with respect to the display region Ad is also preferable. For example, in the configuration in which one seizure prevention circuit 60 is provided for all the data lines 12, the seizure prevention circuit 60 is arranged outside the corner of the display area Ad (for example, the position B shown in FIG. 11). ).

<B-3: Modification 3>
In the above embodiment, the configuration in which the period for charging the capacitive element 61 and the period for conducting the data line 12 and the counter electrode 21 are switched according to the voltage applied to the power supply line 324 is exemplified. The voltage applied to the line 324 is not limited. For example, a configuration is adopted in which a signal that maintains an active level during a period in which an image is being displayed and also transitions to an inactive level when the display is stopped is input to the control circuit 65, and then this signal is the active level. In this case, the capacitor element 61 is charged when the switching element 63 is turned on, while the switching element 63 is turned on by the voltage held in the capacitor element 61 when the inactive level is reached. In other words, in the present invention, reference signals having first and second signal levels that are different from each other (the power supplied to the power supply line 324 is also the higher voltage Vdd that is the first signal level and the second signal level. It is sufficient that the charging of the capacitive element 61 and the conduction of the data line 12 and the counter electrode 21 are switched on the basis of the voltage signal that becomes the lower voltage Gnd). The significance is unquestioned. Therefore, means for inputting the signal to the burn-in prevention circuit 60 is not limited to the power supply line 324.

  Further, in the above-described embodiment, the configuration in which the voltage corresponding to the high-side voltage Vdd is held in the capacitive element 61 when the voltage applied to the power supply line 324 is the high-side voltage Vdd is exemplified. The voltage held at is not limited to the voltage according to the signal level of the reference signal. For example, when the reference signal is at the first signal level between one end of the capacitive element 61 and the wiring 32 to which a predetermined voltage is applied (in the above embodiment, the voltage applied to the power supply line 324 is the high voltage Vdd). And the capacitor 61 may be charged by being conducted.

<B-4: Modification 4>
In the above embodiment, the case where the electrode 611 of the capacitor 61 is formed in the same process as the semiconductor layer 141 and the electrode 612 is formed in the same process as the gate electrode 111 is illustrated. The material and the process for forming are not limited to this. For example, the electrode 611 of the capacitor 61 may be formed in the same process as the gate electrode 111 and the electrode 612 may be formed in the same process as the data line 12. That is, it is sufficient that the electrode 611 or the electrode 612 of the capacitor 61 is made of a material common to any of the semiconductor layer 141, the gate electrode 111, and the wiring (data line 12) of the TFT 14. Alternatively, the capacitor element 61 may be formed in a process common to the storage capacitor 171. In this case, the electrode 611 of the capacitor 61 is formed in a process common to the wiring 32 (capacitor line 322), and the electrode 612 is formed in a process common to the data line 12. Of course, the capacitive element 61 may be formed by a process independent of other components of the liquid crystal device D.

<C: Electronic equipment>
Next, a projector using the above-described liquid crystal device D as a light valve will be described as an example of an electronic device using the electro-optical device according to the above-described embodiment. FIG. 12 is a plan view showing the configuration of the projector. As shown in this figure, a projector 2100 is provided with a lamp unit 2102 composed of a white light source such as a halogen lamp. The projection light emitted from the lamp unit 2102 is separated into three primary colors of R (red), G (green), and B (blue) by three mirrors 2106 and two dichroic mirrors 2108 arranged inside. Are guided to the light valves 100R, 100G and 100B corresponding to the respective primary colors. Note that B light has a longer optical path than other R and G colors, and therefore, in order to prevent the loss, B light passes through a relay lens system 2121 including an incident lens 2122, a relay lens 2123, and an exit lens 2124. Led.

  Here, the configuration of the light valves 100R, 100G, and 100B is the same as that of the liquid crystal device D in the above-described embodiment, and is an image signal corresponding to each color of R, G, and B supplied from a processing circuit (not shown). Each is driven. The lights modulated by the light valves 100R, 100G, and 100B are incident on the dichroic prism 2112 from three directions. In the dichroic prism 2112, the R and B light beams are refracted at 90 degrees, while the G light beam travels straight. Therefore, after the images of the respective colors are combined, a color image is projected onto the screen 2120 by the projection lens 2114.

  Since light corresponding to the primary colors R, G, and B is incident on the light valves 100R, 100G, and 100B by the dichroic mirror 2108, it is not necessary to provide a color filter. In addition, the transmission images of the light valves 100R and 100B are projected after being reflected by the dichroic prism 2112, whereas the transmission image of the light valve 100G is projected as it is, so the horizontal scanning direction by the light valves 100R and 100B is The left-right reversed image is displayed in the direction opposite to the horizontal scanning direction by the light valve 100G.

  In addition to the projector shown in FIG. 12, the electronic apparatus in which the electro-optical device according to the invention can be used includes a mobile phone, a portable personal computer, a liquid crystal television, a viewfinder type (or a monitor direct view type). Video recorders, car navigation devices, pagers, electronic notebooks, calculators, word processors, workstations, videophones, POS terminals, devices equipped with touch panels, and the like.

It is a perspective view which shows the structure of the liquid crystal device which concerns on embodiment of this invention. It is sectional drawing seen from the II-II line | wire in FIG. It is sectional drawing seen from the III-III line in FIG. It is a block diagram which shows the structure of each element provided on the element board | substrate among the liquid crystal devices. 2 is a circuit diagram illustrating a configuration of a pixel in the liquid crystal device. FIG. It is sectional drawing which expands and shows each element on an element board | substrate among the liquid crystal devices. It is a circuit diagram which shows the structure of the image sticking prevention circuit among the liquid crystal devices. It is a circuit diagram which shows the structure of the burn-in prevention circuit among the liquid crystal devices which concern on a modification. It is a block diagram which shows the structure of each element provided on the element board | substrate among the liquid crystal devices which concern on the modification. It is a circuit diagram which shows the structure of the burn-in prevention circuit among the liquid crystal devices which concern on a modification. It is a figure for demonstrating the predominance of the liquid crystal device which concerns on embodiment. It is a figure which shows the structure of the projector which is an example of the electronic device which concerns on this invention.

Explanation of symbols

D: Liquid crystal device (electro-optical device), 10: Element substrate (substrate), 10a, 10b, 10c, 10d ... Edge, As ... Seal region, Ad ... Display region, P ... Pixel, 11 ... ... Scanning line, 12 ... Data line, 14 ... TFT, 15 ... Pixel electrode, 172 ... Liquid crystal capacitance, 141 ... Semiconductor layer, 111 ... Gate electrode, 142 ... Gate insulating film, 20 ... Opposite Substrate (other substrate), 21... Counter electrode, 31 .. connection terminal, 32 .. wiring, 34 .. vertical conduction electrode, 321 .. common wiring, 324 .. power supply line, 325. (41a, 41b) ... scanning line drive circuit, 43 ... data line drive circuit, 51 ... sealing material, 52 ... conducting material, 53 ... liquid crystal (electro-optical material), 60 ... seizure prevention circuit (Charge removal circuit), 61... Capacitance element, 611, 612 ... electrode, 63 ...... switching element (switching means), 65 ...... control circuit (control means).

Claims (8)

A charge removal circuit for an electro-optical device, comprising: a pixel electrode disposed corresponding to an intersection of a scanning line and a data line; and a counter electrode facing the pixel electrode with an electro-optical material interposed therebetween,
A resistor for electrically connecting the counter electrode and the ground line;
A power supply line to which a reference signal that changes from a higher voltage to a lower voltage lower than the higher voltage is input;
A capacitive element that holds the voltage;
Switching means for conducting the data line and the ground line when an on-voltage is applied to the gate;
A first transistor having a gate electrode and a drain electrode connected to the power supply line, a gate electrode connected to the power supply line, and a source electrode connected to the source electrode of the first transistor and one end of the capacitor element, respectively. The transistor and the gate electrode are connected to the power supply line, the drain electrode is connected to the drain electrode of the second transistor and the gate of the switching means, and the third electrode is connected to the ground line. When the reference signal input to the power supply line is the high voltage, the first and third transistors are turned on and the second transistor is turned off, and the power supply line and the control circuit are control circuits. by conduction and capacitive elements, one for holding the voltage on the capacitor, the reference signal is the low-potential electrostatic When becomes, the first and third transistors are turned off state and the second transistor is turned on, a control circuit for applying a voltage held in the capacitive element to the gate of the switching means as the ON voltage equipped with,
The resistance is 100 kΩ or more and 500 kΩ or less, and when the data line and the ground line are made conductive by the switching means, the attenuation of the voltage per unit time of the counter electrode in which the supply of the common potential is stopped A charge removal circuit in which the amount is set to a resistance value larger than a voltage attenuation amount per unit time of the data line . A substrate for holding an electro-optic material;
A pixel electrode disposed on the substrate corresponding to the intersection of the scan line and the data line;
A counter electrode facing the pixel electrode across the electro-optic material;
The charge removal circuit of claim 1 disposed on the substrate;
An electro-optical device comprising: The electro-optical device according to claim 2 , wherein a plurality of the charge removal circuits each corresponding to one or a plurality of the data lines are arranged on the substrate . The electro-optical device according to claim 3 , wherein the plurality of charge removal circuits are arranged at substantially equal intervals along the periphery of the substrate . A substrate for holding an electro-optic material;
A plurality of pixel electrodes each disposed on the substrate corresponding to an intersection of a plurality of scanning lines and a plurality of data lines;
A counter electrode facing each of the pixel electrodes with the electro-optic material interposed therebetween;
A charge removal circuit disposed on the substrate;
The charge removal circuit includes:
A resistor for electrically connecting the counter electrode and the ground line;
A power supply line to which a reference signal that changes from a higher voltage to a lower voltage lower than the higher voltage is input;
A capacitive element that holds the voltage;
Switching means for conducting the data line and the ground line when an on-voltage is applied to the gate;
A first transistor having a gate electrode and a drain electrode connected to the power supply line, a gate electrode connected to the power supply line, and a source electrode connected to the source electrode of the first transistor and one end of the capacitor element, respectively. The transistor and the gate electrode are connected to the power supply line, the drain electrode is connected to the drain electrode of the second transistor and the gate of the switching means, and the third electrode is connected to the ground line. When the reference signal input to the power supply line is the high voltage, the first and third transistors are turned on and the second transistor is turned off, and the power supply line and the control circuit are control circuits. by conduction and capacitive elements, one for holding the voltage on the capacitor, the reference signal is the low-potential electrostatic When becomes, the first and third transistors are turned off state and the second transistor is turned on, a control circuit for applying a voltage held in the capacitive element to the gate of the switching means as the ON voltage equipped with,
The resistance is 100 kΩ or more and 500 kΩ or less, and when the data line and the ground line are made conductive by the switching means, the attenuation of the voltage per unit time of the counter electrode in which the supply of the common potential is stopped An electro-optical device in which the amount is set to a resistance value larger than the voltage attenuation amount per unit time of the data line . Another substrate that sandwiches the electro-optic material in a gap with the substrate;
Comprising a sealing material for bonding the substrate and the other substrate;
At least a part of the charge removal circuit is disposed in a region of the substrate facing the sealing material.
The electro-optical device according to claim 2 . Comprises a semi-conductor layer and the gate electrode layer and a wiring layer, comprising a transistor turned on thereby turning on said pixel electrode and the data line when the scanning line is selected,
At least one electrode constituting the capacitance element includes a semiconductor layer, an electro-optical device according to any one of claims 2 to 6, and one of the gate electrode layer and a wiring layer made of a common conductive material of said transistor.   An electronic apparatus comprising the electro-optical device according to claim 2 as a display device.

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