JP4501947B2 - Electro-optical device, display device, and electronic apparatus including the same - Google Patents

Description

  The present invention relates to, for example, an electro-optical device, a display device, and an electronic apparatus including the same.

  2. Description of the Related Art In recent years, a technology for mounting a photosensor function on a display device, particularly in a liquid crystal display device using a thin film transistor, has been developed (for example, Patent Document 1). The purpose of mounting the optical sensor is (1) to reduce power consumption and improve image quality by measuring external light and adjusting brightness, etc. (2) measuring backlight and adjusting brightness or chromaticity, (3 3) The position of the finger or light pen is recognized and used as a touch key. Examples of the optical sensor include a thin film transistor, a PIN (p-intrinsic-n) diode, and a PN diode. In any case, the light receiving portion is a silicon thin film and does not increase the manufacturing cost. Therefore, it is desirable that the light receiving portion is manufactured in the same manufacturing process as the silicon thin film constituting the display switching element. When the photosensor is composed of a thin film transistor, PIN diode, PN diode, etc., the current flowing through the sensor is the sum of the photocurrent that changes according to the illuminance of the irradiated light and the thermal current that increases with an exponential function of the absolute temperature of the sensor. Become. For this reason, in order to obtain correct illuminance even at a relatively high temperature, it is necessary to effectively remove this thermal current. For this reason, there is a case where a light-shielded light-shielding sensor for a thermal current reference and a light-receiving sensor that is not shielded from light are arranged (for example, Patent Document 1).

JP 2006-118965 A

  When the light-shielding sensor and light-receiving sensor are placed near the display area, the light from the display area partially becomes stray light and is irradiated to the light-receiving sensor and the light-shielding sensor, so the photocurrent for stray light is detected as an error. . In addition, a temperature difference occurs between the light receiving sensor and the light shielding sensor, the thermal current is not uniform, and this thermal current difference also becomes an error. The present invention solves these problems and realizes an electro-optical device including a photosensor with higher accuracy.

The present invention relates to a panel (a liquid crystal panel 911 in the embodiment) in which a display region is formed by sandwiching an electro-optical material (a nematic phase liquid crystal material 922 in the embodiment) between the first and second substrates. A light detection unit (in the embodiment, a detection circuit 360, a light receiving sensor 350P, and the like) that detects the illuminance of ambient light of the panel, and a light source (in the embodiment, a back light) that irradiates the display area of the panel The second substrate is provided with a counter electrode to which a signal that is periodically inverted is applied, and the light detection unit is provided on the first substrate. A first photosensor (light receiving sensor 350P) provided at the peripheral edge of the display area and irradiated with external light, and a second photosensor (blocking sensor 350D in the embodiment) that blocks external light irradiation. Wherein the a first optical sensor and the second optical sensor includes a light shielding electrode and the second transparent electrode disposed on the side opposite the substrate that blocks emission of light from a light source The first optical sensor and the second optical sensor are electro-optical devices which are opposed to the counter electrode and are arranged in a plurality at the periphery of the display area. With this arrangement, it is possible to prevent the detection result from being remarkably changed by a finger or a small shadow, and at the same time, it is possible to prevent a decrease in accuracy due to a thermal current difference caused by the temperature distribution in the apparatus.

The present invention, before Symbol light source is a display region periphery, the first optical sensor and the second optical sensor is an electro-optical device is disposed on a side that is not disposed.
If comprised in this way, since the difference of the thermal current between the said 1st photosensor and said 2nd photosensor by the temperature gradient by a light source can be made as small as possible, a thermal current can be excluded accurately.

  The present invention is the electro-optical device in which the first photosensor and the second photosensor are alternately arranged. With this arrangement, even if there is a temperature distribution in the display device, there is no significant difference between the average temperatures of the first photosensor and the second photosensor, so that the thermal current can be excluded more accurately.

  Further, according to the present invention, the first photosensor and the second photosensor arranged adjacent to the first photosensor are mutually connected to a boundary side of the display region (in the embodiment, a dotted line indicating a boundary side of the display region 310). The electro-optical device is characterized in that the distances from are substantially equal. With this arrangement, so-called stray light generated by multiple reflection of light from the display region at the interface between the glass substrate and the insulating film is evenly emitted by the first photosensor and the second photosensor. The accuracy difference due to stray light does not occur by taking the current difference between the first optical sensor and the second optical sensor.

  Further, the present invention provides a plurality of openings (in the embodiment, light receiving openings 990-1 to 990-1) provided in the first or second substrate for irradiating the first light sensor with ambient light of the panel. 990-10) The size is in the range of 0.5 mm to 20 mm in the direction parallel to the boundary edge of the display area periphery where the opening is disposed, and the display area periphery where the opening is disposed. The electro-optical device is formed to have a thickness of 0.05 mm or more and not more than the thickness of the counter substrate in a direction orthogonal to the boundary side of the part. When the opening is set in this way, the stray light is small and the difference in thermal current due to the temperature distribution in the apparatus is also reduced, so that a reduction in accuracy can be prevented.

  Further, according to the present invention, the plurality of openings are a first opening (in the embodiment, a light receiving opening 990) disposed on a side opposite to the side on which the light source is disposed, in the periphery of the front region. -1 to 990-6) and a second opening (in the embodiment, light receiving openings 990-7 to 990-10) arranged on a side substantially orthogonal to the arrangement side, the first In the electro-optical device, the opening area of the opening is larger than the second opening area. When the temperature gradient varies depending on the location of the opening, the influence of the temperature gradient can be reduced by reducing the size of the opening as the temperature gradient increases. More specifically, among the four sides of the display area, the side close to the first opening and the side close to the second opening are different display devices. The size of the opening may be reduced as the temperature gradient becomes larger.

  In the invention, it is preferable that the first photosensor and the second photosensor are PIN junction diodes or PN junction diodes using thin film polysilicon. Such a diode has the merit that it can be formed on a semiconductor device using a polysilicon thin film transistor without an additional manufacturing step, but the ratio of the thermal current to the photocurrent is larger than the photosensors formed on the single crystal wafer. It is suitable for applying the present invention.

  The present invention also proposes an electronic device using these display devices. The built-in photo sensor with high accuracy regardless of temperature makes it easy to control the backlight according to the external light, does not increase the power consumption meaningless, and does not increase the cost. In addition, since the photo sensor can be arranged near the display area, the degree of freedom in design is improved.

  Hereinafter, embodiments of an electro-optical device, a display device, and an electronic apparatus including the same according to the present invention will be described with reference to the drawings.

[First Embodiment]
FIG. 1 is a perspective configuration diagram (partially sectional view) of a liquid crystal display device 910 according to the present embodiment. The liquid crystal display device 910 includes an active matrix substrate 101 (semiconductor device) and a counter substrate 912 that are bonded to each other with a sealant 923 at a predetermined interval and sandwiched with a nematic phase liquid crystal material 922. Although not shown, an alignment material made of polyimide or the like is applied onto the active matrix substrate 101 and rubbed to form an alignment film. The counter substrate 912 includes a color filter corresponding to a pixel (not shown), a black matrix 940 made of a low-reflection / low-transmittance resin for preventing light leakage and improving contrast, and an active matrix substrate 101. A counter electrode 930 made of an ITO film to which a common potential that is short-circuited with the counter conductive portions 330-1 to 330-2 is supplied is formed. An alignment material made of polyimide or the like is applied to the surface in contact with the nematic phase liquid crystal material 922, and is rubbed in a direction orthogonal to the direction of the rubbing treatment of the alignment film of the active matrix substrate 101.

  Further, an upper polarizing plate 924 is disposed outside the counter substrate 912, and a lower polarizing plate 925 is disposed outside the active matrix substrate 101, so that the polarization directions thereof are orthogonal to each other (crossed Nicols). Further, a backlight unit 926 and a light guide plate 927 are disposed below the lower polarizing plate 925, and light is emitted from the backlight unit 926 toward the light guide plate 927. The light guide plate 927 activates light from the backlight unit 926. It functions as a light source of the liquid crystal display device 910 by reflecting and refracting light so that it becomes a vertical and uniform surface light source toward the matrix substrate 101. The backlight unit 926 is an LED unit in this embodiment, but may be between cold cathodes (CCFL). The backlight unit 926 is connected to the electronic device main body through the connector 929 and supplied with power. In this embodiment, the amount of light from the backlight unit 926 is adjusted by appropriately adjusting the power source to an appropriate current and voltage. It has a function.

  Although not shown, if necessary, the periphery may be covered with an outer shell, or a protective glass or acrylic plate may be attached further above the upper polarizing plate 924, and optical for improving the viewing angle. A compensation film may be attached.

  Further, an optical sensor light receiving opening 990 is provided on the outer peripheral portion of the liquid crystal display device 910. The active matrix substrate 101 is provided with a protruding portion 102 that extends from the counter substrate 912, and an FPC (flexible substrate) 928 is mounted on and electrically connected to the signal input terminal 320 in the protruding portion 102. ing. An FPC (flexible substrate) 928 is connected to the main body of the electronic device and supplied with necessary power, control signals, and the like.

  Further, on the liquid crystal display device 910, six light sensor light receiving openings 990-1 to 990-6 are provided. These light receiving openings 990-1 to 990-6 are formed by partially removing the black matrix 940 on the counter electrode 930 so that external light reaches the active matrix substrate 101. . The black matrix 940 on the counter electrode 930 is not removed around each of the light receiving openings 990-1 to 990-6, and external light does not reach the active matrix substrate 101.

  FIG. 2 is a block diagram of the active matrix substrate 101. On the active matrix substrate 101, 480 scanning lines 201-1 to 201-480 and 1920 data lines 202-1 to 202-1920 are formed orthogonally, and 480 capacitance lines 203-1 are formed. ˜203-480 are arranged in parallel with the scanning lines 201-1 to 201-480. The capacitor lines 203-1 to 203-480 are short-circuited to each other, connected to the common potential wiring 335, and further connected to the two opposing conductive portions 330-1 to 330-2, and 0 V-5 V from the signal input terminal 320. A common potential having an inversion signal and an inversion time of 35 μsec is applied. The scanning lines 201-1 to 201-480 are connected to the scanning line driving circuit 301, and the data lines 202-1 to 202-1920 are connected to the data line driving circuit 302 and are driven appropriately. The scanning line driver circuit 301 and the data line driver circuit 302 are supplied with signals necessary for driving from a signal input terminal 320. The signal input terminal 320 is disposed on the overhanging portion 102. On the other hand, the scanning line driver circuit 301 and the data line driver circuit 302 are arranged in a region overlapping with the counter substrate 912, that is, outside the projecting portion 102. The scanning line driving circuit 301 and the data line driving circuit 302 are formed on the active matrix substrate by a system-on-glass (SOG) technology that integrates circuit functions necessary for driving on the active matrix substrate by a low-temperature polysilicon TFT process. It is formed by integrating polysilicon thin film transistors, and is a so-called drive circuit built-in type liquid crystal display device manufactured in the same process as a pixel switching element 401-nm described later.

  In addition, six light receiving sensors 350P-1 to 350P-6 are respectively formed in areas overlapping with the six light receiving openings 990-1 to 990-6, and the six light shielding sensors 350D are alternately arranged. -1 to 350D-6 are formed. The light receiving sensors 350P-1 to 350P-6 and the light shielding sensors 350D-1 to 350D-6 are also formed on the active matrix substrate by the system on glass (SOG) technology. Thus, manufacturing cost can be reduced by manufacturing on the glass substrate by the same process as pixel switching element 401-nm.

  The light receiving sensors 350P-1 to 350P-6 overlap with the light receiving openings 990-1 to 990-6 in plan view, and external light reaches the sensor, but the light blocking sensors 350D-1 to 350D-6 are light receiving openings 990. -1 to 990-6 do not overlap in plane, and external light is absorbed by the black matrix 940 on the counter electrode 930 and hardly reaches. The light receiving sensors 350P-1 to 350P-6 are connected to the wiring PBT, the wiring VSH, and the wiring SENSE, and the light shielding sensors 350D-1 to 350D-6 are connected to the wiring DBT, the wiring VSL, and the wiring SENSE. These wiring PBT, wiring VSH, wiring SENSE, wiring DBT, and wiring VSL are connected to the detection circuit 360. The detection circuit 360 converts the signal into a binary output signal OUT having a pulse length corresponding to the output analog current correlated with the external light illuminance from the light receiving sensors 350P-1 to 350P-6 and the light shielding sensors 350D-1 to 350D-6. Output to the input terminal 320. Further, the wiring VCHG, the wiring RST, the wiring VSL, and the wiring VSH are also supplied to the detection circuit 360 through the signal input terminal 320.

  Although details will be described later, the light receiving sensors 350P-1 to 350P-6 are backlight light shielding electrodes 611P-1 to 611P-6, and the light shielding sensors 350D-1 to 350D-6 are backlight light shielding electrodes 611D-1 to 611D-6. Since the light beams from the backlights are shielded from each other in a planar manner, the detection accuracy of the external light is not lowered by the light from the backlights. The light receiving sensors 350P-1 to 350P-6 also overlap with the transparent electrodes 612P-1 to 612P-6, and the light shielding sensors 350D-1 to 350D-6 overlap with the transparent electrodes 612D-1 to 612D-6. The dotted line indicates the boundary side of the display area 310.) The detection accuracy is not deteriorated by electromagnetic noise generated when driving. With these configurations, the light receiving sensors 350P-1 to 350P-6 and the light shielding sensors 350D-1 to 350D-6 do not deteriorate the detection accuracy even if they are arranged near the display area 310, so that the degree of freedom in design is higher than that of conventional products. Has improved.

  Here, as shown in the present embodiment, the light receiving openings 990-1 to 990-6 are preferably divided into a plurality of portions and dispersed in as wide a range as possible. For example, even if a shadow such as a finger partially covers the liquid crystal display device 910, the total area of the light receiving openings is preferably as large as possible in consideration of reducing the influence on the detection of external light. If the sensors are gathered in one place, the distance from the light shielding sensor is inevitably increased, and a temperature distribution is generated in the liquid crystal display device 910, so that an average temperature difference occurs between the light receiving sensor portion and the light shielding sensor portion. Therefore, if the sensor is divided into several parts as in the present embodiment and more preferably alternately arranged, the average temperature of the light receiving sensor part and the light shielding sensor part can be made substantially equal. In the present embodiment, it is divided into six, but of course, it may be smaller or larger.

  At this time, the light receiving openings 990-1 to 990-6 may be arranged to have the same distance from the display area 310. Similarly, the distances from the light receiving sensors 350P-1 to 350P-6 and the light shielding sensors 350D-1 to 350D-6 to the display area 310 are preferably equal. Light that is transmitted from the display region 310 to the outside for display is, for example, multiply reflected by the glass constituting the active matrix substrate 101 and the counter substrate 912, the surface of the upper polarizing plate 924, the interfaces of various insulating films, and the like. Although stray light enters each optical sensor, the amount of stray light between the light receiving sensors 350P-1 to 350P-6 and the light shielding sensors 350D-1 to 350D-6 becomes substantially constant when arranged as described above. If the current difference between each light receiving sensor 350P-1 to 350P-6 and each light shielding sensor 350D-1 to 350D-6 is taken as in this embodiment, the stray light component can be substantially removed. From this point of view, it is preferable that the light receiving openings 990-1 to 990-6 are divided into a plurality of parts and dispersed in as wide a range as possible because the display pattern of the display area 310 is less affected.

  Further, it is preferable that the light receiving sensors 350P-1 to 350P-6 and the light shielding sensors 350D-1 to 350D-6 are arranged as far as possible from the backlight unit 926 as shown in the present embodiment. Since the backlight unit 926 is a heat source, whether it is an LED or a CCFL, the closer to the backlight unit 926, the greater the thermal gradient in the active matrix substrate 101, and the light receiving sensors 350P-1 to 350P-6, the light shielding sensors. This is because a temperature difference is easily generated between 350D-1 to 350D-6.

  The size of the light receiving openings 990-1 to 990-6 is a direction parallel to the boundary edge of the peripheral portion of the display area 310 where the light receiving openings 990-1 to 990-6 are arranged (hereinafter referred to as X direction). )), It is affected by temperature distribution and stray light. Further, if the size is increased in a direction orthogonal to the boundary side of the display area 310 (hereinafter referred to as Y direction), the frame area becomes larger and the outer size of the liquid crystal display device 910 becomes larger, and the counter substrate 912 and the upper polarizing plate. The light in the display area 310 reflected at the interface 924 is strongly irradiated as stray light to the light receiving sensors 350P-1 to 350P-6 and the light shielding sensors 350D-1 to 350D-6, which causes a measurement error. On the other hand, if it is made too small in the X direction, the placement efficiency will deteriorate, the channel width (W) of the PIN diode will become small, and if it is made small in the Y direction, the light capture efficiency will deteriorate, affecting the detection accuracy. Occurs. As a result of examination based on the above conditions, it is desirable that the thickness is in the range of 0.5 mm to 20 mm in the X direction and 0.05 mm to the thickness of the counter substrate 912 (0.6 mm in this embodiment) in the Y direction. The conclusion was reached. Based on the above, in this embodiment, the X direction is set to 10 mm and the Y direction is set to 0.3 mm.

  The arrangement pitch of the light receiving openings 990-1 to 990-6 is 20 mm, the pitch of the light receiving sensor 350P-1 and the light shielding sensor 350D-1 is 10 mm, the pitch of the light shielding sensor 350D-1 and the pitch of the light receiving sensor 350P-2. The light receiving sensors 350P-1 to 350P-6 and the light shielding sensors 350D-1 to 350D-6 are alternately arranged at a pitch of 10 mm.

  FIG. 3 is a circuit diagram near the intersection of the mth data line 202-m and the nth scanning line 201-n in the display area indicated by the dotted line 310 in FIG. A pixel switching element 401-nm including an N-channel field effect polysilicon thin film transistor is formed at each intersection of the scanning line 201-n and the data line 202-m, and the gate electrode thereof is the scanning line 201-n. The source and drain electrodes are connected to the data line 202-m and the pixel electrode 402-nm, respectively. The pixel electrode 402-nm and the electrode short-circuited to the same potential form a capacitor line 203-n and an auxiliary capacitor 403-nm, and when assembled as a liquid crystal display device, the liquid crystal element is sandwiched. Thus, a capacitor is formed with the counter electrode 930 (common electrode).

  FIG. 4 is a block diagram showing a specific configuration of the electronic apparatus in this embodiment. The liquid crystal display device 910 is the liquid crystal display device described in FIG. 1, and the external power supply circuit 784 and the video processing circuit 780 send necessary signals and power to the liquid crystal display device 910 through an FPC (flexible substrate) 928 and a connector 929. Supply. The central processing circuit 781 acquires input data from the input / output device 783 via the external I / F circuit 782. Here, the input / output device 783 is, for example, a keyboard, a mouse, a trackball, an LED, a speaker, an antenna, or the like. The central processing circuit 781 performs various arithmetic processing based on data from the outside, and transfers the result to the video processing circuit 780 or the external I / F circuit 782 as a command. The video processing circuit 780 updates the video information based on the command from the central processing circuit 781 and changes the signal to the liquid crystal display device 910, whereby the display video of the liquid crystal display device 910 changes. Further, the binary output signal OUT from the detection circuit 360 on the liquid crystal display device 910 is input to the central arithmetic circuit 781 through the FPC (flexible substrate) 928, and the central arithmetic circuit 781 determines the pulse length of the binary output signal OUT. Convert to the corresponding discrete value. Next, the central processing circuit 781 accesses a reference table 785 comprising an EEPROM (Electronically Erasable and Programmable Read Only Memory), reconverts the converted discrete value into a value corresponding to an appropriate voltage of the backlight unit 926, and external power supply. Transmit to circuit 784. The external power supply circuit 784 supplies a potential power supply having a voltage corresponding to the transmitted value to the backlight unit 926 in the liquid crystal display device 910 through the connector 929. Since the luminance of the backlight unit 926 varies depending on the voltage supplied from the external power supply circuit 784, the luminance of the liquid crystal display device 910 when displaying all white also varies. Specifically, the electronic device includes a monitor, a TV, a notebook computer, a PDA, a digital camera, a video camera, a mobile phone, a mobile photo viewer, a mobile video player, a mobile DVD player, a mobile audio player, and the like.

  In this embodiment, the luminance of the backlight unit 926 is controlled by the central processing circuit 781 on the electronic device. For example, the liquid crystal display device 910 includes a driver IC and an EEPROM, and the driver IC has a binary output. A conversion function from the signal OUT to the discrete value, a re-conversion function with reference to the EEPROM, and a function for adjusting the output voltage to the backlight unit 926 may be provided. Further, a configuration may be adopted in which a discrete value is converted into a value corresponding to the voltage of the backlight unit 926 by numerical calculation without using a reference table.

  FIG. 5 is a plan view showing an actual configuration of the circuit diagram of the pixel display region shown in FIG. As shown in the legend of FIG. 5, different shaded parts indicate different material wirings, and the same shaded parts indicate the same material wiring. It consists of a five-layer thin film of chromium thin film (Cr), polysilicon thin film (Poly-Si), molybdenum thin film (Mo), aluminum neodymium alloy thin film (AlNd), and indium tin oxide thin film (Indium Tin Oxed = ITO). Thus, an insulating film formed by laminating any one of silicon oxide, silicon nitride, and an organic insulating film is formed between the respective layers. Specifically, the chromium thin film (Cr) has a thickness of 100 nm, the polysilicon thin film (Poly-Si) has a thickness of 50 nm, the molybdenum thin film (Mo) has a thickness of 200 nm, the aluminum-neodymium alloy thin film (AlNd) has a thickness of 500 nm, The indium oxide / tin thin film (ITO) has a thickness of 100 nm. In addition, a base insulating film in which a 100 nm silicon nitride film and a 100 nm silicon oxide film are stacked is formed between the chromium thin film (Cr) and the polysilicon thin film (Poly-Si), and the polysilicon thin film (Poly-Si) and Between the molybdenum thin film (Mo), a gate insulating film made of a 100 nm silicon oxide film is formed. Between the molybdenum thin film (Mo) and the aluminum-neodymium alloy thin film (AlNd), a 200 nm silicon nitride film and a 500 nm oxide film are formed. An interlayer insulating film formed by laminating a silicon film is formed, and a 200 nm silicon nitride film and an average 1 μm organic planarizing film are laminated between an aluminum / neodymium alloy thin film (AlNd) and an indium oxide / tin thin film (ITO). A protective insulating film is formed to insulate the wires from each other, and contact holes are opened at appropriate positions. It is connected to the stomach. In FIG. 5, there is no chromium thin film (Cr) pattern.

  As shown in FIG. 5, the data line 202-m is formed of an aluminum-neodymium alloy thin film (AlNd) and is connected to the source electrode of the pixel switching element 401-nm through a contact hole. The scanning line 201-n is composed of a molybdenum thin film (Mo) and also serves as the gate electrode of the pixel switching element 401-nm. The capacitor line 203-n is made of the same wiring material as the scanning line 201-n, the pixel electrode 402-nm is made of an indium oxide / tin thin film, and a contact hole is formed in the drain electrode of the pixel switching element 401-nm. Connected through. Further, the drain electrode of the pixel switching element 401-nm is also connected to a capacitor electrode 605 made of an n + type polysilicon thin film heavily doped with phosphorus, and overlaps the capacitor line 203-n in plan view to form an auxiliary capacitor. Condenser 403-nm is formed.

  FIG. 6 is a diagram showing a partial cross-sectional structure of the liquid crystal display device 910 corresponding to the AA ′ line portion of FIG. 5 for explaining the structure of the pixel switching element 401 -nm. Note that the scale is not constant in order to make the drawing easier to see. The active matrix substrate 101 is an insulating substrate made of alkali-free glass and having a thickness of 0.6 mm, and is made of a polysilicon thin film through a base insulating film in which a 200 nm silicon nitride film and a 300 nm silicon oxide film are stacked on the substrate. A silicon island 602 is arranged, and the scanning line 201-n is arranged above the silicon island 602 and the gate insulating film.

  In the region overlapping with the scanning line 201-n, the silicon island 602 is an intrinsic semiconductor region 602I in which phosphorus ions are not doped at all or only in a very low concentration, and a sheet resistance of about 20 kΩ in which phosphorus ions are lightly doped on the left and right sides thereof. This is an LDD (Lightly Doped Drain) structure in which n-regions 602L exist and n + regions 602N having a sheet resistance of about 1 kΩ doped with phosphorus ions at a high concentration are present on the left and right sides thereof. The left and right n + regions 602N are connected to the source electrode 603 and the drain electrode 604 through contact holes respectively formed in the interlayer insulating film. The source electrode 603 is connected to the data line 202-m, and the drain electrode 604 is connected to the interlayer insulating film. The pixel electrodes 402-nm are respectively connected to the pixel electrodes 402-nm. A nematic phase liquid crystal material 922 exists between the pixel electrode 402 -nm and the counter electrode 930 on the counter substrate 912. In addition, a black matrix 940 is formed over the counter substrate 912 so as to partially overlap with the pixel electrodes 402-nm. In the case where the light leakage current of the pixel switching element 401-nm becomes a problem, a light shielding layer made of a Cr film may be formed under the silicon island 602. In this embodiment, the light leakage current is hardly a problem, and if such a structure is adopted, the mobility of the pixel switching element 401-nm is lowered, and therefore a configuration in which the Cr film under the silicon island 602 is removed is selected. did.

  FIG. 7 is a diagram showing a partial cross-sectional structure of the liquid crystal display device 910 corresponding to the BB ′ line portion of FIG. 5 for explaining the structure of the auxiliary capacitor 403-nm. The connected capacitor electrode 605 and the capacitor line 203-n overlap with each other with the gate insulating film interposed therebetween to form a storage capacitor.

  FIG. 8 is an enlarged plan view of the vicinity of the light receiving sensor 350P-1 (first optical sensor) and the light shielding sensor 350D-1 (second optical sensor). Note that the vertical and horizontal scales are not constant for easy viewing of the figure. The legend is the same as in FIG. The light receiving sensor 350P-1 overlaps the light receiving opening 990-1 indicated by a thick dotted line in a plan view so that external light is irradiated. The light receiving sensor 350P-1 includes four isolated light receiving portions 350P-1I, an anode region 350P-1P connected to the wiring SENSE adjacent thereto, and a cathode region 350P-1N connected to the wiring VSH. The light receiving part 350P-1I, the anode region 350P-1P, and the cathode region 350P-1N are all configured by separating the same polysilicon thin film islands by the difference in doping concentration, and the anode region 350P-1P has a relatively high concentration. The cathode region 350P-1N is doped with a relatively high concentration of phosphorus ions, and the light receiving portion 350P-1I contains boron ions and phosphorus ions only at a very low concentration. The anode region 350P-1P, the cathode region 350P-1N, and the light receiving portion 350P-1I each have a width of 10 μm, and the length of the light receiving portion 350P-1I is 1000 μm. Thus, the light receiving sensor 350P-1 constitutes a plurality of parallel-connected PIN junction diodes. Although the common potential wiring 335 is disposed on the side of the light receiving sensor 350P-1 and the light shielding sensor 350D-1 that are close to the display area 310, in this embodiment, it is not connected to the light receiving sensor 350P-1 and the light shielding sensor 350D-1. In order to avoid the influence of electromagnetic noise, they are arranged 100 μm apart.

  The light shielding sensor 350D-1 includes four isolated light receiving portions 350D-1I, an anode region 350D-1P connected to the wiring VSL adjacent thereto, and a cathode region 350D-1N connected to the wiring SENSE. The light receiving sensor 350P-1 and the light shielding sensor 350D-1 have the same configuration except that the wiring to which the cathode and the anode are connected is different and that the light receiving opening 990-1 does not overlap in plan view. Description of is omitted. The light receiving sensors 350P-2 to 350P-5 have the same configuration except for the light receiving sensor 350P-1, and the light shielding sensors 350D-2 to 350D-5 have the same structure except for the arrangement positions. Omitted.

  FIG. 9 is a diagram showing a partial cross-sectional structure of the liquid crystal display device 910 corresponding to the line CC ′ line portion of FIG. 8 for explaining the structure of the light receiving sensor 350P-1. A backlight light shielding electrode 611P-1 (first light shielding electrode) is disposed on the active matrix substrate 101 via a base insulating film, and a light receiving sensor 350P-1 made of thin film polysilicon sandwiches the gate insulating film thereon. Formed with. . The light receiving sensor 350P-1 is configured by the four light receiving portions 350P-1I, the anode region 350P-1P connected to the wiring VSL adjacent thereto, and the cathode region 350P-1N connected to the wiring SENSE. It is as follows. Above the light receiving sensor 350P-1, a transparent electrode 612P-1 (first transparent electrode) made of indium oxide and tin thin film (ITO) is disposed via an interlayer insulating film and a planarizing insulating film, and the light receiving part 350P. It functions as an electric field shield against -1I. A nematic liquid crystal material 922 is sealed above the transparent electrode 612P-1, and the counter electrode 930 on the counter substrate 912 is disposed. Depending on the arrangement position of the light receiving sensor 350P-1, a sealing material 923 may be arranged instead of the nematic liquid crystal material 922. The light receiving opening 990-1 is formed by partially removing the black matrix 940 on the counter substrate 912. Although not shown, since the light receiving opening does not exist on the light shielding sensor 350D-1, the black matrix 940 is not removed.

  External light LA is irradiated from above the counter substrate 912, while light (backlight light LB) from the backlight unit 926 is irradiated from below the active matrix substrate 101.

  Although not implemented in this embodiment, an optical correction layer may be inserted in the light receiving opening 990-1 portion. For example, one or a plurality of color materials constituting a color filter corresponding to the pixels formed on the counter substrate 912 are formed so as to overlap with the light receiving opening 990-1, so that the spectral sensitivity characteristics and the light receiving sensor 350P-1 are formed. May be made more consistent. For example, if a color material corresponding to a green pixel is formed on the light receiving opening 990-1, the short wavelength and the long wavelength side are cut, so that the spectral characteristic of the light receiving sensor 350P-1 is shorter than the visibility spectral characteristic. Correction is possible even if the wavelength or wavelength is shifted. In addition, the light receiving opening 990-1 may be overlapped with the antireflection film, the interference layer, the polarizing layer, or the like according to the purpose. Although not shown in the drawing, the upper polarizing plate 924 may be overlapped with the light receiving opening 990-1 or may be removed. The light receiving opening 990-1 is less noticeable when it is overlapped, but if it is removed, the light sensitivity is improved.

  In this embodiment, the liquid crystal display device 910 performs common electrode inversion driving (common AC driving) for applying an inversion signal to the common potential wiring 335 in order to reduce power consumption. Therefore, the counter electrode 930 has an amplitude of V0 to 5V. An AC signal having a frequency of 14 KHz is applied. However, since the electromagnetic wave generated from the counter electrode 930 is shielded by the transparent electrode 612P-1, noise hardly occurs in the light receiving sensor 350P-1 when the counter electrode 930 is reversed. Similarly, the backlight light-shielding electrode 611P-1 functions as a shield against electromagnetic noise from below.

  FIG. 10 is a diagram showing a partial cross-sectional structure of the liquid crystal display device 910 corresponding to the line DD ′ line portion of FIG. The backlight light shielding electrode 611P-1 (first light shielding electrode) and the backlight light shielding electrode 611D-1 (second light shielding electrode) formed on the base insulating film are separated from each other by a light shielding electrode gap 611G, and are separately provided. Given potential. Further, the transparent electrode 612P-1 (first transparent electrode) and the transparent electrode 612D-1 (second transparent electrode) formed on the planarization insulating film are also separated from each other by the transparent electrode gap 612G, and have different potentials. Is given. The backlight shading electrode 611P-1 and the transparent electrode 612P-1 are connected to the intermediate electrode 613P-1 through contact holes formed in the gate insulating film, the interlayer insulating film, and the planarizing insulating film. Connected to the wiring PBT. The backlight shading electrode 611D-1 and the transparent electrode 612D-1 are connected to the intermediate electrode 613D-1 through contact holes formed in the gate insulating film, the interlayer insulating film, and the planarizing insulating film. Connected to the wiring DBT.

  Here, the light shielding electrode gap 611G and the transparent electrode gap 612G do not overlap with each other in the vertical direction of the active matrix substrate 101 and the counter substrate 912. With this configuration, since there is no area that is not shielded both vertically and horizontally, electromagnetic noise entering from the gap is less likely to spread to the left and right, and a reduction in shielding performance due to the gap can be reduced.

  A gap light shielding body 610 made of a molybdenum thin film (Mo) is formed so as to overlap the light shielding electrode gap 611G. As a result, the ratio of the backlight light entering from the light shielding electrode gap 611G is reflected multiple times at various insulating films, glass interfaces, etc., and becomes stray light to reach the light receiving sensor 350P-1 and the light shielding sensor 350D-1. Can be reduced.

  FIG. 11 shows an equivalent circuit of the light receiving sensors 350P-1 to 350P-6 and the light shielding sensors 350D-1 to 350D-6 configured as described above. Each of the light receiving sensors 350P-1 to 350P-6 and the light shielding sensors 350D-1 to 350D-6 has four PIN diodes connected in parallel. The light receiving sensors 350P-1 to 350P-6 are also connected in parallel to each other, and the light shielding sensors 350D-1 to 350D-6 are also connected to each other in parallel. Therefore, finally, FIG. 11 is equivalent to the circuit diagram of FIG. That is, the light shielding sensors 350D-1 to 350D-6 are PIN diodes having a channel width of 24000 μm and a channel length of 10 μm, their anodes connected to the wiring VSL, and their cathodes connected to the wiring SENSE. Further, the backlight light shielding electrodes 611D-1 to 611D-6 and the transparent electrodes 612D-1 to 612D-6, which overlap the light shielding sensors 350D-1 to 350D-6 in a plane, are connected to the wiring DBT. The light receiving sensors 350P-1 to 350P-6 are PIN diodes having a channel width of 24000 μm and a channel length of 10 μm, and their anodes are connected to the wiring SENSE and their cathodes are connected to the wiring VSH. Further, the backlight light shielding electrodes 611P-1 to 611P-6 and the transparent electrodes 612P-1 to 612P-6, which overlap the light receiving sensors 350P-1 to 350P-6 in a plane, are connected to the wiring PBT.

  FIG. 13 is a graph showing characteristics of PIN diodes constituting the light receiving sensors 350P-1 to 350P-6 and the light shielding sensors 350D-1 to 350D-6 when the liquid crystal display device 910 is irradiated with a constant illuminance LX. is there. The horizontal axis represents the bias potential Vd (= anode potential−cathode potential), and the vertical axis represents the amount of current Id flowing between the anode and the cathode. A graph (A) indicated by a solid line is a characteristic of the light receiving sensors 350P-1 to 350P-6, and a graph (B) indicated by a broken line is a characteristic of the light shielding sensors 350D-1 to 350D-6. As described above, in the forward bias region (Id> 0), both are almost the same, but in the reverse bias region (Id <0), the graph (B) of the light receiving sensors 350P-1 to 350P-6 has a larger absolute value of the current. Become. Since the outside light is not irradiated to the light shielding sensors 350D-1 to 350D-6, only the thermal current amount Ileak caused by the temperature flows, but the light receiving part 350P of the PIN diode constituting the light receiving sensors 350P-1 to 350P-6. When light is irradiated to -1I to 350P-6I, a carrier pair is generated and the photoelectric flow rate Iphoto flows. Therefore, in the light receiving sensors 350P-1 to 350P-6, the sum of the photoelectric flow rate and the thermal current amount, Iphoto + Ileak flows. . The amount of thermal current Ileak is dependent on Vd (= anode potential−cathode potential), and can be approximated as a straight line with a slope KA (KA> 0) in the region of −5.0 ≦ Vd ≦ −1.5. Here, KA is a function with respect to temperature, and increases exponentially as the temperature increases. In this Vd region (Vd = −5.0 ≦ Vd ≦ −1.5), the photoelectric flow rate Iphoto flowing through the light receiving sensors 350P-1 to 350P-6 has a substantially constant value, and is proportional to the external light illuminance LX (hereinafter referred to as “light-emitting sensor”). , Iphoto = LX × k). Therefore, the current flowing through the light receiving sensors 350P-1 to 350P-6 (graph (A)) and the current flowing through the light shielding sensors 350D-1 to 350D-6 (graph (B)) are both −5.0 ≦ Vd ≦ −1. The region 5 is a straight line with an inclination KA (KA> 0).

  Here, the bias is set so that the Vd of the light shielding sensors 350D-1 to 350D-6 and the light receiving sensors 350P-1 to 350P-6 are the same, that is, the potential VSENSE of the wiring SENSE is set to the potential VVSH of the wiring VSH and the wiring VSL. When set to (VVSH + VVSL) / 2, which is exactly the middle of the potential VVSL, the amount of thermal current (Ileak) flowing through the light receiving sensors 350P-1 to 350P-6 and the light shielding sensors 350D-1 to 350D-6 is exactly the same. At this time, the amount of current flowing through the wiring VSH (= the amount of current flowing through the light receiving sensors 350P-1 to 350P-6) is Iphoto + Ileak, and the amount of current flowing through the wiring VSL (= the current flowing through the light shielding sensors 350D-1 to 350D-6). The amount of current flowing through the wiring SENSE from Kirchhoff's first law is Iphoto = LX × k, which is proportional to the external light illuminance LX. In the embodiment, the light receiving sensor is connected to the high potential side and the light shielding sensor is connected to the low potential side.

  FIG. 14 is a circuit diagram of the detection circuit 360. The wiring VCHG, the wiring RST, the wiring VSL, the wiring VSH, and the wiring OUT are connected to the signal input terminal 320, and the wiring VSL, the wiring VSH, the wiring SENSE, the wiring PBT, and the wiring DBT wiring are the light receiving sensors 350P-1 to 350P-6 and The light shielding sensors 350D-1 to 350D-6 are connected. Here, the wiring VCHG, the wiring VSL, and the wiring VSH are connected to a DC power supply supplied from the external power supply circuit 784, the VCHG wiring is at a potential VVCHG (= 2.0V), the VSL wiring is at a potential VVSL (= 0.0V), and VSH. The wiring is supplied with a potential VVSH (= 5.0 V). Note that the potential VVSL of the VSL wiring is GND of the liquid crystal display device 910 here.

  The wiring SENSE is connected to each end of the first capacitor C1 and the third capacitor C3. Further, it is connected to the drain electrode of the initial charging transistor NC. The other end of the third capacitor C3 is connected to the wiring VSL. The other end of the first capacitor C1 is connected to the node A. The source electrode of the initial charging transistor NC is connected to the wiring VCHG and is supplied with a potential VVCH (= 2.0 V) power source. The gate electrode of the initial charging transistor NC is connected to the wiring RST. The node A is further connected to the gate electrode of the first N-type transistor N1, the gate electrode of the first P-type transistor P1, and the drain electrode of the reset transistor NR, and further connected to one end of the second capacitor C2. The other end of the second capacitor C2 is connected to the wiring RST. The drain electrode of the first N-type transistor N1, the drain electrode of the first P-type transistor P1, and the source electrode of the reset transistor NR are connected to the node B, and the node B is further connected to the gate electrode of the second N-type transistor N2. Connected to the gate electrode of the second P-type transistor P2. The drain electrode of the second N-type transistor N2 and the drain electrode of the second P-type transistor P2 are connected to the node C. The node C is further connected to the gate electrode of the third N-type transistor N3 and the third P-type transistor P3. To the gate electrode. The drain electrode of the third N-type transistor N3 and the drain electrode of the third P-type transistor P3 are connected to the node D. The node D is further connected to the gate electrode of the fourth N-type transistor N4 and the fourth P-type transistor P4. To the gate electrode. The drain electrode of the fourth N-type transistor N4 and the drain electrode of the fourth P-type transistor P4 are connected to the wiring OUT, and the wiring OUT is further connected to the drain electrode of the fifth N-type transistor N5. The gate electrode of the fifth N-type transistor N5 and the gate electrode of the fifth P-type transistor P5 are connected to the wiring RST, and the drain electrode of the fifth P-type transistor P5 is connected to the source electrode of the fourth P-type transistor P4. Connected. The source electrodes of the first to fifth N-type transistors N1 to N5 are connected to the wiring VSL and supplied with the potential VVSL (= 0V). The source electrodes of the first to third P-type transistors P1 to P3 and the fifth P-type transistor P5 are connected to the wiring VSH and supplied with the potential VVSH (= + 5 V).

  The detection circuit 360 also includes a self-correction voltage circuit 361 that automatically corrects the potential applied to the wiring PBT and the wiring DBT from the threshold voltage (Vth) of the transistor. The self-correcting voltage circuit 361 includes a sixth N-type transistor N11, a drain electrode and a gate electrode of the sixth P-type transistor P11 connected to the wiring PBT, and a seventh N-type transistor N21 and a seventh P-type transistor. The drain electrode and the gate electrode of the transistor P21 are respectively connected to the wiring DBT, and the source electrodes of the sixth N-type transistor N11 and the seventh N-type transistor N21 are connected to the wiring VSL to supply the potential VVSL (= 0V). The source electrodes of the sixth P-type transistor P11 and the seventh P-type transistor P21 are connected to the wiring VSH and supplied with the potential VVSH (= + 5 V).

  The entire surface of the detection circuit 360 is covered with a shield electrode 369 made of the same film as the indium oxide / tin thin film (ITO) constituting the pixel electrode 402-nm. The shield electrode 369 is connected to the GND potential of the liquid crystal display device 910 through the wiring VSL and functions as a shield against electromagnetic noise.

In this embodiment, the channel width of the first N-type transistor N1 is 10 μm, the channel width of the second N-type transistor N2 is 35 μm, and the channel width of the third N-type transistor N3 is 100 μm. The channel width of the fourth N-type transistor N4 is 150 μm, the channel width of the fifth N-type transistor N5 is 150 μm, the channel width of the sixth N-type transistor N11 is 4 μm, and the seventh N-type transistor N5 The channel width of the N-type transistor N21 is 200 μm, the channel width of the first P-type transistor P1 is 10 μm, the channel width of the second P-type transistor P2 is 35 μm, and the channel width of the third P-type transistor P3 The width is 100 μm, the channel width of the fourth P-type transistor P4 is 300 μm, and the fifth The channel width of the P-type transistor P5 is 300 μm, the channel width of the sixth P-type transistor P11 is 200 μm, the channel width of the seventh P-type transistor P21 is 4 μm, and the channel width of the reset transistor NR is The initial charging transistor NC has a channel width of 50 μm, the channel length of all N-type transistors is 8 μm, the channel length of all P-type transistors is 6 μm, and the mobility of all N-type transistors Is 80 cm ² / Vsec, the mobility of all P-type transistors is 60 cm ² / Vsec, the threshold voltage (Vth) of all N-type transistors is +1.0 V, and the threshold voltage of all P-type transistors (Vth) is −1.0 V, and the capacitance of the first capacitor C1 It is 1 pF, the capacitance of the second capacitor C2 is 100 fF, the capacitance of the third capacitor C3 is 100 pF.

  The wiring RST is a pulse wave having a potential amplitude of 0 to 5 V, and is held at a high potential (5 V) for a pulse length of 100 μsec every period of 510 msec, and is maintained at a low potential (0 V) for the remaining 509.9 msec. The When the RST wiring becomes High (5 V) every 510 msec, the initial charging transistor NC and the reset transistor NR are turned ON, the potential of the VCHG wiring (2.0 V) is charged to the wiring SENSE, and the nodes A and B are short-circuited. To do. Since the first N-type transistor N1 and the first P-type transistor P1 constitute an inverter circuit, IN / OUT of the inverter circuit is short-circuited. At this time, the potentials of the node A and the node B finally reach the potential VS represented by the following formula (for detailed calculation, refer to, for example, “Kang Digital Integrated Circuits” Third Edition P206 by Kang Leblebichi).

  Here, Wn: channel width of the first N-type transistor N1, Ln: channel length of the first N-type transistor N1, μn: mobility of the first N-type transistor N1, Vthn: first N-type transistor N1 threshold voltage, Wp: channel width of the first P-type transistor P1, Lp: channel length of the first P-type transistor P1, μp: mobility of the first P-type transistor P1, Vthp: first P Since this is the threshold voltage of the type transistor P1, in this embodiment, VS = 2.5 (V) is calculated. Note that while the wiring RST is High (5 V), the fifth N-type transistor N5 is ON and the fifth P-type transistor P5 is OFF, so the OUT wiring is 0 V.

  When the RST wiring becomes Low (0 V) after 100 μs, the reset transistor NR is turned OFF and the node A and the node B are electrically disconnected. At this time, the inverter circuit composed of the first N-type transistor N1 and the first P-type transistor P1 outputs a potential higher than VS to the node B if the potential of the node A is lower than VS, and the potential of the node A is If higher than VS, a potential lower than VS is output to node B. The second N-type transistor N2, the second P-type transistor P2, and the third N-type transistor N3 and the third P-type transistor P3 also constitute an inverter circuit, respectively. Similarly, the potential of the input stage is lower than VS. If the input stage potential is higher than VS, a potential lower than VS is output. At this time, the difference between the input stage potential VS and the output stage potential VS is larger than the difference between the output stage potential VS and the potential VVSH (= + 5 V) of the wiring VSH or the potential VVSL (= 0 V) of the wiring VSL. As a result, if the potential of the node A is lower than VS, the node D becomes approximately the potential VVSH (= + 5 V) of the VSH wiring, and if the potential of the node A is higher than VS, the node D becomes approximately the potential VVSL of the VSL wiring (= 0 V). . Since the fourth N-type transistor N4, the fifth N-type transistor N5, the fourth P-type transistor P4, and the fifth P-type transistor P5 constitute a NOR circuit, the potential of the RST wiring is Low (0 V). During the period, when the node D is High (+5 V), Low (0 V) is output to the OUT wiring, and when the node D is Low (0 V), High (+5 V) is output to the OUT wiring. That is, during the period when the potential of the RST wiring is Low (0V), if the potential of the node A is lower than VS, the output to the OUT wiring is Low (0V), and if the potential of the node A is higher than VS, the output to the OUT wiring is performed. The output becomes High (+ 5V).

  As described above, in the node A, the wiring RST becomes Low (0 V), the reset transistor NR is turned OFF, and the node A and the node B are electrically disconnected. At the same time, the wiring RST is coupled by the coupling of the second capacitor C2. At the same time, the potential drops. Here, the capacitance CC1 (= 1 pF) of the first capacitor C1 is the capacitance CC2 (= 100 fF) of the capacitor C2, and the gate-drain capacitance of the first N-type transistor N1, the first P-type transistor P1, and the reset transistor NR. (In this embodiment, all are less than 10 fF), and the product of the write impedance of the reset transistor NR and the capacitance of the first capacitor C1 (about 1 μsec in this embodiment) is the falling period of the potential of the wiring RST If it is sufficiently larger than (in this embodiment, 100 nsec), the potential of the node A (hereinafter referred to as VA (t)) when the wiring RST becomes Low (0 V) (hereinafter, this is time t = 0). Is represented by the following equation.

  In this embodiment, VA (t = 0) = 2.0V. At this time, the bias applied to the light receiving sensor 350P-1 is Vd = −3.0V, and the bias applied to the light shielding sensor 350D-1 is Vd = −2.0V. As is apparent from the description of FIG. 13, at this time, the difference between the thermal current amounts Ileak of the PIN diodes constituting the light receiving sensor 350P-1 and the light shielding sensor 350D-1 is expressed by KA × 1.0. Therefore, a current obtained by adding the current amount KA × 1.0 to the photoelectric flow rate Iphoto corresponding to the external light applied to the light receiving sensor 350P-1 flows through the wiring SENSE. Here, if KA << Iphoto, the amount of current flowing through the wiring SENSE can be approximated to only Iphoto, and the contribution of thermal current can be removed. In this embodiment, KA at 70 ° C., which is the upper limit of the guaranteed operating temperature, and Iphoto at an illuminance of 10 lux are equal. Therefore, heat leakage can be effectively removed within the guaranteed operating temperature range when the ambient light illuminance is 100 lux or more.

  Here, as described above, the relationship between the external light and Iphoto is proportional to the external light illuminance LX in which the external light illuminates the light receiving sensor 350P-1 under this bias condition, and Iphoto = LX · k (k is independent of Vd). Constant factor). Since the node A is in a floating state when the RST wiring becomes Low (0 V), the capacitance CC2 of the second capacitor C2, the gate-source capacitance of the first N-type transistor N1, and the first P-type transistor P1 are set. If ignored, the almost effective capacitance is only the capacitance CC3 of the third capacitor C3, and the potential VSENSE of the wiring SENSE changes as shown by the following equation.

  Here, for the purpose of explanation, the light receiving sensor 350P-1, the light shielding sensor 350D-1, and the additional capacitance in the lead wiring are ignored. What is necessary is just to add these additional capacity part to said CC3. In addition, when the additional capacitance in the light receiving sensor 350P-1 and the light shielding sensor 350D-1 and the routing wiring is sufficiently large, the third capacitor C3 may be omitted. Therefore, the lower limit of the value of CC3 is determined from the light receiving sensor 350P-1, the light shielding sensor 350D-1, and the additional capacity of the routing wiring.

  When VSENSE (t) changes, VA (t) changes by the same potential by capacitive coupling. Therefore, the potential VA of the node A is expressed by the following equation.

  Here, the time t0 when VA (t) = VS is expressed by the following equation.

  That is, at time t0, the OUT output is inverted from Low (0 V) to High (5 V), and the ambient light illuminance LX is easily stopped from this time t0.

  The detection circuit 360 malfunctions when the node A is in a floating state while the RST wiring is Low (0 V), and electromagnetic potential enters here and the potential of the node A changes. Therefore, prevention of electromagnetic noise is extremely important, and the shield electrode 369 is disposed for this purpose.

  The lateral type PIN diode or PN type diode as in this configuration has a problem that the photoelectric flow rate Iphoto changes with respect to the electric field in the vertical direction. More specifically, according to the present embodiment, the potentials of the transparent electrodes 612P-1 to 612P-6 and the backlight light shielding electrodes 611P-1 to 611P-6 connected to the wiring PBT (hereinafter referred to as VPBT) are the light receiving sensor 350P. -1 to 350P-6, the potential of the transparent electrodes 612D-1 to 612D-6 and the backlight light shielding electrodes 611P-1 to 611P-6 connected to the wiring DBT (hereinafter referred to as VDBT) is the light shielding sensor 350D-1. It affects the characteristics of ˜350D-6.

  FIG. 15 shows the characteristics of the diodes constituting the light receiving sensors 350P-1 to 350P-6 and the light shielding sensors 350D-1 to 350D-6. The horizontal axis indicates the potential difference between the light shielding electrode (and the transparent electrode) and the cathode electrode. Is a graph when the vertical axis represents the anode-cathode current under conditions of 23 ° C., bias Vd = −2.5 V, and external light of 1000 lux. In this embodiment, the horizontal axis corresponds to VPBT-VVSH for the light receiving sensors 350P-1 to 350P-6 and VDBT-VSENSE for the light shielding sensors 350D-1 to 350D-6.

  The solid line (A) is the result of the sample showing the median value, while the voltage value on the horizontal axis showing the peak current measured the number of samples, and the dotted line (B) is the voltage value on the horizontal axis showing the peak current. Among a plurality of samples measured, the result of the sample showing the maximum value is shown, and the broken line (C) shows the result of the sample showing the minimum value among the plurality of samples measured on the horizontal axis indicating the peak current. It can be seen that all have a proper voltage at the peak (the potential difference between the light-shielding electrode (and the transparent electrode) and the cathode electrode at which the photocurrent reaches a peak is hereinafter referred to as VMAX). This is because if the potential difference between the light shielding electrode (and the transparent electrode) and the cathode electrode is an appropriate voltage, the light receiving portions of the PIN junction diode (corresponding to the light receiving portions 350P-1I and 350D-1I in FIG. 8) are depleted. While light is excited throughout the entire area, the light receiving portion becomes N-type when the potential difference between the light shielding electrode (and the transparent electrode) and the cathode electrode becomes positive from the appropriate voltage. This is because it becomes P-type, the width of the depletion layer is narrowed, and the area where carriers are excited by light is limited. Therefore, in order to obtain a sufficient photocurrent, it is necessary to appropriately control VPBT and VDBT so that they become VMAX points. As can be seen from the graph (A) in FIG. 15, the potential of the light shielding layer and the transparent electrode is preferably about 1.4 V lower than the potential applied to the cathode electrode at the median value of manufacturing variation. However, as can be seen by comparing the graph (A), the graph (B), and the graph (C), the appropriate potential VMAX is actually slightly shifted due to manufacturing variations. This is a phenomenon that occurs because the defect level in the polysilicon thin film and the fixed charge at the interface between the base insulating film and the gate insulating film vary in the manufacturing process.

  FIG. 16 is a scatter diagram showing the correlation between thin film transistors and PIN diodes formed on the same substrate. The horizontal axis represents the average of the threshold voltage (VthN) of the N-type thin film transistor and the threshold voltage (VthP) of the P-type thin film transistor, and the vertical axis represents the appropriate potential VMAX that maximizes the photocurrent of the PIN diode. As can be seen from FIG. 16, the threshold value of the thin film transistor and the appropriate potential VMAX that maximizes the photocurrent of the PIN diode have a strong positive correlation. In this embodiment, as shown in FIG. 16A, when the light shielding electrode (and the transparent electrode) is about 1.4 V lower than the cathode electrode potential, the photocurrent shows the maximum value (VMAX), and the N-type thin film at this time The threshold voltage (VthN) of the transistor is +1.0 V, and the threshold voltage (VthP) of the P-type thin film transistor is −1.0 V, which is an average state during manufacturing variation. When the average was shifted by 1V, VMAX was also shifted by 1V, indicating a positive correlation of approximately y = x (dotted line).

  Based on the above, in this embodiment, the self-correction voltage circuit 361 that self-corrects the voltage based on the threshold value (Vth) of the thin film transistor and applies the voltage to the wiring PBT and the wiring DBT is used. In the present embodiment, average values during the manufacturing variation are VthN = + 1.0 and VthP = −1.0. At this time, the self-correction voltage circuit 361 has 3.6 V in the wiring PBT and wiring DBT. Is applied with 1.4V. In the light receiving sensors 350P-1 to 350P-6, the cathode is connected to the wiring VSH and is 5.0 V. Therefore, the potential difference between the backlight shading electrodes 611P-1 to 611P-6 and the transparent electrodes 612P-1 to 612P-6 and the cathode is It becomes -1.4V, and this is the optimum potential (VMAX) at which a photocurrent can be obtained. The transistor characteristics fluctuate due to manufacturing variations. For example, when VthN = + 1.5 and VthP = −0.5, 4.1 V is applied to the wiring PBT and 1.9 V is applied to the wiring DBT. Similarly, for example, when VthN = + 0.5 and VthP = −1.5, 3.1 V is applied to the wiring PBT and 0.9 V is applied to the wiring DBT. In any case, if the threshold value of the transistor fluctuates, the potential applied to the wiring PBT and the wiring DBT also fluctuates accordingly, so that the photocurrent is always obtained almost at the maximum.

FIG. 17 is a circuit diagram showing a second self-correction voltage circuit 361 ′ which is another configuration of the self-correction voltage circuit 361 of FIG. The gate electrode and drain electrode of the eighth N-type transistor N31 and the gate electrode and drain electrode of the eighth P-type transistor P31 are all connected to the node E. The node E is also connected to the gate electrode of the ninth P-type transistor P41 and the gate electrode of the ninth N-type transistor N41. The source electrode of the ninth P-type transistor P41 is connected to the wiring PBT, and the drain electrode is connected to the wiring VSL. The drain electrode of the tenth P-type transistor P42 is connected to the wiring PBT, the source electrode is connected to the wiring VSH, and the gate electrode is connected to the adjustment power supply wiring Voff1. The The source electrode of the ninth N-type transistor N41 is connected to the wiring DBT, and the drain electrode is connected to the wiring VSH. The drain electrode of the tenth N-type transistor N42 is connected to the wiring DBT, the source electrode is connected to the wiring VSL, and the gate electrode is connected to the adjustment power supply wiring Voff2. The adjustment power supply wiring Voff1 and the adjustment power supply wiring Voff2 are power supplied from the external power supply circuit 784 through the signal input terminal 320. The adjustment power supply wiring Voff1 is set to 3.9V, and the adjustment power supply wiring Voff2 is set to 1.1V. Here, the channel width of the eighth N-type transistor N31 is 10 μm, the channel width of the eighth P-type transistor P31 is 10 μm, the channel width of the ninth N-type transistor N41 is 100 μm, and the channel width of the tenth N-type transistor N42 is The channel width is 100 μm, the channel width of the ninth P-type transistor P41 is 100 μm, the channel width of the tenth P-type transistor P42 is 100 μm, the channel length of all N-type transistors is 8 μm, and all the P-type transistors The transistor channel length is 6 μm, the mobility of all N-type transistors is 80 cm ² / Vsec, and the mobility of all P-type transistors is 60 cm ² / Vsec. With the above configuration, the relationship between the voltage output to the wiring DBT from the second self-correction voltage circuit 361 ′, the voltage output to the wiring PBT, and the threshold voltage (Vth) of the thin film transistor is the self-correction voltage in FIG. This is exactly the same as the circuit 361.

  Compared with the configuration of the self-correction voltage circuit 361 in FIG. 14, the configuration of the second self-correction voltage circuit 361 ′ in FIG. 17 adjusts the potentials of the adjustment power supply wiring Voff1 and the adjustment power supply wiring Voff2 to adjust the active matrix substrate 101. An advantage is that the voltage output to the wiring DBT and the voltage output to the wiring PBT can be adjusted without change. On the other hand, since the number of elements, the number of wirings, and the number of terminals increase, it is a disadvantageous configuration from the viewpoint of circuit area, so which one to adopt can be arbitrarily determined based on the advantages and disadvantages of each Good. Further, the present invention is not limited to these circuit configurations, and any other known voltage circuit may be used instead of the self-correcting voltage circuit 361. Alternatively, the wiring DBT and the wiring PBT may be connected to the external power supply circuit 784 through the signal input terminal 320 and an appropriate potential may be supplied from the external power supply circuit 784. In this case, the product variation can be controlled by writing the set value of the potential output from the external power supply circuit 784 in the EEPROM or the like for each product.

  In this embodiment, the power supply wiring VSH and the power supply wiring VSL connected to the light receiving sensors 350P-1 to 350P-6 and the light shielding sensors 350D-1 to 350D-6 are also used as the driving power supply for the detection circuit 360. These may be separate power supply wirings. With this configuration, there is an advantage that the number of wirings and terminals increases, and the operation noise of the detection circuit 360 hardly affects the light receiving sensors 350P-1 to 350P-6 and the light shielding sensors 350D-1 to 350D-6. .

  In this embodiment, the central processing circuit 781 monitors the signal at the terminal OUT and first obtains the discrete value V10 from the inverted time t0. The discrete value V10 is sampled an arbitrary number of times to obtain the average value V10_. The reference table 785 is referred to from V10_, and an appropriate voltage setting value V20 of the backlight unit 926 corresponding to V10_ is obtained. The central processing circuit 781 sends the V20 value to the external power supply circuit 784 so that the luminance of the backlight unit 926 is changed. Thereby, the brightness at the time of all white display of the liquid crystal display device 910 changes. By suppressing excessive brightness for the user, visibility can be improved and an increase in power consumption can be suppressed.

  In the present embodiment, the relationship between the detected illuminance of external light and the backlight luminance is set as shown in FIG. The illuminance of the backlight is gradually increased up to a detected illuminance of 300 (lux), and the illuminance is increased by a relatively large inclination above 300 lux. The luminance becomes MAX at a detection illuminance of 2000 lux, and thereafter the same state is obtained. With this setting, the backlight is suppressed to the extent that it is not dazzling when the external light is 300 lux or less and the surroundings are extremely dark, and the user's pupil is open, and external light from 300 lux to 2000 lux is reflected on the liquid crystal panel. In the area, the brightness can be increased rapidly in accordance with the surrounding brightness so that the visibility cannot be lowered.

  On the other hand, when a transflective liquid crystal is used instead of a transmissive liquid crystal as in this embodiment, it may be as shown in FIG. The same is true for external light illuminance up to 5000 lux, but beyond that, the reflective part alone provides sufficient visibility, so the backlight is completely turned off and power consumption can be saved. As a result, the battery drive time of the electronic device to be mounted is greatly increased.

  Of course, this control curve is an example, and any curve may be set according to the application, or the curve may be provided with hysteresis in order to suppress flicker. Also, instead of adjusting the brightness for each measurement, the brightness may be adjusted by measuring a plurality of times and taking an average or median value.

  Even when the light receiving sensors 350P-1 to 350P-6 and the light shielding sensors 350D-1 to 350D-6 are configured by phototransistors, basically, as described in the present embodiment, the light receiving sensors 350P-1 to 350P-6 and the light shielding sensors. It is preferable to individually optimize the voltages applied to the electrodes that overlap the sensors 350D-1 to 350D-6 in a planar manner. This is because the spread of the depletion layer in the phototransistor is also affected by the overlapping electrodes.

[Second Embodiment]
FIG. 20 is a perspective configuration view (partially sectional view) of a liquid crystal display device 910B according to the second embodiment, which replaces the liquid crystal display device 910 described in FIG. 1 in the first embodiment. In the following, differences from the liquid crystal display device 910 in FIG. 1 in the first embodiment will be described.

  In the present embodiment, ten light receiving openings 991-1 to 991-10 are arranged instead of the light receiving openings 990-1 to 990-6. Here, the light receiving openings 991-1 to 991-6 are installed at the opposite peripheral edge far from the projecting portion 102, and the light receiving openings 991-7 to 991-10 are installed at the peripheral edge perpendicular to the projecting portion 102. The Further, an active matrix substrate 101B is used instead of the active matrix substrate 101, and the counter substrate 912 is replaced with the counter substrate 912B. Here, the counter substrate 912B has the same configuration as the counter substrate 912 except that the thickness thereof is 0.25 mm. Since the other points are not different from those of the first embodiment shown in FIG.

  FIG. 21 is a block diagram of the active matrix substrate 101B according to the second embodiment, which replaces the active matrix substrate 101 described with reference to FIG. 2 in the first embodiment. The difference from the active matrix substrate 101 in FIG. 2 will be mainly described. In this embodiment, the wiring DBT and the wiring PBT do not exist, the light receiving sensors 350P-1 to 350P-6 are the light receiving sensors 351P-1 to 351P-10, and the light shielding sensors 350D-1 to 350D-6 are the light shielding sensor 351D-1. Replaced with ~ 351D-10, respectively. Here, the light receiving sensors 351P-1 to 351P-6 and the light shielding sensors 351D-1 to 351D-10 are disposed on the same side as the peripheral edge where the light receiving openings 991-1 to 991-6 are provided, and the light receiving sensor 351P-1 ˜351P-6 are arranged to overlap with the light receiving openings 991-1 to 991-6 in a plane. The light receiving sensors 351P-7 to 351P-10 and the light shielding sensors 351D-7 to 351D-10 are disposed on the same side as the peripheral edge where the light receiving openings 991-1 to 991-6 are provided, and the light receiving sensors 351P-1 to 351P-1 are disposed. 351P-6 is configured to overlap with the light receiving openings 991-1 to 991-6 in a planar manner. The light receiving sensors 351P-1 to 351P-10 are connected to the wiring SENSE and the wiring VSH, and the light shielding sensors 351D-1 to 351D-10 are connected to the wiring VSL, the wiring SENSE, and the wiring VCHG. The detection circuit 360 is replaced with a detection circuit 362. In other respects, there is no difference from the first embodiment, and the description is omitted by giving the same symbols. In this embodiment, the potential applied to the wiring VSH is 5.0 V, the potential applied to the wiring VSL is 0.0 V, and the potential applied to the wiring VCHG is 2.0 V, which is applied to the wiring RST. The signal is a pulse wave having a potential amplitude of 0 to 5 V, and is held at a high potential (5 V) for a pulse length of 100 μsec every period of 510 msec, and is held at a low potential (0 V) for the remaining 509.9 msec. . These are no different from those of the first embodiment.

  FIG. 22 is a circuit diagram of the detection circuit 362. Differences from the detection circuit 360 shown in FIG. 14 of the first embodiment will be described. In this embodiment, the wiring DBT and the wiring PBT do not exist, and the self-correction voltage circuit 361 does not exist. Instead, the wiring VCHG is output to the light shielding sensors 351D-1 to 351D-10 as they are. Further, the shield electrode 369 does not exist. As a result, compared with the first embodiment, the additional capacitance of the circuit is reduced, and the operation can be performed more quickly and accurately. On the other hand, it is weak against electromagnetic noise, and the presence / absence of the shield electrode 369 is detected. What is necessary is just to decide by the magnitude of the electromagnetic noise by the arrangement position etc. of a circuit. Connection and capacitance of the first capacitor C1, the second capacitor C2, the third capacitor C3, the initial charging transistor NC, the initial charging transistor NC, the first to fifth N-type transistors N1 to N5, the first to fifth Since the configuration, size, mobility, and threshold voltage (Vth) of the P-type transistors P1 to P5 are all the same as in the first embodiment, description thereof is omitted.

  FIG. 23 is an enlarged plan view of the vicinity of the light receiving sensor 351P-1 (first optical sensor) and the light shielding sensor 351D-1 (first optical sensor). This will be described in comparison with FIG. 8 of the first embodiment. The light receiving sensor 351P-1 is planarly overlapped with the light receiving opening 990-1, and is irradiated with external light. The light receiving sensor 351P-1 includes a light receiving portion 351P-1I, an anode region 351P-1P, and a cathode region 351P-1N. The light shielding sensor 351D-1 does not overlap the light receiving opening 990-1 in a planar manner, and includes a light receiving portion 351D-1I, an anode region 351D-1P, and a cathode region 351D-1N. The light receiving portion 351P-1I, the anode region 351P-1P, the cathode region 351P-1N, the light receiving portion 351D-1I, the anode region 351D-1P, and the cathode region 351D-1N are respectively the light receiving portion 350P-1I and the anode in the first embodiment. Since the configuration, size, connection destination, and the like of the region 350P-1P, the cathode region 350P-1N, the light receiving unit 350D-1I, the anode region 350D-1P, and the cathode region 350D-1N are the same, description thereof is omitted. In this embodiment, the backlight light shielding electrode 614P-1 overlapping with the light receiving sensor 351P-1 is connected to the wiring VSH through the intermediate electrode 616P-1, and the backlight light shielding electrode 614D-1 overlapping with the light shielding sensor 351D-1 is connected to the intermediate electrode 616D-. 1 to the wiring VCHG. Further, the transparent electrode 615 that overlaps the light receiving sensor 351P-1 also overlaps the light shielding sensor 351D-1, and is not separated from each other. Therefore, the transparent electrode gap 612G in the first embodiment does not exist. The transparent electrode 614 is provided with a common potential wiring 335 disposed on the side close to the display area 310 of the light receiving sensor 351P-1 and the light shielding sensor 351D-1, and is given a common potential. In this embodiment, a DC potential is applied to the common potential wiring 335, and the potential is 4.0V. The light receiving sensors 351P-2 to 351P-10 are the same as the light receiving sensor 351P-1, and the light shielding sensors 351D-2 to 351D-10 are exactly the same as the light shielding sensor 351D-1, except for the position, pitch, and direction of arrangement. Is omitted.

  Since the electronic apparatus using the liquid crystal display device 910B is as described in FIG. 4 of the first embodiment, the details are omitted.

  The size of the light receiving openings 991-1 to 991-6 is a direction parallel to the boundary edge of the peripheral edge of the display area 310 where the light receiving openings 990-1 to 990-6 are arranged (hereinafter referred to as the X direction). ) Is the same 10 mm as in the first embodiment. On the other hand, the size in the X direction of the light receiving openings 991-7 to 991-10 is as short as 7 mm in consideration of the fact that the temperature gradient is strong on the side close to the backlight unit 926. Accordingly, the arrangement pitch of the light receiving openings 991-1 to 991-6 is 20 mm, and the arrangement pitch of the light receiving openings 991-7 to 991-10 is 14 mm.

  In the direction orthogonal to the boundary side of the display area 310 (hereinafter referred to as Y direction), the thickness of the counter substrate 912B is 0.25 mm, so stray light becomes strong at 0.3 mm, which is the same as in the first embodiment. Since the measurement accuracy deteriorates, the Y direction is set to a size of 0.2 mm in all the light receiving openings 991-1 to 991-10.

  As shown in this example, it is more preferable to arrange the light receiving sensors on multiple sides, because the influence of fingers and small shadows can be removed. However, it is necessary to pay attention to the temperature gradient from the positional relationship with the light source. . In the present embodiment, the light receiving sensors are arranged on two sides, but naturally, they may be arranged on three or four sides. In this embodiment, the sensor pitch and the size of the opening are changed depending on the side. However, if the temperature gradient is significantly different in the same side, the sensor pitch and the size of the opening may be changed in the same side. Absent.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiments but by the scope of claims for patent, and further includes all modifications within the meaning and scope equivalent to the scope of claims for patent.

[Industrial applicability]
The present invention is not limited to the embodiments, and is used for liquid crystal display devices such as a vertical alignment mode (VA mode) instead of the TN mode, an IPS mode using a lateral electric field, and an FFS mode using a fringe electric field. It doesn't matter. Moreover, not only a total transmission type but also a total reflection type and a reflection / transmission combined type may be used. Further, instead of the liquid crystal display device, it may be used for an organic EL display, a field emission type display, or a semiconductor device other than the liquid crystal display device.

  In addition to controlling the display brightness according to the external light as shown in this embodiment, the brightness and chromaticity of the display device are measured and fed back, and used for a display device free from unevenness and aging. It doesn't matter.

The perspective view of the liquid crystal display device 910 which concerns on the Example of this invention. 1 is a configuration diagram of an active matrix substrate 101 according to a first embodiment of the present invention. 1 is a pixel circuit diagram of an active matrix substrate 101 according to an embodiment of the present invention. 1 is a block diagram illustrating an embodiment of an electronic device of the present invention. The top view of the pixel part of the active matrix substrate 101 which concerns on the Example of this invention. FIG. 5A is a cross-sectional view along AA ′. FIG. 5B is a cross-sectional view taken along the line BB ′. The top view of the light reception sensor 350P-1 and the light-shielding sensor 350D-1 which concern on 1st Example of this invention. FIG. 9 is a cross-sectional view taken along the line CC ′. FIG. 8D is a cross-sectional view taken along the line DD ′. FIG. 3 is an equivalent circuit diagram of the light receiving sensors 350P-1 to 350P-6 and the light shielding sensors 350D-1 to 350D-6 according to the first embodiment of the present invention. FIG. 4 is a simplified equivalent circuit diagram of the light receiving sensors 350P-1 to 350P-6 and the light shielding sensors 350D-1 to 350D-6 according to the first embodiment of the present invention. The graph which showed the characteristic of the PIN diode which comprises the light reception sensor 350P-1 to 350P-6 and the light shielding sensor 350D-1 to 350D-6 which concern on 1st Example of this invention. The circuit diagram of the detection circuit 360 concerning the 1st example of the present invention. The graph of the electric current of the PIN diode which concerns on 1st Example of this invention, and the electric potential between light-shielding electrodes-cathode electrodes. The scatter diagram which shows the characteristic correlation of the thin-film transistor and PIN diode which concern on the Example of this invention. The circuit diagram of 2nd self-correction voltage circuit 361 'which concerns on another structural example of the 1st Example of this invention. FIG. 3 is a setting diagram of detected illuminance of external light and backlight luminance according to an embodiment of the present invention. FIG. 5 is a setting diagram of detection illuminance of external light and backlight luminance for a transflective liquid crystal display device. The perspective view of liquid crystal display device 910B which concerns on the 2nd Example of this invention. The block diagram of the active-matrix board | substrate 101B which concerns on the 2nd Example of this invention. The circuit diagram of the detection circuit 362 which concerns on the 2nd Example of this invention. The top view of the light reception sensor 351P-1 and the light-shielding sensor 351D-1 which concern on the 2nd Example of this invention.

Explanation of symbols

  101, 101B... Active matrix substrate (an example of the “first substrate” or “semiconductor device” of the present invention), 102 ... an overhang, 201-1 to 201-480 ... scanning lines, 202-1 to 202-1920. Data line 301... Scan line driving circuit 302... Data line driving circuit 320 320 Signal input terminal 330-1 to 330-2 Opposing conductive part 335 Common potential wiring 350 P-1 350 P-6, 351 P -1 to 351P-6... Light receiving sensor (an example of the “first optical sensor” in the present invention), 350D-1 to 350D-6, 351D-1 to 351D-6. Example of “optical sensor”), 360, 362... Detection circuit (example of “photodetection unit” of the present invention), 361, 361 ′... Self-correction voltage circuit, 611P-1 to 611P-6, 611D-1 611D-6: Backlight shielding electrode, 612P-1 to 612P-6, 612D-1 to 612D-6 ... Transparent electrode, 781 ... Central processing circuit, 784 ... External power supply circuit, 910 ... Liquid crystal display device, 911 ... Liquid crystal panel (An example of “panel” of the present invention), 912... Counter substrate (an example of “second substrate” of the present invention), 922... Nematic phase liquid crystal material, 923... Sealing material, 926. Light plate, 940... Black matrix, 990-1 to 990-6, 991-1 to 991-10... Light receiving opening, LA .. External light, LB.

Claims (9)

A panel formed with a display region in which an electro-optical material is sandwiched between first and second substrates, a light detection unit for detecting the illuminance of ambient light of the panel, and irradiating light on the display region of the panel An electro-optical device having a light source
The second substrate is provided with a counter electrode to which a periodically inverted signal is applied,
The light detection unit is provided on the periphery of the display area of the first substrate,
A first light sensor irradiated with external light;
A second optical sensor for blocking external light irradiation,
The first photosensor and the second photosensor each include a light-shielding electrode that blocks light irradiation from the light source and a transparent electrode disposed on the side facing the second substrate ,
The first optical sensor and the second optical sensor are opposed to the counter electrode, and a plurality of the first optical sensor and the second optical sensor are arranged at a peripheral portion of the display area. 2. The electro-optical device according to claim 1, wherein the light source is arranged on a side where the first photosensor and the second photosensor are not arranged at a peripheral portion of the display area. The first light sensor;
The electro-optical device according to claim 1, wherein the second optical sensors are alternately arranged with each other. The distance between the first photosensor and the second photosensor arranged adjacent to the first photosensor is substantially equal to the boundary side of the display area. The electro-optical device according to one item. A plurality of opening sizes provided in the first or second substrate for irradiating the first light sensor with ambient light of the panel,
In a direction parallel to the boundary edge of the display area peripheral edge where the opening is arranged, a range of 0.5 mm or more and 20 mm or less is orthogonal to the boundary edge of the display area peripheral edge where the opening is arranged. 5. The electro-optical device according to claim 1, wherein the electro-optical device is formed to have a thickness of 0.05 mm or more and not more than a thickness of the counter substrate. The plurality of openings are a first opening disposed on a side facing the arrangement side on which the light source is arranged, and a second arranged on a side substantially orthogonal to the arrangement side at the peripheral edge of the front region. With an opening of
The electro-optical device according to claim 5, wherein an opening area of the first opening is larger than the second opening area. 7. The electricity according to claim 1, wherein each of the first photosensor and the second photosensor is a PIN junction diode or a PN junction diode using thin film polysilicon. Optical device.   A display device comprising the electro-optical device according to claim 1.   An electronic apparatus using the display device according to claim 8.

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