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JP4498842B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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Publication number
JP4498842B2
JP4498842B2 JP2004198362A JP2004198362A JP4498842B2 JP 4498842 B2 JP4498842 B2 JP 4498842B2 JP 2004198362 A JP2004198362 A JP 2004198362A JP 2004198362 A JP2004198362 A JP 2004198362A JP 4498842 B2 JP4498842 B2 JP 4498842B2
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resin
underfill resin
mounting substrate
protective film
polishing
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JP2006019651A (en
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茂次 村松
正宏 経塚
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector

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  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

本発明は、半導体装置及びその製造方法に係り、特に基板上の樹脂保護膜と半導体部品との間にアンダーフィル樹脂を注入して半導体部品を基板上に実装する半導体装置及びその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device in which an underfill resin is injected between a resin protective film on a substrate and a semiconductor component and the semiconductor component is mounted on the substrate, and a manufacturing method thereof.

配線基板に表面実装タイプの半導体部品を実装する構成とされた半導体装置では、半導体部品と配線基板との間にアンダーフィル樹脂を充填することにより半導体部品と配線基板との熱膨張差により半導体部品と配線基板との間を電気的に接続するバンプが破壊されることを防止して接続信頼性を向上させている(例えば、特許文献1参照)。   In a semiconductor device configured to mount a surface mount type semiconductor component on a wiring board, the semiconductor component is filled with an underfill resin between the semiconductor component and the wiring board due to a difference in thermal expansion between the semiconductor component and the wiring board. The connection reliability is improved by preventing the bumps electrically connecting the wiring board and the wiring board from being broken (see, for example, Patent Document 1).

ここで、図1乃至図3を参照して従来の製造方法の各工程について説明する。   Here, each process of the conventional manufacturing method is demonstrated with reference to FIG. 1 thru | or FIG.

図1(A)〜(C)に示されるように、BGA(Ball grid array)タイプの半導体装置10では、正方形状の半導体チップ14の下面に多数のバンプ(端子)12を配置しており、半導体チップ14を実装基板16の上面に載置すると共に、バンプ12を実装基板16上の電極パッド18にはんだ接合する。実装基板16の表面には、ソルダ−レジスト20が樹脂保護膜として形成されている。   As shown in FIGS. 1A to 1C, in a BGA (Ball grid array) type semiconductor device 10, a large number of bumps (terminals) 12 are arranged on the lower surface of a square-shaped semiconductor chip 14, The semiconductor chip 14 is placed on the upper surface of the mounting substrate 16, and the bumps 12 are soldered to the electrode pads 18 on the mounting substrate 16. On the surface of the mounting substrate 16, a solder resist 20 is formed as a resin protective film.

半導体チップ14とソルダ−レジスト20との間に形成された隙間にアンダーフィル樹脂22を充填し、ベーキングする。これにより、バンプ12の周囲は、アンダーフィル樹脂22によって補強され、半導体チップ14と実装基板16との熱膨張差によるバンプ破壊が防止される。
特開2000−150557号公報
The gap formed between the semiconductor chip 14 and the solder resist 20 is filled with the underfill resin 22 and baked. Thereby, the periphery of the bump 12 is reinforced by the underfill resin 22, and bump destruction due to a difference in thermal expansion between the semiconductor chip 14 and the mounting substrate 16 is prevented.
JP 2000-150557 A

ところが、図2(A)(B)に示されるように、LSIチップからなる半導体チップ14の下面に配置された端子数が増加するに連れて各端子間の離間距離も小さくなり、バンプ12も小さく形成され、バンプ12間が狭ピッチ化される。この際、バンプ12高さもバンプ径の減少により低くなる。また、実装基板16を下方からみると、バンプ12が密集している端子領域αと、バンプ12が形成されていない非端子領域βとが存在する。   However, as shown in FIGS. 2A and 2B, as the number of terminals arranged on the lower surface of the semiconductor chip 14 made of an LSI chip increases, the distance between the terminals also decreases, and the bumps 12 are also formed. It is formed small and the pitch between the bumps 12 is narrowed. At this time, the height of the bump 12 is also lowered due to the decrease in the bump diameter. Further, when the mounting substrate 16 is viewed from below, there are a terminal region α where the bumps 12 are dense and a non-terminal region β where the bumps 12 are not formed.

図2(C)に示されるように、バンプ12間の狭ピッチ化された半導体チップ14を実装基板16の上面に載置し、バンプ12を実装基板16上の電極パッド18にはんだ接合すると、バンプ12高さも低くなることから半導体チップ14とソルダ−レジスト20との隙間Sが狭くなる。   As shown in FIG. 2C, when the semiconductor chip 14 with a narrow pitch between the bumps 12 is placed on the upper surface of the mounting substrate 16 and the bumps 12 are soldered to the electrode pads 18 on the mounting substrate 16, Since the height of the bump 12 is also lowered, the gap S between the semiconductor chip 14 and the solder resist 20 is narrowed.

また、図2(D)にC部を拡大して示されるように、実装基板16の表面には、配線パターン24が形成されているため、ソルダ−レジスト20の表面は、配線パターン24の形状に応じた凹凸形状となっている。そのため、図2(E)にD部を拡大して示されるように、配線パターン24の上部では、半導体チップ14とソルダ−レジスト20との隙間Sが狭くなっており、アンダーフィル樹脂22に含まれたフィラー25,26のうち粒子の小さいフィラー25が上記隙間Sを通過できるが、粒子の大きいフィラー26が上記隙間Sを通りにくくなり、アンダーフィル樹脂22を充填する際の抵抗となって充填速度が遅くなる、または充填できなくなるという問題があった。   Further, as shown in FIG. 2 (D) by enlarging part C, since the wiring pattern 24 is formed on the surface of the mounting substrate 16, the surface of the solder-resist 20 has the shape of the wiring pattern 24. Concave and convex shape according to. Therefore, as shown in FIG. 2E with the D portion enlarged, the gap S between the semiconductor chip 14 and the solder resist 20 is narrowed above the wiring pattern 24 and is included in the underfill resin 22. Among the fillers 25 and 26, the filler 25 with small particles can pass through the gap S, but the filler 26 with large particles becomes difficult to pass through the gap S and becomes a resistance when filling the underfill resin 22. There has been a problem that the speed is slow or filling is impossible.

また、半導体チップ14とソルダ−レジスト20との隙間にアンダーフィル樹脂22を充填する際、アンダーフィル樹脂22は、比較的粘性が小さく液状であるので、実装基板16の一側から注入されて他側に移動するようにして全体に充填される。   Further, when the underfill resin 22 is filled in the gap between the semiconductor chip 14 and the solder resist 20, the underfill resin 22 is in a liquid state with a relatively low viscosity, so that it is injected from one side of the mounting substrate 16 and others. The whole is filled so as to move to the side.

ここで、図3(A)〜(E)を参照して従来のアンダーフィル樹脂22(図3中、梨地模様で示す)の流れ状態について説明する。また、図3(A)〜(E)中、半導体チップ14は、透視されており、一点鎖線で示す。   Here, the flow state of the conventional underfill resin 22 (shown as a satin pattern in FIG. 3) will be described with reference to FIGS. 3A to 3E, the semiconductor chip 14 is seen through and is indicated by a one-dot chain line.

図3(A)〜(E)に示されるように、アンダーフィル樹脂22の流れ速度分布は、実装基板16を上方からみると、バンプ12が密集している端子領域αでの毛管現象によりアンダーフィル樹脂22の流れ速度が速くなる。一方、バンプ12が形成されていない非端子領域βでは、相対的にアンダーフィル樹脂22の流れ速度が若干遅くなる傾向にある。   As shown in FIGS. 3A to 3E, when the mounting substrate 16 is viewed from above, the flow velocity distribution of the underfill resin 22 is caused by the capillary phenomenon in the terminal region α where the bumps 12 are dense. The flow speed of the fill resin 22 is increased. On the other hand, in the non-terminal region β where the bumps 12 are not formed, the flow rate of the underfill resin 22 tends to be relatively slow.

そのため、アンダーフィル樹脂22を実装基板16の一側から他側に充填される際、均一な速度で移動せず、基板中心部分の非端子領域βでアンダーフィル樹脂22の流れ速度が遅れることにより、バンプ12が密集している中心部分を囲む端子領域αにおける流れ速度が相対的に速くなり、実装基板16の他側に到着したアンダーフィル樹脂22の流れの一部が中心部分に向かって周り込むように移動する(図3(E)中、矢印で示す)ことになる。その結果、非端子領域βで遅れた流れと端子領域αから周り込む流れとの間に空洞によるボイド28が形成されてしまうという問題が生じる。   Therefore, when the underfill resin 22 is filled from one side of the mounting substrate 16 to the other side, the underfill resin 22 does not move at a uniform speed, and the flow rate of the underfill resin 22 is delayed in the non-terminal region β in the central portion of the substrate. The flow velocity in the terminal region α surrounding the central portion where the bumps 12 are densely increased, and a part of the flow of the underfill resin 22 arriving at the other side of the mounting substrate 16 is directed toward the central portion. (Indicated by an arrow in FIG. 3E). As a result, there arises a problem that voids 28 are formed by the cavities between the flow delayed in the non-terminal region β and the flow flowing in from the terminal region α.

また、半導体チップ14と実装基板16との隙間の大きさ、アンダーフィル樹脂22の特性によっては端子領域αにおいて、フィラー粒子の影響からアンダーフィル樹脂22の流れが遅くなり、前述とは異なる位置にボイドが発生するという問題が生じる。   Further, depending on the size of the gap between the semiconductor chip 14 and the mounting substrate 16 and the characteristics of the underfill resin 22, the flow of the underfill resin 22 is slowed down in the terminal region α due to the influence of the filler particles in a position different from the above. There arises a problem that voids are generated.

そこで、本発明は上記課題を解決した半導体装置及びその製造方法を提供することを目的とする。   In view of the above, an object of the present invention is to provide a semiconductor device and a method for manufacturing the same that solve the above problems.

本発明は上記課題を解決するため、以下のような特徴を有する。   In order to solve the above problems, the present invention has the following features.

請求項1記載の発明は、実装基板の表面に樹脂保護膜を形成する第1工程と、前記樹脂保護膜の表面を研磨して前記実装基板の配線パターンに応じて形成される前記樹脂保護膜の表面凹凸部分を除去すると共に、前記樹脂保護膜の表面に直線状に延在する複数の研磨痕を一定方向に形成する第2工程と、前記実装基板上の電極パッドに半導体部品の下面に配置されたバンプを接続する第3工程と、前記樹脂保護膜と前記半導体部品との間にアンダーフィル樹脂を充填して前記半導体部品を前記実装基板上に実装する第4工程と、を有することを特徴とする。 The invention according to claim 1 is the first step of forming a resin protective film on the surface of the mounting substrate, and the resin protective film formed according to the wiring pattern of the mounting substrate by polishing the surface of the resin protective film. A second step of forming a plurality of polishing traces extending linearly on the surface of the resin protective film in a certain direction, and an electrode pad on the mounting substrate on the lower surface of the semiconductor component A third step of connecting the arranged bumps, and a fourth step of mounting the semiconductor component on the mounting substrate by filling an underfill resin between the resin protective film and the semiconductor component. It is characterized by.

請求項記載の発明は、前記第4工程において、前記アンダーフィル樹脂の注入方向を前記樹脂保護膜の表面に形成された複数の研磨痕の延在方向に一致させることを特徴とする。 The invention according to claim 2 is characterized in that, in the fourth step, the injection direction of the underfill resin is made to coincide with the extending direction of a plurality of polishing marks formed on the surface of the resin protective film.

請求項記載の発明は、表面に樹脂保護膜が形成された基板の電極パッドに半導体部品の端子を接続した状態で前記樹脂保護膜と前記半導体部品との間にアンダーフィル樹脂を充填して前記半導体部品を前記基板上に実装する半導体装置において、研磨部材により前記樹脂保護膜の表面を研磨して前記樹脂保護膜の表面に直線状に延在する複数の研磨痕を一定方向に形成し、前記アンダーフィル樹脂を充填したことを特徴とする。
請求項4記載の発明は、前記アンダーフィル樹脂を前記複数の研磨痕の延在方向に沿って充填することを特徴とする。
According to a third aspect of the present invention, an underfill resin is filled between the resin protective film and the semiconductor component in a state where the terminals of the semiconductor component are connected to the electrode pads of the substrate having the resin protective film formed on the surface. In a semiconductor device in which the semiconductor component is mounted on the substrate, the surface of the resin protective film is polished by a polishing member to form a plurality of polishing marks extending in a straight direction on the surface of the resin protective film. , characterized in that it was filled with pre-Symbol underfill resin.
The invention according to claim 4 is characterized in that the underfill resin is filled along the extending direction of the plurality of polishing marks.

本発明によれば、樹脂保護膜の表面を研磨して実装基板の配線パターンに応じて形成される樹脂保護膜の表面凹凸部分を除去すると共に、樹脂保護膜の表面に直線状に延在する複数の研磨痕を一定方向に形成した後、樹脂保護膜と半導体部品との間にアンダーフィル樹脂を充填して半導体部品を実装基板上に実装するため、樹脂保護膜の表面形状が平坦化されてフィラーを含むアンダーフィル樹脂の流れをほぼ均一な速度で実装基板の一側から他側に移動させて充填することが可能になる。 According to the present invention, the surface of the resin protective film is polished to remove the uneven surface portion of the resin protective film formed according to the wiring pattern of the mounting substrate, and extends linearly to the surface of the resin protective film. After forming multiple polishing marks in a certain direction, filling the underfill resin between the resin protective film and the semiconductor component to mount the semiconductor component on the mounting substrate, the surface shape of the resin protective film is flattened Thus, the flow of the underfill resin containing the filler can be filled by moving from one side of the mounting substrate to the other side at a substantially uniform speed.

また、アンダーフィル樹脂を樹脂保護膜の表面に直線状に延在する複数の研磨痕に沿って充填することにより、実装基板の一側から他側へアンダーフィル樹脂を充填する過程で他側に到着したアンダーフィル樹脂の流れが周り込むことが抑制され、ボイドの発生を防止することが可能になる。
Further, the underfill resin by filling along a plurality of polishing streaks extending linearly in the surface of the resin protective layer, the other side in the process of filling an underfill resin from one side of the mounting substrate to the other side It is possible to prevent the arrival of the flow of the underfill resin that has arrived, and to prevent generation of voids.

以下、図面と共に本発明の一実施例について説明する。   Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

図4(A)〜(F)は本発明になる半導体装置の製造方法の一実施例を示す工程図である。尚、図4(A)〜(F)において、前述した図1〜図3に示す同一部分には同一符号を付す。   4A to 4F are process diagrams showing one embodiment of a method for manufacturing a semiconductor device according to the present invention. 4A to 4F, the same parts as those shown in FIGS. 1 to 3 are denoted by the same reference numerals.

図4(A)に示されるように、工程1では、実装基板16上に電極パッド18及び配線パターンを形成した後、電極パッド18を除く実装基板16上にソルダレジスト20をスクリーン印刷により形成する。あるいは、感光ソルダレジストを実装基板16上に形成して露光、現像によりレジストパターンを形成しても良い。   As shown in FIG. 4A, in step 1, after the electrode pad 18 and the wiring pattern are formed on the mounting substrate 16, the solder resist 20 is formed on the mounting substrate 16 excluding the electrode pad 18 by screen printing. . Alternatively, a photosensitive solder resist may be formed on the mounting substrate 16 and a resist pattern may be formed by exposure and development.

ソルダレジスト20は、その表面が後述する工程で研磨されるため、通常よりも若干厚く(例えば、配線パターン上の厚さ20μm〜30μm程度)形成される。   Since the surface of the solder resist 20 is polished in a process described later, the solder resist 20 is formed slightly thicker than usual (for example, about 20 μm to 30 μm in thickness on the wiring pattern).

図4(B)にA部を拡大して示されるように、実装基板16上には、配線パターン24が形成されており、配線パターン24上にもソルダレジスト20が被覆されるため、ソルダレジスト20の表面20aは、配線パターン24上が凸部20bになり、配線パターン24が存在しない領域が凹部20cになる。   As shown in FIG. 4B in which the A portion is enlarged, the wiring pattern 24 is formed on the mounting substrate 16 and the solder resist 20 is also coated on the wiring pattern 24. Therefore, the solder resist The surface 20a of 20 has a convex portion 20b on the wiring pattern 24, and a concave portion 20c in a region where the wiring pattern 24 does not exist.

図4(C)に示されるように、工程2では、図5に示すバフ研磨機30を用いてソルダレジスト(樹脂保護膜)20の表面20aを研磨して表面凹凸部分を除去する。そのため、ソルダレジスト(樹脂保護膜)20の表面20aは、見かけ上平坦化されており、粒子の大きさが異なるフィラー25,26を有するアンダーフィル樹脂22が流れやすくなり、アンダーフィル樹脂22の充填速度が表面凹凸部分によって変化することが防止される。   As shown in FIG. 4C, in step 2, the surface unevenness portion is removed by polishing the surface 20a of the solder resist (resin protective film) 20 using the buffing machine 30 shown in FIG. Therefore, the surface 20a of the solder resist (resin protective film) 20 is apparently flattened, and the underfill resin 22 having fillers 25 and 26 having different particle sizes can easily flow. It is possible to prevent the speed from changing due to the uneven surface portion.

ここで、バフ研磨機30について図5を参照して説明する。
図5に示されるように、バフ研磨機30は、実装基板16の上面に形成されたソルダレジスト20を研磨するロール状研磨部材としての上面用バフロール32と、実装基板16の下面を研磨する下面用バフロール34とを有しており、実装基板16の上下面を同時に研磨するように構成されている。また、上面用バフロール32の下方には、実装基板16を上方に押圧する押圧用ローラ36が設けられ、下面用バフロール34の上方には、実装基板16を下方に押圧する押圧用ローラ38が設けられている。これにより、実装基板16の上下面は、モータ(図示せず)により回転駆動される上面用バフロール32及び下面用バフロール34に対して所定の荷重で押圧されることになり、荷重の大きさに応じた厚さが研磨される。
Here, the buffing machine 30 will be described with reference to FIG.
As shown in FIG. 5, the buffing machine 30 includes an upper surface baffle 32 as a roll-shaped polishing member for polishing the solder resist 20 formed on the upper surface of the mounting substrate 16, and a lower surface for polishing the lower surface of the mounting substrate 16. And the upper and lower surfaces of the mounting substrate 16 are polished at the same time. A pressing roller 36 that presses the mounting substrate 16 upward is provided below the upper surface baffle 32, and a pressing roller 38 that presses the mounting substrate 16 downward is provided above the lower surface baffle 34. It has been. Accordingly, the upper and lower surfaces of the mounting substrate 16 are pressed with a predetermined load against the upper surface baffle 32 and the lower surface baffle 34 that are rotationally driven by a motor (not shown). The corresponding thickness is polished.

また、バフ研磨機30は、実装基板16を上面用バフロール32及び下面用バフロール34に搬送するための複数の搬送ローラ40,42が設けられている。搬送ローラ40,42は、モータ(図示せず)により実装基板16を矢印で示す搬送方向に所定の搬送速度で搬送する。   Further, the buffing machine 30 is provided with a plurality of transport rollers 40 and 42 for transporting the mounting substrate 16 to the upper surface baffle 32 and the lower surface baffle 34. The transport rollers 40 and 42 transport the mounting substrate 16 at a predetermined transport speed in a transport direction indicated by an arrow by a motor (not shown).

尚、バフ研磨機30では、一対の上面用バフロール32及び下面用バフロール34を設けた構成であるが、上面用バフロール32及び下面用バフロール34の配置数は2対あるいは3対とすることも可能である。従って、上面用バフロール32及び下面用バフロール34の数は、研磨されるソルダレジスト20の研磨量に応じて選択され、且つ上面用バフロール32及び下面用バフロール34の種類(砥粒の大きさ)を選択することによって実装基板16の表面20aに残される研磨痕の深さを任意の深さに設定することが可能になる。   The buffing machine 30 has a configuration in which a pair of upper surface baffles 32 and lower surface buffols 34 are provided, but the number of upper surface baffles 32 and lower surface baffles 34 may be two or three. It is. Accordingly, the numbers of the upper surface buffules 32 and the lower surface buffols 34 are selected according to the polishing amount of the solder resist 20 to be polished, and the types (sizes of abrasive grains) of the upper surface buffol 32 and the lower surface buffol 34 are selected. By selecting, the depth of the polishing mark left on the surface 20a of the mounting substrate 16 can be set to an arbitrary depth.

図4(D)にB部を拡大して示されるように、上記バフ研磨機30によるソルダレジスト20の研磨工程を行うことにより、ソルダレジスト20は表面20aの凹凸を除去されて平面に加工されると共に、ソルダレジスト20の表面20aには微細な研磨痕44が搬送方向に沿って直線状に形成される。   As shown in FIG. 4D in which the portion B is enlarged, the solder resist 20 is processed into a flat surface by removing the irregularities on the surface 20a by performing the polishing process of the solder resist 20 by the buffing machine 30. At the same time, fine polishing marks 44 are linearly formed on the surface 20a of the solder resist 20 along the conveying direction.

すなわち、実装基板16は、回転する上面用バフロール32を通過することにより研磨されたソルダレジスト20の表面20aに、例えば、深さ1〜10μmの微細な複数の溝からなる直線状の研磨痕44が形成される。この微細な研磨痕44は、アンダーフィル樹脂22を充填する際にアンダーフィル樹脂22の流れ方向を規制する規制手段として機能するものである。   That is, the mounting substrate 16 is formed on the surface 20a of the solder resist 20 polished by passing through the rotating upper surface baffle 32, for example, a linear polishing mark 44 made of a plurality of fine grooves having a depth of 1 to 10 μm. Is formed. This fine polishing mark 44 functions as a regulating means for regulating the flow direction of the underfill resin 22 when the underfill resin 22 is filled.

また、アンダーフィル樹脂22は、微細な溝からなる研磨痕44にも充填されることでソルダレジスト20の表面20aに対してより強固に接着されることになる。   Further, the underfill resin 22 is also bonded to the surface 20a of the solder resist 20 more firmly by filling the polishing marks 44 formed of fine grooves.

図4(E)に示されるように、工程3では、実装基板16上の電極パッド18に半導体チップ14の下面に配置されたバンプ12をはんだ接続する。   As shown in FIG. 4E, in step 3, the bumps 12 arranged on the lower surface of the semiconductor chip 14 are soldered to the electrode pads 18 on the mounting substrate 16.

図4(F)に拡大して示されるように、工程4では、研磨工程により平坦化されたソルダレジスト20の表面20aと半導体チップ14の下面との隙間Sにアンダーフィル樹脂22を充填してベーキングして半導体チップ14を実装基板16上に実装する。アンダーフィル樹脂22は、粒子の大きさが異なるフィラー25,26を有するが、上記研磨工程によりソルダレジスト20の表面20aが平坦化されているため、ソルダレジスト20の表面20aと半導体チップ14の下面との隙間Sが一定寸法に保たれており、粒子の大きいフィラー26も自由に移動することが可能になり、アンダーフィル樹脂22の流れがスムーズに行える。   As shown in an enlarged view in FIG. 4F, in step 4, an underfill resin 22 is filled in the gap S between the surface 20a of the solder resist 20 planarized by the polishing step and the lower surface of the semiconductor chip 14. The semiconductor chip 14 is mounted on the mounting substrate 16 by baking. The underfill resin 22 has fillers 25 and 26 having different particle sizes. Since the surface 20a of the solder resist 20 is flattened by the polishing process, the surface 20a of the solder resist 20 and the lower surface of the semiconductor chip 14 are provided. The filler S 26 having a large particle size can be moved freely, and the flow of the underfill resin 22 can be performed smoothly.

これにより、実装基板16の側方からアンダーフィル樹脂22を上記隙間Sに注入した場合、アンダーフィル樹脂22がソルダレジスト20の表面20aの凹凸によって流れ方向が変化したり、粒子の大きいフィラー26の移動が規制されずに済み、ソルダレジスト20と半導体チップ14との間の全体にアンダーフィル樹脂22を充填することが可能になる。   Accordingly, when the underfill resin 22 is injected into the gap S from the side of the mounting substrate 16, the flow direction of the underfill resin 22 changes due to the unevenness of the surface 20 a of the solder resist 20, or the filler 26 having large particles 26 The movement is not restricted and the entire area between the solder resist 20 and the semiconductor chip 14 can be filled with the underfill resin 22.

ここで、図6(A)〜(F)を参照してアンダーフィル樹脂22を充填する際のアンダーフィル樹脂22(図6中、梨地模様で示す)の流れ状態について説明する。また、図6中、半導体チップ14は、透視されており、一点鎖線で示す。   Here, the flow state of the underfill resin 22 (shown as a satin pattern in FIG. 6) when filling the underfill resin 22 will be described with reference to FIGS. In FIG. 6, the semiconductor chip 14 is seen through and is indicated by a one-dot chain line.

図6(A)中破線で示されるように、実装基板16上のソルダレジスト20の表面20aには、一定方向(X方向)に延在するように微細な溝からなる研磨痕44が形成されている。そして、実装基板16の右側方からソルダレジスト20の表面20aと半導体チップ14の下面との隙間Sにアンダーフィル樹脂22を注入する。尚、アンダーフィル樹脂22は、樹脂充填ノズル(図示せず)の先端吐出口よりソルダレジスト20上に吐出され、半導体チップ14の右側に沿うように充填される。   As shown by a broken line in FIG. 6A, a polishing mark 44 made of a fine groove is formed on the surface 20a of the solder resist 20 on the mounting substrate 16 so as to extend in a certain direction (X direction). ing. Then, the underfill resin 22 is injected into the gap S between the surface 20 a of the solder resist 20 and the lower surface of the semiconductor chip 14 from the right side of the mounting substrate 16. The underfill resin 22 is discharged onto the solder resist 20 from the tip discharge port of a resin filling nozzle (not shown) and filled along the right side of the semiconductor chip 14.

このように、ソルダレジスト20上に盛り付けられたアンダーフィル樹脂22は、図6(B)に示されるように、ソルダレジスト20の表面20aと半導体チップ14の下面との隙間Sに流入する。また、アンダーフィル樹脂22は、粘性の低い液状であり、且つソルダレジスト20の表面20aが研磨工程により凹凸の無い平面に形成されているので、隙間Sを移動しやすく、特に図6(B)中矢印で示すように多数のバンプ12が密集された端子領域αでの流速(充填速度)が毛管現象により非端子領域βよりも速くなる。   Thus, the underfill resin 22 placed on the solder resist 20 flows into the gap S between the surface 20a of the solder resist 20 and the lower surface of the semiconductor chip 14, as shown in FIG. 6B. In addition, the underfill resin 22 is a low-viscosity liquid, and the surface 20a of the solder resist 20 is formed on a flat surface having no irregularities by the polishing process, so that the gap S can be easily moved, particularly in FIG. As indicated by the middle arrow, the flow velocity (filling speed) in the terminal region α where many bumps 12 are densely packed becomes faster than that in the non-terminal region β due to capillary action.

図6(C)に示されるように、アンダーフィル樹脂22は、多数のバンプ12が密集された端子領域αを積極的に進行するのに対し、非端子領域βでの移動が遅れる。   As shown in FIG. 6C, the underfill resin 22 positively progresses in the terminal region α where a large number of bumps 12 are densely packed, but the movement in the non-terminal region β is delayed.

図6(D)に示されるように、アンダーフィル樹脂22が非端子領域βに充填される頃には、端子領域αをX方向に進行したアンダーフィル樹脂22が半導体チップ14の他側に到達している。しかしながら、アンダーフィル樹脂22は、ソルダレジスト20の表面20aに形成された微小な研磨痕44の延在方向に移動するため、半導体チップ14の他側に到達したアンダーフィル樹脂22は、研磨痕44によって中心側に向うY方向への流れが抑制される。   As shown in FIG. 6D, when the underfill resin 22 is filled in the non-terminal region β, the underfill resin 22 that has traveled in the X direction in the terminal region α reaches the other side of the semiconductor chip 14. is doing. However, since the underfill resin 22 moves in the extending direction of the minute polishing marks 44 formed on the surface 20 a of the solder resist 20, the underfill resin 22 that has reached the other side of the semiconductor chip 14 has the polishing marks 44. This suppresses the flow in the Y direction toward the center.

図6(E)に示されるように、端子領域αをX方向に進行したアンダーフィル樹脂22が研磨痕44によってY方向への流れが抑制されている間に、非端子領域βをX方向に進行したアンダーフィル樹脂22が半導体チップ14の他側付近まで進行する。   As shown in FIG. 6E, while the underfill resin 22 that has traveled in the X direction through the terminal region α is restrained from flowing in the Y direction by the polishing marks 44, the non-terminal region β is moved in the X direction. The advanced underfill resin 22 advances to the vicinity of the other side of the semiconductor chip 14.

図6(F)に示されるように、最終的には、非端子領域βをX方向に進行したアンダーフィル樹脂22が半導体チップ14の他側に到達した時点で、ソルダレジスト20と半導体チップ14との隙間全体にアンダーフィル樹脂22の充填が完了する。   As shown in FIG. 6F, finally, when the underfill resin 22 having advanced in the non-terminal region β in the X direction reaches the other side of the semiconductor chip 14, the solder resist 20 and the semiconductor chip 14. The filling of the underfill resin 22 is completed in the entire gap.

このように、ソルダレジスト20の表面20aに形成された微小な研磨痕44がアンダーフィル樹脂22の流れ方向を一方向(X方向)に規制することにより非端子領域βをX方向に進行したアンダーフィル樹脂22の流速が遅くなっても端子領域αを進行したアンダーフィル樹脂22がY方向に周り込むことが抑制され、ボイドの発生が防止されるため、アンダーフィル樹脂充填工程の信頼性を高めることが可能になる。   As described above, the minute polishing marks 44 formed on the surface 20a of the solder resist 20 regulate the flow direction of the underfill resin 22 in one direction (X direction), thereby causing the under-terminal region β to advance in the X direction. Even if the flow rate of the fill resin 22 is slow, the underfill resin 22 that has advanced through the terminal region α is prevented from entering in the Y direction, and the generation of voids is prevented. Therefore, the reliability of the underfill resin filling process is improved. It becomes possible.

アンダーフィルを用いたBGAパッケージの半導体装置10の実装工程を説明するための縦断面図である。It is a longitudinal cross-sectional view for demonstrating the mounting process of the semiconductor device 10 of the BGA package using an underfill. バンプピッチが小さくなった半導体チップの実装工程を説明するための縦断面図である。It is a longitudinal cross-sectional view for demonstrating the mounting process of the semiconductor chip with which bump pitch became small. 従来のアンダーフィル樹脂の流れを説明するための平面図である。It is a top view for demonstrating the flow of the conventional underfill resin. 本発明になる半導体装置の製造方法の一実施例を示す工程図である。It is process drawing which shows one Example of the manufacturing method of the semiconductor device which becomes this invention. バフ研磨機30の構成例を示す斜視図である。2 is a perspective view showing a configuration example of a buffing machine 30. FIG. アンダーフィル樹脂22を充填する際のアンダーフィル樹脂22の流れ状態を説明するための平面図である。5 is a plan view for explaining a flow state of the underfill resin 22 when filling the underfill resin 22. FIG.

符号の説明Explanation of symbols

12 バンプ
14 半導体チップ
16 実装基板
18 電極パッド
20 ソルダ−レジスト
22 アンダーフィル樹脂
24 配線パターン
25,26 フィラー
30 バフ研磨機
32 上面用バフロール
34 下面用バフロール
36,38 押圧用ローラ
40,42 搬送ローラ
44 研磨痕
12 Bump 14 Semiconductor chip 16 Mounting substrate 18 Electrode pad 20 Solder resist 22 Underfill resin 24 Wiring pattern 25, 26 Filler 30 Buffing machine 32 Upper surface baffle 34 Lower surface baffle 36, 38 Pressing roller 40, 42 Conveying roller 44 Polishing mark

Claims (4)

実装基板の表面に樹脂保護膜を形成する第1工程と、
前記樹脂保護膜の表面を研磨して前記実装基板の配線パターンに応じて形成される前記樹脂保護膜の表面凹凸部分を除去すると共に、前記樹脂保護膜の表面に直線状に延在する複数の研磨痕を一定方向に形成する第2工程と、
前記実装基板上の電極パッドに半導体部品の下面に配置されたバンプを接続する第3工程と、
前記樹脂保護膜と前記半導体部品との間にアンダーフィル樹脂を充填して前記半導体部品を前記実装基板上に実装する第4工程と、
を有することを特徴とする半導体装置の製造方法。
A first step of forming a resin protective film on the surface of the mounting substrate;
The surface of the resin protective film is polished to remove surface irregularities of the resin protective film formed according to the wiring pattern of the mounting substrate, and a plurality of linearly extending surfaces of the resin protective film are formed. A second step of forming polishing marks in a certain direction ;
A third step of connecting a bump disposed on the lower surface of the semiconductor component to the electrode pad on the mounting substrate;
A fourth step of mounting an underfill resin between the resin protective film and the semiconductor component and mounting the semiconductor component on the mounting substrate;
A method for manufacturing a semiconductor device, comprising:
前記第4工程において、前記アンダーフィル樹脂の注入方向を前記樹脂保護膜の表面に形成された複数の研磨痕の延在方向に一致させることを特徴とする請求項記載の半導体装置の製造方法。 In the fourth step, the method of manufacturing a semiconductor device according to claim 1, characterized in that to match the injection direction of the underfill resin in the extending direction of the plurality of polishing marks formed on the surface of the resin protective layer . 表面に樹脂保護膜が形成された基板の電極パッドに半導体部品の端子を接続した状態で前記樹脂保護膜と前記半導体部品との間にアンダーフィル樹脂を充填して前記半導体部品を前記基板上に実装する半導体装置において、
研磨部材により前記樹脂保護膜の表面を研磨して前記樹脂保護膜の表面に直線状に延在する複数の研磨痕を一定方向に形成し、前記アンダーフィル樹脂を充填したことを特徴とする半導体装置。
An underfill resin is filled between the resin protective film and the semiconductor component with the terminal of the semiconductor component connected to the electrode pad of the substrate having the resin protective film formed on the surface, and the semiconductor component is placed on the substrate. In the semiconductor device to be mounted,
A plurality of polishing streaks extending linearly in the surface of the resin protective layer of the resin protective layer by polishing the surface of the polishing member is formed in a predetermined direction, characterized by being filled with pre-Symbol underfill resin Semiconductor device.
前記アンダーフィル樹脂を前記複数の研磨痕の延在方向に沿って充填することを特徴とする請求項3記載の半導体装置 4. The semiconductor device according to claim 3, wherein the underfill resin is filled along an extending direction of the plurality of polishing marks .
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JP2000298352A (en) * 1999-04-14 2000-10-24 Jsr Corp Material for electronic parts and method for using same
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