JP4497952B2 - Multilayer wiring board - Google Patents
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- JP4497952B2 JP4497952B2 JP2004047012A JP2004047012A JP4497952B2 JP 4497952 B2 JP4497952 B2 JP 4497952B2 JP 2004047012 A JP2004047012 A JP 2004047012A JP 2004047012 A JP2004047012 A JP 2004047012A JP 4497952 B2 JP4497952 B2 JP 4497952B2
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 61
- 239000011889 copper foil Substances 0.000 claims description 50
- 239000010410 layer Substances 0.000 claims description 46
- 239000002245 particle Substances 0.000 claims description 18
- 239000012212 insulator Substances 0.000 claims description 13
- JEIPFZHSYJVQDO-UHFFFAOYSA-N iron(III) oxide Inorganic materials O=[Fe]O[Fe]=O JEIPFZHSYJVQDO-UHFFFAOYSA-N 0.000 claims description 12
- 229910052802 copper Inorganic materials 0.000 claims description 11
- 239000010949 copper Substances 0.000 claims description 11
- 239000011164 primary particle Substances 0.000 claims description 11
- 239000006087 Silane Coupling Agent Substances 0.000 claims description 10
- 239000011163 secondary particle Substances 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 10
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims description 8
- 229910052725 zinc Inorganic materials 0.000 claims description 8
- 239000011701 zinc Substances 0.000 claims description 8
- 239000011229 interlayer Substances 0.000 claims description 5
- 230000002265 prevention Effects 0.000 claims description 5
- 229920003002 synthetic resin Polymers 0.000 claims description 5
- 239000000057 synthetic resin Substances 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 claims 1
- 230000005540 biological transmission Effects 0.000 description 8
- 230000000052 comparative effect Effects 0.000 description 8
- 230000003449 preventive effect Effects 0.000 description 7
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 5
- 229910052709 silver Inorganic materials 0.000 description 5
- 239000004332 silver Substances 0.000 description 5
- 239000011888 foil Substances 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 238000005868 electrolysis reaction Methods 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 238000007788 roughening Methods 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910020175 SiOH Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 238000004220 aggregation Methods 0.000 description 1
- 230000002776 aggregation Effects 0.000 description 1
- 125000003545 alkoxy group Chemical group 0.000 description 1
- 125000003277 amino group Chemical group 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 229910000365 copper sulfate Inorganic materials 0.000 description 1
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000008151 electrolyte solution Substances 0.000 description 1
- 125000003700 epoxy group Chemical group 0.000 description 1
- 125000001301 ethoxy group Chemical group [H]C([H])([H])C([H])([H])O* 0.000 description 1
- 239000012765 fibrous filler Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 230000007062 hydrolysis Effects 0.000 description 1
- 238000006460 hydrolysis reaction Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 125000000956 methoxy group Chemical group [H]C([H])([H])O* 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 125000005372 silanol group Chemical group 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 125000000391 vinyl group Chemical group [H]C([*])=C([H])[H] 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Manufacturing Of Printed Wiring (AREA)
Description
本発明は、積層配線基板に関するものである。 The present invention relates to a laminated wiring board.
従来、表面に第１の配線パターンを備えるコア基板上に、プリプレグ等の合成樹脂系シートからなる絶縁体層を介して銅箔等の導電体層を積層し、該導電体層をエッチングすることにより第２の配線パターンを形成した積層配線基板が知られている。前記積層基板では、第１、第２の両配線パターンは層間接続部材により電気的に接続されている。 Conventionally, a conductor layer such as a copper foil is laminated on a core substrate having a first wiring pattern on the surface via an insulator layer made of a synthetic resin-based sheet such as a prepreg, and the conductor layer is etched. A multilayer wiring board having a second wiring pattern formed thereon is known. In the laminated substrate, both the first and second wiring patterns are electrically connected by an interlayer connection member.
また、前記積層基板において、前記導電体層の所定の位置にバンプを形成しておき、該バンプを前記プリプレグ等の絶縁体層に貫通させた後、該バンプの先端を前記コア基板表面の第１の配線パターンに圧着させて、前記層間接続部材としたものが知られている（例えば特許文献１参照）。 In the laminated substrate, a bump is formed at a predetermined position of the conductor layer, and the bump is passed through an insulating layer such as the prepreg. There is known one that is crimped to one wiring pattern to form the interlayer connection member (see, for example, Patent Document 1).
前記バンプは、例えば、前記銅箔上に所定の位置に貫通孔を備えるメタルマスクを積層し、該メタルマスクを介して銀ペースト、銅ペースト等の導電性ペーストをスクリーン印刷して該貫通孔に導電性ペーストを充填した後、該導電性ペーストを乾燥させることにより形成される。前記バンプは、例えば、直径０．２０ｍｍ、高さ１８０μｍの円錐形状に形成される。 The bump is formed, for example, by laminating a metal mask having a through hole at a predetermined position on the copper foil, and screen printing a conductive paste such as a silver paste or a copper paste through the metal mask. After the conductive paste is filled, the conductive paste is dried. The bump is formed in a conical shape having a diameter of 0.20 mm and a height of 180 μm, for example.
また、前記銅箔は、例えば、厚さ１８μｍの電解銅箔の表面に、平均粒子径２μｍの銅の一次粒子が付着せしめられて平均粒子径２０μｍの二次粒子を形成している粗化面と、該粗化面を被覆する平均０．３０ｍｇ／ｄｍ2の亜鉛からなる防錆層とを備えるものが用いられる。前記粗化面を備える銅箔は、例えば、前記銅箔の一方の表面を硫酸と硫酸銅とからなる電解液中で交流電解処理した後、陰極電解処理または陰極パルス電解処理して前記銅の一次粒子を付着させることにより形成することができる（例えば特許文献２参照）。 The copper foil is a roughened surface in which, for example, primary particles of copper having an average particle diameter of 2 μm are adhered to the surface of an electrolytic copper foil having a thickness of 18 μm to form secondary particles having an average particle diameter of 20 μm. And a rust preventive layer made of zinc having an average of 0.30 mg / dm 2 covering the roughened surface. The copper foil provided with the roughened surface is, for example, subjected to AC electrolytic treatment on one surface of the copper foil in an electrolytic solution composed of sulfuric acid and copper sulfate, and then subjected to cathodic electrolysis treatment or cathodic pulse electrolysis treatment. It can be formed by adhering primary particles (see, for example, Patent Document 2).
前記銅箔上に前述のようにして形成されるバンプは、該銅箔との間の電気抵抗が平均１０ｍΩとなっている。 The bumps formed on the copper foil as described above have an average electrical resistance of 10 mΩ with the copper foil.
一方、積層配線基板では、電子部品の進歩と共に配線密度を高くする必要があり、配線の幅、間隔、ランド径を小さくすることが行われている。これに伴って、前記バンプもまた直径を小さくすることが望まれる。 On the other hand, in the multilayer wiring board, it is necessary to increase the wiring density with the progress of electronic components, and the width, interval, and land diameter of the wiring are reduced. Accordingly, it is desirable that the bumps also have a small diameter.
しかしながら、前記銅箔上に前記バンプを形成するときに、バンプ径を２００μｍ未満、例えば１５０μｍとすると、該バンプと銅箔との間の電気抵抗が大きくなって発熱し、伝送損失、伝送ノイズが大きくなるという不都合がある。
本発明は、かかる不都合を解消して、伝送損失、伝送ノイズを低減することができる積層配線基板を提供することを目的とする。 An object of the present invention is to provide a multilayer wiring board capable of eliminating such disadvantages and reducing transmission loss and transmission noise.
かかる目的を達成するために、本発明は、基板上に形成された第１の配線パターンと、第１の配線パターン上に積層された合成樹脂系シートからなる絶縁体層と、該絶縁体層上に積層された銅箔をエッチングすることにより形成された第２の配線パターンと、該銅箔上の所定の位置に形成されたバンプを該絶縁体層に貫通せしめて両配線パターンを接続する層間接続部材とを備える積層配線基板において、該銅箔は表面に平均粒子径０．５〜１．５μｍの銅の一次粒子が付着せしめられて平均粒子径５〜１５μｍの二次粒子を形成している粗化面と、該粗化面を被覆する０．０１〜０．２０ｍｇ／ｄｍ2の亜鉛からなる防錆層とを備え、該バンプは０．２０ｍｍ未満の直径を備えることを特徴とする。 In order to achieve such an object, the present invention provides a first wiring pattern formed on a substrate, an insulating layer made of a synthetic resin-based sheet laminated on the first wiring pattern, and the insulating layer. The second wiring pattern formed by etching the copper foil laminated thereon and the bump formed at a predetermined position on the copper foil are penetrated through the insulator layer to connect the two wiring patterns. In a multilayer wiring board provided with an interlayer connection member, the copper foil has secondary particles having an average particle diameter of 5 to 15 μm formed by adhering primary particles of copper having an average particle diameter of 0.5 to 1.5 μm to the surface. And a rust preventive layer made of 0.01 to 0.20 mg / dm 2 of zinc covering the roughened surface, and the bump has a diameter of less than 0.20 mm. To do.
本発明の積層配線基板では、前記銅箔に付着せしめる銅の一次粒子の平均粒子径を０．５〜１．５μｍの範囲としたので、該一次粒子が凝集して形成される二次粒子の平均粒子径が５〜１５μｍの範囲となり、従来の銅箔の粗化面よりも細かい二次粒子を備える粗化面が得られる。従って、前記粗化面とバンプの底面との接触面積が大きくなる。 In the multilayer wiring board of the present invention, since the average particle diameter of the primary particles of copper adhered to the copper foil is in the range of 0.5 to 1.5 μm, the secondary particles formed by aggregation of the primary particles An average particle diameter becomes the range of 5-15 micrometers, and the roughening surface provided with a secondary particle finer than the roughening surface of the conventional copper foil is obtained. Accordingly, the contact area between the roughened surface and the bottom surface of the bump is increased.
また、本発明の積層配線基板では、前記粗化面上に形成される防錆層の亜鉛の量が０．０１〜０．２０ｍｇ／ｄｍ2の範囲とされ、従来の銅箔の防錆層よりも低減されている。従って、銅よりも電気抵抗値の大きい亜鉛による電気抵抗の増加が抑制される。 In the multilayer wiring board of the present invention, the amount of zinc in the rust prevention layer formed on the roughened surface is in the range of 0.01 to 0.20 mg / dm 2 , and the conventional rust prevention layer of copper foil is used. Has been reduced. Therefore, an increase in electrical resistance due to zinc having a larger electrical resistance value than copper is suppressed.
この結果、前記銅箔上に、０．２０ｍｍ未満、好ましくは０．１５ｍｍ以下の直径を備えるバンプを形成した場合にも、該銅箔の粗化面と該バンプの底面との接触面積が大きくなり、しかも該粗化面上に形成されている防錆層の電気抵抗が小さくなる。従って、本発明の積層配線基板によれば、該銅箔と該バンプとの電気抵抗を低減して発熱を低減することができ、伝送損失、伝送ノイズを低減することができる。 As a result, even when a bump having a diameter of less than 0.20 mm, preferably 0.15 mm or less is formed on the copper foil, the contact area between the roughened surface of the copper foil and the bottom surface of the bump is large. In addition, the electric resistance of the rust preventive layer formed on the roughened surface is reduced. Therefore, according to the multilayer wiring board of the present invention, the heat resistance can be reduced by reducing the electrical resistance between the copper foil and the bump, and transmission loss and transmission noise can be reduced.
前記銅の一次粒子の平均粒子径は、０．５μｍ未満とすることは技術的に難しく、１．５μｍを超えると二次粒子の径が大きくなりやすい。また、前記二次粒子の平均粒子径は、５μｍ未満とすることは技術的に難しく、１５μｍを超えると、前記粗化面と前記バンプの底面との接触面積を大きくして電気抵抗を低減する効果が得られない。 It is technically difficult to make the average particle diameter of the copper primary particles less than 0.5 μm, and when it exceeds 1.5 μm, the diameter of the secondary particles tends to be large. Further, it is technically difficult to make the average particle diameter of the secondary particles less than 5 μm, and when it exceeds 15 μm, the contact area between the roughened surface and the bottom surface of the bump is increased to reduce the electric resistance. The effect is not obtained.
また、前記銅箔は、前記防錆層上に島状に形成されたシランカップリング剤層を備えることが好ましい。前記銅箔は、前記シランカップリング層を備えることにより、前記絶縁体層を形成する合成樹脂系シートに対する密着性を向上させることができる。尚、前記シランカップリング剤層自体は絶縁体であるが、前記防錆層上に島状に形成されているので、前記銅箔と前記バンプとの電気抵抗を増大させることはない。 Moreover, it is preferable that the said copper foil is equipped with the silane coupling agent layer formed in the island shape on the said antirust layer. The said copper foil can improve the adhesiveness with respect to the synthetic resin type | system | group sheet | seat which forms the said insulator layer by providing the said silane coupling layer. In addition, although the said silane coupling agent layer itself is an insulator, since it is formed in island shape on the said rust preventive layer, the electrical resistance of the said copper foil and the said bump is not increased.
次に、添付の図面を参照しながら本発明の実施の形態についてさらに詳しく説明する。図１は本実施形態の積層配線基板の構成を示す説明的断面図である。 Next, embodiments of the present invention will be described in more detail with reference to the accompanying drawings. FIG. 1 is an explanatory cross-sectional view showing the configuration of the multilayer wiring board of the present embodiment.
図１（ａ）に示すように、本実施形態の積層配線基板１は、コア基板２上に形成された第１の配線パターン３と、配線パターン３上に積層されたプリプレグ等の合成樹脂製シートからなる絶縁体層４と、絶縁体層４上に形成された第２の配線パターン５とを備えている。そして、配線パターン３，５はバンプ６を層間接続部材として互いに電気的に接続されている。
As shown in FIG. 1A, the laminated wiring board 1 of the present embodiment is made of a
積層配線基板１は、図１（ｂ）に示すように銅箔７上の所定の位置にバンプ６を形成した後、バンプ６を絶縁体層４に貫通させ、さらに図１（ｃ）に示すようにバンプ６の先端を配線パターン３に圧着させ加熱プレスして、基板２、絶縁体層４、銅箔７を一体化することにより形成される。尚、配線パターン５は、前述のようにして、基板２、絶縁体層４、銅箔７を一体化した後、銅箔７をそれ自体公知の方法によりエッチングすることにより形成することができる。
In the multilayer wiring board 1,
バンプ６は、直径０．２０ｍｍ未満、好ましくは０．１５ｍｍ以下、高さ１５０μｍの円錐形状を備えている。また、銅箔７は、例えば厚さ９〜３５μｍの電解銅箔であり、製箔機の表面形状が転写された最大高さ約１μｍの凹凸を備える表面に、平均粒子径０．５〜１．５μｍ、例えば平均粒子径１μｍの銅の一次粒子が付着せしめられ、該一次粒子が凝集して形成された平均粒子径５〜１５μｍ、例えば平均粒子径１０μｍの二次粒子からなる粗化面が備えられている。前記粗化面の上には０．０１〜０．２０ｍｇ／ｄｍ2、例えば０．１０ｍｇ／ｄｍ2の亜鉛からなる防錆層が形成されており、該防錆層の上にさらに島状のシランカップリング剤層が形成されている。前記防錆層は１〜１００ｎｍの範囲の厚さを備えており、前記シランカップリング剤層は１〜１０ｎｍの範囲の厚さを備えている。
The
前記シランカップリング剤としては、一方の端部にアミノ基、ビニル基、エポキシ基等の有機物と反応できる基を備え、他方の端部に−Ｓｉ（ＯＲ）3（ただし、ＯＲはメトキシ基、エトキシ基等のアルコキシ基）の化学式で表される基を備える化合物である。−Ｓｉ（ＯＲ）3基は加水分解によりシラノール基（−ＳｉＯＨ）を生成することができる。銅箔７は、前記シランカップリング剤からなるシランカップリング剤層を備えることにより、前述のようにして基板２、絶縁体層４と一体化したときに、絶縁体層４との密着性を向上させることができる。
The silane coupling agent includes a group capable of reacting with an organic substance such as an amino group, a vinyl group, or an epoxy group at one end, and -Si (OR) 3 (wherein OR is a methoxy group, It is a compound having a group represented by a chemical formula of an alkoxy group such as an ethoxy group. The —Si (OR) 3 group can generate a silanol group (—SiOH) by hydrolysis. The
このような銅箔７として、例えば、古河サーキットフォイル株式会社製ＦＣＮ−ＭＰＬ箔（商品名）等を用いることができる。
As such a
バンプ６は、銅箔７の上に、所定位置に貫通孔を備えるメタルマスクを積層し、該メタルマスクを介して導電性ペーストをスクリーン印刷した後、該貫通孔に充填された導電性ペーストを乾燥することにより形成される。前記導電性ペーストは、銀、金、銅、半田、ニッケル、カーボン等の導電性粉末または繊維状のフィラーと、バインダー成分と、溶剤とを混合したもの等を用いることができる。
The
本実施形態の積層配線基板１では、バンプ６と銅箔７との間の電気抵抗を電気抵抗を低減して発熱を低減することができるので、伝送損失、伝送ノイズを低減することができる。
In the multilayer wiring board 1 of the present embodiment, the electrical resistance between the
次に、本発明の実施例及び比較例を示す。 Next, examples and comparative examples of the present invention are shown.
本実施例では、表面に平均粒子径１μｍの銅の一次粒子が付着せしめられて形成された平均粒子径１０μｍの二次粒子からなる粗化面と、該粗化面の上に形成された０．１０ｍｇ／ｄｍ2の亜鉛からなる防錆層と、該防錆層の上に形成された島状のシランカップリング剤層とを備える厚さ１８μｍの銅箔Ａ（古河サーキットフォイル株式会社製ＦＣＮ−ＭＰＬ箔（商品名））を用い、該銅箔Ａ上に銀ペーストからなる直径０．１５ｍｍのバンプを形成した。前記バンプと前記銅箔Ａとの間の電気抵抗を測定したところ、平均１０ｍΩであった。結果を表１に示す。
〔比較例１〕
本比較例では、表面に平均粒子径２μｍの銅の一次粒子が付着せしめられて形成された平均粒子径２０μｍの二次粒子からなる粗化面と、該粗化面の上に形成された０．３０ｍｇ／ｄｍ2の亜鉛からなる防錆層と、該防錆層の上に形成された島状のシランカップリング剤層とを備える厚さ１８μｍの銅箔Ｂ（古河サーキットフォイル株式会社製ＴＣＮ箔（商品名））を用い、該銅箔Ｂ上に銀ペーストからなる直径０．１５ｍｍのバンプを形成した。前記バンプと前記銅箔Ｂとの間の電気抵抗を測定したところ、平均２０ｍΩであった。結果を表１に示す。
〔比較例２〕
本比較例では、直径を０．２０ｍｍとした以外は比較例１と全く同一にして前記銅箔Ｂ上に銀ペーストからなるバンプを形成した。前記バンプと前記銅箔Ｂとの間の電気抵抗を測定したところ、平均１０ｍΩであった。結果を表１に示す。
In this example, a roughened surface composed of secondary particles having an average particle diameter of 10 μm formed by adhering primary particles of copper having an average particle diameter of 1 μm to the surface, and 0 formed on the roughened surface. 18 μm thick copper foil A (FCN manufactured by Furukawa Circuit Foil Co., Ltd.) comprising a rust prevention layer made of 10 mg / dm 2 of zinc and an island-shaped silane coupling agent layer formed on the rust prevention layer -MPL foil (trade name)) was used, and a 0.15 mm diameter bump made of a silver paste was formed on the copper foil A. When the electrical resistance between the bump and the copper foil A was measured, it was 10 mΩ on average. The results are shown in Table 1.
[Comparative Example 1]
In this comparative example, a roughened surface composed of secondary particles having an average particle diameter of 20 μm formed by adhering primary particles of copper having an average particle diameter of 2 μm to the surface, and 0 formed on the roughened surface. .18 μm thick copper foil B (TCN manufactured by Furukawa Circuit Foil Co., Ltd.) comprising a rust-proof layer made of 30 mg / dm 2 zinc and an island-shaped silane coupling agent layer formed on the rust-proof layer Using a foil (trade name), a bump having a diameter of 0.15 mm made of a silver paste was formed on the copper foil B. When the electrical resistance between the bump and the copper foil B was measured, the average was 20 mΩ. The results are shown in Table 1.
[Comparative Example 2]
In this comparative example, a bump made of a silver paste was formed on the copper foil B in exactly the same manner as in Comparative Example 1 except that the diameter was 0.20 mm. When the electrical resistance between the bump and the copper foil B was measured, it was 10 mΩ on average. The results are shown in Table 1.
１…積層配線基板、 ２…基板、 ３…第１の配線パターン、 ４…絶縁体層、 ５…第２の配線パターン、 ６…バンプ、 ７…銅箔。 DESCRIPTION OF SYMBOLS 1 ... Laminated wiring board, 2 ... Board | substrate, 3 ... 1st wiring pattern, 4 ... Insulator layer, 5 ... 2nd wiring pattern, 6 ... Bump, 7 ... Copper foil.
Claims (3)
該銅箔は表面に平均粒子径０．５〜１．５μｍの銅の一次粒子が付着せしめられて平均粒子径５〜１５μｍの二次粒子を形成している粗化面と、該粗化面を被覆する０．０１〜０．２０ｍｇ／ｄｍ2の亜鉛からなる防錆層とを備え、
該バンプは０．２０ｍｍ未満の直径を備えることを特徴とする積層配線基板。 By etching a first wiring pattern formed on the substrate, an insulator layer made of a synthetic resin sheet laminated on the first wiring pattern, and a copper foil laminated on the insulator layer In a multilayer wiring board comprising: the formed second wiring pattern; and an interlayer connection member that connects the wiring patterns by penetrating bumps formed at predetermined positions on the copper foil through the insulator layer,
The copper foil has a roughened surface on which copper primary particles having an average particle diameter of 0.5 to 1.5 μm are adhered to form secondary particles having an average particle diameter of 5 to 15 μm, and the roughened surface. And 0.01 to 0.20 mg / dm 2 of a rust-preventing layer comprising zinc,
The bump is provided with a diameter of less than 0.20 mm.
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|---|---|---|---|---|
| JPH06350248A (en) * | 1993-06-14 | 1994-12-22 | Furukawa Saakitsuto Foil Kk | Surface treatment method of copper foil for printed wiring board |
| JPH07231152A (en) * | 1993-12-24 | 1995-08-29 | Mitsui Mining & Smelting Co Ltd | Copper foil for printed circuit inner layer and its manufacture |
| JPH08125331A (en) * | 1994-10-19 | 1996-05-17 | Toshiba Corp | Manufacture of printed circuit board |
| JPH08158100A (en) * | 1994-10-06 | 1996-06-18 | Furukawa Circuit Foil Kk | Roughening of copper foil surface |
| JPH1079579A (en) * | 1996-09-05 | 1998-03-24 | Toshiba Corp | Printed circuit board and manufacturing method of printed circuit board |
| JPH11135947A (en) * | 1997-10-28 | 1999-05-21 | Matsushita Electric Works Ltd | Printed wiring board and manufacture thereof |
| JPH11340596A (en) * | 1998-05-21 | 1999-12-10 | Furukawa Electric Co Ltd:The | Copper foil for printed circuit board and copper foil attached with resin |
| JP2004006829A (en) * | 2002-04-25 | 2004-01-08 | Matsushita Electric Ind Co Ltd | Wiring transfer sheet and its manufacturing method, and wiring board and its manufacturing method |
-
2004
- 2004-02-23 JP JP2004047012A patent/JP4497952B2/en not_active Expired - Fee Related
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06350248A (en) * | 1993-06-14 | 1994-12-22 | Furukawa Saakitsuto Foil Kk | Surface treatment method of copper foil for printed wiring board |
| JPH07231152A (en) * | 1993-12-24 | 1995-08-29 | Mitsui Mining & Smelting Co Ltd | Copper foil for printed circuit inner layer and its manufacture |
| JPH08158100A (en) * | 1994-10-06 | 1996-06-18 | Furukawa Circuit Foil Kk | Roughening of copper foil surface |
| JPH08125331A (en) * | 1994-10-19 | 1996-05-17 | Toshiba Corp | Manufacture of printed circuit board |
| JPH1079579A (en) * | 1996-09-05 | 1998-03-24 | Toshiba Corp | Printed circuit board and manufacturing method of printed circuit board |
| JPH11135947A (en) * | 1997-10-28 | 1999-05-21 | Matsushita Electric Works Ltd | Printed wiring board and manufacture thereof |
| JPH11340596A (en) * | 1998-05-21 | 1999-12-10 | Furukawa Electric Co Ltd:The | Copper foil for printed circuit board and copper foil attached with resin |
| JP2004006829A (en) * | 2002-04-25 | 2004-01-08 | Matsushita Electric Ind Co Ltd | Wiring transfer sheet and its manufacturing method, and wiring board and its manufacturing method |
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| JP2005236231A (en) | 2005-09-02 |
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