JP4493933B2 - Display device - Google Patents

Description

【００４１】
スパッタガスとして用いるＡｒは、基板を加熱するためのガスとして基板裏面側に吹き付けるように導入され、最終的にＮ₂と混合されてスパッタに寄与する。また、表１に示す成膜条件は、代表的な条件であってここに示す数値に限定されるものではなく、成膜されたＳｉＮ膜の物性パラメータが後に表４において示す物性パラメータの範囲内に入る限り、実施者が適宜変更しても良い。
【００４２】
ここで上記高周波スパッタ法により窒化シリコン膜を成膜するにあたって使用するスパッタ装置の概略図を図１７に示す。図１７において、３０はチャンバー壁、３１は磁場を形成するための可動式マグネット、３２は単結晶シリコンターゲット、３３は防護シャッター、３４は被処理基板、３６ａ及び３６ｂはヒーター、３７は基板チャック機構、３８は防着板、３９はバルブ（コンダクタンスバルブもしくはメインバルブ）である。また、チャンバー壁３０には、ガス導入管４０、４１は、それぞれＮ₂（もしくはＮ₂と希ガスの混合ガス）及び希ガスの導入管である。
【００４３】
また、比較例として従来のプラズマＣＶＤ法により形成される窒化シリコン膜の成膜条件を表２に示す。なお、表中の「ＰＣＶＤ−ＳｉＮ」とは、プラズマＣＶＤ法により形成された窒化シリコン膜を指す。
【００４４】
【表２】

【００４５】
次に、表１の成膜条件で成膜された窒化シリコン膜と表２の成膜条件で成膜された窒化シリコン膜の代表的な物性値（物性パラメータ）について、比較した結果を表３にまとめる。なお、「ＲＦＳＰ−ＳｉＮ（Ｎｏ．１）」と「ＲＦＳＰ−ＳｉＮ（Ｎｏ．２）」との違いは、成膜装置による違いであり、本発明のバリア膜として用いる窒化シリコン膜としての機能を損なうものではない。また、内部応力は、圧縮応力か引っ張り応力かで数値の正負の符号が変わるが、ここでは絶対値のみを取り扱う。
【００４６】
【表３】

【００４７】
表３に示すように、これらＲＦＳＰ−ＳｉＮ（Ｎｏ．１）及びＲＦＳＰ−ＳｉＮ（Ｎｏ．２）に共通の特徴点は、ＰＣＶＤ−ＳｉＮ膜と比較して、エッチング速度（ＬＡＬ５００を用いて２０℃でエッチングした際のエッチング速度をいう。以下、同じ。）が遅く、水素濃度が低い点が挙げられる。なお、「ＬＡＬ５００」とは、橋本化成株式会社製「ＬＡＬ５００ ＳＡバッファードフッ酸」であり、ＮＨ₄ＨＦ₂（７．１３％）とＮＨ₄Ｆ（１５．４％）の水溶液である。また、内部応力は、プラズマＣＶＤ法で成膜された窒化シリコン膜よりも絶対値で比較して小さい値となっている。
【００４８】
ここで本発明者らが表１の成膜条件によって成膜した窒化シリコン膜の諸物性のパラメータを表４にまとめる。
【００４９】
【表４】

【００５０】
また、当該窒化シリコン膜をＳＩＭＳ（質量二次イオン分析）により調べた結果を図１１に、そのＦＴ−ＩＲの結果を図１２に、その透過率を図１３に示す。なお、図１３には表２の成膜条件で成膜した窒化シリコン膜についても併せて表記する。透過率については、従来のＰＣＶＤ−ＳｉＮ膜と比べて遜色はない。
【００５１】
本発明で用いる窒化シリコン膜においては、表４に示すパラメータを満たす窒化シリコン膜が望ましい。即ち、窒化シリコン膜として、▲１▼エッチング速度が９ｎｍ以下（好ましくは、０．５〜３．５ｎｍ以下）である窒化シリコン膜を用いること、▲２▼水素濃度が１×１０²¹atoms／ｃｍ^-3以下（好ましくは、５×１０²⁰atoms／ｃｍ^-3以下）であること、▲３▼水素濃度が１×１０²¹atoms／ｃｍ^-3以下（好ましくは、５×１０²⁰atoms／ｃｍ^-3以下）で、かつ、酸素濃度が５×１０¹⁸〜５×１０²¹atoms／ｃｍ^-3（好ましくは、１×１０¹⁹〜１×１０²¹atoms／ｃｍ^-3）であること、▲４▼エッチング速度が９ｎｍ以下（好ましくは、０．５〜３．５ｎｍ以下）で、かつ、水素濃度が１×１０²¹atoms／ｃｍ^-3以下（好ましくは、５×１０²⁰atoms／ｃｍ^-3以下）であること、▲５▼エッチング速度が９ｎｍ以下（好ましくは、０．５〜３．５ｎｍ以下）で、かつ、水素濃度が１×１０²¹atoms／ｃｍ^-3以下（好ましくは、５×１０²⁰atoms／ｃｍ^-3以下）で、かつ、酸素濃度が５×１０¹⁸〜５×１０²¹atoms／ｃｍ^-3（好ましくは、１×１０¹⁹〜１×１０²¹atoms／ｃｍ^-3）であること、のいずれかを満たすことが望ましい。
【００５２】
また、内部応力の絶対値は、２×１０¹⁰ｄｙｎ／ｃｍ²以下、好ましくは５×１０⁹ｄｙｎ／ｃｍ²以下、さらに好ましくは５×１０⁸ｄｙｎ／ｃｍ²以下とすると良い。内部応力を小さくすれば、他の膜との界面における準位の発生を低減できる。さらに、内部応力による膜はがれを防止できる。
【００５３】
また、表１の成膜条件による窒化シリコン膜は、Ｎａ、Ｌｉその他の周期表の１族もしくは２族に属する元素に対するブロッキング効果が極めて強く、これらの可動イオン等の拡散を効果的に抑制することができる。例えば、本発明に用いる陰極としては、アルミニウムに０．２〜１．５ｗｔ％（好ましくは０．５〜１．０ｗｔ％）のリチウムを添加した金属膜が電荷注入性その他の点で好適であるが、この場合において、リチウムの拡散によってトランジスタの動作に害を及ぼすことが懸念される。しかしながら、本発明では、バリア膜で完全に保護されることとなるため、リチウムのトランジスタ方向への拡散は気にする必要がない。
【００５４】
この事実を示すデータを図１４〜１６に示す。図１４は、表２の成膜条件で成膜した窒化シリコン膜（ＰＣＶＤ−ＳｉＮ膜）を誘電体としたＭＯＳ構造のＢＴストレス試験前後におけるＣ−Ｖ特性の変化を示す図である。試料の構造は、図１６（Ａ）に示す通りであり、表面電極にＡｌ−Ｌｉ（リチウムを添加したアルミニウム）電極を用いることによりリチウム拡散による影響の有無を確かめることができる。図１４によれば、ＢＴストレス試験によりＣ−Ｖ特性が大きくシフトし、表面電極からのリチウムの拡散による影響が顕著に現れていることが確認できる。
【００５５】
次に、図１５（Ａ）、（Ｂ）は、表１の成膜条件で成膜した窒化シリコン膜を誘電体としたＭＯＳ構造のＢＴストレス試験前後におけるＣ−Ｖ特性である。図１５（Ａ）、（Ｂ）の違いは、図１５（Ａ）が表面電極にＡｌ−Ｓｉ（シリコンを添加したアルミニウム膜）電極を用いるのに対し、図１５（Ｂ）が表面電極にＡｌ−Ｌｉ（リチウムを添加したアルミニウム膜）電極を用いる点である。なお、図１５（Ｂ）の結果は、図１６（Ｂ）に示すＭＯＳ構造の測定結果である。ここで熱酸化膜との積層構造としたのは、窒化シリコン膜とシリコン基板との間の界面準位の影響を低減するためである。
【００５６】
図１５（Ａ）、（Ｂ）の両グラフを比較すると、両グラフともにＢＴストレス試験前後におけるＣ−Ｖ特性のシフトは殆ど差がなく、リチウム拡散の影響が現れていないこと、即ち、表１の成膜条件で成膜した窒化シリコン膜が効果的にブロッキング膜として機能していることが確認できる。
【００５７】
このように、本発明に用いる窒化シリコン膜は、非常に緻密でＮａやＬｉといった可動元素に対するブロッキング効果が高いため、平坦化膜からの脱ガス成分の拡散を抑制すると共に、Ａｌ−Ｌｉ電極等からのＬｉ拡散を効果的に抑制することで信頼性の高い表示装置を実現することができる。緻密である理由として、本発明者らは、単結晶シリコンターゲットの表面で薄い窒化シリコン膜が形成され、その窒化シリコン膜が基板へ積層されて成膜されるため、膜中にシリコンクラスタが混入されにくくなった結果として緻密になるのではないかと推測している。
【００５８】
また、室温から２００℃程度の低温下のスパッタ法で成膜されるため、本発明のバリア膜として用いる場合のように、樹脂膜の上に成膜できる点においてプラズマＣＶＤ法よりも有利である。
【００５９】
〔実施の形態２〕
本実施の形態は、実施の形態１とは異なる構成で電流源用Ｃｓを形成した例であり、第３の金属層を電極として用いている。なお、その他の構成は、実施の形態１と同じであるから、実施の形態１の説明を参照すれば良い。従って、本実施の形態では、実施の形態１と異なる点のみに着目して説明する。
【００６０】
図３（Ａ）、（Ｂ）は、実施の形態１における図２（Ａ）、（Ｂ）に相当する図面であり、実施の形態１と同じ符号を付してある部分は、実施の形態１で説明したものと同じ構成を有している。本実施の形態の場合、電流源用Ｃｓ２６の構成に特徴があり、図２（Ａ）において、平坦化層１２１を除去してある。即ち、第１電極１０９、誘電体（ゲート絶縁膜１１３）及び第２電極１１７で構成される第１の容量素子、第２電極１１７、誘電体（第１パッシベーション膜１１８）及び第３電極１２０で構成される第２の容量素子並びに第３電極１２０、バリア膜１２２及び第４電極３０１で構成される第３の容量素子の三つの容量素子を積層形成した構成となっている。
【００６１】
本実施の形態では、容量素子を三つ形成するために第１電極１０９及び第３電極１２０を固定電位としている。勿論、第２電極１１７及び第４電極３０１を固定電位としても同様である。即ち、交互に固定電位の電極を重ねておくことで最大限に容量を形成することができる。ただし、どの電極を固定電位とするかは回路設計において自由に設定可能であり、前掲の構成に限定する必要はない。
【００６２】
以上の構成を採用すると、三つの容量素子を小さい面積で形成することが可能となるため、開口率を損失を最小限に抑えつつ大容量を確保することができる。なお、本実施の形態に示す容量素子の構成は、電流源用Ｃｓへの適用に限られるものではなく、ビデオ用Ｃｓ１９その他の画素内に必要とされる容量素子（Ｃｓ）として用いることができる。
【００６３】
〔実施の形態３〕
本実施の形態は、実施の形態１とは異なる構成で電流源用Ｃｓを形成した例であり、第３の金属層を電極として用いている。なお、その他の構成は、実施の形態１と同じであるから、実施の形態１の説明を参照すれば良い。従って、本実施の形態では、実施の形態１と異なる点のみに着目して説明する。
【００６４】
図４（Ａ）、（Ｂ）は、実施の形態１における図２（Ａ）、（Ｂ）に相当する図面であり、実施の形態１と同じ符号を付してある部分は、実施の形態１で説明したものと同じ構成を有している。本実施の形態の場合、電流源用Ｃｓ２８の構成に特徴があり、図２（Ａ）において、平坦化層１２１及び第３電極１２０を除去してある。即ち、第１電極１０９、ゲート絶縁膜１１３及び第２電極１１７で構成される第１の容量素子並びに第２電極１１７、誘電体（第１パッシベーション膜１１８及びバリア膜１２２の積層体）及び第４電極４０１で構成される第２の容量素子の二つの容量素子を積層形成した構成となっている。この場合、誘電体が積層形成されているので、ピンホール等による不良の発生確率が大幅に低減するという利点がある。
【００６５】
本実施の形態では、容量素子を二つ形成するために第１電極１０９及び第４電極４０１を固定電位としている。ただし、どの電極を固定電位とするかは回路設計において自由に設定可能であり、前掲の構成に限定する必要はない。
【００６６】
以上の構成を採用すると、二つの容量素子を小さい面積で形成することが可能となるため、開口率を損失を抑えつつ大容量を確保することができる。なお、本実施の形態に示す容量素子の構成は、電流源用Ｃｓへの適用に限られるものではなく、ビデオ用Ｃｓ１９その他の画素内に必要とされる容量素子（Ｃｓ）として用いることができる。
【００６７】
〔実施の形態４〕
本実施の形態は、実施の形態１とは異なる構成で電流源用Ｃｓを形成した例であり、第３の金属層を電極として用いている。なお、その他の構成は、実施の形態１と同じであるから、実施の形態１の説明を参照すれば良い。従って、本実施の形態では、実施の形態１と異なる点のみに着目して説明する。
【００６８】
図５（Ａ）、（Ｂ）は、実施の形態１における図２（Ａ）、（Ｂ）に相当する図面であり、実施の形態１と同じ符号を付してある部分は、実施の形態１で説明したものと同じ構成を有している。本実施の形態の場合、電流源用Ｃｓ３０の構成に特徴があり、図５（Ａ）において、平坦化層１２１、第３電極１２０及び第２電極１１７を除去してある。即ち、第１電極１０９、誘電体（ゲート絶縁膜１１３、第１パッシベーション膜１１８及びバリア膜１２２の積層体）及び第４電極５０１で構成される容量素子となっている。本実施の形態では、第１電極１０９を固定電位としているが、どの電極を固定電位とするかは回路設計において自由に設定可能であり、前掲の構成に限定する必要はない。また、この場合、誘電体が三層の絶縁膜で積層形成されているので、ピンホール等による不良の発生確率を最小限に抑えることができるという利点がある。
【００６９】
また、本実施の形態とした場合、第２電極１１７が存在しないため第１電極１０９、即ち半導体には導電型を付与する不純物が添加される。即ち、図１〜図４の構成とした場合は、第２電極１１７に定電圧を印加しないと第１電極１０９を電極として機能させることができないが、本実施の形態の構成とすると、第４電極５０１に定電圧を与えなくても常に容量として機能させることができる。この効果は表示装置の消費電力の低減に寄与する。
【００７０】
なお、以上の構成は、電流源用Ｃｓへの適用に限られるものではなく、ビデオ用Ｃｓ１９その他の画素内に必要とされる容量素子（Ｃｓ）として用いることもできる。
【００７１】
〔実施の形態５〕
本実施の形態は、実施の形態１とは異なる構成で電流源用Ｃｓを形成した例であり、第３の金属層を電極として用いている。なお、その他の構成は、実施の形態１と同じであるから、実施の形態１の説明を参照すれば良い。従って、本実施の形態では、実施の形態１と異なる点のみに着目して説明する。
【００７２】
図６（Ａ）、（Ｂ）は、実施の形態１における図２（Ａ）、（Ｂ）に相当する図面であり、実施の形態１と同じ符号を付してある部分は、実施の形態１で説明したものと同じ構成を有している。本実施の形態の場合、電流源用Ｃｓ３２の構成に特徴があり、図２（Ａ）において、第２電極１１７を除去してある。即ち、第１電極１０９が不純物の添加によって電極化しているため、第３電極１２０に定電圧を印加しておかなくても常に電極として機能させることができ、低消費電力化に寄与する。
【００７３】
また、電流源用Ｃｓ３２の構成は、第１電極１０９、誘電体（ゲート絶縁膜１１３及び第１パッシベーション膜１１８の積層体）及び第３電極１２０で構成される。この場合、誘電体が積層形成されているので、ピンホール等による不良の発生確率が大幅に低減するという利点がある。また、本実施の形態では、第１電極１０９を固定電位としているが、どの電極を固定電位とするかは回路設計において自由に設定可能であり、前掲の構成に限定する必要はない。
【００７４】
なお、以上の構成は、電流源用Ｃｓへの適用に限られるものではなく、ビデオ用Ｃｓ１９その他の画素内に必要とされる容量素子（Ｃｓ）として用いることもできる。また、実施の形態１〜４のいずれの構成とも組み合わせて実施することが可能である。
【００７５】
〔実施の形態６〕
本実施の形態は、実施の形態１とは異なる構成で電流源用Ｃｓを形成した例であり、第３の金属層を電極として用いている。なお、その他の構成は、実施の形態１と同じであるから、実施の形態１の説明を参照すれば良い。従って、本実施の形態では、実施の形態１と異なる点のみに着目して説明する。
【００７６】
図７（Ａ）、（Ｂ）は、実施の形態１における図２（Ａ）、（Ｂ）に相当する図面であり、実施の形態１と同じ符号を付してある部分は、実施の形態１で説明したものと同じ構成を有している。本実施の形態の場合、電流源用Ｃｓ３４の構成に特徴があり、図２（Ａ）において、第１電極１０９を除去してある。
【００７７】
また、電流源用Ｃｓ３４の構成は、第２電極１１７、誘電体（第１パッシベーション膜１１８）及び第３電極１２０で構成される。なお、本実施の形態では、第３電極１２０を固定電位としているが、どの電極を固定電位とするかは回路設計において自由に設定可能であり、前掲の構成に限定する必要はない。
【００７８】
なお、以上の構成は、電流源用Ｃｓへの適用に限られるものではなく、ビデオ用Ｃｓ１９その他の画素内に必要とされる容量素子（Ｃｓ）として用いることもできる。また、実施の形態１〜４のいずれの構成とも組み合わせて実施することが可能である。
【００７９】
〔実施の形態７〕
本実施の形態は、画素の構成を実施の形態１とは異なる構成とした例について、図８を用いて説明する。図８（Ａ）に示す画素構成の特徴は、選択ゲート線１２、消去ゲート線１５及び電流ゲート線１６がいずれも同じ層の金属層（第１の金属層）で形成され、信号線１１、電流線１３及び電源線１４がいずれも同じ層の金属層（第２の金属層）で形成されると共に、第１の金属層と第２の金属層が交差する構成となっている点にある。この場合、その間に０．１〜０．５μｍ程度の比較的薄い第１パッシベーション膜１１８しか存在せず寄生容量が形成されてしまうが、実施の形態１の構成よりもコンタクト数が減少するため、開口率が向上するという利点がある。
【００８０】
なお、本実施の形態の画素構成において、画素内には実施の形態１〜６に示したいずれの構成の容量素子を形成しても良い。
【００８１】
〔実施の形態８〕
実施の形態１〜７に示した薄膜トランジスタの構成はいずれもトップゲート構造（具体的にはプレーナ構造）であるが、各実施の形態では、ボトムゲート構造（具体的には逆スタガ構造）とすることも可能である。その場合、活性層等の半導体層とゲート電極等の第１の金属層の位置が逆向きになるだけである。また当然のことながら、薄膜トランジスタに限らず、シリコンウェルを用いて形成されたＭＯＳ構造のトランジスタに適用しても良い。
【００８２】
〔実施の形態９〕
実施の形態１〜８に示した表示装置は、いずれもエレクトロルミネセンス表示装置を例示しているが、デバイス構成自体は、液晶表示装置に適用する場合についても共通であり、画素電極の構造を変更すれば、液晶表示装置、フィールドエミッション表示装置その他の複数の画素を有する表示装置に適用しても良い。
【００８３】
〔実施の形態１０〕
本実施の形態では、本発明を適用しうるエレクトロルミネセンス表示装置の全体の構成について、図９を用いて説明する。図９は、薄膜トランジスタが形成された素子基板をシーリング材によって封止することによって形成されたエレクトロルミネセンス表示装置の上面図であり、図９（Ｂ）は、図９（Ａ）のＢ−Ｂ’における断面図、図９（Ｃ）は、図９（Ａ）のＡ−Ａ’における断面図である。
【００８４】
基板２０１上には、画素部（表示部）２０２、該画素部２０２を囲むように設けられたデータ線駆動回路２０３、ゲート線駆動回路２０４ａ、２０４ｂ及び保護回路２０５が配置され、これらを囲むようにしてシール材２０６が設けられている。画素部２０２の構造については、実施の形態１〜８及びその説明を参照すれば良い。シーリング材２０６としては、ガラス材、金属材（代表的にはステンレス材）、セラミックス材、プラスチック材（プラスチックフィルムも含む）を用いることができるが、実施の形態１〜８に示したように絶縁膜のみで封止することも可能である。
【００８５】
このシール材２０６は、データ線駆動回路２０３、ゲート線駆動回路２０４ａ、２０４ｂ及び保護回路２０５の一部に重畳させて設けても良い。そして、該シール材２０６を用いてシーリング材２０７が設けられ、基板２０１、シール材２０６及びシーリング材２０７によって密閉空間２０８が形成される。シーリング材２０７には予め凹部の中に吸湿剤（酸化バリウムもしくは酸化カルシウム等）２０９が設けられ、上記密閉空間２０８の内部において、水分や酸素等を吸着して清浄な雰囲気に保ち、発光体の劣化を抑制する役割を果たす。この凹部は目の細かいメッシュ状のカバー材２１０で覆われており、該カバー材２１０は、空気や水分は通し、吸湿剤２０９は通さない。なお、密閉空間２０８は、窒素もしくはアルゴン等の希ガスで充填しておけばよく、不活性であれば樹脂もしくは液体で充填することも可能である。
【００８６】
また、基板２０１上には、データ線駆動回路２０３及びゲート線駆動回路２０４ａ、２０４ｂに信号を伝達するための入力端子部２１１が設けられ、該入力端子部２１１へはＦＰＣ（フレキシブルプリントサーキット）２１２を介してビデオ信号等のデータ信号が伝達される。入力端子部２１１の断面は、図９（Ｂ）の通りであり、ゲート配線もしくはデータ配線と同時に形成された配線からなる入力配線２１３とＦＰＣ２１２側に設けられた配線２１５とを、導電体２１６を分散させた樹脂２１７を用いて電気的に接続してある。なお、導電体２１６としては、球状の高分子化合物に金もしくは銀といったメッキ処理を施したものを用いれば良い。
【００８７】
また、図９（Ｃ）において、点線で囲まれた領域２１８の拡大図を図９（Ｄ）に示す。保護回路２０５は、薄膜トランジスタ２１９やコンデンサ２２０を組み合わせて構成すれば良く、コンデンサ２２０として実施の形態１〜７に示した構成の容量素子を用いれば良い。
【００８８】
本実施の形態において、保護回路２０５は入力端子部２１１とデータ線駆動回路２０３との間に設けられ、両者の間に突発的なパルス信号等の静電気が入った際に、該パルス信号を外部へ逃がす役割を果たす。その際、まず瞬間的に入る高電圧の信号をコンデンサ２２０によって鈍らせ、その他の高電圧を薄膜トランジスタや薄膜ダイオードを用いて構成した回路によって外部へと逃がすことができる。勿論、保護回路は、他の場所、例えば画素部２０２とデータ線駆動回路２０３との間や画素部２０２とゲート線駆動回路２０４ａ、２０４ｂの間などに設けても構わない。
【００８９】
以上のように、本実施の形態では、本発明を実施するにあたって、入力端子部に設けられた静電気対策等の保護回路に用いられるコンデンサを同時形成する例を示しており、実施の形態１〜９のいずれの構成とも組み合わせて実施することが可能である。
【００９０】
〔実施の形態１１〕
本発明の表示装置を表示部に用いた電子機器として、ビデオカメラ、デジタルカメラ、ゴーグル型ディスプレイ（ヘッドマウントディスプレイ）、ナビゲーションシステム、音響再生装置（カーオーディオ、オーディオコンポ等）、ノート型パーソナルコンピュータ、ゲーム機器、携帯情報端末（モバイルコンピュータ、携帯電話、携帯型ゲーム機または電子書籍等）、記録媒体を備えた画像再生装置（具体的にはDigital Versatile Disc（ＤＶＤ）等の記録媒体を再生し、その画像を表示しうるディスプレイを備えた装置）などが挙げられる。それらの電子機器の具体例を図１０に示す。
【００９１】
図１０（Ａ）はテレビであり、筐体２００１、支持台２００２、表示部２００３、スピーカー部２００４、ビデオ入力端子２００５等を含む。本発明は表示部２００３に適用することができる。なお、パソコン用、ＴＶ放送受信用、広告表示用などの全ての情報表示用のテレビが含まれる。
【００９２】
図１０（Ｂ）はデジタルカメラであり、本体２１０１、表示部２１０２、受像部２１０３、操作キー２１０４、外部接続ポート２１０５、シャッター２１０６等を含む。本発明は、表示部２１０２に適用することができる。
【００９３】
図１０（Ｃ）はノート型パーソナルコンピュータであり、本体２２０１、筐体２２０２、表示部２２０３、キーボード２２０４、外部接続ポート２２０５、ポインティングマウス２２０６等を含む。本発明は、表示部２２０３に適用することができる。
【００９４】
図１０（Ｄ）はモバイルコンピュータであり、本体２３０１、表示部２３０２、スイッチ２３０３、操作キー２３０４、赤外線ポート２３０５等を含む。本発明は、表示部２３０２に適用することができる。
【００９５】
図１０（Ｅ）は記録媒体を備えた携帯型の画像再生装置（具体的にはＤＶＤ再生装置）であり、本体２４０１、筐体２４０２、表示部Ａ２４０３、表示部Ｂ２４０４、記録媒体（ＤＶＤ等）読み込み部２４０５、操作キー２４０６、スピーカー部２４０７等を含む。表示部Ａ２４０３は主として画像情報を表示し、表示部Ｂ２４０４は主として文字情報を表示するが、本発明は表示部Ａ、Ｂ２４０３、２４０４に適用することができる。なお、記録媒体を備えた画像再生装置には家庭用ゲーム機器なども含まれる。
【００９６】
図１０（Ｆ）はゴーグル型ディスプレイ（ヘッドマウントディスプレイ）であり、本体２５０１、表示部２５０２、アーム部２５０３を含む。本発明は、表示部２５０２に適用することができる。
【００９７】
図１０（Ｇ）はビデオカメラであり、本体２６０１、表示部２６０２、筐体２６０３、外部接続ポート２６０４、リモコン受信部２６０５、受像部２６０６、バッテリー２６０７、音声入力部２６０８、操作キー２６０９、接眼部２６１０等を含む。本発明は、表示部２６０２に適用することができる。
【００９８】
図１０（Ｈ）は携帯電話であり、本体２７０１、筐体２７０２、表示部２７０３、音声入力部２７０４、音声出力部２７０５、操作キー２７０６、外部接続ポート２７０７、アンテナ２７０８等を含む。本発明は、表示部２７０３に適用することができる。なお、表示部２７０３は黒色の背景に白色の文字を表示することで携帯電話の消費電流を抑えることができる。
【００９９】
以上の様に、本発明を実施して得た表示装置は、あらゆる電子機器の表示部として用いても良い。なお、本実施の形態の電子機器には、実施の形態１〜９に示したいずれの構成を有した表示装置を用いても良い。
【０１００】
【発明の効果】
本発明により、第１に、平坦化膜が第１パッシベーション膜及びバリア膜により封入されているため、平坦化膜からの脱ガス等による経時劣化の問題がなく、信頼性の高い表示装置を得ることができる。また、第２に、容量素子を積層形成することにより少ない面積で大きな容量値を確保できる。また、第３に、図２（Ｂ）に示した特殊な構造の画素電極を発光素子の陽極として用いることにより光取り出し効率を高め、輝度が高く明るいエレクトロルミネセンス表示装置とすることができると共に、低消費電力化することにより発光素子の劣化の進行度を抑え、信頼性を高くすることができる。
【０１０１】
以上のように、本発明の表示装置は、多層配線を活用することにより各画素に必要とされる容量値（電荷保持用の容量値）を十分な大きさで確保し、かつ、発光素子の劣化を極力抑えるための構造とすることで信頼性が高く輝度の高い表示装置となる。
【図面の簡単な説明】
【図１】 表示装置の画素構成を示す上面図及び回路図。
【図２】 表示装置のデバイス構成を示す断面図。
【図３】 表示装置のデバイス構成を示す断面図。
【図４】 表示装置のデバイス構成を示す断面図。
【図５】 表示装置のデバイス構成を示す断面図。
【図６】 表示装置のデバイス構成を示す断面図。
【図７】 表示装置のデバイス構成を示す断面図。
【図８】 表示装置の画素構成を示す上面図及び回路図。
【図９】 表示装置の外観を示す上面図及び断面図。
【図１０】 電子機器の一例を示す図。
【図１１】 窒化シリコン膜中の不純物分布を示す図。
【図１２】 窒化シリコン膜のＦＴ−ＩＲ測定結果を示す図。
【図１３】 窒化シリコン膜の透過率を示す図。
【図１４】 窒化シリコン膜のＣ−Ｖ特性を示す図。
【図１５】 窒化シリコン膜のＣ−Ｖ特性を示す図。
【図１６】 窒化シリコン膜を用いたＭＯＳ構造の断面図。
【図１７】 窒化シリコン膜の成膜に用いるスパッタ装置を示す図。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a display device using a semiconductor element (typically a transistor) as a device, in particular, a technical field related to a light-emitting device typified by an electroluminescence display device, and an electronic apparatus including the display device in an image display unit. Belongs to the technical field.
[0002]
[Prior art]
In recent years, development of a liquid crystal display device or an electroluminescence display device in which transistors (particularly thin film transistors) are integrated on a substrate has been advanced. Each of these display devices is characterized in that a transistor is formed on a glass substrate by using a thin film formation technique, the transistor is arranged in each pixel arranged in a matrix, and functions as a display device that performs image display. .
[0003]
There are various specifications required for an image display area (hereinafter referred to as a pixel portion) of the display device. First, the number of dots is high and the definition is high, and the area of the effective display area of each pixel is large and bright. For example, image display is possible, and there is no defect that causes point defects or line defects over the entire pixel portion. In order to satisfy these specifications, not only the performance of the transistors arranged in each pixel is good, but also a technique capable of forming transistors with a stable process and high yield is required.
[0004]
In addition, among organic electroluminescence display devices, organic electroluminescence display devices use an organic compound for a light emitting element that serves as a light emitting source, and therefore, a device for suppressing deterioration of the organic compound is an important issue in ensuring reliability ( For example, see Patent Document 1.) In other words, in order to obtain a display device with high reliability, it is necessary to take measures against reliability in consideration of not only during the production but also the deterioration with time after completion.
[0005]
[Patent Document 1]
JP 2001-203076 A
[0006]
[Problems to be solved by the invention]
The present invention provides a structure for suppressing deterioration of a light emitting element as much as possible in a light emitting device typified by an electroluminescence display device, and sufficiently securing a capacitor element (capacitor) required for each pixel. It is an object to provide a structure.
[0007]
[Means for Solving the Problems]
The gist of the present invention is characterized in that as means for solving the above-mentioned problems, means for preventing the influence of the flattening film due to aging and means having a large charge retention characteristic without impairing the aperture ratio are provided. It is a display device. In other words, by encapsulating a planarization film covering a transistor with a dense insulating film such as a silicon nitride film, the change with time (degassing, etc.) is prevented, and furthermore, the multilayer structure capacitive element can be utilized by taking advantage of the multilayer wiring. By providing the pixel, a pixel including a capacitor with good charge retention characteristics without impairing the aperture ratio is provided.
[0008]
Here, the light-emitting element is a light-emitting body (light-emitting layer, carrier injection layer, carrier transport layer, carrier blocking layer, or other organic compound or inorganic compound required for light emission) between a pair of electrodes (anode and cathode). It is a device provided with a laminated body. For example, an electroluminescent element corresponds to a light emitting element.
[0009]
Specifically, the present invention relates to a semiconductor, a gate insulating film on the semiconductor, a first metal layer on the gate insulating film, a first passivation film provided above the semiconductor, and on the first passivation film. A display device comprising: a second metal layer; a planarization film on the second metal layer; a barrier film on the planarization film; and a third metal layer on the barrier film,
The side surface of the first opening provided in the planarizing film is covered with the barrier film, and the stacked body includes the gate insulating film, the first passivation film, and the barrier film inside the first opening. A second opening provided, and the third metal layer is connected to the semiconductor through the first opening and the second opening;
A first capacitor composed of the semiconductor, the gate insulating film, and the first metal layer, and a second capacitor composed of the first metal layer, the first passivation film, and the second metal layer. And an element.
[0010]
In the present invention, the capacitor element may be configured by a first capacitor element including the semiconductor, the gate insulating film, and the first metal layer, the first metal layer, the first passivation film, and A configuration comprising: a second capacitor element configured by the second metal layer; and a third capacitor element configured by the second metal layer, the barrier film, and the third metal. If so, the charge retention characteristics can be further improved.
[0011]
Further, in the present invention, the configuration of the capacitive element includes a first capacitive element composed of the semiconductor, the gate insulating film, and the first metal layer, the first metal layer, the first passivation film, A second capacitor element including the barrier film and the third metal layer may be provided.
[0012]
In the present invention, the capacitive element includes the capacitive element including the semiconductor, the gate insulating film, the first passivation film, the barrier film, and the third metal layer. It may be what you do.
[0013]
In the present invention described above, the structure of the capacitive element includes the capacitive element including the semiconductor, the gate insulating film, the first passivation film, and the second metal layer. May be.
[0014]
In the present invention described above, the structure of the capacitive element includes a capacitive element including the first metal layer, the first passivation film, and the second metal layer. Also good.
[0015]
Hereinafter, embodiments of the display device according to the present invention will be described in detail with reference to the drawings.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
[Embodiment 1]
This embodiment is an example of the electroluminescent display device of the present invention. 1A is a top circuit diagram (CAD drawing) in one pixel of an electroluminescence display device, and FIG. 1B is a circuit diagram schematically showing the circuit configuration. Each pixel of the electroluminescent display device shown in FIG. 1B includes a signal line 11, a selection gate wiring 12, a current line 13, a power supply line (wiring for supplying a constant voltage or a constant current) 14, an erase gate line 15, and Each pixel has a current gate line 16, and each pixel includes a selection transistor 17, a driving transistor 18, a video Cs (video capacitive element) 19, an erasing transistor 20, a current source transistor 21, an input transistor 22, a holding transistor 23, a current A source Cs (capacitor element for current source) 24 and a light emitting element 25 are provided. Note that the circuit configuration of the pixel shown in this embodiment is described in Japanese Patent Application No. 2001-289983 by the present applicant, and is a novel configuration according to the invention of the present applicant.
[0017]
As a feature of the electroluminescent display device of this embodiment mode, light extraction is performed in a direction opposite to that of a substrate over which a transistor is formed. Therefore, an aperture ratio (( The ratio of the effective display area to the pixel area is not reduced. Of course, the application of the present invention is not limited to the configuration shown in FIGS. 1A and 1B, and application to other circuit configurations may be appropriately performed by those skilled in the art.
[0018]
Next, typical cross-sectional structures of one pixel of the electroluminescent display device illustrated in FIGS. 1A and 1B are illustrated in FIGS. 2A is a cross-sectional view of the selection transistor 17 and the current source Cs (current source capacitor) 14, and FIG. 2B is a cross-sectional view of the current source Cs 24 and the drive transistor 18. .
[0019]
In FIG. 2A, reference numeral 101 denotes a substrate, which can be a glass substrate, a ceramic substrate, a quartz substrate, a silicon substrate, or a plastic substrate (including a plastic film). Reference numeral 102 denotes a base film made of a silicon nitride oxide film, a silicon oxynitride film, or a laminated film thereof. Further, a semiconductor serving as an active layer of the selection transistor 17 is provided on the base film 102. The active layer includes a source region 103, a drain region 104, LDD regions 105a to 105d, and channel formation regions 106a and 106b. In addition, two channel formation regions and four LDD regions are provided between the source region 103 and the drain region 104. At the same time, the lower electrode 108 of the video Cs 19, the lower electrode 109 of the current source Cs 24, the source region 110, the drain region 111, and the channel formation region 112 constituting the active layer of the driving transistor 18 are formed.
[0020]
Note that the source region 103, the drain region 104, and the LDD regions 105a to 105d of the selection transistor 17 are n-type impurity regions, and the source region 110 and the drain region 111 of the driving transistor 18 are p-type impurity regions. Further, the channel forming regions 106a and 106b of the selection transistor 17, the channel forming region 112 of the driving transistor 18, the first electrode (lower electrode) 108 of the video Cs 19 and the first electrode (lower electrode) 109 of the current source Cs 24. Is an intrinsic (so-called i-type) semiconductor.
[0021]
On these semiconductors, a silicon oxide film, a silicon oxynitride film (containing 25 to 35 atomic% of Si, 55 to 65 atomic% of oxygen, 1 to 20 atomic% of nitrogen, and 0.1 to 10 atomic% of hydrogen) A gate insulating film 113 using an aluminum nitride film, an aluminum oxide film, an aluminum oxynitride film, or a stacked film of these insulating films and a silicon nitride film is provided. The gate insulating film 113 functions as a gate insulating film of the selection transistor 17 and the driving transistor 18 and also serves as a dielectric of the video Cs 19 and a first dielectric (lower dielectric) of the current source Cs 24.
[0022]
On the gate insulating film 113, the first metal layer is patterned to provide the gate electrodes 114 a and 114 b of the selection transistor 17 and the gate electrode 115 of the driving transistor 18. Each gate electrode is different in shape of the first layer electrode (tantalum nitride film) and the second layer electrode (tungsten film), and the first layer electrode has a wider line width than the second layer electrode. ing. For the formation method of this feature and the reason and advantage of the gate electrode having such a structure, refer to Japanese Patent Application Laid-Open No. 2002-57162 filed by the present applicant. Simultaneously with the formation of the gate electrode, the second electrode (upper electrode) 116 of the video Cs 19 and the second electrode (intermediate electrode) 117 of the current source Cs 24 are provided.
[0023]
On these gate electrode and Cs electrode, as a first passivation film 118, a silicon nitride oxide film (Si is 25 to 35 atomic%, oxygen is 15 to 30 atomic%, nitrogen is 20 to 35 atomic%, and hydrogen is 15 A silicon compound film contained at ˜25 atomic% (hereinafter the same), or a silicon nitride film formed by plasma CVD is provided at a thickness of 0.1 to 1 μm (preferably 0.2 to 0.5 μm). Since the first passivation film 118 contains hydrogen at a concentration of 15 to 25 atomic%, the first passivation film 118 can function as a hydrogen supply source by heating, and can perform hydrogen termination of the semiconductor serving as the active layer. At the same time, the current source Cs24 functions as a second dielectric (upper dielectric).
[0024]
On the first passivation film 118, the drain wiring 119 of the selection transistor 17 and the third electrode (upper electrode) 120 of the current source Cs 24 are provided by patterning the second metal layer. The drain wiring 119 electrically connects the drain region 104 of the selection transistor 17 and the second electrode 116 of the video Cs 19. Note that any metal film may be used as the second metal layer, but it is desirable to use a low-resistance aluminum film or a copper thin film (including a copper alloy film). In addition, it is desirable to consider the adhesion with the planarization layer 119 formed thereon.
[0025]
On the drain wiring 119 and the third electrode 120, a planarizing film 121 is provided with a thickness of 0.5 to 3 μm (preferably 1 to 2 μm). As the planarization film 121, an organic resin film or an inorganic insulating film that can be formed by a spin coating method (coating method) can be used. Of course, an inorganic insulating film formed by a CVD method, a sputtering method, or other vapor phase method may be polished (including mechanical polishing, chemical polishing, or a combination thereof). In practicing the present invention, a photosensitive organic resin film (preferably a positive type) that does not require plasma treatment may be used. Since a photosensitive organic resin film (typically a photosensitive acrylic film) can be patterned only by etching with a developer, it can be formed without leaving plasma damage in the film.
[0026]
The planarizing film 121 is subjected to exposure and development processes, the source region 103 of the selection transistor 17, the source regions 110 and 111 of the driving transistor 18, and the first electrode 108 (strictly speaking, adjacent to the first electrode 108) of the video Cs19. P-type impurity region) and an opening (the opening provided in the planarization film 121 is referred to as a first opening, hereinafter the same) above the third electrode 120 of the current source Cs24. Provided. A barrier film 122 is provided with a thickness of 30 to 100 nm (preferably 40 to 60 nm) so as to cover the planarization film 121 provided with the first opening, and the barrier film is provided inside the first opening. 122, the first passivation film 118 and the gate insulating film 113 are provided with openings (the openings provided in these insulating films are referred to as second openings, hereinafter the same).
[0027]
A characteristic point here is that a silicon nitride film having an extremely dense film quality is used as the barrier film 122. This point will be described later.
[0028]
In the first opening, the barrier film 122 and the first passivation film 118 are in contact with each other in the range of 1 to 5 μm (typically 2 to 3 μm). Therefore, the planarization film 121 is in contact with the barrier film 122 and the first film. The film is completely confined by one passivation film 118. As a result, even when an organic resin film or a spin-on-glass (SOG) film is used as the planarization film 121, it is possible to effectively suppress the occurrence of degassing due to aging. Deterioration with time can be suppressed.
[0029]
On the barrier film 122, the source wiring 123 of the selection transistor 17 (corresponding to the signal line 11 in FIG. 1B), the first electrode 108 of the video Cs 19 and the third electrode 120 of the current source Cs 24 are provided. A connection wiring 124 (which also serves as a source wiring of the driving transistor 18 and corresponds to the power supply line 14 in FIG. 1B) and a pixel electrode 125 are provided. These electrodes are electrically connected to the corresponding electrodes through the first opening or the second opening, respectively. In the present embodiment, these electrodes are arranged in three layers in order from the bottom: a titanium film 31, a titanium nitride film 32, and an aluminum film (including an aluminum alloy film and an aluminum film added with other elements; the same applies hereinafter) 33. It has a structure. The reason is as follows: (1) The titanium film is preferable as the lowermost layer in order to improve the ohmic contact with the silicon film, and (2) The titanium nitride film is used in order to reduce the contact resistance between the titanium film and aluminum. Preferred is (3) that a titanium nitride film can be used as the pixel electrode (anode of the light emitting element), and (4) that the light extraction efficiency can be expected to be improved by utilizing the cross section of the aluminum film.
[0030]
In the present embodiment, the electrode to be the pixel electrode 125 is composed of the titanium film 31, the titanium nitride film 32, and the aluminum film 33, and the aluminum film 33 is selectively removed in the light emitting region (effective display region). The titanium nitride film 32 is exposed. As a result, the surface of the titanium nitride film 32 can be used as the anode of the light emitting element 25. Further, when the aluminum film 33 is etched using the organic resin film 126, as shown in FIG. 2B, the light emitter 126 is laterally adjusted by adjusting the cross-sectional shape of the aluminum film 33 to be a tapered shape. The light propagating in the direction can be reflected upward, and an improvement in light extraction efficiency can be expected as a whole. This reflection effect is obtained all around the pixel electrode, that is, along the contour of the pixel electrode.
[0031]
Note that the light-emitting body (a carrier injection layer, a carrier transport layer, a carrier blocking layer, a light-emitting layer, an organic compound or an inorganic compound that contributes to carrier recombination, or a stacked body thereof. (Titanium nitride film) 32 and a cathode (referring to an electrode containing an element belonging to Group 1 or Group 2 of the periodic table; the same applies hereinafter) 127 to form a light emitting element 25. It is protected by the second passivation film 128. The second passivation film 128 may be made of the same material as the first passivation film 118, but the same material as the barrier film 122 is preferable because it has a higher protective function. The light emitter 126 may be made of any known material.
[0032]
The pixel configuration (FIG. 1A) of the electroluminescent display device of the present invention including the above configuration is characterized in that the selection gate line 12, the erase gate line 15 and the current gate line 16 are all the same metal layer ( The signal line 11, the current line 13, and the power line 14 are all formed of the same metal layer (second metal layer), and the first metal layer and the second metal layer are formed of the first metal layer. The portion where the metal layers intersect is bridged by using a third metal layer that is further above the second metal layer.
[0033]
That is, when the first metal layer and the second metal layer intersect, only the relatively thin first passivation film 118 of about 0.1 to 0.5 μm exists between them, and a parasitic capacitance is formed. When the first metal layer and the third metal layer are crossed, the parasitic capacitor can be almost ignored because the thick planarizing film 121 having a thickness of 0.5 to 3 μm exists between the first metal layer and the third metal layer.
[0034]
The device configuration is characterized in that, first of all, since the planarization film 121 is enclosed by the first passivation film 118 and the barrier film 122, there is a problem of deterioration with time due to degassing from the planarization film 121 and the like. In addition, a highly reliable display device can be obtained.
[0035]
Second, a large capacitance value can be ensured with a small area by stacking capacitive elements. For example, in the current source Cs 24, the first electrode 109, the second electrode 117, and the dielectric (gate insulating film) 113 constitute a first capacitive element, and the second electrode 117, the third electrode 120, and the dielectric (first The second capacitive element is composed of the passivation film 118), and these are connected in parallel. Although not shown, the first electrode 109 and the third electrode 120 are fixed potentials (or the same potential may be used). As described above, the laminated structure of the first capacitor element constituted by the semiconductor / gate insulating film / first metal layer and the second capacitor element constituted by the first metal layer / first passivation film / second metal layer. By using the capacitive element, a large capacitance value can be secured with a small area.
[0036]
In the video Cs 19, the first electrode 108, the second electrode 116, and the dielectric (gate insulating film) 113 constitute a capacitive element. As described above, in the case where a stacked structure is not necessary, a capacitor element using two electrodes can be formed.
[0037]
Third, by using the pixel electrode 125 having a special structure shown in FIG. 2B as the anode of the light-emitting element 25, the light extraction efficiency is increased, and an electroluminescence display device having high brightness and brightness is obtained. it can. Note that high brightness means that a bright image can be obtained with low power consumption, and thus low power consumption can be achieved. Further, by reducing power consumption, the degree of deterioration of the light emitting element 25 can be improved. It is possible to suppress and increase reliability.
[0038]
As described above, the electroluminescence display device according to the present embodiment ensures a sufficient capacitance value (capacitance value for charge retention) required for each pixel by utilizing multilayer wiring, In addition, the display device has high reliability and high luminance.
[0039]
(About the silicon nitride film used in the present invention)
The silicon nitride film used in the present invention is an extremely dense silicon nitride film formed by high-frequency sputtering, and is formed under the process conditions shown in Table 1 below (typical examples are also shown). . Note that the silicon nitride film described here can be applied to all portions where the silicon nitride film is used in the present invention. Further, “RFSP-SiN” in the table refers to a silicon nitride film formed by a high frequency sputtering method. “T / S” is the distance between the target and the substrate.
[0040]
[Table 1]

[0041]
Ar used as a sputtering gas is introduced so as to be sprayed to the back side of the substrate as a gas for heating the substrate, and finally N ₂ And contributes to sputtering. The film formation conditions shown in Table 1 are representative conditions and are not limited to the numerical values shown here. The physical property parameters of the formed SiN film are within the range of the physical property parameters shown in Table 4 later. As long as it enters, the practitioner may make changes as appropriate.
[0042]
FIG. 17 shows a schematic diagram of a sputtering apparatus used for forming a silicon nitride film by the high frequency sputtering method. In FIG. 17, 30 is a chamber wall, 31 is a movable magnet for forming a magnetic field, 32 is a single crystal silicon target, 33 is a protective shutter, 34 is a substrate to be processed, 36a and 36b are heaters, and 37 is a substrate chuck mechanism. , 38 is a deposition preventing plate, and 39 is a valve (conductance valve or main valve). Further, the gas introduction pipes 40 and 41 are respectively connected to the chamber wall 30 with N. ₂ (Or N ₂ And a rare gas inlet tube.
[0043]
Table 2 shows the conditions for forming a silicon nitride film formed by a conventional plasma CVD method as a comparative example. In the table, “PCVD-SiN” refers to a silicon nitride film formed by a plasma CVD method.
[0044]
[Table 2]

[0045]
Next, Table 3 shows a comparison result of typical physical property values (physical property parameters) of the silicon nitride film formed under the film formation conditions in Table 1 and the silicon nitride film formed under the film formation conditions in Table 2. To summarize. The difference between “RFSP-SiN (No. 1)” and “RFSP-SiN (No. 2)” is a difference depending on the film forming apparatus, and the function as the silicon nitride film used as the barrier film of the present invention is different. There is no loss. Further, the sign of the numerical value of the internal stress changes depending on the compressive stress or the tensile stress, but only the absolute value is handled here.
[0046]
[Table 3]

[0047]
As shown in Table 3, the common feature of these RFSP-SiN (No. 1) and RFSP-SiN (No. 2) is that the etching rate (20 ° C. using LAL500 is 20 ° C. compared with the PCVD-SiN film). The etching rate at the time of etching is the same, the same applies hereinafter), and the hydrogen concentration is low. “LAL500” is “LAL500 SA buffered hydrofluoric acid” manufactured by Hashimoto Kasei Co., Ltd. _Four HF ₂ (7.13%) and NH _Four It is an aqueous solution of F (15.4%). The internal stress is smaller than the silicon nitride film formed by the plasma CVD method in absolute value.
[0048]
Here, Table 4 summarizes parameters of various physical properties of the silicon nitride film formed by the inventors under the film forming conditions shown in Table 1.
[0049]
[Table 4]

[0050]
Further, FIG. 11 shows the result of examining the silicon nitride film by SIMS (mass secondary ion analysis), FIG. 12 shows the result of FT-IR, and FIG. 13 shows the transmittance. In FIG. 13, the silicon nitride film formed under the film formation conditions shown in Table 2 is also shown. The transmittance is not inferior to that of the conventional PCVD-SiN film.
[0051]
The silicon nitride film used in the present invention is preferably a silicon nitride film that satisfies the parameters shown in Table 4. That is, as the silicon nitride film, (1) a silicon nitride film having an etching rate of 9 nm or less (preferably 0.5 to 3.5 nm or less) is used, and (2) the hydrogen concentration is 1 × 10. ^{twenty one} atoms / cm ^-3 The following (preferably 5 × 10 ²⁰ atoms / cm ^-3 3) Hydrogen concentration is 1 × 10 ^{twenty one} atoms / cm ^-3 The following (preferably 5 × 10 ²⁰ atoms / cm ^-3 And the oxygen concentration is 5 × 10 ¹⁸ ~ 5x10 ^{twenty one} atoms / cm ^-3 (Preferably 1 × 10 ¹⁹ ~ 1x10 ^{twenty one} atoms / cm ^-3 4) The etching rate is 9 nm or less (preferably 0.5 to 3.5 nm or less), and the hydrogen concentration is 1 × 10 ^{twenty one} atoms / cm ^-3 The following (preferably 5 × 10 ²⁰ atoms / cm ^-3 5) The etching rate is 9 nm or less (preferably 0.5 to 3.5 nm or less), and the hydrogen concentration is 1 × 10 ^{twenty one} atoms / cm ^-3 The following (preferably 5 × 10 ²⁰ atoms / cm ^-3 And the oxygen concentration is 5 × 10 ¹⁸ ~ 5x10 ^{twenty one} atoms / cm ^-3 (Preferably 1 × 10 ¹⁹ ~ 1x10 ^{twenty one} atoms / cm ^-3 It is desirable to satisfy any of the above.
[0052]
The absolute value of the internal stress is 2 × 10 ^Ten dyn / cm ² Or less, preferably 5 × 10 ⁹ dyn / cm ² Or less, more preferably 5 × 10 ⁸ dyn / cm ² The following should be used. If the internal stress is reduced, the generation of levels at the interface with other films can be reduced. Furthermore, film peeling due to internal stress can be prevented.
[0053]
Further, the silicon nitride film according to the film formation conditions shown in Table 1 has a very strong blocking effect on Na, Li and other elements belonging to Group 1 or 2 of the periodic table, and effectively suppresses the diffusion of these mobile ions and the like. be able to. For example, as the cathode used in the present invention, a metal film in which 0.2 to 1.5 wt% (preferably 0.5 to 1.0 wt%) of lithium is added to aluminum is preferable in terms of charge injection and other points. However, in this case, there is a concern that the operation of the transistor is adversely affected by the diffusion of lithium. However, in the present invention, since it is completely protected by the barrier film, it is not necessary to worry about diffusion of lithium in the transistor direction.
[0054]
Data showing this fact are shown in FIGS. FIG. 14 is a diagram showing changes in CV characteristics before and after the BT stress test of a MOS structure using a silicon nitride film (PCVD-SiN film) formed under the film formation conditions shown in Table 2 as a dielectric. The structure of the sample is as shown in FIG. 16A. By using an Al—Li (aluminum to which lithium is added) electrode as the surface electrode, it is possible to confirm the influence of lithium diffusion. According to FIG. 14, it can be confirmed that the CV characteristic is greatly shifted by the BT stress test, and the influence of the diffusion of lithium from the surface electrode appears remarkably.
[0055]
Next, FIGS. 15A and 15B show the CV characteristics before and after the BT stress test of the MOS structure using the silicon nitride film formed under the film forming conditions shown in Table 1 as a dielectric. 15A and 15B is different from FIG. 15A in that FIG. 15A uses an Al—Si (aluminum film added with silicon) electrode for the surface electrode, whereas FIG. This is the point of using a -Li (aluminum film to which lithium is added) electrode. Note that the result of FIG. 15B is a measurement result of the MOS structure shown in FIG. Here, the laminated structure with the thermal oxide film is used to reduce the influence of the interface state between the silicon nitride film and the silicon substrate.
[0056]
Comparing both graphs of FIGS. 15A and 15B, there is almost no difference in the CV characteristic shift before and after the BT stress test in both graphs, and the influence of lithium diffusion does not appear. It can be confirmed that the silicon nitride film formed under the film forming conditions effectively functions as a blocking film.
[0057]
As described above, since the silicon nitride film used in the present invention is very dense and has a high blocking effect on movable elements such as Na and Li, the diffusion of degas components from the planarization film is suppressed, and an Al-Li electrode or the like is used. A display device with high reliability can be realized by effectively suppressing Li diffusion from the substrate. The reason for this is that the present inventors have formed a thin silicon nitride film on the surface of the single crystal silicon target, and the silicon nitride film is laminated on the substrate, so that silicon clusters are mixed in the film. It is speculated that it may become dense as a result of being difficult to do.
[0058]
Further, since the film is formed by sputtering at a low temperature of about 200 ° C. from room temperature, it is more advantageous than the plasma CVD method in that it can be formed on the resin film as in the case of using the barrier film of the present invention. .
[0059]
[Embodiment 2]
The present embodiment is an example in which the current source Cs is formed with a configuration different from that of the first embodiment, and a third metal layer is used as an electrode. Note that other configurations are the same as those of the first embodiment, and therefore the description of the first embodiment may be referred to. Therefore, the present embodiment will be described by paying attention only to differences from the first embodiment.
[0060]
3 (A) and 3 (B) are drawings corresponding to FIGS. 2 (A) and 2 (B) in the first embodiment, and portions denoted by the same reference numerals as those in the first embodiment are the same as those in the first embodiment. 1 has the same configuration as described in 1. In the case of the present embodiment, the structure of the current source Cs 26 is characterized, and in FIG. 2A, the planarization layer 121 is removed. That is, the first capacitor 109 formed by the first electrode 109, the dielectric (gate insulating film 113) and the second electrode 117, the second electrode 117, the dielectric (first passivation film 118) and the third electrode 120. The third capacitor element, which is the third capacitor element formed by the second capacitor element and the third electrode 120, the barrier film 122, and the fourth electrode 301, is stacked.
[0061]
In this embodiment mode, the first electrode 109 and the third electrode 120 are set to a fixed potential in order to form three capacitors. Of course, the same applies when the second electrode 117 and the fourth electrode 301 are set to a fixed potential. That is, the capacitance can be formed to the maximum by alternately stacking electrodes having a fixed potential. However, which electrode is set to a fixed potential can be freely set in circuit design, and need not be limited to the above-described configuration.
[0062]
When the above configuration is adopted, the three capacitive elements can be formed with a small area, and thus a large capacity can be secured while minimizing the loss of the aperture ratio. Note that the structure of the capacitor element described in this embodiment is not limited to the application to the current source Cs, and can be used as a capacitor element (Cs) required in the video Cs19 and other pixels. .
[0063]
[Embodiment 3]
The present embodiment is an example in which the current source Cs is formed with a configuration different from that of the first embodiment, and a third metal layer is used as an electrode. Note that other configurations are the same as those of the first embodiment, and therefore the description of the first embodiment may be referred to. Therefore, the present embodiment will be described by paying attention only to differences from the first embodiment.
[0064]
4 (A) and 4 (B) are drawings corresponding to FIGS. 2 (A) and 2 (B) in the first embodiment, and the portions denoted by the same reference numerals as those in the first embodiment are the same as those in the first embodiment. 1 has the same configuration as described in 1. In the case of the present embodiment, the structure of the current source Cs 28 is characterized. In FIG. 2A, the planarization layer 121 and the third electrode 120 are removed. That is, the first capacitive element including the first electrode 109, the gate insulating film 113, and the second electrode 117, the second electrode 117, the dielectric (a stacked body of the first passivation film 118 and the barrier film 122), and the fourth In this configuration, two capacitive elements of the second capacitive element constituted by the electrodes 401 are stacked. In this case, since the dielectrics are laminated, there is an advantage that the probability of occurrence of defects due to pinholes or the like is greatly reduced.
[0065]
In this embodiment mode, the first electrode 109 and the fourth electrode 401 are set at a fixed potential in order to form two capacitors. However, which electrode is set to a fixed potential can be freely set in circuit design, and need not be limited to the above-described configuration.
[0066]
When the above configuration is adopted, the two capacitor elements can be formed with a small area, so that a large capacity can be secured while suppressing a loss in aperture ratio. Note that the structure of the capacitor element described in this embodiment is not limited to the application to the current source Cs, and can be used as a capacitor element (Cs) required in the video Cs19 and other pixels. .
[0067]
[Embodiment 4]
The present embodiment is an example in which the current source Cs is formed with a configuration different from that of the first embodiment, and a third metal layer is used as an electrode. Note that other configurations are the same as those of the first embodiment, and therefore the description of the first embodiment may be referred to. Therefore, the present embodiment will be described by paying attention only to differences from the first embodiment.
[0068]
5 (A) and 5 (B) are drawings corresponding to FIGS. 2 (A) and 2 (B) in the first embodiment, and the portions denoted by the same reference numerals as those in the first embodiment are the embodiments. 1 has the same configuration as described in 1. In the case of this embodiment, the structure of the current source Cs30 is characterized. In FIG. 5A, the planarization layer 121, the third electrode 120, and the second electrode 117 are removed. In other words, the capacitor element includes the first electrode 109, the dielectric (a stacked body of the gate insulating film 113, the first passivation film 118, and the barrier film 122) and the fourth electrode 501. In the present embodiment, the first electrode 109 is set to a fixed potential. However, which electrode is set to a fixed potential can be freely set in circuit design, and need not be limited to the above-described configuration. Further, in this case, since the dielectric is formed by stacking three layers of insulating films, there is an advantage that the probability of occurrence of defects due to pinholes can be minimized.
[0069]
In this embodiment mode, since the second electrode 117 does not exist, an impurity imparting conductivity is added to the first electrode 109, that is, the semiconductor. 1 to 4, the first electrode 109 cannot function as an electrode unless a constant voltage is applied to the second electrode 117. However, with the configuration of the present embodiment, the fourth electrode Even if a constant voltage is not applied to the electrode 501, it can always function as a capacitor. This effect contributes to a reduction in power consumption of the display device.
[0070]
The above configuration is not limited to the application to the current source Cs, but can also be used as a capacitance element (Cs) required in the video Cs19 and other pixels.
[0071]
[Embodiment 5]
The present embodiment is an example in which the current source Cs is formed with a configuration different from that of the first embodiment, and a third metal layer is used as an electrode. Note that other configurations are the same as those of the first embodiment, and therefore the description of the first embodiment may be referred to. Therefore, the present embodiment will be described by paying attention only to differences from the first embodiment.
[0072]
6 (A) and 6 (B) are drawings corresponding to FIGS. 2 (A) and 2 (B) in the first embodiment, and portions denoted by the same reference numerals as those in the first embodiment are the same as those in the first embodiment. 1 has the same configuration as described in 1. In the case of the present embodiment, the configuration of the current source Cs32 is characteristic, and the second electrode 117 is removed in FIG. That is, since the first electrode 109 is made into an electrode by adding an impurity, it can always function as an electrode without applying a constant voltage to the third electrode 120, which contributes to a reduction in power consumption.
[0073]
Further, the configuration of the current source Cs 32 includes a first electrode 109, a dielectric (a stacked body of a gate insulating film 113 and a first passivation film 118), and a third electrode 120. In this case, since the dielectrics are laminated, there is an advantage that the probability of occurrence of defects due to pinholes or the like is greatly reduced. Further, in the present embodiment, the first electrode 109 is set to a fixed potential, but which electrode can be set to a fixed potential can be freely set in the circuit design, and need not be limited to the above-described configuration.
[0074]
The above configuration is not limited to the application to the current source Cs, but can also be used as a capacitance element (Cs) required in the video Cs19 and other pixels. Moreover, it is possible to implement in combination with any structure of Embodiment 1-4.
[0075]
[Embodiment 6]
The present embodiment is an example in which the current source Cs is formed with a configuration different from that of the first embodiment, and a third metal layer is used as an electrode. Note that other configurations are the same as those of the first embodiment, and therefore the description of the first embodiment may be referred to. Therefore, the present embodiment will be described by paying attention only to differences from the first embodiment.
[0076]
FIGS. 7A and 7B are drawings corresponding to FIGS. 2A and 2B in the first embodiment, and the portions denoted by the same reference numerals as those in the first embodiment are the same as those in the first embodiment. 1 has the same configuration as described in 1. In the case of the present embodiment, the configuration of the current source Cs 34 is characteristic, and the first electrode 109 is removed in FIG.
[0077]
The current source Cs 34 includes a second electrode 117, a dielectric (first passivation film 118), and a third electrode 120. In the present embodiment, the third electrode 120 is set to a fixed potential. However, which electrode is set to a fixed potential can be freely set in circuit design, and need not be limited to the above-described configuration.
[0078]
The above configuration is not limited to the application to the current source Cs, but can also be used as a capacitance element (Cs) required in the video Cs19 and other pixels. Moreover, it is possible to implement in combination with any structure of Embodiment 1-4.
[0079]
[Embodiment 7]
In this embodiment, an example in which the pixel structure is different from that in Embodiment Mode 1 will be described with reference to FIGS. The feature of the pixel configuration shown in FIG. 8A is that the selection gate line 12, the erase gate line 15, and the current gate line 16 are all formed of the same metal layer (first metal layer), and the signal line 11, The current line 13 and the power supply line 14 are both formed of the same metal layer (second metal layer), and the first metal layer and the second metal layer intersect each other. . In this case, only the relatively thin first passivation film 118 of about 0.1 to 0.5 μm is present in the meantime, and a parasitic capacitance is formed. However, the number of contacts is reduced as compared with the configuration of the first embodiment. There is an advantage that the aperture ratio is improved.
[0080]
Note that in the pixel structure of this embodiment mode, any of the capacitor elements shown in Embodiment Modes 1 to 6 may be formed in the pixel.
[0081]
[Embodiment 8]
Each of the thin film transistors described in Embodiments 1 to 7 has a top gate structure (specifically, a planar structure), but in each embodiment, a bottom gate structure (specifically, an inverted staggered structure) is used. It is also possible. In that case, the positions of the semiconductor layer such as the active layer and the first metal layer such as the gate electrode are only reversed. Needless to say, the present invention is not limited to a thin film transistor, and may be applied to a MOS transistor formed using a silicon well.
[0082]
[Embodiment 9]
Each of the display devices described in Embodiments 1 to 8 exemplifies an electroluminescence display device, but the device configuration itself is common when applied to a liquid crystal display device, and the structure of the pixel electrode is the same. If changed, the present invention may be applied to a liquid crystal display device, a field emission display device, or other display devices having a plurality of pixels.
[0083]
[Embodiment 10]
In this embodiment mode, an entire structure of an electroluminescent display device to which the present invention can be applied will be described with reference to FIGS. FIG. 9 is a top view of an electroluminescent display device formed by sealing an element substrate on which a thin film transistor is formed with a sealing material, and FIG. 9B is a cross-sectional view taken along line BB in FIG. 9A. FIG. 9C is a cross-sectional view taken along the line AA ′ of FIG. 9A.
[0084]
On the substrate 201, a pixel portion (display portion) 202, a data line driver circuit 203, gate line driver circuits 204a and 204b, and a protection circuit 205 provided so as to surround the pixel portion 202 are arranged so as to surround them. A sealing material 206 is provided. For the structure of the pixel portion 202, Embodiment Modes 1 to 8 and the description thereof may be referred to. As the sealing material 206, a glass material, a metal material (typically, a stainless steel material), a ceramic material, or a plastic material (including a plastic film) can be used. As shown in Embodiments 1 to 8, the insulating material is used. It is also possible to seal with only a film.
[0085]
The sealant 206 may be provided so as to overlap with part of the data line driver circuit 203, the gate line driver circuits 204a and 204b, and the protection circuit 205. A sealing material 207 is provided using the sealing material 206, and a sealed space 208 is formed by the substrate 201, the sealing material 206, and the sealing material 207. The sealing material 207 is provided with a moisture absorbent (barium oxide, calcium oxide, or the like) 209 in the recess in advance, and adsorbs moisture, oxygen, etc. in the sealed space 208 to maintain a clean atmosphere. Plays a role in suppressing deterioration. The concave portion is covered with a fine mesh-shaped cover material 210, and the cover material 210 allows air and moisture to pass therethrough and does not allow the moisture absorbent 209 to pass. Note that the sealed space 208 may be filled with a rare gas such as nitrogen or argon, and may be filled with a resin or a liquid if inactive.
[0086]
An input terminal portion 211 for transmitting signals to the data line driving circuit 203 and the gate line driving circuits 204 a and 204 b is provided on the substrate 201, and an FPC (flexible printed circuit) 212 is connected to the input terminal portion 211. A data signal such as a video signal is transmitted via the. The cross section of the input terminal portion 211 is as shown in FIG. 9B. An input wiring 213 formed of a wiring formed simultaneously with a gate wiring or a data wiring and a wiring 215 provided on the FPC 212 side are connected to a conductor 216. Electrical connection is made using a dispersed resin 217. Note that the conductor 216 may be a spherical polymer compound that is plated with gold or silver.
[0087]
Further, in FIG. 9C, an enlarged view of a region 218 surrounded by a dotted line is shown in FIG. The protective circuit 205 may be configured by combining the thin film transistor 219 and the capacitor 220, and the capacitor having the structure described in any of Embodiments 1 to 7 may be used as the capacitor 220.
[0088]
In this embodiment mode, the protection circuit 205 is provided between the input terminal portion 211 and the data line driving circuit 203. When static electricity such as a sudden pulse signal enters between the two, the pulse signal is externally transmitted. Play the role of escape. At that time, a high voltage signal that enters instantaneously is blunted by the capacitor 220, and other high voltages can be released to the outside by a circuit configured using a thin film transistor or a thin film diode. Needless to say, the protection circuit may be provided in another place, for example, between the pixel portion 202 and the data line driver circuit 203 or between the pixel portion 202 and the gate line driver circuits 204a and 204b.
[0089]
As described above, in the present embodiment, an example in which a capacitor used in a protection circuit such as a countermeasure against static electricity provided in an input terminal portion is simultaneously formed in implementing the present invention is shown. It can be implemented in combination with any of the nine configurations.
[0090]
[Embodiment 11]
As an electronic device using the display device of the present invention as a display unit, a video camera, a digital camera, a goggle type display (head mounted display), a navigation system, an audio playback device (car audio, audio component, etc.), a notebook type personal computer, Reproducing a recording medium such as a game machine, a portable information terminal (mobile computer, cellular phone, portable game machine or electronic book), an image reproducing apparatus (specifically, a digital versatile disc (DVD)) provided with a recording medium, And a device provided with a display capable of displaying the image). Specific examples of these electronic devices are shown in FIGS.
[0091]
FIG. 10A illustrates a television which includes a housing 2001, a support base 2002, a display portion 2003, a speaker portion 2004, a video input terminal 2005, and the like. The present invention can be applied to the display portion 2003. Note that all information display televisions such as a personal computer, a TV broadcast reception, and an advertisement display are included.
[0092]
FIG. 10B shows a digital camera, which includes a main body 2101, a display portion 2102, an image receiving portion 2103, operation keys 2104, an external connection port 2105, a shutter 2106, and the like. The present invention can be applied to the display portion 2102.
[0093]
FIG. 10C illustrates a laptop personal computer, which includes a main body 2201, a housing 2202, a display portion 2203, a keyboard 2204, an external connection port 2205, a pointing mouse 2206, and the like. The present invention can be applied to the display portion 2203.
[0094]
FIG. 10D illustrates a mobile computer, which includes a main body 2301, a display portion 2302, a switch 2303, operation keys 2304, an infrared port 2305, and the like. The present invention can be applied to the display portion 2302.
[0095]
FIG. 10E illustrates a portable image reproducing device (specifically, a DVD reproducing device) provided with a recording medium, which includes a main body 2401, a housing 2402, a display portion A2403, a display portion B2404, and a recording medium (DVD or the like). A reading unit 2405, operation keys 2406, a speaker unit 2407, and the like are included. Although the display portion A 2403 mainly displays image information and the display portion B 2404 mainly displays character information, the present invention can be applied to the display portions A, B 2403, and 2404. Note that an image reproducing device provided with a recording medium includes a home game machine and the like.
[0096]
FIG. 10F illustrates a goggle type display (head mounted display), which includes a main body 2501, a display portion 2502, and an arm portion 2503. The present invention can be applied to the display portion 2502.
[0097]
FIG. 10G illustrates a video camera, which includes a main body 2601, a display portion 2602, a housing 2603, an external connection port 2604, a remote control receiving portion 2605, an image receiving portion 2606, a battery 2607, an audio input portion 2608, operation keys 2609, and an eyepiece. Part 2610 and the like. The present invention can be applied to the display portion 2602.
[0098]
FIG. 10H illustrates a mobile phone, which includes a main body 2701, a housing 2702, a display portion 2703, an audio input portion 2704, an audio output portion 2705, operation keys 2706, an external connection port 2707, an antenna 2708, and the like. The present invention can be applied to the display portion 2703. Note that the display portion 2703 can suppress current consumption of the mobile phone by displaying white characters on a black background.
[0099]
As described above, the display device obtained by implementing the present invention may be used as a display unit of any electronic device. Note that a display device having any of the structures described in Embodiments 1 to 9 may be used for the electronic device of this embodiment.
[0100]
【The invention's effect】
According to the present invention, first, since the planarization film is sealed by the first passivation film and the barrier film, there is no problem of deterioration with time due to degassing from the planarization film, and a highly reliable display device is obtained. be able to. Second, a large capacitance value can be ensured with a small area by stacking capacitive elements. Third, by using the pixel electrode having a special structure shown in FIG. 2B as the anode of the light emitting element, the light extraction efficiency can be improved, and a bright and bright electroluminescence display device can be obtained. By reducing power consumption, the progress of deterioration of the light-emitting element can be suppressed and reliability can be increased.
[0101]
As described above, the display device of the present invention secures a sufficient capacitance value (capacitance value for charge retention) for each pixel by using the multilayer wiring, and the light-emitting element. By adopting a structure for suppressing deterioration as much as possible, a display device with high reliability and high luminance is obtained.
[Brief description of the drawings]
1A and 1B are a top view and a circuit diagram illustrating a pixel structure of a display device.
FIG. 2 is a cross-sectional view illustrating a device configuration of a display device.
FIG. 3 is a cross-sectional view illustrating a device configuration of a display device.
FIG. 4 is a cross-sectional view illustrating a device configuration of a display device.
FIG. 5 is a cross-sectional view illustrating a device configuration of a display device.
FIG. 6 is a cross-sectional view illustrating a device configuration of a display device.
FIG. 7 is a cross-sectional view illustrating a device configuration of a display device.
FIGS. 8A and 8B are a top view and a circuit diagram illustrating a pixel structure of a display device. FIGS.
9A and 9B are a top view and a cross-sectional view illustrating the appearance of a display device.
FIG 10 illustrates an example of an electronic device.
FIG. 11 is a diagram showing an impurity distribution in a silicon nitride film.
FIG. 12 is a diagram showing a FT-IR measurement result of a silicon nitride film.
FIG. 13 is a graph showing the transmittance of a silicon nitride film.
FIG. 14 shows CV characteristics of a silicon nitride film.
FIG. 15 is a graph showing CV characteristics of a silicon nitride film.
FIG. 16 is a cross-sectional view of a MOS structure using a silicon nitride film.
FIG 17 is a view showing a sputtering apparatus used for forming a silicon nitride film.

Claims (8)

A semiconductor layer;
An insulating film provided on the semiconductor layer;
A first metal layer provided on the insulating film;
A passivation film provided on the first metal layer;
A second metal layer provided on the passivation film;
A planarizing film made of an organic resin film or an SOG film provided on the second metal layer;
A barrier film provided on the planarizing film;
A third metal layer provided on the barrier film,
A transistor formed using the semiconductor layer, the insulating film, and the first metal layer;
A first capacitor element formed using the semiconductor layer, the insulating film, and the first metal layer;
A second capacitive element formed using the first metal layer, the passivation film and the second metal layer;
An electrode formed using the third metal layer,
Wherein are side of the first opening provided in the flattening film is covered with the barrier film, and, at the bottom of the first opening, and the barrier film and the passivation film is in contact with each other,
The bottom of the first opening has a second opening provided in the insulating film, the passivation film and the barrier film;
The display device, wherein the electrode is electrically connected to the semiconductor layer of the transistor through the first opening and the second opening. A semiconductor layer;
An insulating film provided on the semiconductor layer;
A first metal layer provided on the insulating film;
A passivation film provided on the first metal layer;
A second metal layer provided on the passivation film;
A planarizing film made of an organic resin film or an SOG film provided on the second metal layer;
A barrier film provided on the planarizing film;
A third metal layer provided on the barrier film,
A transistor formed using the semiconductor layer, the insulating film, and the first metal layer;
A first capacitor element formed using the semiconductor layer, the insulating film, and the first metal layer;
A second capacitive element formed using the first metal layer, the passivation film and the second metal layer;
A third capacitive element formed using the second metal layer, the barrier film, and the third metal layer;
An electrode formed using the third metal layer,
Wherein are side of the first opening provided in the flattening film is covered with the barrier film, and, at the bottom of the first opening, and the barrier film and the passivation film is in contact with each other,
The bottom of the first opening has a second opening provided in the insulating film, the passivation film and the barrier film;
The display device, wherein the electrode is electrically connected to the semiconductor layer of the transistor through the first opening and the second opening.   The display device according to claim 1, further comprising a light-emitting element using the electrode as a pixel electrode.   4. The display device according to claim 1, wherein the third metal layer is formed by stacking a titanium film, a titanium nitride film, and an aluminum film in order from the bottom.   5. The light-emitting element according to claim 1, wherein the electrode formed using the third metal layer is used as a pixel electrode, and the third metal layer is titanium in order from the bottom. A display device comprising: a film, a titanium nitride film, and an aluminum film, wherein the aluminum film is selectively removed in a light emitting region of the light emitting element. In any one of claims 1 to 5, a display device which comprises using the silicon nitride film as the barrier film. In any one of claims 1 to 6, a display device which is characterized by using the oxynitride as a passivation film silicon film or a silicon nitride film. It claims 1 to an electronic apparatus, characterized by comprising a display unit to display device according to any one of claims 7.

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