JP4493405B2 - Variable capacitor, circuit module and communication device - Google Patents

Description

  The present invention relates to a variable capacitor, a circuit module, and a communication device that can operate satisfactorily with low dielectric loss even in a high-frequency region. The present invention relates to a variable capacitor that can suppress distortion, has excellent power resistance, is not affected by the polarity of an applied voltage, and is easy to handle, and a circuit module and a communication device using the variable capacitor.

A paraelectric strontium titanate (SrTiO ₃ ) thin film and a ferroelectric barium strontium titanate ((Ba, Sr) TiO ₃ ) thin film are conventionally used as dielectric thin film capacitors for ICs. As a dielectric material suitable for reducing the area of dielectric thin film capacitors for ICs, it has a higher dielectric constant than silicon (SiO ₂ ) thin films, silicon nitride (Si ₃ N ₄ ) thin films, and thallium oxide (Ta ₂ O ₅ ) thin films. Expected.

  A thin film capacitor using a ferroelectric oxide thin film having a perovskite structure such as strontium titanate or barium strontium titanate as a dielectric layer has been proposed (see, for example, Patent Document 1).

  A thin film capacitor 200 proposed in Patent Document 1 includes a first electrode layer 202, a thin film dielectric layer 203, and a second electrode layer 204 on a support substrate 201, as shown in a sectional view in FIG. Sequentially deposited and formed. Specifically, a conductor layer to be the first electrode layer 202 is deposited on substantially the entire surface of the support substrate 201, and then patterned into an electrode shape to form the first electrode layer 202 having a predetermined shape. Next, a thin film dielectric layer 203 is formed on the first electrode layer 202. The thin film dielectric layer 203 is formed by placing a mask at a predetermined position and forming it by a thin film forming method, or forming it by a spin coating method and then patterning it into a predetermined shape. Note that the thin film dielectric layer 203 is heat-cured as necessary. Next, a conductor layer to be the second electrode layer 204 is formed on substantially the entire surface of the thin film dielectric layer 203, and then the second electrode layer 204 having a predetermined shape is formed by patterning the electrode shape of the second electrode 204. Thus, the thin film capacitor 200 was formed. Here, in the thin film dielectric layer 203, a facing region actually sandwiched between the first electrode layer 202 and the second electrode layer 204 is a capacitance generation region.

When such a thin film capacitor 200 is actually used, a predetermined DC bias voltage (bias signal) is applied to the thin film dielectric layer 203 to control the dielectric constant of the thin film dielectric layer 203 to a desired value. As a result, the capacitance characteristic can be controlled, and as a result, it functions as a variable capacitor. Here, the first electrode layer 202 and the second electrode layer 204 have two roles of an electrode that generates a predetermined capacitance component controlled by a bias signal and an electrode that supplies the bias signal to the thin film dielectric layer 203. I played.
Japanese Patent Laid-Open No. 11-260667

  However, in this thin film capacitor 200, for example, as shown in the equivalent circuit diagrams in FIGS. 12A and 12B, the bias signal is an external circuit (bias supply circuit) formed on the wiring board on which the thin film capacitor 200 is mounted. ) G was supplied.

  Here, in FIG. 12A, a choke coil 205 as an inductance component is arranged between a connection point A between the thin film capacitor 200 and the bias supply circuit G and the bias terminal V.

  In FIG. 12B, a strip line 206 having a λ / 4 line length with respect to the wavelength λ of the high frequency signal operated by the thin film capacitor 200 is formed in the bias supply circuit G. One end of the strip line 206 on the bias terminal V side is grounded, and a DC limiting capacitance element 208 is formed between one end of the strip line 206 on the bias terminal V side and the ground portion.

  When such a thin film capacitor 200 is used, in addition to the thin film capacitor 200, a bias supply circuit G corresponding to the structure and characteristics of the thin film capacitor 200 must be prepared on the wiring board. For this reason, it is necessary to design the bias supply circuit G corresponding to the thin film capacitor 200 mounted on the wiring board, and there is a problem that adjustment is very complicated. Furthermore, since the thin film capacitor 200 and the bias supply circuit G are configured separately, there is a problem that the size of the thin film capacitor 200 and the bias supply circuit G increase as a whole.

  In the conventional thin film capacitor 200, since the high frequency signal terminal and the bias terminal V are used in common, the high frequency component (signal component of the high frequency signal) and the direct current are used by using the choke coil 205 or the like in the external circuit. It was necessary to separate the component (bias signal).

  Further, in order to change the capacitance greatly in the thin film capacitor 200, it is necessary to reduce the thickness of the thin film dielectric layer 203. However, since the capacitance of the capacitor is proportional to the area of the dielectric and inversely proportional to the thickness, if the thickness of the thin film dielectric layer 203 is reduced, the first electrode layer, which is a capacitance generating portion, can be realized in order to realize a low capacitance value. There is a problem in that the electrode facing areas of 202 and the second electrode layer 204 have to be reduced, making it difficult to manufacture.

  In addition, when the thin film capacitor 200 as described above is used as a high frequency electronic component, a DC bias voltage for changing the capacitance and a high frequency signal voltage (high frequency voltage) are simultaneously applied to the thin film capacitor 200. become. However, when the high-frequency voltage is high, the capacitance of the thin film capacitor 200 is also changed by the high-frequency voltage, so that waveform distortion, intermodulation distortion, and the like occur in the high-frequency electronic component. In order to reduce the waveform distortion, intermodulation distortion, etc., it is necessary to reduce the capacitance change due to the high-frequency voltage by reducing the high-frequency electric field strength. For this purpose, it is effective to increase the thickness of the dielectric layer 203. However, when the thickness of the dielectric layer 200 is increased, the DC electric field strength is also reduced, so that there is a problem that the rate of change in capacitance due to the DC bias voltage is also reduced.

  In addition, since a current easily flows through the capacitor in the high frequency region, there is a problem in terms of power resistance that the capacitor generates heat and breaks due to the loss resistance of the capacitor when the capacitor is used in the high frequency region. It is effective to increase the thickness of the dielectric layer 203 and reduce the amount of heat generated per unit volume in order to cope with such a problem of withstand power. However, as described above, the thickness of the thin film dielectric layer 203 is reduced. If the thickness is increased, the DC electric field strength is also reduced, and the capacity change rate due to the DC bias voltage is also lowered.

  In the thin film capacitor 200, the state of the interface between the thin film dielectric layer 203 and the first electrode layer 202 is generally different from the state of the interface between the thin film dielectric layer 203 and the second electrode layer 204. When a bias voltage is applied, the leakage current characteristics may differ depending on the polarity. This phenomenon is well known as a Schottky emission current. That is, when the first electrode layer 202 and the second electrode layer 204 are formed of different materials, the work function of the first electrode layer 202 with respect to the thin film dielectric layer 203 and the thin film dielectric of the second electrode layer 204 Since the work function for the body layer 203 is different, the magnitude of the leakage current differs depending on whether the leakage current is generated by emitting electrons from the first electrode layer 202 or the second electrode layer 204. That is, the leak current varies depending on the polarity of the DC bias voltage. Even if the first electrode layer 202 and the second electrode layer 204 are made of the same material, the state of the interface between the first electrode layer 202 and the thin film dielectric layer 203 formed thereon and the thin film dielectric layer The work state is different because the state of the interface between the second electrode layer 204 and the second electrode layer 204 formed on the surface is microscopically different, and also in this case, the leakage current differs depending on the polarity of the DC bias voltage. Become. For this reason, the thin film capacitor 200 has a problem that attention must be paid to the polarity of the DC bias voltage not only at the time of design but also at the time of mounting.

  The present invention has been devised in view of the above-described problems in the prior art, and its object is to eliminate the need for forming an independent external bias supply circuit for the variable capacitor and to make the variable easy to handle. It is to provide a capacitor.

  Another object of the present invention is to provide a variable capacitor that can be manufactured with high productivity even when the required characteristic for the variable capacitor is low.

  Still another object of the present invention is to provide a variable capacitor in which a change in capacitance due to a high-frequency signal is suppressed, intermodulation distortion is small, power resistance is excellent, and a capacitance can be changed greatly by a DC bias. .

  Still another object of the present invention is to provide a variable capacitor that can be easily mounted without considering the polarity of the DC bias voltage by suppressing the difference in capacitance characteristics of the variable capacitor due to the difference in polarity of the DC bias voltage. It is in.

  Still another object of the present invention is to provide a circuit module and a communication device using the variable capacitor of the present invention.

  The first variable capacitor according to the present invention includes a first electrode layer and a second electrode layer disposed above and below on a support substrate, and a dielectric whose dielectric constant varies depending on an applied voltage sandwiched between these two electrode layers. N variable capacitors composed of body layers (where N = 2n and n is a natural number) are variable capacitors connected in series in the left-right direction, and one of the variable capacitors adjacent to each other. The first electrode layer and the second electrode layer of the other variable capacitance element are electrically connected, and 2i−1 (provided i) from the variable capacitance element located at one end in the left-right direction. Is a natural number equal to or less than n) at least of a resistance component and an inductor component electrically connected to the first electrode layer of the variable capacitance element and the second electrode layer of the variable capacitance element located at the other end, respectively. Including one At least a resistance component and an inductor component electrically connected to the first bias line and the first electrode layer of the 2i-th variable capacitance element from the variable capacitance element located at the one end in the left-right direction, respectively. A second bias line including one is formed.

  The second variable capacitor of the present invention is characterized in that, in the above configuration, the variable capacitance elements positioned at the one end and the other end are respectively connected to a signal terminal via a direct current limiting capacitance element. To do.

  The third variable capacitor of the present invention is characterized in that, in the above configuration, the direct current limiting capacitive element is formed immediately below the signal terminal.

  The fourth variable capacitor of the present invention is characterized in that, in the above configuration, the dielectric layer is made of barium strontium titanate.

  The circuit module of the present invention is characterized in that the first to fourth variable capacitors of the present invention are used as capacitors constituting a resonance circuit.

  The communication device of the present invention is characterized in that the circuit module of the present invention is used as filter means.

  According to the first variable capacitor of the present invention, the dielectric constant changes depending on the applied voltage between the first electrode layer and the second electrode layer disposed above and below the support substrate and the two electrode layers. N variable capacitance elements (where N = 2n and N is a natural number), which are composed of dielectric layers, are variable capacitors connected in series in the left-right direction, and one of the variable capacitance elements adjacent to each other The first electrode layer and the second electrode layer of the other variable capacitance element are electrically connected, and 2i−1 from the variable capacitance element located at one end in the left-right direction (where i is n or less) A first bias line including at least one of a resistance component and an inductor component electrically connected to the first electrode layer of the (natural number) th variable capacitance element and the second electrode layer of the variable capacitance element located at the other end; , Left and right A second bias line including at least one of a resistance component and an inductor component electrically connected to the first electrode layer of the 2i-th variable capacitance element from the variable capacitance element located at the end is formed; Therefore, an independent bias supply circuit mounted on an external wiring board like a conventional variable capacitor becomes unnecessary, and the circuit board on which the variable capacitor is mounted can be downsized and handled easily. .

  Further, according to the first variable capacitor of the present invention, since the N variable capacitance elements are connected in series, the first and second capacitances are compared with the case where the capacitance is formed at one place by one variable capacitance element. Since the electrode layer area can be increased, even if the required characteristics for variable capacitors are low, manufacturing is simplified, processing accuracy is improved, and the desired capacitance value is achieved with good accuracy and reproducibility. Can increase productivity.

  In the first variable capacitor of the present invention, the first electrode layer of one of the variable capacitance elements adjacent to each other and the second electrode layer of the other variable capacitance element are electrically connected to each other, and The second electrode layer of the variable capacitance element located at the first electrode layer and the second electrode layer of the variable capacitance element located at the other end are electrically connected to the 2i−1 (where i is a natural number equal to or less than n) variable capacitance elements located at one end, respectively. And a second bias line electrically connected to the first electrode layer of the 2i-th variable capacitance element from the variable capacitance element located at one end in the left-right direction, respectively. Therefore, a DC bias voltage (bias signal) as an applied voltage supplied from the first bias line or the second bias line can be varied via the first bias line or the second bias line. It is applied solely to the amount element, by then passing to a second bias line or first bias line through the ground side, each of the variable capacitance element is connected in parallel to the direct current. For this reason, a desired DC bias voltage can be applied to each variable capacitance element, whereby the capacity change rate of each variable capacitance element due to the DC bias voltage can be maximized, and the capacitance can be increased. It can be changed.

  In the first variable capacitor of the present invention, since the first and second bias lines include at least one of a resistance component and an inductor component, the impedance becomes sufficiently high for a high-frequency signal. Capacitance elements are connected in series in terms of high frequency. For this reason, since the high-frequency voltage applied to the variable capacitors is divided into each variable capacitance element, the high-frequency voltage applied to each variable capacitance element is divided and reduced. Capacitance fluctuations with respect to signals can be suppressed to a small level, and waveform distortion, intermodulation distortion, and the like can be effectively suppressed. Furthermore, since a plurality of variable capacitance elements are connected in series in terms of high frequency, the amount of heat generated per unit area due to the loss resistance of the variable capacitor of the present invention can be reduced by dividing the high frequency voltage, and withstand power Can be improved. Thus, according to the variable capacitor of the present invention, since a plurality of variable capacitance elements are connected in series in terms of high frequency, capacitance change due to high frequency signals is suppressed, intermodulation distortion is small, and power resistance is excellent. It will be.

  In the first variable capacitor of the present invention, the first electrode layer of one of the variable capacitance elements adjacent to each other and the second electrode layer of the other variable capacitance element are electrically connected to each other, and The second electrode layer of the variable capacitance element located at the first electrode layer and the second electrode layer of the variable capacitance element located at the other end are electrically connected to the 2i−1 (where i is a natural number equal to or less than n) variable capacitance elements located at one end, respectively. And a second bias line electrically connected to the first electrode layer of the 2i-th variable capacitance element from the variable capacitance element located at one end in the left-right direction, respectively. Yes. For this reason, when a DC bias voltage is applied via the first or second bias line, the electrode layers that emit electrons to the dielectric layer are alternately arranged by the adjacent variable capacitance elements, and the variable capacitance is arranged. Since the number of elements is an even number, the difference in material between the first electrode layer and the second electrode layer, the interface between the dielectric layer and the first electrode layer, and the interface between the dielectric layer and the second electrode layer Even if the work function is different due to the difference in the interface state, the difference in leakage current characteristics in each variable capacitance element is canceled out in the entire variable capacitor. As a result, even if the polarity of the DC bias voltage is changed, the variable capacitor It is possible to suppress the change in the capacitance characteristics. Further, according to such a variable capacitor, it is not necessary to consider the polarity of the DC bias voltage, and it can be easily mounted.

  According to the second variable capacitor of the present invention, in the first variable capacitor of the present invention, the variable capacitance elements located at one end and the other end are connected to the signal terminal via the direct current limiting capacitance element, respectively. Therefore, it is not necessary to form an independent DC limiting capacitor element on the external wiring board on which the variable capacitor is mounted unlike the conventional variable capacitor, so that the circuit board on which the variable capacitor is mounted can be reduced in size. At the same time, handling becomes easy.

  According to the third variable capacitor of the present invention, in the second variable capacitor of the present invention described above, when the DC limiting capacitance element is formed immediately below the signal terminal, the DC limiting is performed in the planar shape of the variable capacitor. Since the area for forming the capacitive element is not required, the variable capacitor can be miniaturized, and the wiring board on which the variable capacitor is mounted can be further miniaturized, and the handling becomes easy.

  According to the fourth variable capacitor of the present invention, in the first to third variable capacitors of the present invention, when the dielectric layer is made of barium strontium titanate, the dielectric loss is low and the capacitance change rate is low. It will be a big thing.

  Further, according to the circuit module of the present invention, since the first to fourth variable capacitors of the present invention are used as the capacitors constituting the resonance circuit, the capacitance change rate of the capacitor is large and a desired capacitance is accurately obtained. By being able to obtain well, a desired resonance frequency can be obtained with high accuracy over a wide frequency range. Further, since the capacitor constituting the resonance circuit has excellent power resistance and does not depend on the polarity of the DC bias voltage, it is highly reliable, can be easily manufactured, and has high productivity.

  In addition, according to the communication device of the present invention, since the circuit module of the present invention is used as the filter means, a desired resonance frequency can be set with high accuracy over a wide frequency range, so that the frequency range usable as the filter means is obtained. And a desired filter function can be obtained with high accuracy.

  Hereinafter, a variable capacitor, a circuit module, and a communication device of the present invention will be described in detail with reference to the drawings.

  1 and 2 show an example of an embodiment of a first variable capacitor according to the present invention, and shows a case where N = 4 (n = 2). FIG. 1 is a plan view showing a see-through state, and FIG. 2 is a cross-sectional view taken along line A-A ′ of FIG. 1.

  1 and 2, 1 is a support substrate, 2 is a first electrode layer, 4 is a dielectric layer, 5 is a second electrode layer, and 31, 32, 33, and 34 are conductors, respectively. 61, 62, 63, 64 and 65 are thin film resistors, 7 is an insulating layer, 8 is the first electrode layer 2 of one of the variable capacitors adjacent to each other, and 8 of the other variable capacitor. A lead electrode layer for electrically connecting the second electrode layer 5, 9 is a solder diffusion preventing layer, 10 is a protective layer, and 111, 112, 113, and 114 are solder terminal portions, respectively. .

  The solder diffusion preventing layer 9 and the solder terminal portions 111 and 112 constitute a signal terminal. Also, the solder diffusion preventing layer 9 and the solder terminal portions 113 and 114 constitute a bias terminal. Hereinafter, a signal terminal composed of the solder diffusion preventing layer 9 and the solder terminal portion 111 is a first signal terminal, a signal terminal composed of the solder diffusion preventing layer 9 and the solder terminal portion 112 is a second signal terminal, A bias terminal composed of the solder diffusion preventing layer 9 and the solder terminal portion 114 is referred to as a first bias terminal, and a bias terminal composed of the solder diffusion preventing layer 9 and the solder terminal portion 113 is referred to as a second bias terminal. In FIG. 1 and FIG. 2, C1, C2, C3, and C4 are a first electrode layer 2 and a second electrode layer 5 disposed above and below, and a dielectric sandwiched between these two electrode layers 2 and 5, respectively. The variable capacitance element which a layer changes in capacity | capacitance by the direct current bias voltage as an applied voltage consisting of the layer 4 is shown.

  Further, in the example shown in FIG. 1, the first bias line including at least one of the resistance component and the inductor component is configured by connecting the thin film resistors 61, 62, and 63 as resistance components to the conductor lines 31 and 32. The second bias line including at least one of the component and the inductor component is configured by connecting the thin film resistors 64 and 65 as resistance components to the conductor lines 33 and 34.

  The support substrate 1 is a ceramic substrate such as alumina, a single crystal substrate such as sapphire, or the like. Then, the first electrode layer 2, the dielectric layer 4, and the second electrode layer 5 are sequentially formed on the entire surface of the support substrate 1 on the support substrate 1. After the formation of these layers, the second electrode layer 5, the dielectric layer 4 and the first electrode layer 2 are sequentially etched into a predetermined shape.

  When forming the first electrode layer 2, the dielectric layer 4, and the second electrode layer 5, between the first electrode layer 2 and the dielectric layer 4 and between the dielectric layer 4 and the second electrode layer 5. In the meantime, it is desirable to minimize the mixing of impurities such as particles, which can cause the characteristics of the variable capacitor to deteriorate. Therefore, it is desirable that the first electrode layer 2, the dielectric layer 4 and the second electrode layer 5 be formed continuously with the same film forming apparatus without opening the film forming chamber to the atmosphere. For this reason, sputtering is suitable as a specific film forming method.

  The first electrode layer 2 needs to have a high melting point so that it can withstand the high temperature because high temperature sputtering is required for forming the dielectric layer 4. Specifically, it is made of a metal material such as Pt or Pd. Further, after the first electrode layer 2 is formed by high-temperature sputtering, the first electrode layer 2 is heated to 700 to 900 ° C., which is the sputtering temperature of the dielectric layer 4, and held for a certain period of time until the sputtering of the dielectric layer 4 is started. It becomes.

  The thickness of the first electrode layer 2 is desirably thick in consideration of the resistance component and continuity of the first electrode layer 2 itself, but is relatively thin in consideration of adhesion to the support substrate 1. It is preferable to determine both. Specifically, it is 0.1 μm to 10 μm. This is because if the thickness of the first electrode layer 2 is less than 0.1 μm, the resistance of the first electrode layer 2 itself increases and the continuity of the first electrode layer 2 may not be ensured. On the other hand, if the thickness is greater than 10 μm, the internal stress increases, and the adhesion to the support substrate 1 may be reduced, or the support substrate 1 may be warped.

  The dielectric layer 4 is preferably a high dielectric constant dielectric layer made of perovskite oxide crystal particles containing at least Ba, Sr, and Ti. Among them, it is preferable to use barium strontium titanate because the dielectric loss is low and the capacity change rate is large. The dielectric layer 4 is formed on the surface (upper surface) of the first electrode layer 2. For example, using a dielectric material from which a perovskite oxide crystal can be obtained as a target, film formation by sputtering is performed until a desired thickness is reached. At this time, by performing high temperature sputtering at a high substrate temperature, for example, 800 ° C., a low loss dielectric layer 4 having a high dielectric constant and a large capacitance change rate can be obtained without performing a heat treatment after sputtering. .

  As the material of the second electrode layer 5, Au having a low resistivity is desirable in order to reduce the resistance of this layer. However, in order to improve the adhesion with the dielectric layer 4, Pt is used or Pt or the like is adhered. It is desirable to use it as a layer. The thickness of the second electrode layer 5 is 0.1 μm to 10 μm. The lower limit of the thickness is set in consideration of the resistance and continuity of the second electrode layer 5 itself, like the first electrode layer 2. Further, the upper limit of the thickness is set in consideration of the adhesion to the dielectric layer 4, but by setting the upper limit of the thickness to be equal to or less than the thickness of the dielectric layer 4, the dielectric layer is etched when the second electrode layer 5 is etched later. Since the influence on the body layer 4 can be reduced and the patterning accuracy by etching is improved, a desired capacitance value can be obtained with high accuracy.

  After the film formation as described above, the second electrode layer 5, the dielectric 4 and the first electrode layer 2 are sequentially etched into a predetermined shape. Etching is performed by wet etching or dry etching after uniformly applying a resist on the entire surface by spin coating or the like, patterning the resist into a predetermined shape by photolithography. Since the capacitance values of the variable capacitance elements C <b> 1 to C <b> 4 are determined by the area of the second electrode layer 5, it is desirable to use dry etching with higher accuracy in the etching of the second electrode layer 5.

  The dry etching can be performed using, for example, an electron cyclotron resonance apparatus (ECR apparatus) and argon plasma as an etchant.

  The dielectric layer 4 may be etched by either wet etching or dry etching.

  The first electrode layer 2 may be etched by either wet etching or dry etching. However, when the thickness of the first electrode layer 2 is large, the second electrode layer 5 Similarly, it is desirable to carry out by dry etching.

  In the etching of the second electrode layer 5, the dielectric layer 4 and the first electrode layer 2 as described above, the lower surface of the dielectric layer 4 is smaller than the upper surface of the first electrode layer 2, and the lower surface of the second electrode layer 5 is Etching is performed to be smaller than the upper surface of the dielectric layer 4. As a result, the dielectric layer 4 does not exist at the outer edge portion of the first electrode layer 2 where the electric field tends to concentrate, so that the leakage current characteristics are improved.

  In this way, variable capacitance elements C1 to C4 can be obtained.

  Here, in order to electrically connect the first signal terminal and the variable capacitance element C1, and the variable capacitance element C4 and the second signal terminal, the first and second signal terminals on the support substrate 1 are connected. It is desirable to form a conductive layer made of a conductive material at a position to be formed. This conductive layer may be formed by forming a new film after forming the variable capacitors C1 to C4. However, when the first electrode layer 2 is patterned, these conductive layers are formed simultaneously. By patterning, the first electrode layer 2 may be formed using the same material and the same process.

  The first bias line is composed of conductor lines 31 and 32 and thin film resistors 61, 62, and 63. The first bias line is connected between the first bias terminal and the first electrode layer 2 of the first variable capacitance element C1. Between the first electrode layer 2 of the third variable capacitance element C3 and the second electrode layer 5 of the fourth variable capacitance element C4, that is, the second electrode layer 5 and the extraction electrode 8 of the fourth variable capacitance element C4. Between the conductive layers formed at the arrangement positions of the second signal terminals that are electrically connected via the first bias terminal and connected to an external circuit via the first bias terminal. .

  The second bias line includes conductor lines 33 and 34 and thin film resistors 64 and 65. The second bias line extends from the second bias terminal to the first electrode layer 2 of the second variable capacitance element C2 and the fourth. The variable capacitance element C4 is provided so as to be connected to the first electrode layer 2 and is connected to an external circuit via a second bias terminal.

  By providing the first and second bias lines having such a configuration, the variable capacitance elements C1 to C4 are connected in parallel via the first and second bias lines.

  The conductor lines 31, 32, 33, and 34 are formed by sequentially forming the first electrode layer 2, the dielectric layer 4, and the second electrode layer 5 in a desired shape and then forming a new film. be able to. In that case, it is desirable to use a lift-off method in order to protect the already formed first electrode layer 2, dielectric layer 4 and second electrode layer 5.

  The conductor lines 31, 32, 33, and 34 are not limited to this, and are formed by patterning so that the conductor lines 31 to 34 are simultaneously formed when the first electrode layer 2 is patterned. Thus, the first electrode layer 2 may be formed using the same material and the same process.

  Here, in order to electrically connect the conductor line 31 and the conductor line 32, and the conductor line 33 and the conductor line 34 at the positions where the first and second bias terminals are formed, the first and second bias terminals on the support substrate 1 are connected. It is desirable to form a conductive layer made of a conductive material at a position where the first and second bias terminals are formed. The conductive layer may be formed by forming a film after forming the variable capacitors C1 to C4. However, when the conductor lines 31 to 34 are formed, the first and second conductor lines 31 to 34 are formed. By forming the shape at the position where the bias terminal is formed in accordance with the shape of the first and second bias terminals, patterning is performed so that these conductive layers are also formed integrally, thereby forming the conductor line 31. May be formed by the same material and the same process as .about.34.

  Incidentally, the first and second bias terminals are arranged at positions symmetrical with respect to the center of the variable capacitor of the present invention, so that the variable capacitor can be arranged upside down in the plan view shown in FIG. Since it can be mounted on, it becomes easy to handle.

  Next, as a material of the thin film resistors 61 to 65 constituting the first and second bias lines, a material having a specific resistance of 1 Ωcm or more is desirable. By using such a high resistance material, the thin film resistors 61 to 65 having a desired resistance can be manufactured in a small shape, which is advantageous for miniaturization and integration. Specific examples of the thin film resistors 61 to 65 include tantalum nitride, TaSiN, and Ta—Si—O. For example, in the case of tantalum nitride, thin film resistors 61 to 65 having a desired composition ratio and resistivity are formed by a reactive sputtering method in which sputtering is performed by adding nitrogen to the atmosphere using Ta (tantalum) as a target. can do.

  By appropriately selecting the sputtering conditions, a film having a specific resistance of 1 Ωcm or more can be produced. Furthermore, after the sputtering is completed, a resist is applied to form a predetermined shape, and then an etching process such as reactive ion etching (RIE) is performed using the resist as a mask, thereby enabling easy patterning.

  The resistance values of the first and second bias lines are set so that the impedances of the first and second bias lines are larger than the impedances of the variable capacitance elements C1 to C4 in the frequency region to be used. Since the resistance values of the conductor lines 31 to 34 are much smaller than the resistance values of the thin film resistors 61 to 65, the resistance values of the first and second bias lines are substantially equal to the resistance values of the thin film resistors 61 to 65. . Accordingly, the resistance values of the thin film resistors 61 to 65 are set to be larger than the impedances of the variable capacitance elements C1 to C4 in the frequency region to be used. For example, when this variable capacitor is used at a frequency of 1 GHz and the capacitances of the variable capacitance elements C1 to C4 are set to 4 pF, a thin film is formed so as not to adversely affect the impedance from 1/10 of this frequency (100 MHz). If the resistance values of the resistors 61 to 65 are set to a resistance value of 10 times or more the impedance at 100 MHz of the variable capacitance elements C1 to C4, the required resistance value of the thin film resistors 61 to 65 is about 4 kΩ or more. On the other hand, when the thin film resistors 61 to 65 are formed using the above-described material having a specific resistance of 1 Ωcm, for example, with a film thickness of 50 nm and an aspect ratio (length / width) of 50, a resistance value of 10 kΩ is obtained. Therefore, the thin film resistors 61 to 65 having a resistance value of 4 kΩ or more can be easily realized without increasing the shape.

  The first and second bias lines including these thin film resistors 61 to 65 are formed directly on the support substrate 1. This eliminates the need for an insulator layer for ensuring insulation between the first electrode layer 2, the second electrode layer 5, and the extraction electrode layer 8, which is necessary when forming on the variable capacitance elements C <b> 1 to C <b> 4. The configuration of the variable capacitor can be simplified. Further, by providing the first and second bias lines in the variable capacitor, it is not necessary to form an external bias supply circuit on the wiring board on which the variable capacitor is mounted, so that the circuit can be reduced in size and handled. Becomes easy.

  In the example shown in FIG. 1, one end of each of the thin film resistors 61 to 65 is joined to the conductive layers formed at the positions where the first electrode layer 2 and the second signal terminal of the variable capacitance elements C1 to C4 are formed. The other ends of 61 to 65 are joined to the conductor lines 31 to 34, and the first and second conductive layers formed at the positions where the first electrode layer 2 and the second signal terminal of the variable capacitance elements C1 to C4 are formed. Thin film resistors 61 to 65 may be provided in the middle of the conductor lines 31 to 34 connecting the second bias terminal.

  Next, the insulating layer 7 is formed. The insulating layer 7 is variable by ensuring insulation between the extraction electrode layer 8 formed on the second electrode layer 5 and the first electrode layer 2 in the same variable capacitance element and covering the dielectric layer 4. It is formed for the purpose of improving the moisture resistance of the capacitor.

  The insulating layer 7 is formed by processing into a desired shape by a dry etching method using a normal resist or the like. The insulating layer 7 includes a through-hole for connecting the first signal terminal and the first electrode layer 2 of the variable capacitor C1, which is indicated by a dotted line in FIG. 1, and the second electrode layer 5 and the extraction electrode layer. 8, a through hole for connecting the extraction electrode layer 8 of the adjacent variable capacitance element and the first electrode layer 2, and a connection between the extraction electrode layer 8 and the second signal terminal. Through-holes are provided.

  For example, silicon dioxide or silicon nitride can be used as the material of the insulating layer 7 in order to improve moisture resistance. These are preferably formed by a chemical vapor deposition (CVD) method or the like in consideration of coverage.

  Next, the extraction electrode layer 8 includes the second electrode layer 5 of the variable capacitance element C1, the first electrode layer 2 of the variable capacitance element C2, the second electrode layer 5 of the variable capacitance element C2, and the first of the variable capacitance element C3. The electrode layer 2, the second electrode layer 5 of the variable capacitance element C3, the first electrode layer 2 of the variable capacitance element C4, the second electrode layer 5 of the variable capacitance element C4, and the second signal terminal are formed. Each of the formed conductive layers is formed so as to be electrically connected through the through hole of the insulating layer 7.

  Here, the variable capacitance elements C1 to C4 are connected in series from the first signal terminal to the second signal terminal by electrically connecting the first electrode layer 2 of the variable capacitance element C1 to the first signal terminal. Is done. In order to electrically connect the first electrode layer 2 of the variable capacitance element C1 to the first signal terminal, for example, the film is formed at a position where the first electrode layer 2 and the first signal terminal of the variable capacitance element C1 are formed. The first electrode layer 2 of the variable capacitor C1 may be electrically connected to the first conductive layer, or the first electrode layer 2 may be shared by the first signal terminal and the variable capacitor C1. You may form continuously until the position which forms a 1st signal terminal.

  As a material for the extraction electrode layer 8, it is desirable to use a low resistance metal such as Au or Cu. In consideration of the adhesion of the insulating layer 7 to the extraction electrode layer 8, an adhesion layer such as Ti or Ni may be used.

  When the extraction electrode layer 8 is formed, a layer made of the material constituting the extraction electrode layer 8 may be formed at the positions where the first and second signal terminals and the first and second bias terminals are formed. preferable. This is because mounting is facilitated by aligning the heights of the positions where the first and second signal terminals and the first and second bias terminals are formed.

  Next, the solder diffusion preventing layer 9 is formed. The solder diffusion preventing layer 9 is used to prevent the solder terminal portions 111 to 114 from diffusing into the lead electrode layer 8 or the first electrode layer 2 during reflow or mounting when the solder terminal portions 111 to 114 are formed. To form. As a material of the solder diffusion preventing layer 9, Ni is suitable. On the surface of the solder diffusion preventing layer 9, about 0.1 μm of Au, Cu or the like having high solder wettability may be formed in order to improve solder wettability.

  Next, the protective layer 10 is formed so that the solder terminal portions 111 to 114 are exposed and the other parts are covered. The protective layer 10 is for protecting the components of the variable capacitor mechanically and protecting them from contamination by chemicals and the like. However, when this protective layer 10 is formed, it is formed by exposing the solder diffusion preventing layer 9 at the positions where the solder terminals 111 to 114 are to be formed. As a material for the protective layer 10, a material having high heat resistance and excellent coverage with respect to a step is preferable. Specifically, a polyimide resin, a BCB (benzocyclobutene) resin, or the like is used. These are formed by applying a resin raw material solution by a spin coating method or the like and then curing it at a predetermined temperature.

  Finally, solder terminal portions 111, 112, 113 and 114 are formed on the solder diffusion preventing layer 9. These are formed to facilitate the mounting of the variable capacitor on the external wiring board. These solder terminal portions 111, 112, 113, 114 are generally formed by reflowing after solder paste is printed on the solder terminal portions 111, 112, 113, 114 using a predetermined mask.

  In the variable capacitor of the present invention configured as described above, the variable capacitance elements C1 to C4 are connected in series between the first and second signal terminals serving as the input terminal and the output terminal, and the first and second Since the thin film resistors 61 to 65 constituting the bias line have impedance components sufficiently larger than the impedances of the variable capacitance elements C1 to C4, the high frequency signals supplied from the first and second signal terminals are the first and second. A high frequency signal does not leak through the second bias line. For this reason, in the variable capacitor of the present invention, the variable capacitance elements C1 to C4 are connected in series in terms of high frequency.

  Accordingly, since the areas of the first electrode layer 2 and the second electrode layer 5 that become the capacitance forming portions of the variable capacitance elements C1 to C4 can be increased, the processing accuracy is improved, and the desired accuracy and reproducibility are improved. The capacitance value to be realized can be realized.

  Further, since the high-frequency voltage applied to the variable capacitors C1 to C4 connected in series is divided into the variable capacitors C1 to C4, the high-frequency voltages applied to the individual variable capacitors C1 to C4 are Decrease. As a result, it is possible to suppress the capacitance fluctuation with respect to the high-frequency signal to be small, to effectively suppress waveform distortion, intermodulation distortion, and the like in the high-frequency electronic component, and to improve power durability.

  In the variable capacitance elements C1 to C4 of the present invention, the DC bias voltage, which is an applied voltage for controlling the capacitance characteristics of the variable capacitance elements C1 to C4, is supplied from the first or second bias terminal to the first and second biases. It flows to the variable capacitance elements C1 to C4 through the line. Depending on the magnitude of the DC bias voltage applied to the variable capacitance elements C1 to C4, the variable capacitance elements C1 to C4 have a predetermined dielectric constant, and as a result, desired capacitance characteristics are obtained.

  Here, since the variable capacitance elements C1 to C4 are connected in parallel via the first and second bias lines, the DC bias voltage can be stably supplied to the individual variable capacitance elements C1 to C4. Thus, the variable capacitor can be easily controlled in capacitance characteristics.

  In addition, since the high frequency voltage applied to the variable capacitance elements C1 to C4 does not leak a high frequency signal via the first and second bias lines, the DC bias voltage is more stably applied to the variable capacitance elements C1 to C4. As a result, the capacity change rate of the variable capacitance elements C1 to C4 due to the DC bias voltage can be utilized to the maximum.

  Here, the capacitance characteristics of the variable capacitance elements C1 to C4 are controlled by applying a DC bias voltage. The DC bias voltage applied from the outside is Vo, the resistance components of the first and second bias lines are Rb, When the magnitude of the insulation resistance of the dielectric layer 4 of the variable capacitance elements C1 to C4 is Rc, the magnitude of the DC bias voltage actually applied to the variable capacitance elements C1 to C4 is determined by the first and second bias lines. Since it has a resistance component, the voltage is divided into Vo × Rc / (Rb + Rc). Since the magnitude Rc of the insulation resistance of the variable capacitance elements C1 to C4 varies depending on the magnitude of the leakage current, the magnitude of the DC bias voltage actually applied to the variable capacitance elements C1 to C4 when the polarity of the DC bias voltage is different. It will be different. As a result, even when the same DC bias voltage is applied from the outside, the capacitance characteristics of the variable capacitance elements C1 to C4 differ depending on the polarity of the DC bias voltage.

  Therefore, in the variable capacitor of the present invention, by arranging the electrodes that emit electrons to the dielectric layer 4 when the DC bias voltage is applied to the variable capacitance elements C1 to C4, the adjacent variable capacitance elements are alternately arranged up and down. Focusing on the individual variable capacitance elements C1 to C4, the variable capacitance elements C1 and C3 and the variable capacitance elements C2 and C4 have different leakage current characteristics, and the resulting capacitance characteristics also differ. Since the change in capacitance characteristics between the variable capacitance elements C1 and C3 and the variable capacitance elements C2 and C4 is offset by making the number of the numbers even, the capacitance of the entire variable capacitor changes even if the polarity of the DC bias voltage is changed. It will not do. Therefore, when mounting the variable capacitor of the present invention, it is not necessary to consider the polarity, and it can be easily mounted.

  Next, FIG. 3 and FIG. 4 show an example of an embodiment of the second variable capacitor of the present invention.

  These drawings show the case of N = 4 (n = 2), FIG. 3 is a plan view showing a see-through state, and FIG. 4 is a cross-sectional view taken along the line A-A ′ of FIG. 3.

  In FIGS. 3 and 4, the same parts as those in FIGS. 1 and 2 are denoted by the same reference numerals, and redundant description thereof will be omitted.

  3 and 4, C5 and C6 are direct current limiting capacitors. These DC limiting capacitance elements C5 and C6 are formed so as not to transmit the influence of the DC bias voltage to the first and second signal terminals. The DC limiting element C5 is between the first signal terminal and the variable capacitance element C1, and the DC limiting element C6 is between the variable capacitance element C4 and the second signal terminal, and the same material as the variable capacitance elements C1 to C5, respectively. , In the same process.

  The first electrode layer 2 common to the DC limiting capacitor element C5 and the variable capacitor element C1 is used, and the first electrode layer 2 of the DC limiting capacitor element C6 is connected to the second electrode layer 2 and the extraction electrode layer of the variable capacitor element C4. The DC limiting capacitive elements C5 and C6 are electrically connected to the first and second signal terminals by the lead-out electrode layer 8 from the second electrode layer 5, respectively. One signal terminal, DC limiting capacitive element C5, variable capacitive elements C1 to C4, DC limiting capacitive element C6, and second signal terminal are connected in series. The first electrode layer 2 of the DC limiting capacitor C5 is continuously connected to the position where the first signal terminal is formed so that the first electrode layer 2 is shared by the first signal terminal and the DC limiting capacitor C5. The DC limiting capacitive element C5 and the variable capacitive element C1 are connected to the second electrode layer 5 of the DC limiting capacitive element C5 and the variable capacitive element C1 in the same manner as the connection methods of the variable capacitive elements C1 to C4. The first electrode layer 2 is electrically joined to the first electrode terminal 2 via the lead electrode 8, and the first signal terminal, the direct current limiting capacitor element C5, the variable capacitive elements C1 to C4, the direct current limiting capacitor element C6, and the second signal terminal You may connect in series in order.

  The capacitance values of the DC limiting capacitance elements C5 and C6 affect the capacitance value of the variable capacitor in the high frequency band, for example, by making the formation area of the DC limiting capacitance elements C5 and C6 larger than the variable capacitance elements C1 to C4. It should be large enough not to be. As a result, it is possible to obtain a capacitance change rate substantially equal to the capacitance change rate when there is no DC limiting capacitive element C5, C6.

  In the DC limiting capacitance elements C5 and C6, the same material as that of the variable capacitance elements C1 to C5 is used for the dielectric layer 4, but as described above, these capacitance values are the capacitance values of the variable capacitors in the high frequency band. Therefore, even if the capacitances of the DC limiting capacitors C5 and C6 are changed, there is almost no influence on the capacitance value and the capacitance change rate of the variable capacitor.

  According to the second variable capacitor of the present invention configured as described above, since it is not necessary to form a DC limiting capacitor element on the wiring board on which the variable capacitor is mounted, the circuit can be reduced in size and handled. It becomes an easy variable capacitor.

  Next, FIG. 5 and FIG. 6 show an example of the embodiment of the third variable capacitor of the present invention.

  These drawings show the case of N = 4 (n = 2), FIG. 5 is a plan view showing a see-through state, and FIG. 6 is a cross-sectional view taken along line A-A ′ of FIG. 5.

  5 and 6 are denoted by the same reference numerals as those in FIGS. 3 and 4, and redundant description thereof will be omitted.

  In FIGS. 5 and 6, C5 and C6 are direct current limiting capacitors, which are formed immediately below the first and second signal terminals. The DC limiting capacitive elements C5 and C6 are formed by forming the first electrode layer 2 at positions where the first and second signal terminals are formed on the support substrate 1, and forming the insulating layer 7 as a dielectric layer thereon, The second electrode layer 5 is shared with the first and second signal terminals. Here, it is necessary to reduce the film thickness of the insulating layer 7 in the corresponding portion so that the capacitance values of the DC limiting capacitors C5 and C6 become a desired value. The direct current limiting elements C5 and C6 may be formed using the same material and the same process as the variable capacitance elements C1 to C4, and the first and second signal terminals may be provided on the second electrode layer 5.

  The first electrode layer 2 common to the DC limiting capacitive element C5 and the variable capacitive element C1 is used to connect the first electrode layer 2 of the DC limiting capacitive element C6 to the second electrode layer 5 of the variable capacitive element C4. By electrically connecting through the extraction electrode layer 8, the first signal terminal, the direct current limiting capacitive element C5, the variable capacitive elements C1 to C4, the direct current limiting capacitive element C6, and the second signal terminal are connected in series. The

  The capacitance values of these DC limiting capacitance elements C5 and C6 are sufficiently large so as not to affect the capacitance value of the variable capacitor in the high frequency band. As a result, it is possible to obtain a capacitance change rate substantially equal to the capacitance change rate when there is no DC limiting capacitive element C5, C6.

  In the third variable capacitor of the present invention having the above-described configuration, it is not necessary to form a DC limiting capacitor element on the wiring board on which the variable capacitor is mounted. Since the area on the plane for formation can be reduced, the size of the variable capacitor itself can be reduced.

  Next, the circuit module and communication device of the present invention will be described.

  The circuit module of the present invention is configured as a resonance circuit including the variable capacitor of the present invention, at least one of an inductor and a resistor, and a voltage supply unit that can apply a voltage to these. Since the variable capacitor of the present invention is used as a capacitor constituting a resonance circuit, the capacitance change rate of the capacitor is large and a desired capacitance can be obtained with high accuracy. A desired resonance frequency can be obtained with high accuracy. In addition, since the capacitor has excellent power resistance and does not depend on the polarity of the DC bias voltage, it has high reliability, can be easily manufactured, and has high productivity.

  Further, the communication device of the present invention has a configuration using the circuit module having the above configuration as a filter means. For example, by combining the above circuit module with an inductor, a capacitor, etc., it becomes a band pass filter, and a desired resonance frequency can be set with high accuracy over a wide frequency range, so that a usable frequency range is wide and a desired pass band is accurately set. It can be obtained. As described above, according to the communication device of the present invention, a desired resonance frequency can be accurately set over a wide frequency range, so that a frequency range that can be used as a filter means is wide and a desired filter function can be obtained with high accuracy. It will be possible.

  In addition, this invention is not limited to the example of the above embodiment, In the range which does not deviate from the summary of this invention, a various change may be added at all.

  For example, the variable capacitor according to the present invention including variable capacitance elements connected in series to a plurality of regions on the support substrate 1 may be formed, or the first and second bias lines may be formed of inductors or transmission lines.

  In the example of the above embodiment, the first electrode layer 2 is formed on the support substrate 1 and the dielectric layer 4 and the second electrode layer 5 are formed thereon. A plurality of variable capacitance elements are connected in series so that the first electrode layer 2 of the element is connected to one signal terminal and the second electrode layer 5 of the variable capacitance element located at the other end is connected to the other signal terminal. In this case, the second electrode layer 5 may be formed on the support substrate 1, and the dielectric layer 4 and the first electrode layer 2 may be formed thereon.

  Next, an embodiment that further embodies the present invention will be described. As an example, the first variable capacitor of the present invention shown in FIGS. 1 and 2 will be described.

  A variable capacitor in which variable capacitance elements C1 to C4 having a capacitance value of 4 pF when no DC bias voltage is applied and a capacitance change rate of 23% when a DC bias voltage of 3 V is applied is connected in series is manufactured as follows. did.

On the support substrate 1 made of a sapphire R substrate, Pt was deposited as a first electrode layer 2 by a sputtering method at a substrate temperature of 500 ° C. Next, a target made of (Ba _0.5 Sr _0.5 ) TiO ₃ was used as the dielectric layer 4, the substrate temperature was 800 ° C., the film formation time was 15 minutes, and the film was formed by sputtering in the same batch . Before starting the formation of the dielectric layer 4, the annealing was performed at 800 ° C. for 15 minutes as annealing for planarizing the first electrode layer 2 made of Pt. On top of that, Pt was deposited as the second electrode layer 5 in the same batch by the sputtering method.

  Next, after applying a photoresist and processing the photoresist into a predetermined shape by a photolithography technique, the second electrode layer 5 was etched into an intended shape by an ECR apparatus. Thereafter, the dielectric layer 4 and the first electrode layer 2 were similarly etched into a desired shape. The shape of the first electrode layer 2 includes the conductive layers 31 to 34, the first and second signal terminals, and the conductive layers at positions where the first and second bias terminals are formed.

  Next, as the thin film resistors 61 to 65, tantalum nitride was formed at 100 ° C. by a sputtering method. After sputtering, the photoresist was formed into a predetermined shape by photolithography, and then etched using an RIE apparatus to remove the photoresist layer. The aspect ratios of the thin film resistors were all 20.

Next, as the insulating layer 7, a SiO ₂ film was formed by a CVD apparatus using TEOS gas as a raw material. After forming the resist in a predetermined shape, the resist was etched by an RIE apparatus and processed into a desired shape.

  Next, as the extraction electrode layer 8, Pt and Au were formed into a film by a sputtering method, a resist was formed in a predetermined shape, and then etched by an RIE apparatus to be processed into a desired shape.

  Finally, the solder diffusion preventing layer 9, the protective layer 10, and the solder terminals 111, 112, 113, and 114 were sequentially formed. Ni was used for the solder diffusion preventing layer 9 and polyimide resin was used for the protective layer 10.

The film thickness of the thin film resistors 61 to 65 was 43 nm, and the sheet resistance value was measured separately to be 510 kΩ / cm ² . Thereby, the specific resistance of the thin film resistors 61 to 65 was about 2 Ωcm, and the resistance value of the thin film resistors 61 to 65 was about 10 MΩ.

FIG. 7 shows the results of measuring the electrical characteristics of the variable capacitor thus obtained with an impedance analyzer (model number HP4291A, manufactured by Agilent). In FIG. 7, the horizontal axis represents frequency (unit: Hz), the left side represents impedance (unit: Ω), and the right side represents phase (unit: deg). In the figure, 1.0E + 06 represents 10 ⁶ or 1M.

  FIG. 7 confirmed that the variable capacitor had normal impedance characteristics in the measurement frequency region.

  Next, the frequency dependence of the capacitance of the variable capacitor is shown in FIG. In FIG. 8, the horizontal axis represents frequency (unit: Hz), and the vertical axis represents capacitance (unit: pF). According to FIG. 8, since the resistance values of the thin film resistors 61 to 65 included in the first and second bias lines are very high, the influence of the first and second bias lines is not observed in the measurement frequency region, and the capacitance is approximately 1 pF. It was constant. From this, it was confirmed that the four variable capacitance elements C1 to C4 are connected in series in terms of high frequency. The capacity change rate was about 23% when DC 3 V was applied. From this, it was confirmed that the four variable capacitance elements C1 to C4 are connected in parallel in terms of direct current.

Next, FIG. 9 shows the leakage current characteristics of the variable capacitor obtained above. In FIG. 9, the horizontal axis represents the applied voltage (unit: V), and the vertical axis represents the logarithmic value (unit: A) of the leakage current. In the figure, 1.0E-12 represents ^10-12, that is, 1p.

  From FIG. 9, it can be seen that the leakage current characteristic has almost the same leakage current value regardless of the polarity of the applied voltage if the absolute values thereof are equal. That is, it was confirmed that the variable capacitor of the present invention has the same leakage current characteristics even when the polarity of the DC bias voltage is changed.

  Next, FIG. 10 shows the applied voltage dependence of the capacitance change rate of the variable capacitor. In FIG. 10, the horizontal axis represents the applied voltage (unit: V), and the vertical axis represents the capacity change rate (unit:%).

  From FIG. 10, it can be seen that the capacitance change rate is almost the same, regardless of the polarity of the applied voltage, if the absolute value is equal. That is, in the variable capacitor of the present invention, it was confirmed that even if the polarity of the DC bias voltage was changed, the same capacity change rate was obtained.

It is a top view of the see-through state which shows an example of embodiment of the 1st variable capacitor of this invention. FIG. 2 is a cross-sectional view taken along line A-A ′ of FIG. 1. It is a top view of the see-through state which shows an example of embodiment of the 2nd variable capacitor of this invention. FIG. 4 is a cross-sectional view taken along line A-A ′ of FIG. 3. It is a top view of the see-through state which shows an example of embodiment of the 3rd variable capacitor of this invention. FIG. 6 is a cross-sectional view taken along line A-A ′ of FIG. 5. It is a diagram which shows the example of the frequency characteristic of the impedance in the 1st variable capacitor of this invention, and a phase. It is a diagram which shows the example of the frequency characteristic of the capacity | capacitance in the 1st variable capacitor of this invention. It is a diagram which shows the example of the applied DC bias voltage characteristic of the leakage current in the 1st variable capacitor of this invention. It is a diagram which shows the example of the applied DC bias voltage characteristic of the capacity | capacitance change rate in the 1st variable capacitor of this invention. It is sectional drawing which shows the example of the conventional thin film capacitor. (A) And (b) is an equivalent circuit diagram of the conventional variable capacitor, respectively.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Support substrate 2 ... 1st electrode layer
31, 32, 33, 34 ... conductor line 4 ... dielectric layer 5 ... second electrode layer
61, 62, 63, 64, 65 ... Thin film resistor 7 ... Insulating layer 8 ... Lead electrode layer 9 ... Solder diffusion prevention layer
10 ... Protective layer
111, 112, 113, 114 ... Solder terminal portion C1, C2, C3, C4 ... Variable capacitance element C5, C6 ... DC limiting capacitance element

Claims (6)

N of a variable capacitance element comprising a first electrode layer and a second electrode layer disposed above and below on a support substrate, and a dielectric layer that is sandwiched between these two electrode layers and whose dielectric constant changes depending on the applied voltage. (Where N = 2n and n is a natural number) are variable capacitors arranged in series in the left-right direction and connected in series, the first electrode layer of one of the variable capacitance elements adjacent to each other and the variable of the other The second electrode layer of the capacitive element is electrically connected, and the 2i-1 variable (where i is a natural number equal to or less than n) from the variable capacitive element located at one end in the left-right direction. A first bias line including at least one of a resistance component and an inductor component electrically connected to the first electrode layer of the capacitive element and the second electrode layer of the variable capacitive element located at the other end; Left and right A second bias line including at least one of a resistance component and an inductor component electrically connected to the first electrode layer of the 2i-th variable capacitance element from the variable capacitance element located at the one end in the direction; A variable capacitor characterized in that is formed. 2. The variable capacitor according to claim 1, wherein the variable capacitance elements positioned at the one end and the other end are respectively connected to a signal terminal via a direct current limiting capacitance element. The variable capacitor according to claim 2, wherein the direct current limiting capacitive element is formed immediately below the signal terminal. 4. The variable capacitor according to claim 1, wherein the dielectric layer is made of barium strontium titanate. 5. A circuit module, wherein the variable capacitor according to claim 1 is used as a capacitor constituting a resonance circuit. 6. A communication apparatus, wherein the circuit module according to claim 5 is used as filter means.

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