JP4488187B2 - Method for manufacturing substrate having via hole - Google Patents

Description

The present invention relates to a method of manufacturing a board having a via hole, to the interlayer connection structure of a printed wiring board by particular filled via.

  Conventionally, the through-hole method has been widely used as a method for interlayer connection in printed wiring boards. However, due to the recent demand for miniaturization of electronic devices, build-up that enables finer and higher-density wiring formation is possible. The law is rapidly being put into practical use. 7A and 7B and FIGS. 8A and 8B show the interlayer connection process in the through-hole method and the build-up method, respectively.

  As shown in FIGS. 7A and 7B, in the through-hole method, a hole 4 is formed by drilling in an insulating substrate 3 having conductor foils 1 and 2 on its surface (FIGS. 7A and 7B), and the inner wall thereof is included. After electroless plating is performed on the entire surface to form the underlying conductor layer 5 (FIG. (C)), electrical connection is formed by applying electrolytic plating 6 ((d) in the same figure). Further, after forming a resist pattern 7 (FIG. (E)) and etching (FIG. (F)), the resist 7 is peeled off (FIG. (G)).

  On the other hand, in the build-up method shown in FIGS. 8A and 8B, the conductor pattern 12 is formed on the surface of the core substrate 11 (FIG. 8A) (FIG. 8B), and the insulating layer 13 is provided thereon (see FIG. 8A). (C), a via hole 14 is formed ((d) in the figure). Then, an underlying conductor layer 15 is formed (FIG. (E)), a plating resist 16 is disposed (FIG. (F)), and then electrolytic plating 17 is applied (FIG. (G)). Thereafter, the resist 16 is peeled off ((h) in the same figure), and the underlying conductor layer 15 is removed by etching ((i) in the same figure).

  Furthermore, there is an invention described in the following patent document as a method for forming a filled via filled with a plating metal in a via hole.

JP 2000-59022 A

JP 2000-77845 A

  By the way, in the conventional through-hole method, even if an NC drill machine is used, the diameter of the hole that can be formed is limited to about 100 μm at most because of problems such as breakage of the drill blade and swinging of the blade during processing. The land area is becoming a factor limiting the recent high-density wiring. In addition, in the through-hole method, since there is no conductor in the center of the hole, the connection resistance is large, and since the conductor pattern is usually formed by the subtractive method using wet etching, sufficient accuracy cannot be obtained, and the fine pattern cannot be obtained. Disadvantages such as inability to cope with the problem and further thinning of the substrate have made it difficult to handle during processing.

  On the other hand, the build-up method that has been rapidly spread recently has the following problems, and further improvement is desired. That is, the number of processes is large and the mass productivity is poor. The palladium used to form the underlying conductor layer may remain on the resin surface and reduce the reliability of the board. The area cannot be made sufficiently small, and when a filled via is formed in order to improve the conduction reliability, the plating time becomes long and the mass productivity is lowered. Furthermore, the formation of the conductor pattern is a semi-additive method, and the accuracy is inevitably lower than that of the full additive method, and a somewhat thick core substrate is required to ensure handling in each process. It is disadvantageous for thinning.

  On the other hand, in the invention described in the patent document, an adhesive layer or an electrodeposition resin layer is provided in contact with the wiring conductor, which may adversely affect the electrical characteristics. This is because the Q value of the adhesive or the electrodeposition resin is generally low, and these increase the dielectric loss of the wiring portion. This is particularly noticeable in the high frequency region. Further, it is necessary to soften the adhesive layer to some extent at the time of bonding, but at this time, the adhesive flows into the via hole, and there is a risk of reducing the connection reliability of the via hole. In particular, this problem is likely to occur in a small diameter via hole having a hole diameter of 200 μm or less.

  Furthermore, since the adhesive layer is a structure that adheres only to the bottom surface of the conductor, the peel strength is inferior, and in the case of a high aspect pattern with a fine and thick conductor layer, the conductor layer tends to peel off, If an attempt is made to embed the entire pattern in the adhesive layer in order to prevent it, the above-mentioned problem that the adhesive flows into the via and lowers the connection reliability is likely to occur.

  Accordingly, an object of the present invention is to eliminate such problems in the conventional substrate structure, increase the wiring density and the reliability of the substrate, and particularly improve the mass productivity of the substrate.

In order to achieve the object and solve the problem, a first substrate manufacturing method according to the present invention includes a step of forming a first conductor pattern on a surface of a first transfer substrate having conductivity, and the transfer Forming a second conductor pattern on the surface of a second transfer substrate different from the transfer substrate, the first conductor pattern supported by the first transfer substrate, and the second transfer substrate Pressing the second conductor pattern supported by the substrate with an insulating material interposed therebetween, separating the second transfer substrate leaving the first transfer substrate, and the second transfer Drilling a hole in the insulating material from the peeled surface side from which the substrate is peeled, drilling a hole for a via hole that penetrates the insulating material and reaches the first conductor pattern from the surface of the insulating material; The first transfer is performed so that the plating metal is filled in the via hole. And a step of through the use substrates carrying out plating by energizing the first conductor pattern, and a step of removing the first transfer substrate.

  As described above, in the first substrate manufacturing method of the present invention, a hole for a via hole is formed in a state where the substrate (first conductor pattern, insulating material and second conductor pattern) is supported on the conductive transfer substrate. Since the via hole plating is performed by energizing only the bottom of the via, the generation of voids containing the plating solution is suppressed, and it is possible to perform filled via plating in a short time by supplying a large current to the transfer substrate. It becomes. In addition, since the formation of the underlying conductor layer and the etching process of the underlying conductor are not required, the number of processes can be reduced compared to the build-up method, and the underlying conductor layer is unnecessary and palladium may remain on the substrate surface. Therefore, the reliability of the substrate can be improved. Furthermore, since the substrate to be processed is supported by the transfer substrate during the processing step, a thick core substrate is not required, and the workability does not deteriorate even if the substrate (insulating material) is thinned. Further, since the interlayer connection is performed by filled vias, the connection resistance can be reduced.

The second substrate manufacturing method according to the present invention includes a step of forming a first conductor pattern on the surface of the first transfer substrate having conductivity, and a second transfer different from the transfer substrate. Forming a second conductor pattern on the surface of the transfer substrate so that a conductor is disposed even in a region where a via hole is to be formed; and a first conductor pattern supported by the first transfer substrate; A step of pressing the second conductive pattern supported by the second transfer substrate with an insulating material interposed therebetween, and a step of separating the second transfer substrate leaving the first transfer substrate And a step of providing a resist pattern covering a region other than the region where the via hole is to be formed on the peeling surface from which the second transfer substrate is peeled, and forming the via hole of the second conductor pattern. The conductor in the power region is removed by etching Forming a hole in the insulating material by blasting using the resist pattern as a mask and penetrating the insulating material from the surface of the insulating material to the first conductor pattern. A step of energizing the first conductor pattern through the first transfer substrate so that the plating metal is filled in the via hole, and the first transfer substrate. And a step of peeling off .

  In the second substrate manufacturing method, as in the first manufacturing method, a filled via is formed by using a transfer substrate to perform interlayer connection, but a via hole is formed by a blast method. . According to the blast method, for example, it is possible to manufacture a substrate at a lower cost than in the case of forming a via by a laser.

  Further, in the second substrate manufacturing method, in the step of removing the conductor in the via hole forming region by etching, the conductor may be removed larger than the diameter of the via hole to be formed by over-etching.

  This is to avoid the danger that the plating abnormally precipitates and grows upward from the peripheral edge of the hole due to the current concentration, thereby improving the reliability of the substrate. This will be described in detail in the section of the embodiment of the present invention with reference to the drawings.

The third substrate manufacturing method according to the present invention includes a step of forming a first conductor pattern on the surface of the first transfer substrate having conductivity, and a second transfer different from the transfer substrate. Forming a second conductor pattern including a conductor wiring for connection to a via hole on the surface of the substrate for transfer, the first conductor pattern supported on the first transfer substrate and the second transfer pattern Pressing the second conductive pattern supported by the substrate with an insulating material interposed therebetween, peeling the second transfer substrate leaving the first transfer substrate, and the second A step of disposing a resist pattern covering a region other than a region where a via hole is to be formed on a separation surface from which the transfer substrate has been separated; and a conductor existing in a region where the via hole is to be formed in the second conductor pattern. Process to remove by etching and before Forming a hole in the insulating material by a blast method using a resist pattern as a mask, and forming a hole for a via hole that penetrates the insulating material and reaches the first conductor pattern from the surface of the insulating material; Plating is performed by energizing the first conductor pattern through the first transfer substrate so that the plating metal is filled in the hole for the via hole, and the via hole and the conductor wiring are electrically connected by the plating. A step of connecting and forming a landless via hole; and a step of peeling off the first transfer substrate .

  In the substrate manufacturing method of the present invention, since the filled via is directly connected to the conductor wiring on the side of the second conductor pattern forming side to be connected by plating treatment (plating growth) for forming a filled via, No land is provided), and the wiring density can be further improved.

  As the insulating material, an insulating material formed of a composite material in which a functional material is mixed in a vinyl benzyl ether compound may be used.

  When such a material is used, for example, when a SUS substrate having excellent mechanical properties is used as a transfer substrate, the peelability from the transfer substrate is improved and a functional material (for example, silica filler) is added. The substrate characteristics can be improved (for example, a low dielectric constant and a high Q value).

The conductor line widths and conductor lines gap between the first and second conductor patterns may be both 30μm or less.

  According to such a substrate structure, fine wiring is possible, electronic parts and functional modules formed using the substrate can be reduced in size and thickness, and design can be facilitated.

Further, the conductor line thickness of the first conductor pattern t1, a conductor line width w1, a conductor line thickness of the second conductor pattern t2, the conductor line width is taken as w2, t1 / w1 and there is a case to the t2 / w2 both 1.0 or more.

With such a ratio of the conductor line thickness to the line width of the conductor line width or the wiring conductor (aspect ratio) t1 / w1 and t2 / w2 of 1.0 or more, it is possible to reduce the electric resistance of the wiring, This makes it possible to reduce transmission loss and heat generation.

  According to the present invention, the wiring density and the reliability of the substrate can be increased, and the mass productivity of the substrate can be improved. Other objects, features, and advantages of the present invention will become apparent from the following description of embodiments and examples of the present invention.

  Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 to 6 of the accompanying drawings. In the drawings, the same reference numerals denote the same or corresponding parts.

[First embodiment]
FIG. 1 is a process diagram showing a substrate manufacturing method according to a first embodiment of the present invention. As shown in the figure, in this embodiment, a substrate is manufactured by performing interlayer connection as follows.

  First, a transfer substrate 21 is prepared (FIG. 1A (a)), and a first conductor pattern 22 is formed on the surface of the transfer substrate 21 (FIG. 1 (b)). Further, another (second) transfer substrate 31 is prepared, and a second conductor pattern 32 is formed on the surface (FIG. 3C). As these transfer substrates 21 and 31, for example, SUS304TA material having a length of 100 mm, a width of 100 mm, and a thickness of 0.1 mm can be used. The conductor patterns 22 and 32 are formed by, for example, a pattern plating method. At this time, for example, a dry film having a thickness of 29 μm is used as the resist, and a pattern having a thickness of 20 μm is formed by copper sulfate plating. In forming the second conductor pattern 32, a donut-shaped pattern having a width of 50 μm, for example, is disposed outside the position where the via hole is formed. Thereafter, the resist is peeled off.

  Next, the second transfer substrate 31 is inverted to face the first transfer substrate 21, and an insulating material 25 is sandwiched between the transfer substrates 21 and 31 to perform vacuum pressing, thereby forming the conductor patterns 22 and 32. Transfer is performed ((d) to (e) in the figure). For the insulating material 25, for example, an adhesive sheet having a thickness of 40 μm formed of a composite material obtained by mixing 40 vol% (volume percent) of a spherical silica filler having an average particle diameter of 5 μm into vinyl benzyl ether compound resin (VB) can be used. . The thickness of the interlayer insulating layer after the transfer (the interval between the conductor patterns 22 and 32) is 20 μm. Such an insulating material formed of a vinyl benzyl ether compound resin is preferable in terms of good peelability from the SUS substrate.

  After pressing, the second transfer substrate 31 is peeled off (FIG. 1B (f)), and a via hole 35 reaching the first conductor pattern layer 22 is opened at a predetermined via hole formation position by, for example, a UVYAG laser (FIG. )). For example, the via hole 35 has a top diameter of 100 μm and a bottom diameter of 70 μm. Thereafter, smear is removed using, for example, a potassium permanganate desmear solution.

Then, the first transfer substrate 21 is energized to perform plating, and copper is deposited from the first conductor pattern 22 side on the lower surface to fill the hole 35, thereby forming a filled via 36 (FIG. 11 (h)). ). As the plating conditions at this time, for example, a plating solution of copper sulfate pentahydrate 200 g / l and sulfuric acid 100 g / l is used, and plating is performed at a current density of 8 A / dm ² . The plating time is 30 minutes.

  When the inside of the hole is filled with the plated copper 36, the first transfer substrate 21 is peeled off ((i) in the figure) to complete the interlayer connection structure according to this embodiment. Furthermore, it is possible to form a multilayer substrate by appropriately laminating an insulating material and a conductor pattern on both surfaces of the substrate by a known method.

[Second Embodiment]
FIG. 2 is a process diagram showing a substrate manufacturing method according to the second embodiment of the present invention.

  As shown in the figure, this embodiment is similar to the first embodiment (FIGS. 1A (a) to 1B (f)), and the predetermined conductor patterns 22 are respectively formed on the first and second transfer substrates. 32 is formed, pressing is performed with the insulating material 25 interposed therebetween, and the second transfer substrate is peeled off. However, in this embodiment, the second conductor pattern 32 is formed so that the upper surface portion of the position 41 where the via hole is formed is also covered with the conductor.

  Then, a resist pattern 42 covering a region other than the position 41 where the via hole is to be formed is disposed on the peeling surface (the surface on the second conductor pattern side) from which the second transfer substrate has been peeled (FIG. 5A). . As this resist 42, for example, a dry film can be used, and the resist 42 is arranged so that, for example, a hole (a portion having no resist) having a diameter of 100 μm is arranged at the via hole forming position 41 in accordance with the diameter of the via hole to be formed. Form.

  Thereafter, etching is performed to remove the conductor (second conductor pattern 32) at the via hole forming position 41 (FIG. 5B). At this time, the conductor 32 is removed by being overetched to be larger than the diameter of the via hole to be formed. This is due to the following reason.

  As shown in FIG. 3A, when the conductor 32 is etched to exactly the via hole diameter (top diameter) (the conductor 32 is present up to the periphery of the via hole), in the process of forming a filled via described later, Since the land portion 32 is also energized from the time when it is filled with the plated copper and connected to the land portion (second conductor pattern 32) ((b) in the figure), plating deposition occurs. At this time, in particular, the inner edge corner portion (hole inner edge) 32a of the land portion 32 has a high growth rate of plating due to current concentration. Therefore, FIG. 10C and FIG. There exists a possibility that the protrusion part 45 which protruded upwards may be formed. Such a protrusion 45 is not preferable because it may cause insulation failure as the interlayer becomes smaller.

  Therefore, in the second manufacturing method and the present embodiment of the present invention, the second conductor 32 of the via hole forming portion 41 is over-etched to remove the conductor larger than the diameter of the via hole to be formed. Thereby, generation | occurrence | production of this plating protrusion part 45 can be prevented and the reliability of a board | substrate can be improved.

  After the etching of the second conductor pattern 32, a via hole 43 is formed in the insulating layer 25 by blasting (FIG. 2C). According to the blast processing, a large number of via holes can be formed at one time, and the equipment is simple, so that the manufacturing cost of the substrate can be reduced as compared with laser processing.

  Thereafter, the first transfer substrate 21 is energized to form a filled via 36 as in the first embodiment (FIG. 2D), and after removing the resist 42, the transfer substrate 21 is peeled off (same as above). (E). In the formation of filled vias, since the inner edge of the land portion of the second conductor 32 is covered with the resist 42, the plating protrusion as described above is not formed.

[Third embodiment]
FIG. 4 is a process diagram showing a third embodiment of the present invention. In this embodiment, as in the first and second embodiments, the interlayer connection is formed by using the transfer method and filled via, but the interlayer connection is performed by a landless via hole in which no land is provided. .

  First, in the same manner as in the first embodiment (FIGS. 1A (a) to 1B (f)), predetermined conductor patterns 22 and 32 are formed on the first and second transfer substrates, respectively, and an insulating material 25 is interposed. Then, pressing is performed to peel off the second transfer substrate. However, in this embodiment, as shown in FIGS. 4A (a1) and (a2), the second conductor pattern 32 is formed so that the conductor exists in at least a part of the upper surface portion of the via hole forming position 41. In this example, the second conductor pattern 32 is formed so that the conductor is arranged in a circular shape at the via hole forming position 41 as shown in FIG. As shown, the wiring 51 (which is a part of the second conductor pattern 32) may be projected as it is to the via hole forming position 41. In addition, (a2)-(e2) of FIG. 4A and 4B is the top view which looked at the board | substrate from the upper surface side.

  Next, as in the second embodiment, a resist pattern 42 that covers a region other than the position 41 where the via hole is to be formed is arranged on the peeling surface (second conductor pattern side surface) of the second transfer substrate. Then (FIGS. 4A (a1) and (a2)), the conductor 32 at the via hole formation position 41 is removed by etching (FIG. 4 (b1) and (b2)).

  Then, after forming a via hole hole 43 reaching the first conductor pattern 22 by blasting (FIGS. (C1) and (c2)), the first transfer substrate 21 is energized to fill the via hole with copper. Then, the filled via 36 is formed (FIG. 4B (d1), (d2)), and the first transfer substrate 21 is peeled off (FIG. 4 (e1), (e2)).

  According to such an embodiment, it is possible to eliminate the land that is becoming a limiting factor for increasing the density of wiring and the lands that are becoming more recent, and thus it is possible to realize even higher density wiring.

  The advantages of the manufacturing methods according to the first to third embodiments are summarized as follows.

  First, the wiring density of the substrate can be improved. Since it is a full additive method, a precise and highly accurate conductor pattern can be formed and it can respond to a fine pattern. Further, as in the third embodiment, landless formation is possible, and the area of the connection portion can be reduced.

  Second, mass productivity is improved. For example, when compared with the build-up method, the formation process of the base conductor layer and the etching process of the base conductor can be omitted, and the number of processes is small. In addition, since the via is filled from the bottom using the transfer substrate, filled via plating can be performed in a short time with a large current, and the plating processing time can be reduced.

  Third, a highly reliable and high performance substrate can be manufactured. This is because the base conductor layer is unnecessary and palladium does not remain on the substrate surface. In addition, the interlayer connection is performed with a filled via having a low connection resistance.

  Fourth, it is excellent in handling properties in the manufacturing process. This is because the transfer substrate is always on at least one side in the process, so that handling becomes easy. As a transfer substrate, a transfer plate with high mechanical strength such as a SUS plate can be used, and since a thick core substrate is not required, the thickness of the interlayer insulating layer can be reduced. For example, a thin interlayer insulating layer of 100 μm or less It is also possible to easily manufacture a multilayer substrate having

[Fourth embodiment]
FIG. 6 shows a substrate structure according to the fourth embodiment of the present invention. As shown in the figure, the substrate of this embodiment includes an insulating material 25, a first conductor pattern 22 formed on one surface of the insulating material 25, and a second conductor formed on the other surface of the insulating material 25. The first and second conductor patterns 22 and 32 are formed so as to be embedded in the insulating material 25, and both surfaces 25a and 25b of the insulating material 25 are substantially flat. According to this structure, when a multilayer substrate is formed by stacking the substrates, it is possible to suppress the resin flow of the insulating material superimposed on the substrate and to easily control the thickness of the multilayer substrate, and It is possible to prevent the deviation.

  The via hole 36 that connects the first conductor pattern 22 and the second conductor pattern 32 is a filled via in which a plated metal is filled in the hole. Thereby, the electrical resistance in an interlayer connection part can be made small.

  The conductor line widths w1 and w2 and the conductor line gap w0 in the first and second conductor patterns 22 and 32 are both set to 30 μm or less. As a result, fine wiring becomes possible, and electronic components and functional modules formed using the substrate can be reduced in size and thickness.

  Further, when the conductor line thickness in the first conductor pattern 22 is t1, and the conductor line thickness in the second conductor pattern 32 is t2, both t1 / w1 and t2 / w2 are 1.0 or more. Each of the conductor patterns 22 and 32 is formed. This can reduce the electrical resistance of the wiring and reduce transmission loss.

  In manufacturing the substrate according to the present embodiment, the substrate manufacturing methods according to the first to third embodiments can be appropriately used.

  Although the embodiments of the present invention have been described above, the present invention is not limited to these embodiments, and it will be apparent to those skilled in the art that various modifications can be made within the scope of the claims. .

(A) to (e) are substrate cross-sectional views sequentially showing the steps of the substrate manufacturing method according to the first embodiment of the present invention. (F) to (i) are substrate cross-sectional views sequentially showing the steps of the substrate manufacturing method according to the first embodiment of the present invention. (A) to (e) are substrate cross-sectional views sequentially showing the steps of the substrate manufacturing method according to the second embodiment of the present invention. (A) to (d) are substrate cross-sectional views for explaining the advantages of the second manufacturing method and the second embodiment of the present invention. (A1) to (c1) are substrate cross-sectional views sequentially showing the steps of the substrate manufacturing method according to the third embodiment of the present invention. Further, (a2) to (c2) are plan views of (a1) to (c1). (D1) to (e1) are substrate cross-sectional views sequentially showing the steps of the substrate manufacturing method according to the third embodiment of the present invention. Further, (d2) to (e2) are plan views of (d1) to (e1). It is a top view which shows the modification in said 3rd embodiment. It is sectional drawing which shows the board | substrate which concerns on 4th embodiment of this invention. (A) to (d) are substrate cross-sectional views sequentially showing steps of interlayer connection by a conventional through-hole method. (E) to (g) are cross-sectional views of the substrate sequentially illustrating steps of interlayer connection by a conventional through-hole method. (A) to (e) are substrate cross-sectional views sequentially showing interlayer connection steps in a conventional build-up method. (F) to (i) are cross-sectional views of the substrate sequentially illustrating the steps of interlayer connection in the conventional build-up method.

Explanation of symbols

21 and 31 Transfer substrate 22 and 32 Conductor pattern 25 Insulating material 35 and 43 Hole for via hole 36 Filled via 42 Resist

Claims (5)

Forming a first conductor pattern on the surface of the first transfer substrate having conductivity;
Forming a second conductor pattern on the surface of a second transfer substrate different from the transfer substrate, so that a conductor is disposed even for a region where a via hole is to be formed;
Pressing the first conductor pattern supported on the first transfer substrate and the second conductor pattern supported on the second transfer substrate with an insulating material interposed therebetween;
Separating the second transfer substrate leaving the first transfer substrate;
A step of disposing a resist pattern covering a region other than the region where the via hole is to be formed on the peeling surface from which the second transfer substrate is peeled;
Removing the conductor in the region where the via hole is to be formed in the second conductor pattern by etching;
Drilling a hole in the insulating material by a blast method using the resist pattern as a mask, and forming a hole for a via hole that penetrates the insulating material and reaches the first conductor pattern from the surface of the insulating material;
Conducting the plating by energizing the first conductor pattern through the first transfer substrate so that the plating metal is filled in the via hole.
Look including a step of removing the first transfer substrate,
In the step of etching and removing the conductor in the via hole forming region, the conductor is over-etched so as to be removed larger than the diameter of the via hole to be formed . The manufacturing method of the board | substrate of Claim 1. The insulating material formed with the composite material which mixed the functional material in the vinyl benzyl ether compound is used as the said insulating material. Wherein one or both of the first transfer substrate and the second transfer substrate of the method of producing a substrate according to claim 1 or 2 is a SUS substrate. The method for manufacturing a substrate according to any one of claims 1 to 3 , wherein a conductor line width and a conductor line gap in the first and second conductor patterns are both set to 30 µm or less. When the conductor line thickness in the first conductor pattern is t1, the conductor line width is w1, the conductor line thickness in the second conductor pattern is t2, and the conductor line width is w2, t1 / w1 and t2 / The method for manufacturing a substrate according to any one of claims 1 to 4 , wherein both w2 are 1.0 or more.

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