JP4483157B2 - Multilayer electronic components - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a multilayer electronic component, and more particularly to a multilayer electronic component such as a delay line provided with a via hole therein.
[0002]
[Prior art]
Conventionally, for example, a delay line described in Japanese Patent Laid-Open No. 3-125504 is known as this type of multilayer electronic component. As shown in FIG. 9, the delay line has green sheets 152, 154, 156, and 158 provided with ground inner conductors 152a, 154a, 156a, and 158a on the surface, and strip conductors 153a, 155a, and 157a on the surface, respectively. An external electrode for input, an external electrode for output, and two external electrodes for ground are provided on the side surface and the upper and lower surface portions of a laminate formed by stacking the provided green sheets 153, 155, and 157 and protective green sheets 151 and 159. Is provided.
[0003]
Each of the ground internal conductors 152a, 154a, 156a, 158a is drawn to the side surface of the multilayer body by the lead portions 152b, 154b, 156b, 158b, and is electrically connected to the ground external electrode. The strip conductors 153a, 155a, 157a are electrically connected in series via via holes 153c, 154c, 155c, 156c provided in the green sheets 153-156.
[0004]
[Problems to be solved by the invention]
However, in the conventional delay line 150, the lead portions 152b, 154b, 156b, and 158b of the ground inner conductors 152a, 154a, 156a, and 158a are stacked at the same position as seen in plan view due to the arrangement of the external electrodes. Is provided. For this reason, the stacking direction of the lead-out portions 152b, 154b, 156b, and 158b locally increases in thickness, and the laminated body may be swelled. In general, since the interlayer adhesion strength between the green sheet and the internal conductor is lower than that between the green sheets, there is a problem that delamination occurs in the laminated body at the lead portions 152b, 154b, 156b, and 158b. there were.
[0005]
Accordingly, an object of the present invention is to provide a multilayer electronic component that suppresses undulation due to a local increase in thickness of the laminate and has high interlayer adhesion strength.
[0006]
[Means and Actions for Solving the Problems]
In order to achieve the above object, a multilayer electronic component according to the present invention includes a plurality of insulating layers provided with a signal inner conductor on the surface, an insulating layer provided with a first ground inner conductor on the surface, and a second ground. An insulating layer provided with an internal conductor on the surface; a plurality of ground via holes provided in any of the insulating layers and electrically connecting the first and second ground internal conductors; and the first and second ground interiors An insulating layer electrically connected to the ground via hole between the insulating layers provided with the conductor, and having a third ground inner conductor provided on the surface so that the position of the ground via hole is shifted in plan perspective It is characterized by further comprising a ground external electrode which is provided with a laminated body and is not in contact with the third ground internal conductor . The third ground inner conductor is, for example, a strip-shaped conductor, and has a smaller area than the first and second ground inner conductors.
[0007]
With the above configuration, the via hole for ground can easily change the interlayer connection position compared with the lead portion of the conventional ground inner conductor, and the area is smaller than that of the conventional lead portion. There is little increase and the undulation of the laminate is also small. Also, the interlayer adhesion strength is unlikely to decrease.
[0008]
Further, the third ground inner conductor is composed of a plurality, and is provided in the same shape so as to overlap in the stacking direction of the stacked body. Thereby, even if the position of the ground via hole is shifted, it is not necessary to change the design of the internal pattern. Further, when the positions of the ground via holes that electrically connect the plurality of third ground inner conductors are shifted in plan perspective, the ground generated in the stacked body when the ground via holes are connected in the stacking direction. The via hole is not raised. Therefore, the local thickness increase of the laminate is further reduced.
[0009]
A plurality of ground via holes that electrically connect between the first ground inner conductor and the third ground inner conductor and between the third ground inner conductor and the second ground inner conductor are laminated. And the number of ground via holes connected between the first and third ground inner conductors and the ground connected between the third and second ground inner conductors. The number of via holes for use is different. With the above configuration, some of the ground via holes can be reduced, and the local thickness increase of the stacked body can be further suppressed. The ground external electrode is in contact with only the first ground internal conductor.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of a multilayer electronic component according to the present invention will be described below with reference to the accompanying drawings. Each embodiment will be described with reference to a delay line for delaying signal transmission in a computer, a measuring instrument or the like, but the present invention is not necessarily limited to this. In general, the present invention can also be applied to a multilayer electronic component having via holes for interlayer connection between three ground internal conductors adjacent in the stacking direction.
[0011]
[First Embodiment, FIGS. 1 to 5]
As shown in FIG. 1, the lumped constant delay line 51 has U-shaped coil conductors (signal internal conductors) 80a to 80d and relay ground internal conductors (third ground internal conductors) 95a to 95d on the surface. Insulating sheets 58-61 provided on the surface, insulating sheets 54, 56, 63, 65 provided with capacitor conductors 75, 76 on the surface, and ground internal conductors 71, 72, 73, 74 provided on the surface, respectively. Insulating sheets 53, 55, 64, 66, insulating sheets 57, 62 each having relay signal conductors 81, 82 provided on the surface thereof, protective insulating sheet 52 having no conductors provided on the surface in advance, etc. It is configured.
[0012]
The coil conductors 80a to 80d are electrically connected in series via signal via holes 90 provided in the insulating sheets 58 to 61, respectively, to form ten helical coils L. The capacitor conductor 75 generates electrostatic capacitance between the ground inner conductors 71 and 72 to form six capacitors C. The capacitor conductor 76 generates a capacitance between the ground inner conductors 73 and 74 and forms six capacitors C. These capacitors C are electrically connected to the spiral coil L via the relay signal conductors 81 and 82 and the signal via hole 90.
[0013]
Each of the insulating sheets 52 to 66 described above is repeatedly stacked a plurality of times as appropriate, and then pressed and integrally fired to form a substantially rectangular parallelepiped laminate 100 shown in FIG. An input external electrode 101, an output external electrode 102, and a ground external electrode G are formed on the front and back side surfaces of the laminate 100, respectively. The input external electrode 101 and the output external electrode 102 are electrically connected to lead conductors 83 and 84 provided on the insulating sheet 53, respectively. The ground external electrode G is electrically connected to the lead portion of the ground internal conductor 71. FIG. 3 is an electrical equivalent circuit diagram of the delay line 51.
[0014]
From the above configuration, the delay line 51 conducts the ground external electrode G and the ground internal conductors 71 to 74 only at the lead portion of the ground internal conductor 71. That is, the ground internal conductors 72 to 74 are electrically connected to the ground internal conductor 71 via the ground via holes 91 and 96 a to 96 d provided in the multilayer body 100 and the relay ground internal conductors 95 a to 95 d.
[0015]
As described above, the structure in which the ground internal conductors 71 to 74 are conducted through the ground via hole 91 and the relay ground internal conductors 95a to 95d is electrically connected to the ground external electrode through the lead portion. Compared with the conventional connection structure for connecting to the interlayer connection position, the interlayer connection position can be easily changed. In addition, since the cross section of the ground via hole 91 has a smaller area than that of the conventional lead portion, the local thickness of the laminate 100 is not increased and the interlayer adhesion strength is not easily lowered.
[0016]
Furthermore, as shown in FIG. 4, the ground via hole 91,96a~96d and relay ground inner conductor 95a~95d is, the two ground internal conductors 7 2 73 adjacent to each other across the insulating sheet 55 to 63 Connect electrically. Then, in the ground via holes 96a to 96d, the positions of two ground via holes (for example, 96a and 96b, or 96b and 96c, etc.) adjacent to each other in the stacking direction of the stacked body 100 are planarly seen (laminated from the top surface of the stacked body). (In the state viewed in the direction) (the cross-sectional view of FIG. 4 has a substantially meandering shape), it is possible to prevent the via hole from being raised in the stacked body when the via holes are connected in the stacking direction. . Therefore, the local thickness increase of the laminate 100 is further reduced. Unlike the connection between the signal internal conductors, the connection is between the ground internal conductors, so that the electrical characteristics are not greatly affected.
[0017]
In addition, strip-shaped relay ground inner conductors 95a to 95d having the same shape and electrically connected to the ground via holes 96a to 96d overlap in plan view, and one end of one of the adjacent ground via holes is the other. It is in contact with the relay ground inner conductor connected to the ground via hole. As described above, by using the relay ground inner conductors 95a to 95d having the same shape, even if the positions of the ground via holes 96a to 96d are gradually shifted in a staircase pattern as shown in FIG. Redesign is unnecessary.
[0018]
[Second Embodiment, FIGS. 6 to 8]
As shown in FIG. 6, the distributed constant delay line 1 includes insulating sheets 9, 8, 6, 5, 3 having meandering coil conductors (signal internal conductors) 11 to 20 on the surfaces, Insulating sheet 10 provided with one ground inner conductor 21 on the surface, insulating sheet 7 provided with the third ground inner conductor 22 on the surface, and insulating sheet provided with the second ground inner conductor 23 on the surface 4 and a laminated body constituted by previously stacking protective insulating sheets 2 and the like not provided with a conductor on the surface.
[0019]
The coil conductors 11 to 15 are disposed in a substantially left half region of the insulating sheets 9, 8, 6, 5 and 3, and are electrically connected via signal via holes 31 a to 31 f provided in the insulating sheets 8 to 3, respectively. Are connected in series. The coil conductors 16 to 20 are disposed in a substantially right half region of the insulating sheets 3, 5, 6, 8, and 9, and are electrically connected via signal via holes 31 g to 31 l provided in the insulating sheets 3 to 8, respectively. Are connected in series. Furthermore, when one end of the coil conductor 15 and one end of the coil conductor 16 are electrically connected, the coil conductors 11 to 15 and 16 to 20 are electrically connected in series.
[0020]
Between the first ground inner conductor 21 and the third ground inner conductor 22 having a large area, coil conductors 11, 12, 19, and 20 are disposed so as to face each other. Coil conductors 13, 14, 17, and 18 are disposed between the large-area third and second ground inner conductors 22 and 23 so as to face each other. Thus, each microstrip line is configured.
[0021]
Between the coil conductors 15 and 16, ground via holes 32g and 33g are disposed. The ground via holes 32g and 33g are electrically connected to the second ground inner conductor 23 to prevent electromagnetic coupling between the magnetic field generated by the coil conductor 15 and the magnetic field generated by the coil conductor 16. Yes.
[0022]
Further, ground via holes 32d, 33d, 32e, 33e, 32f, and 33f are disposed between the coil conductors 13, 14 and 18, 17. The ground via holes 32d, 33d, 32e, 33e, 32f, and 33f are electrically connected to the third and second ground internal conductors 22 and 23, and the magnetic field generated by the coil conductors 13 and 14 and the coil The magnetic fields generated by the conductors 18 and 17 are prevented from being electromagnetically coupled. Since the coil axes of the coil conductors 13 and 14 are orthogonal to each other, the magnetic field generated by the coil conductor 13 and the magnetic field generated by the coil conductor 14 are hardly electromagnetically coupled. For the same reason, the magnetic field generated by the coil conductor 17 and the magnetic field generated by the coil conductor 18 are hardly electromagnetically coupled.
[0023]
Further, ground via holes 34c, 34b, 34a are disposed between the coil conductors 11, 12 and 20, 19. The ground via holes 34c, 34b, and 34a are electrically connected to the first and third ground inner conductors 21 and 22, and the magnetic field generated by the coil conductors 11 and 12 and the coil conductors 20 and 19 are used. The generated magnetic field is prevented from being electromagnetically coupled. Since the coil axes of the coil conductors 11 and 12 are orthogonal to each other, the magnetic field generated by the coil conductor 11 and the magnetic field generated by the coil conductor 12 are hardly electromagnetically coupled. For the same reason, the magnetic field generated by the coil conductor 19 and the magnetic field generated by the coil conductor 20 are hardly electromagnetically coupled.
[0024]
For the insulating sheets 2 to 10, a dielectric material, for example, a composite material in which glass and a filler (alumina, silica, etc.) are combined, glass ceramic, or the like is used. The conductors 11 to 20, 21 to 23 and the via holes 31a to 31l, 32d to 32g, 33d to 33g, 34a to 34c are made of Pt, Ag, Pd, Cu, Au, Ag-Pd, etc., and printing, sputtering, vapor deposition, photo It is formed by a method such as lithography.
[0025]
After laminating each of the insulating sheets 2 to 10 described above, the laminate 40 having a substantially rectangular parallelepiped shape shown in FIG. 7 is formed by pressure bonding and firing integrally. Here, the insulating sheets 4 to 6 are laminated three times. An input external electrode 41, an output external electrode 42, and a ground external electrode G are formed on the front and back side surfaces of the laminate 40, respectively.
[0026]
The input external electrode 41 is electrically connected to the lead portion of the coil conductor 11. The output external electrode 42 is electrically connected to the lead portion of the coil conductor 20. The ground external electrode G is electrically connected to the lead portion of the first ground internal conductor 21. FIG. 8 is an electrical equivalent circuit diagram of the delay line 1. The delay line 1 secures a capacitor component by a stray capacitance generated between the coil conductors 11 to 20 and the first to third ground inner conductors 21 to 23.
[0027]
In the delay line 1 configured as described above, the ground external electrode G and the first to third ground internal conductors 21 to 23 are electrically connected only by the lead portion of the first ground internal conductor 21. That is, the third and second ground inner conductors 22 and 23 are electrically connected to the ground inner conductor 21 through the ground via holes 32d to 32f, 33d to 33f, and 34a to 34c provided in the multilayer body 40. . The ground via holes 32d to 32g, 33d to 33g, and 34a to 34c are arranged on different axes in the stacking direction of the stacked body 40, respectively.
[0028]
The lead portion of the first ground inner conductor 21 is led to the side surface of the multilayer body 40 and connected to the ground external electrode G. However, a lead-out via hole may be further provided in the first ground inner conductor 21, drawn out to the back surface of the multilayer body 40, and connected to a ground land electrode provided on the back surface.
[0029]
As described above, the structure in which the ground internal conductors 21 to 23 are electrically connected through the ground via holes 32d to 32f, 33d to 33f, and 34a to 34c allows all of the ground internal conductors to be electrically connected to the ground external electrode via the lead portion. As compared with the conventional connection structure that connects the two, the interlayer connection position can be easily changed. Moreover, since the cross sections of the ground via holes 32d to 32g, 33d to 33g, and 34a to 34c are smaller in area than the conventional lead-out portion, the local thickness increase of the laminate 40 is small, and the undulation of the laminate 40 is also small. . Also, the interlayer adhesion strength is unlikely to decrease.
[0030]
[Other Embodiments]
The multilayer electronic component according to the present invention is not limited to the above-described embodiment, and can be variously modified within the scope of the gist thereof.
[0031]
Although the embodiment has been described by taking the case of individual products as an example, in the case of mass production, a mother board having a plurality of electronic components can be manufactured and cut into a desired size to obtain a product. Further, in the above-described embodiment, the insulating sheets on which the conductors are formed are stacked and then fired integrally. However, the embodiment is not necessarily limited thereto. A sheet fired in advance may be used. Moreover, you may manufacture an electronic component with the manufacturing method demonstrated below. An insulating layer is formed by applying a paste-like insulating material by means such as printing, and then an arbitrary conductor is formed by applying a paste-like conductor material on the surface of the insulating layer. Next, a paste-like insulating material is applied over the conductor. In this way, an electronic component having a laminated structure can be obtained by sequentially applying in layers.
[0032]
【The invention's effect】
As is apparent from the above description, according to the present invention, the ground via hole can be easily changed in interlayer connection position as compared with the lead portion of the conventional ground inner conductor, and has an area larger than that of the conventional lead portion. Therefore, the local thickness increase of the laminate is small, and the undulation of the laminate is also small. Also, the interlayer adhesion strength is unlikely to decrease.
[0033]
Further, the third ground inner conductor is composed of a plurality, and is provided in the same shape so as to overlap in the stacking direction of the stacked body. This eliminates the need to change the design of the internal pattern even if the position of the ground via hole is shifted. Further, when the positions of the ground via holes that electrically connect the plurality of third ground inner conductors are shifted in plan perspective, the ground generated in the stacked body when the ground via holes are connected in the stacking direction. The via hole is not raised. Therefore, the local thickness increase of the laminate can be further reduced.
[0034]
Further, the number of ground via holes connected between the first and third ground internal conductors is different from the number of ground via holes connected between the third and second ground internal conductors. As a result, some of the ground via holes can be reduced, and the local increase in thickness of the stacked body can be further suppressed.
[Brief description of the drawings]
FIG. 1 is an exploded perspective view showing a first embodiment of a multilayer electronic component according to the invention.
FIG. 2 is a perspective view showing an appearance of the multilayer electronic component shown in FIG.
3 is an electrical equivalent circuit diagram of the multilayer electronic component shown in FIG. 2. FIG.
4 is a schematic cross-sectional view of a via hole for interlayer connection between ground internal conductors of the multilayer electronic component shown in FIG. 1;
FIG. 5 is a schematic cross-sectional view showing a modified example of a via hole for interlayer connection between ground internal conductors.
FIG. 6 is an exploded perspective view showing a second embodiment of the multilayer electronic component according to the invention.
7 is a perspective view showing an appearance of the multilayer electronic component shown in FIG. 6. FIG.
8 is an electrical equivalent circuit diagram of the multilayer electronic component shown in FIG.
FIG. 9 is an exploded perspective view showing a conventional multilayer electronic component.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1,51 ... Delay line 2-10, 52-66 ... Insulating sheet 11-20, 80a-80d ... Coil conductors 21-23, 71-74 ... Ground internal conductors 32d-32g, 33d-33g, 34a-34c , 91, 96a to 96d... Ground via hole 40, 100... Laminated bodies 95a to 95d.

Claims (6)

A plurality of insulating layers provided with signal inner conductors on the surface;
An insulating layer provided on the surface with a first ground inner conductor;
An insulating layer provided on the surface with a second ground inner conductor;
A plurality of ground via holes provided in any of the insulating layers and electrically connecting the first and second ground inner conductors;
A third ground internal conductor is electrically connected to the ground via hole between the insulating layers provided with the first and second ground internal conductors, and the position of the ground via hole is shifted in plan perspective. An insulating layer provided on the surface;
Comprises a laminate comprising,
The multilayer electronic component further comprising a ground external electrode not in contact with the third ground internal conductor . 2. The multilayer electronic component according to claim 1, wherein the third ground inner conductor is a strip-shaped conductor and has an area smaller than that of the first and second ground inner conductors.   3. The multilayer electronic component according to claim 1, wherein the third ground internal conductor includes a plurality of conductors, and is provided in the same shape so as to overlap in the stacking direction of the multilayer body.   4. The multilayer electronic component according to claim 3, wherein the ground via hole for electrically connecting the plurality of third ground inner conductors is disposed so as to be displaced in a plan view. 5. .   The plurality of grounds that electrically connect between the first ground inner conductor and the third ground inner conductor and between the third ground inner conductor and the second ground inner conductor, respectively. Via holes are connected in the stacking direction of the stacked body, and between the number of ground via holes connected between the first and third ground inner conductors and between the third and second ground inner conductors. 2. The multilayer electronic component according to claim 1, wherein the number of ground via holes connected to each other is different. 6. The multilayer electronic component according to claim 1, wherein the ground external electrode is in contact with only the first ground internal conductor.

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