JP4479167B2 - Solid-state imaging device and method for manufacturing solid-state imaging device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a solid-state imaging device and a method for manufacturing the solid-state imaging device, and in particular, a vertical transfer unit in an interline transfer (IT) system (or frame interline transfer (FIT) system) solid-state image sensor having a vertical overflow drain structure. And a method of manufacturing a solid-state imaging device having the vertical transfer unit.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, in a solid-state imaging device, for example, an IT (or FIT) CCD (Charge Coupled Device) solid-state imaging device having a vertical overflow drain structure, an entire P-well region that is an overflow barrier region along with a light receiving portion on a semiconductor substrate In the vertical transfer section formed via the P-type well region, a P-type well region is formed under the N-type transfer channel. In order to secure a necessary charge amount of the vertical transfer section, the P-type well region is formed. The well region is formed close to the N-type transfer channel to improve the depletion layer capacitance between the N-type transfer channel and the P-type well region (see, for example, Patent Document 1).
[0003]
[Patent Document 1]
Japanese Patent Laid-Open No. 2002-343958
FIG. 5 shows a cross-sectional structure of a unit cell in this type of CCD solid-state imaging device. In the figure, a P well region 102 is formed as an overflow barrier region on an N type semiconductor substrate 101, and a P ⁻ or N ⁻ type semiconductor layer 103 is further formed on the P well region 102. A light receiving unit 104, a vertical transfer unit 105, and a reading gate unit 106 are formed on 103.
[0005]
The light receiving unit 104 includes an N-type signal charge storage region 107 formed on the surface layer of the semiconductor layer 103 and a P ⁺ -type positive charge storage region 108 formed thereon. The vertical transfer unit 105 includes an N-type transfer channel 109 formed in the surface layer portion of the semiconductor layer 103, a P-type well region 110 formed thereunder, and an insulating film 111 on the substrate surface above the transfer channel 109. And the transfer electrode 112 formed via the electrode.
[0006]
In the vertical transfer unit 105, a part of the transfer electrode 112 extends to the vicinity of the light receiving unit 104, and the electrode of this extended part is also used as the gate electrode of the read gate unit 106. In other words, the read gate unit 106 includes a gate electrode that also serves as a part of the transfer electrode 112 and a channel region under the gate electrode. A channel stop unit 113 is formed between the vertical transfer unit 105 and the light receiving unit in the adjacent column.
[0007]
The region excluding the upper region of the light receiving unit 104, that is, the top of the vertical transfer unit 105 and the readout gate unit 106 is covered with a light shielding film 115 through an interlayer insulating film 114. As a result, the upper region of the light receiving unit 104 that is not covered by the light shielding film 115 becomes the opening 116, and incident light is taken into the light receiving unit 104 through the opening 116.
[0008]
[Problems to be solved by the invention]
Incidentally, in recent years, in CCD solid-state imaging devices, the size of unit cells tends to be reduced for the purpose of increasing the number of pixels. As the unit cell size is reduced, the area of the opening 116 is also reduced, and the amount of incident light that can be taken into the light receiving unit 104 is reduced accordingly, resulting in a reduction in sensitivity. In order to suppress the decrease in sensitivity due to the reduction in the size of the unit cell as much as possible, as shown in FIG. 5, light incident obliquely through the opening 116 (hereinafter referred to as oblique incident light) is also subjected to photoelectric conversion. So that it can be used as signal charges.
[0009]
However, as described above, in the CCD solid-state imaging device adopting the structure in which the P-type well region 110 is formed in the vicinity of the N-type transfer channel 109 in order to secure the necessary handling charge amount of the vertical transfer unit 105, When obliquely incident light is photoelectrically converted in the P-type well region 110, most of minority carriers (here, electrons in the P-type semiconductor) are applied to the electric field between the P-type well region 110 and the N-type substrate 101. Since it is pulled out and flows out to the substrate 101, a phenomenon that it cannot be taken into the signal charge accumulation region 107 of the light receiving portion 104 occurs.
[0010]
This phenomenon will be described in detail with reference to the potential diagram of FIG. FIG. 6 is a potential diagram showing the potential distribution (solid line) A in the section taken along the line AA ′ in FIG. 5 and the potential distribution (dotted line) B in the section taken along the line BB ′. In the potential distribution A, a region having a deep potential corresponds to the N-type transfer channel 109 and a region having a shallow potential corresponds to the P-type well region 110. Further, in the potential distribution B, a region from the substrate surface to the shallowest potential point (overflow barrier peak point) b is a photoelectric conversion region of the light receiving unit 104.
[0011]
As is clear from the potential diagram of FIG. 6, the point a having the shallowest potential in the potential distribution A is located closer to the substrate surface than the point b having the shallowest potential in the potential distribution B. When photoelectric conversion is performed in the P-type well region 110 of the transfer unit 105, most minority carriers generated on the N-type substrate 101 side from the point a having the shallowest potential are P-type well region 110 and the N-type substrate. It is pulled by the electric field between the two and the N-type substrate 101.
[0012]
That is, the minority carriers photoelectrically converted in the P-type well region 110 can contribute to the sensitivity improvement by taking them into the signal charge storage region 107 of the light receiving unit 104, but most of them contribute to the P-type well. Since it is pulled by the N-type substrate 101 by being pulled by the electric field between the region 110 and the N-type substrate 101, it cannot contribute to the improvement in sensitivity. In other words, the minority carrier flowed out to the N-type substrate 101 is the sensitivity loss.
[0013]
The present invention has been made in view of the above problems, and its object is to collect minority carriers obtained by photoelectric conversion accompanying obliquely incident light under a vertical transfer unit in a signal charge accumulation region of a light receiving unit. Accordingly, it is an object of the present invention to provide a solid-state imaging device whose sensitivity is improved and a method for manufacturing the solid-state imaging device.
[0014]
[Means for Solving the Problems]
The solid-state imaging device according to the present invention is
A signal obtained by photoelectrically converting incident light, including a signal conductivity storage region formed on a first conductivity type substrate through a second conductivity type whole well region and a first or second conductivity type semiconductor layer. A light receiving portion for accumulating charges in the signal charge accumulation region ;
Is formed through the entire well region on said substrate, a transfer channel of the first conductivity type for transferring photoelectrically converted signal charges in the light receiving unit,
A first well region of a second conductivity type formed immediately below the transfer channel;
A second well region of a second conductivity type formed below the first well region;
An impurity region of a first conductivity type interposed between the first well region and the second well region and storing charges based on obliquely incident light on the light receiving portion ;
In addition to performing pixel separation, a channel stop portion electrically coupled to the second well region is provided.
[0015]
In the solid-state imaging device having the above-described configuration, among the obliquely incident light taken into the light receiving unit, light that reaches the bottom of the transfer channel is subjected to photoelectric conversion in a region between the first well region and the second well region. Is called. At this time, the first well region and the second well region form a barrier against minority carriers generated by photoelectric conversion. As a result, minority carriers accumulate in the portion of the impurity region surrounded by these barriers and are collected in the signal charge accumulation region of the light receiving portion without being taken into the transfer channel or the substrate. As a result, sensitivity is improved. Further, when the minority carriers generated by photoelectric conversion are, for example, electrons, it is necessary to remove holes in the second well region in operation, and these holes are discharged through the channel stop portion.
[0016]
A manufacturing method of a solid-state imaging device according to the present invention includes:
In forming the vertical transfer portion on the first conductivity type substrate through the second conductivity type whole well region and the first or second conductivity type semiconductor layer ,
Forming a second conductivity type well region in the whole well region;
A second step of forming a first conductivity type impurity region that accumulates charges based on obliquely incident light on the light receiving portion on the well region formed in the first step;
A third step of forming a second conductivity type well region on the impurity region formed in the second step;
A fourth step of forming a first conductivity type transfer channel on the well region formed in the third step;
And a fifth step of deeply forming a channel stop portion for performing pixel separation up to the position of the well region formed in the first step and electrically coupling the channel stop portion to the well region.
[0017]
By forming the vertical transfer portion by the above-described steps, a vertical transfer portion having a twin well structure can be formed. In the vertical transfer unit having the twin well structure, when the light reaching the lower part of the transfer channel among the obliquely incident light taken into the light receiving unit is photoelectrically converted between the two well regions, the two well regions are blocked. Form. As a result, minority carriers accumulate in the portion of the impurity region surrounded by these barriers and are collected in the signal charge accumulation region of the light receiving portion without being taken into the transfer channel or the substrate. Therefore, a highly sensitive solid-state imaging device can be manufactured.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0019]
FIG. 1 shows the structure of a unit cell (unit pixel and a corresponding vertical transfer unit) of an IT system (or IT system) CCD solid-state imaging device having a vertical overflow drain structure according to an embodiment of the present invention. It is sectional drawing. Here, as an example, a case where the first conductivity type is N-type and the second conductivity type is P-type will be described as an example, but the present invention is not limited to this.
[0020]
In FIG. 1, an entire P well region (overflow barrier region) 12 is formed on an N type semiconductor substrate 11, and a P ⁻ type or N ⁻ type semiconductor layer 13 is further formed on the entire P well region 12. On the semiconductor layer 13, a light receiving unit 14, a vertical transfer unit 15, and a readout gate unit 16 are formed. Specifically, the light receiving unit 14 includes an N-type signal charge accumulation region (photoelectric conversion region) 17 formed in the surface layer portion of the semiconductor layer 13 and a P ⁺ -type positive charge accumulation region 18 formed thereon. It consists of and.
[0021]
The vertical transfer unit 15 includes an N-type transfer channel 19 formed in the surface layer portion of the semiconductor layer 13, a first P-type well region 20 formed under the transfer channel 19, and a first P-type well. A second P-type well region 21 formed below the region 20, an N-type impurity region 22 interposed between the P-type well regions 20, 21, and a gate insulating film on the substrate surface above the transfer channel 19 23 and a transfer electrode 24 formed via 23.
[0022]
In the vertical transfer portion 15, the second P-type well region 21 has a concentration maximum portion at a position shallower than the concentration maximum portion of the entire P-type well region 12, for example, at a position of 2 μm to 6 μm from the substrate surface. Further, the N-type impurity region 22 is formed of impurities having a concentration (N ⁻ ) lower than the impurity concentration of the transfer channel 19. The transfer electrode 24 has, for example, a two-layer electrode structure, and performs a transfer operation when a multiphase transfer clock is applied.
[0023]
In the electrode structure of the vertical transfer unit 15, the transfer electrode 24 to which a transfer clock of a specific phase is applied is provided to extend to the vicinity of the light receiving unit 14, and this extended part electrode is a read gate unit. This is also used for 16 gate electrodes. That is, the read gate portion 16 is composed of a gate electrode that also serves as a part of the transfer electrode 24 and a channel region under the gate electrode.
[0024]
A P ⁺ -type channel stop unit 25 for pixel separation is formed between the vertical transfer unit 15 and the light receiving unit in the adjacent column. The channel stop portion 25 is formed deep up to the position of the second P-type well region 21 and is electrically coupled to the P-type well region 21. Here, the electrical coupling means that the channel stop portion 25 is electrically connected to the second P-type well region 21 or the holes in the second P-type well region 21 are channel stop portions. The state which can move to 25 is said.
[0025]
The region excluding the upper region of the light receiving unit 14, that is, the top of the vertical transfer unit 15 and the read gate unit 16 is covered with a light shielding film 27 made of aluminum, tungsten, or the like via an interlayer insulating film 26. As a result, the upper region of the light receiving unit 14 that is not covered by the light shielding film 24 becomes the opening 28, and incident light is taken into the light receiving unit 14 through the opening 28.
[0026]
In the IT type (or FIT type) CCD solid-state imaging device having the vertical overflow drain structure configured as described above, incident light taken through the opening 28 is photoelectrically converted by the light receiving unit 14. The photoelectrically converted minority carriers (here, electrons), that is, signal charges are accumulated in the signal charge accumulation region 17. The accumulated signal charges are read to the transfer channel 19 of the vertical transfer unit 15 by the read gate unit 16 and are vertically transferred by applying a transfer clock to the transfer electrode 24. The above is the behavior of the signal charge generated by the photoelectric conversion in the light receiving unit 14.
[0027]
Next, the behavior of signal charges obtained by photoelectrically converting obliquely incident light under the transfer channel 19 of the vertical transfer unit 15 will be described. That is, as shown by an arrow in FIG. 1, when oblique incident light is taken in through the opening 28 and reaches the bottom of the transfer channel 19 of the vertical transfer unit 15, the first P-type well region 20 and Photoelectric conversion is performed in a region between the second P-type well region 21. As shown in FIG. 2, the first P-type well region 20 and the second P-type well region 21 form a potential barrier against signal charges (electrons) generated by the photoelectric conversion. As a result, the signal charge is accumulated in the portion of the N ⁻ -type impurity region 22 surrounded by these barriers.
[0028]
2 is a potential diagram showing the potential distribution (dotted line) B in the section taken along the line BB ′ of FIG. 1 and the potential distribution (solid line) C in the section taken along the line CC ′. In the potential distribution B, the region from the substrate surface to the shallowest point of the potential (the peak point of the overflow barrier) is the photoelectric conversion region of the light receiving unit 14. In the potential distribution C, a region having a deep potential corresponds to the N-type transfer channel 19, and a region between two peak points having a shallow potential is a photoelectric conversion region for obliquely incident light.
[0029]
Here, the potential of the N ⁻ -type impurity region 22 is equal to or higher than the potential of the light receiving portion 14 corresponding to the impurity region 22, specifically, the potential of the semiconductor layer 13 below the signal charge storage region 17. It is set to be shallow. Moreover, since the second P-type well region 21 is formed so as to have a concentration maximum portion at a position shallower than the concentration maximum portion of the entire P-type well region 12, the potential barrier by the second P-type well region 21 is formed. The peak point is always located on the substrate surface side with respect to the overflow barrier peak point of the light receiving unit 14.
[0030]
Therefore, the signal charge accumulated in the N ⁻ -type impurity region 22 is collected in the signal charge accumulation region 17 of the light receiving unit 14 without being taken into the N-type transfer channel 19 or the N-type semiconductor substrate 11. As a result, the signal charge obtained by photoelectrically converting obliquely incident light under the transfer channel 19 of the vertical transfer unit 15 is also used as the signal charge of the pixel, contributing to an improvement in sensitivity. As a result, the sensitivity of the CCD solid-state imaging device can be improved. Further, in the operation, it is necessary to extract holes in the second P-type well region 21, but these holes are discharged (extracted) through the channel stop portion 25.
[0031]
As described above, the vertical overflow drain structure having the configuration in which the first P-type well region 20 is formed in the vicinity of the N-type transfer channel 19 in order to secure the necessary handling charge amount of the vertical transfer unit 15. In an IT system (or FIT transfer system) CCD solid-state imaging device, a second P-type well region 21 is formed below the first P-type well region 20, and N between the P-type well regions 20 and 21 is formed. ^- by which the impurity regions 22 twin P-well structure is interposed, without the signal charges obtained by the oblique incident light is photoelectrically converted under the transfer channel 19 is flushed to the N-type semiconductor substrate 11 side , And can be collected in the signal charge storage region 17 of the light receiving unit 14.
[0032]
As a result, the size of the unit cell is reduced, so that the area of the opening 28 is also reduced, and even if the incident light that can be taken into the light receiving portion 14 is reduced accordingly, the signal charge based on the oblique incident light is also reduced. Since signal charges based on obliquely incident light can be used as charges, that is, contribute to improvement in sensitivity, it is possible to suppress a decrease in sensitivity due to a reduction in the size of the unit cell, or to further improve the sensitivity.
[0033]
In addition, the channel stop portion 25 for pixel separation is formed deeply up to the position of the second P-type well region 21 and is electrically coupled to the P-type well region 21, thereby providing the second Since the holes in the P-type well region 21 are discharged through the channel stop portion 25, the twin P-well structure is provided by providing the second P-type well region 21. There is no problem.
[0034]
Next, the procedure of the method for manufacturing the CCD solid-state imaging device according to this embodiment having the above-described configuration will be described with reference to the process diagrams of FIGS.
[0035]
First, as shown in FIG. 3A, an N-type semiconductor substrate 22 is prepared as a substrate for forming a CCD solid-state imaging device according to this embodiment. As this N-type semiconductor substrate 22, for example, a silicon CZ (Czochralski) substrate having a resistivity of 8 to 12 Ωcm and a size of 8 ″ φ is used. Next, as shown in FIG. The P-type well region 12 is formed as an overflow barrier region by ion implantation using, for example, boron as an impurity element in a part of the upper part.This P-type well region 12 is an image where the light receiving unit 14 and the vertical transfer unit 15 are formed. It is formed over the entire area.
[0036]
Next, as shown in FIG. 3C, a P ⁻ -type or N ⁻ -type semiconductor layer 13 is formed by an epitaxial growth method. Next, as shown in FIG. 3D, by ion implantation, a concentration maximum portion is formed at a position shallower than the concentration maximum portion of the entire P-type well region 12, for example, at a position of 2 μm to 6 μm from the substrate surface. Two P-type well regions 21 are formed, and a low-concentration N ⁻ -type impurity region 22 is formed on the P-type well region 21.
[0037]
Next, as shown in FIG. 4A, a first P-type well region 20 is formed on the N ⁻ -type impurity region 22 in the semiconductor layer 13, and then N ^- type is formed on the P-type well region 20. A type transfer channel 19 is formed, and further a P ⁺ type channel stop 25 is formed deeply to the position of the second P type well region 21 and is electrically coupled to the P type well region 21. A gate oxide film 23 is formed on the entire surface of the semiconductor layer 13 by thermal oxidation.
[0038]
Next, as shown in FIG. 4B, a transfer electrode 24 made of polycrystalline silicon is formed above the transfer channel 19 via a gate insulating film 23, and an N-type impurity is masked using the transfer electrode 24 as a mask. A signal charge accumulation region (photoelectric conversion region) 17 is formed by ion implantation, and a positive charge accumulation region 18 is formed in the surface layer portion of the substrate by ion implantation of P ⁺ type impurity using the transfer electrode 24 as a mask. Thereafter, as shown in FIG. 4C, an interlayer insulating film 26 is formed, and a light shielding film 27 is further formed. Thereafter, although not shown, a planarization film, a passivation film, a color filter, an on-chip microlens, and the like are sequentially formed by a known method.
[0039]
As described above, in the CCD solid-state imaging device having the vertical overflow drain structure, when the vertical transfer portion 15 is formed, the second P-type well region 21 is formed in the whole well region 21, and then the second P-type. An N ⁻ type impurity region 22 is formed on the well region 21, then a first P type well region 20 is formed on the N ⁻ type impurity region 22, and then on the first P type well region 20. By forming the N-type transfer channel 19 and then forming the channel stop portion 25 deeply up to the position of the second P-type well region 21 to be electrically coupled to the P-type well region 21, between P-type well region 20, 21 N ^- -type impurity regions 22 a twin P-well structure is interposed, and can discharge the holes in the second P-type well region 21 through the channel stop portion 25 It can form a vertical transfer portion 15.
[0040]
In the CCD solid-state imaging device having the vertical transfer unit 15 having the twin P well structure, as described above, the signal charge obtained by photoelectrically converting the oblique incident light under the transfer channel 19 is transferred to the N-type semiconductor substrate 11 side. Since it can be collected in the signal charge storage region 17 of the light receiving unit 14 without being poured out, the sensitivity can be improved. Therefore, according to the manufacturing method of the present invention, a highly sensitive CCD solid-state imaging device can be manufactured.
[0041]
【The invention's effect】
As described above, according to the solid-state imaging device according to the present invention, the vertical transfer portion has a twin well structure in which the second conductivity type impurity region is interposed between the first conductivity type two well regions . As a result, the incident light is obtained by photoelectric conversion under the transfer channel , and the charge accumulated in the impurity region of the second conductivity type can also be used as a signal charge. Even if the incident light that can be taken into the light receiving portion is reduced, the sensitivity can be increased.
[0042]
Further, according to the method for manufacturing a solid-state imaging device according to the present invention, the vertical transfer portion has a twin well structure in which the second conductivity type impurity region is interposed between the two well regions of the first conductivity type , and oblique incident light is transmitted. A charge that is photoelectrically converted under the transfer channel and accumulated in the impurity region of the second conductivity type can also be used as a signal charge, so that a highly sensitive solid-state imaging device can be manufactured.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing the structure of a unit cell of an IT system (or FIT system) CCD solid-state imaging device having a vertical overflow drain structure according to an embodiment of the present invention.
2 is a potential diagram showing a potential distribution B in the cross section taken along the line BB ′ of FIG. 1 and a potential distribution C in the cross section taken along the line CC ′ of FIG.
FIG. 3 is a process diagram (part 1) illustrating the procedure of the method for manufacturing the CCD solid-state imaging device according to the embodiment of the present invention.
FIG. 4 is a process diagram (part 2) illustrating the procedure of the method for manufacturing the CCD solid-state imaging device according to the embodiment of the present invention.
FIG. 5 is a cross-sectional view showing a structure of a unit cell of an IT method (or FIT method) CCD solid-state imaging device having a vertical overflow drain structure according to a conventional example.
6 is a potential diagram showing a potential distribution A in the cross section taken along the line AA ′ in FIG. 5 and a potential distribution B in the cross section taken along the line BB ′ in FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 11 ... N-type semiconductor substrate, 12 ... Whole P-type well area | region, 14 ... Light-receiving part, 15 ... Vertical transfer part, 16 ... Read-out gate part, 17 ... Signal charge storage area, 18 ... Positive charge storage area, 19 ... Transfer channel , 20... First P-type well region, 21... Second P-type well region, 22... N ^- type impurity region, 24... Transfer electrode, 25.

Claims (7)

A signal obtained by photoelectrically converting incident light, including a signal conductivity storage region formed on a first conductivity type substrate through a second conductivity type whole well region and a first or second conductivity type semiconductor layer. A light receiving portion for accumulating charges in the signal charge accumulation region ;
A transfer channel of a first conductivity type formed on the substrate through the whole well region and transferring a signal charge photoelectrically converted by the light receiving unit;
A first well region of a second conductivity type formed immediately below the transfer channel;
A second well region of a second conductivity type formed below the first well region;
An impurity region of a first conductivity type interposed between the first well region and the second well region and storing charges based on obliquely incident light on the light receiving portion ;
It performs pixel separation, the solid-state imaging device that includes a channel stop portion electrically coupled to said second well region. The solid-state imaging device according to claim 1, wherein the second well region has a concentration maximum portion at a position shallower than the concentration maximum portion of the whole well region. The solid-state imaging device according to claim 2, wherein the second well region has a concentration maximum portion at a position of 2 μm to 6 μm from the surface of the substrate. The solid-state imaging device according to claim 1, wherein a potential of the impurity region is equal to or shallower than a potential of a region of the light receiving unit corresponding to the impurity region. The solid-state imaging device according to claim 1, wherein the impurity region is formed of an impurity having a concentration lower than an impurity concentration of the transfer channel. In forming the vertical transfer portion on the first conductivity type substrate through the second conductivity type whole well region and the first or second conductivity type semiconductor layer ,
Forming a second conductivity type well region in the whole well region;
A second step of forming a first conductivity type impurity region that accumulates charges based on obliquely incident light on the light receiving portion on the well region formed in the first step;
A third step of forming a second conductivity type well region on the impurity region formed in the second step;
A fourth step of forming a first conductivity type transfer channel on the well region formed in the third step;
Method for producing at least including solid-state imaging device and a fifth step of the well region and electrically coupled to deeply form a channel stop portion to a position of well regions formed in the first step of performing pixel separation. The method of manufacturing a solid-state imaging device according to claim 6, wherein in the first step, the well region is formed so as to have a concentration maximum portion at a position shallower than the concentration maximum portion of the whole well region.

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