JP4478132B2 - High frequency power amplifier circuit - Google Patents

Description

  The present invention relates to a high-frequency power amplifier circuit using a high-frequency power MOS-FET.

  Conventionally, as a circuit compensation technique in a high frequency power amplifier circuit using a MOS-FET, there is a MOS-FET amplifier circuit to which a compensation circuit composed of a MOS-FET and a constant current circuit is added.

In a high-frequency power amplifier circuit using a high-frequency power MOS-FET that intermittently amplifies high-frequency power by pulse operation, if the output pulse width is increased, the characteristics (transient thermal resistance) of the power MOS-FET , The idle current (ΔId) flowing through the drain increases, self-heating increases, the drain current (ID) continues to rise, eventually exceeds the SOA area (Safe Operating Area), and the destruction of the power MOS FET Invite. For this reason, conventionally, when configuring a high-frequency high-frequency power amplifier circuit that obtains a high-frequency power amplification output of several kilowatts to several tens of kilowatts, a plurality of high-frequency power MOSs selected according to the required output power value FETs were connected in parallel circuit, and each power MOS FET was operated with an output pulse width operating in the SOA region.
JP 2001-68948 A NEC User's Manual “Safe Operating Area of Power MOS FET” (issued in March 2004)

  As described above, in a high-frequency power amplifier circuit using a high-frequency power MOS • FET that intermittently performs high-frequency power amplification by a pulse operation, conventionally, each power MOS • FET to be mounted is respectively within the SOA region. Since it is necessary to operate with an output pulse width that operates safely, when configuring a high-frequency high-power amplifier circuit for high power using a plurality of power MOS FETs, the circuit configuration becomes complicated and large, and the economy In particular, there was a problem of increasing the cost.

  The present invention solves the above-mentioned problems, and devise how to apply a bias voltage by a gate pulse in a high-frequency power amplification circuit using a high-frequency power MOS • FET that intermittently performs high-frequency power amplification by pulse operation. By providing a high-frequency power amplifier circuit with an economically advantageous circuit configuration that enables efficient power amplification by widening the output pulse width of the power MOS • FET and that can be expected to have a highly safe operation For the purpose.

  The present invention relates to a high-frequency power amplifier circuit using a power MOS / FET that intermittently performs high-frequency power amplification by pulse operation, and a gate pulse input terminal for inputting a gate pulse, and pulse width modulation in synchronization with the gate pulse. A high-frequency signal input terminal for inputting the high-frequency signal, a waveform shaping circuit for shaping the gate pulse inputted to the gate pulse input terminal into a gate pulse of a predetermined width where the output potential gradually decreases, and the waveform shaping circuit And an amplifying unit using a power MOS • FET for amplifying the power of the high-frequency signal input to the high-frequency signal input terminal based on the gate pulse.

  According to the present invention, in a high-frequency power amplification circuit using a high-frequency power MOS-FET that intermittently performs high-frequency power amplification by a pulse operation, a safety is achieved by devising how to apply a bias voltage by a gate pulse. The output pulse width of the power MOS / FET can be expanded while ensuring a high operation of this, and this reduces the number of mounted power MOS / FETs when configuring a high-frequency, high-power amplifier circuit for high power, It is possible to provide a high-frequency power amplifier circuit having an economically advantageous configuration with a simplified circuit configuration.

  In the pulse output operation of a power MOS • FET, if the pulse width is expanded, the self-heating increases due to the transient thermal resistance of the power MOS • FET as described above, and the drain current (ID) continues to rise. Beyond the SOA region, the power MOS • FET is destroyed. Therefore, in the embodiment of the present invention, when, for example, class AB push-pull amplification is performed using a power MOS • FET for high-frequency power amplification, the idle current gradually decreases in the gate bias circuit of the power MOS • FET. Such a compensation circuit is provided so that the pulse width of the gate bias can be increased as compared with a circuit configuration in which no compensation circuit is provided. As a result, the transient thermal resistance of the power MOS / FET can be reduced equivalently, and when configuring a high-frequency high-power amplifier circuit for high power, the number of mounted power MOS / FETs is reduced, and the circuit configuration is reduced. It can be simplified.

  Embodiments of the present invention will be described below with reference to the drawings.

  A configuration of a high-frequency power amplifier circuit according to an embodiment of the present invention is shown in FIG.

  The high-frequency power amplifier circuit according to the embodiment of the present invention includes an amplifier circuit 10 and a gate pulse waveform shaping circuit 20.

  The amplifier circuit 10 amplifies the power of the high frequency signal input to the high frequency signal input terminal 11. The high frequency signal input terminal 11 is supplied with a sinusoidal high frequency signal RF (in) intermittently pulse-width modulated at a predetermined interval.

  The gate pulse waveform shaping circuit 20 shapes the gate pulse input to the gate pulse input terminal 21 and supplies it to the amplifier circuit 10. The gate pulse input terminal 21 is supplied with a gate pulse GP (in) having a predetermined width synchronized with the high-frequency signal RF (in).

  The amplifier circuit 10 is input to a high-frequency signal input terminal 11, a pair of high-frequency power amplification power MOS FETs 12 and 13 that constitute a class AB push-pull amplifier circuit, a high-frequency signal output terminal 15, and a high-frequency signal input terminal 11. The high-frequency signal RF (in) that has been generated is supplied to the gate electrodes (G) of the power MOS FETs 12 and 13, and the gate pulse GP (out) output from the waveform shaping circuit 20 is supplied to the gates of the power MOS FETs 12 and 13. A circuit for supplying the electrode (G), a circuit for supplying a high voltage (eg, 130 to 150 V) power amplification operating power supply (VDD) to the drain electrodes (D) of the power MOS FETs 12 and 13, and a power MOS FET 12 , 13 and a circuit for outputting the high frequency signal RF (out) amplified in power to the high frequency signal output terminal 15. A circuit for supplying a gate pulse GP (out) to the gate electrodes (G) of the power MOS FETs 12 and 13, and an operation power supply (VDD) for power amplification to the drain electrodes (D) of the power MOS FETs 12 and 13 A choke coil for RF cut (high frequency component removal) is inserted in the circuit.

  The gate pulse waveform shaping circuit 20 includes a CR time constant circuit 22 that generates an integrated waveform of the gate pulse GP (in) input to the gate pulse input terminal 21, and a gate pulse GP (in) input to the gate pulse input terminal 21. The switching circuit 23 that validates the output of the integrated waveform generated by the CR time constant circuit 22, the operational amplifier 24 that inverts and amplifies the output of the CR time constant circuit 22, and the output gate pulse GP (out) And an arithmetic circuit element 25 that adjusts the width of the high frequency signal RF (in) within a range not exceeding the signal width. The gate pulse GP (out) after waveform shaping output to the output terminal (output terminal of the arithmetic circuit element 25) 26 of the gate pulse waveform shaping circuit 20 is powered through a variable resistor (VR) for gate bias adjustment. A gate bias signal is supplied to the gate electrodes (G) of the MOS • FETs 12 and 13.

  The waveform of the gate pulse GP (out) output from the gate pulse waveform shaping circuit 20 is shown in FIG. 2A. The drains of the power MOS FETs 12 and 13 associated with the waveform shaped gate pulse GP (out) are shown in FIG. A current (ID) waveform is shown in FIG.

  As shown in FIG. 2A, the gate pulse GP (out) output from the gate pulse waveform shaping circuit 20 is a signal width (pulse width modulation) of the high-frequency signal RF (in) input to the high-frequency signal input terminal 11. This is a pulse waveform in which the potential gradually decreases (gradually decreases) that is expanded within a range not exceeding the width of the generated high-frequency signal. In FIG. 2B, ΔId indicated by a broken line is an idle current included in the drain currents (ID) of the power MOS FETs 12 and 13, and a rising change portion is an increase (gradual increment) of the idle current (ΔId). ). The gate pulse GP (out) shown in FIG. 2A cancels the increase (gradual increase) of the idle current (ΔId) shown by the broken line from the drain current (ID) shown in FIG. In other words, the pulse is a pulse whose potential is gradually decreased (so that the increase in the idle current (ΔId) is apparently removed from the idle current (ΔId) included in the drain current (ID)) and whose width is expanded. .

  In the above configuration, the high frequency signal RF (in) is supplied to the high frequency signal input terminal 11 of the amplifier circuit 10 and the gate pulse GP (in) is supplied to the gate pulse input terminal 21 of the waveform shaping circuit 20. The amplifier circuit 10 receives the gate bias of the waveform shaping circuit 20 and amplifies the high frequency signal RF (in) supplied to the high frequency signal input terminal 11 by high frequency power.

  At this time, the waveform shaping circuit 20 applies the gate pulse GP (in) input to the gate pulse input terminal 21 within a range not exceeding the signal width of the high-frequency signal RF (in) as shown in FIG. A gate pulse GP (out) whose width is increased and whose potential gradually decreases is output.

  In the waveform shaping circuit 20, the gate pulse GP (in) input to the gate pulse input terminal 21 is integrated by the CR time constant circuit 22, and the integrated waveform is applied to the operational amplifier over the switch-off period of the switching circuit 23. 24 is input to the negative side (−) input terminal and inverted and amplified, and further, the pulse width is adjusted by the arithmetic circuit element 25, and is output from the output terminal 26 as a gate pulse GP (out) after waveform shaping.

  The gate pulse GP (in) waveform-shaped by the waveform shaping circuit 20 as shown in FIG. 2A is supplied to the amplifier circuit 10 via a variable resistor (VR) for gate bias adjustment. It is supplied to the gate electrodes (G) of the MOS • FETs 12 and 13.

  In the amplifier circuit 10, the high frequency signal RF (in) input to the high frequency signal input terminal 11 is amplified by the power MOS • FETs 12 and 13, and is output from the high frequency signal output terminal 15 as the high frequency signal RF (out). The At this time, the power MOS FETs 12 and 13 are input from the waveform shaping circuit 20 through the variable resistor (VR) for gate bias adjustment, and have a pulse waveform with a gradually decreasing potential shown in FIG. The gate pulse GP (out) is received by the gate electrode (G), and the high frequency signal RF (in) input to the high frequency signal input terminal 11 is subjected to class AB push-pull amplification using this pulse signal as a gate bias.

  In this way, a compensation circuit that apparently cancels the gradual increase of the idle current (ΔId) is provided in the gate bias of the power MOS • FETs 12 and 13, and the gates of the power MOS • FETs 12 and 13 By inputting a gate pulse with reverse characteristics that suppresses the increase in drain current (ID) due to transient thermal resistance, the pulse width can be expanded compared to the case without the compensation circuit, and efficient power amplification Can be done. In particular, when configuring a high-frequency high-frequency power amplifier circuit as described above, it is possible to provide an efficient and economically advantageous high-frequency power amplifier circuit by reducing the number of power MOS-FETs mounted.

The block diagram which shows the structure of the high frequency power amplifier circuit which concerns on embodiment of this invention. The figure which shows the signal waveform of the gate pulse and drain current which concern on the said embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Amplifier circuit, 11 ... High frequency signal input terminal, 12, 13 ... Power MOS * FET, 15 ... High frequency signal output terminal, 20 ... Waveform shaping circuit, 21 ... Gate pulse input terminal, 23 ... Switching circuit, 24 ... Operational amplifier, 25: arithmetic circuit element, 26: output terminal, VR: variable resistor for gate bias adjustment.

Claims (4)

In a high frequency power amplifier circuit using power MOS / FET that intermittently performs high frequency power amplification by pulse operation,
A gate pulse input terminal for inputting a gate pulse; and
A high-frequency signal input terminal for inputting a high-frequency signal pulse-width-modulated in synchronization with the gate pulse;
A waveform shaping circuit for shaping the gate pulse input to the gate pulse input terminal into a gate pulse of a predetermined width in which the output potential gradually decreases;
A high-frequency power comprising: an amplifying unit using a power MOS FET that amplifies a high-frequency signal input to the high-frequency signal input terminal based on a gate pulse output from the waveform shaping circuit Amplification circuit.   2. The high frequency power amplifier circuit according to claim 1, wherein the waveform shaping circuit outputs a gate pulse having a waveform shape in which the potential gradually decreases so that the increment of the idle current is canceled out from the drain current of the power MOS FET. . The waveform shaping circuit is:
A CR time constant circuit for integrating the gate pulse input to the gate pulse input terminal;
An operational amplifier for inverting and amplifying the output signal of the CR time constant circuit;
The high frequency power amplifier circuit according to claim 2, further comprising a circuit element that adjusts an output width of the gate pulse.   The high-frequency power amplifier circuit according to claim 1, wherein the amplifying unit includes a pair of power MOS • FETs that perform push-pull operation in a class AB.

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