JP4476088B2 - Data transfer apparatus and image forming system - Google Patents

Description

  The present invention relates to a data transfer apparatus and an image forming system using a serial bus.

  There is a data transfer apparatus having a virtual channel function for transmitting packet data of a plurality of traffic by using a serial bus in a time division manner in units of virtual channels and an arbitration function for arbitrating the priority for issuing packet data for each virtual channel . According to the data transfer apparatus having such a mechanism, it is possible to adjust a transfer rate when packet data of a plurality of traffics having different data transfer priorities are to be transferred simultaneously using a serial bus.

  As an example, in the arbitration algorithm of a virtual channel (Virtual Channel) of a serial interface (for example, see Non-Patent Document 1) that is a PCI Express (registered trademark) equivalent to the successor standard of the PCI bus method, a round robin (Round Robin) method, There are a weighted round robin method and a strict method, and it is possible to adjust the priority of packets transferred on the serial bus in units of transactions. Although these methods will be described later, the round robin method is a method in which packet data is issued at an equal frequency for each virtual channel VC, and the weighted round robin method can be arbitrarily designated for each virtual channel VC. The method of issuing packet data at a weighted frequency according to the table, the strict method is a method of issuing packet data in a fixed priority order for each virtual channel VC.

“Outline of PCI Express Standard” Interface, July’2003 Naoshi Satomi

  However, according to the arbitration function of the virtual channel VC of the PCI Express standard, simply specifying the priority of the packet data issue frequency for each virtual channel VC has a low degree of freedom in priority control, and is high for packet data of multiple traffic. It is difficult to accurately control the data transfer rate.

  An object of the present invention is to enable high-precision data transfer rate control with a high degree of freedom in a data transfer apparatus having arbitration means for adjusting the priority of issuing packet data for each virtual channel.

According to the first aspect of the present invention, virtual channel means for transmitting packet data of a plurality of traffic by using a serial bus in a time division manner in units of virtual channels, and arbitration means for arbitrating priority for issuing packet data for each virtual channel Means for detecting a packet issuance frequency for each virtual channel, designation means for designating a setting value of a data transfer rate for each virtual channel, and packet issuance for each detected virtual channel The ratio between the virtual channels of the integrated value of the frequency and the payload size of the packet data issued for each virtual channel approaches the ratio of the set value of the data transfer rate for each virtual channel specified by the specifying means. as a value, payload of packet data for each of the virtual channel Comprises a payload size determining means for determining a size in the break conditions of channel B., and packet generating means for outputting said arbitration means generates the packet data of the determined payload size for each of the virtual channel.

According to a second aspect of the present invention, there is provided virtual channel means for transmitting packet data of a plurality of traffic by using a serial bus in a time division manner in units of virtual channels, and arbitration means for arbitrating the priority for issuing packet data for each virtual channel. Means for detecting a packet issuance frequency for each virtual channel, designation means for designating a setting value of a data transfer rate for each virtual channel, and packet data issued for each virtual channel The ratio of the data transfer rate between the virtual channels by means of feedback control based on the means for detecting the payload size of the packet, the packet issue frequency for each detected virtual channel, and the payload size of the detected packet data for each virtual channel but it is designated by the designation unit Wherein to a value closer to the ratio of the set value of the data transfer rate for each virtual channel a, and payload size determining means for determining a modified payload size of the packet data for each of the virtual channel, determined for each of the virtual channel Packet generating means for generating packet data of the payload size thus set and outputting the packet data to the arbitration means.

According to a third aspect of the present invention, in the data transfer device according to the second aspect, the payload size determining means includes the detected packet issue frequency for each virtual channel and the detected payload size of the packet data for each virtual channel. Means for calculating the ratio of the data transfer rate between the virtual channels by the integration process, and setting the data transfer rate ratio between the virtual channels for each virtual channel specified from the outside. Means for determining the level of priority for each virtual channel compared with a ratio between the virtual channels of a fixed value, and between the virtual channels according to the result of the level of priority for each determined virtual channel The payload size for each virtual channel is determined by relatively modifying the size relationship of the payload size of the packet data. It has a stage, a.

Invention of claim 4, wherein the data transfer device of claim 3 wherein said means for determining the said determined the result of the level of priority for each virtual channel, a lower priority than the setpoint virtual If the channel exists, the payload size of the packet data issued by the virtual channel is corrected so as to be larger than the current value.

Invention of claim 5, wherein the data transfer device of claim 3 wherein said means for determining the said determined the result of the level of priority for each virtual channel, a lower priority than the setpoint virtual If a channel exists, the payload size of packet data issued by a virtual channel other than the virtual channel is corrected so as to be smaller than the current value.

Invention of claim 6, wherein the data transfer device of claim 3 wherein said means for determining the said determined the result of the level of priority for each virtual channel, a lower priority than the setpoint virtual If a channel exists, the payload size of the packet data issued by the virtual channel is larger than the current value, and the payload size of the packet data issued by another virtual channel other than the virtual channel is smaller than the current value. Modify to be.

Invention of claim 7, wherein the data transfer device of any one of claims 3 to 6, wherein the means for determining is the determined said high and low priority for each virtual channel a result, from the set value If a virtual channel with high priority exists, the payload size of the packet data issued by the virtual channel is corrected so as to be smaller than the current value.

Invention of claim 8, wherein the data transfer device of any one of claims 3 to 6, wherein the means for determining is the determined said high and low priority for each virtual channel a result, from the set value If a virtual channel with high priority exists, the payload size of packet data issued by other virtual channels other than the virtual channel is corrected so as to be larger than the current value.

Invention of claim 9, wherein the data transfer device of any one of claims 3 to 6, wherein the means for determining is the determined said high and low priority for each virtual channel a result, from the set value If there is a virtual channel with a higher priority, the payload size of the packet data issued by the virtual channel is smaller than the current value, and the payload size of the packet data issued by another virtual channel other than the virtual channel Is corrected to be larger than the current value.

  According to a tenth aspect of the present invention, in the data transfer device according to any one of the first to ninth aspects, the serial bus is a PCI Express standard serial bus.

  The invention according to claim 11 is the data transfer apparatus according to claim 10, wherein the algorithm for each virtual channel of the arbitration means is a round robin of the PCI Express standard or a weighted round. Robin (Weighted Round Robin).

  According to a twelfth aspect of the present invention, in the data transfer apparatus according to the eleventh aspect, the means for detecting the packet issue frequency is a round robin of the PCI Express standard as an algorithm for each virtual channel of the arbitration means. (Round Robin) or a weighted round robin (Weighted Round Robin).

  According to a thirteenth aspect of the present invention, in the data transfer apparatus according to the twelfth aspect, the means for detecting the packet issue frequency is a weighted signal of the PCI Express standard as an algorithm for each virtual channel of the arbitration means. When it is detected that Round Robin is used, the packet issue frequency for each virtual channel is detected by referring to the arbitration table for each virtual channel defined by the PCI Express standard. .

  An image forming system according to a fourteenth aspect of the present invention includes an engine having a plurality of devices having different data transfer rates required in the same packet data transfer direction, a controller for controlling and driving the engine, and these controllers, 14. An interface using a serial data transfer device according to claim 1, wherein the device in the engine is connected to the device by a serial bus using a single link.

According to the present invention, in addition to the function of the arbitration means for arbitrating the priority for issuing packet data for each virtual channel , the means for detecting the packet issue frequency for each virtual channel and the setting of the data transfer rate for each virtual channel The ratio between the virtual channels of the integrated value of the designation means for designating the value and the detected packet issuance frequency for each virtual channel and the payload size of the packet data issued for each virtual channel is designated by the designation means. Payload size determination means for determining the payload size of the packet data for each virtual channel and packet data of the payload size determined for each virtual channel so that the value approaches the ratio of the setting value of the data transfer rate for each channel. Packet generating means for generating and outputting to the arbitration means Since it is, the payload size of the packet data, by determining as setting value of the data transfer rate required to be designated by the designating means is obtained to adjust the data transfer rate only arbitration priority by arbitration means Compared to the case, it is possible to control the data transfer rate with high accuracy with a higher degree of freedom.

According to another aspect of the present invention, in addition to the function of arbitration means for adjusting the priority for issuing packet data for each virtual channel , means for detecting the packet issue frequency for each virtual channel, and data for each virtual channel Specification means for specifying the set value of the transfer rate, means for detecting the payload size of the packet data issued for each virtual channel, packet issue frequency for each detected virtual channel, packet data for each detected virtual channel Feedback control based on the payload size of each virtual channel so that the ratio of the data transfer rate between virtual channels approaches the ratio of the data transfer rate setting value for each virtual channel specified by the specifying means. Payload size that determines the modified payload size of the packet data A constant section, so generates the packet data payload size determined for each virtual channel includes a packet generating means for outputting the arbitration unit, the need for a payload size of the packet data is designated by the designating means by setting values of the data transfer rate is determined while dynamically modified based on the feedback control to obtain, compared to the case of adjusting the data transmission rate only arbitration priority by arbitration means, more flexibility In a high state, it is possible to control the data transfer rate with high accuracy.

    The best mode for carrying out the present invention will be described with reference to the drawings.

[Outline of PCI Express standard]
First, this embodiment conforms to PCI Express (registered trademark), which is one of high-speed serial buses. As a premise of this embodiment, an outline of the PCI Express standard is a part of Non-Patent Document 1. Explained with excerpts. Here, the high-speed serial bus means an interface capable of exchanging data at high speed (about 100 Mbps or more) by serial (serial) transmission using a single transmission line.

  PCI Express is a standardized expansion bus that can be used for all computers as a successor to PCI. In general, low-voltage differential signal transmission, point-to-point independent communication channels, and packetization Split transactions and high scalability due to differences in link configuration.

  FIG. 1 shows a configuration example of an existing PCI system, and FIG. 2 shows a configuration example of a PCI Express system. In the existing PCI system, PCI-X (PCI upward compatible standard) devices 104a and 104b connect the PCI-X bridge 105a to the host bridge 103 to which the CPU 100, the AGP graphics 101, and the memory 102 are connected. Or a PCI bridge 105b to which the PCI devices 104c and 104d are connected and a PCI bridge 107 to which the PCI bus slot 106 is connected are connected via the PCI bridge 105c (tree structure). Yes.

  On the other hand, in the PCI Express system, the PCI Express graphics 113 is connected by the PCI Express 114a to the root complex 112 to which the CPU 110 and the memory 111 are connected, and the endpoint 115a and the legacy endpoint 116a. The switch 117a connected by the PCI Express 114b is connected by the PCI Express 114c, and the PCI bridge 119 to which the switch 117b to which the end point 115b and the legacy end point 116b are connected by the PCI Express 114d and the PCI bus slot 118 are connected is a PCI. The switch 117c connected by the Express 114e has a tree structure (tree structure) connected by the PCI Express 114f.

  An example of an actually assumed PCI Express platform is shown in FIG. The illustrated example shows an application example to desktop / mobile. For example, graphics 125 is x16 with respect to a memory hub 124 (corresponding to a root complex) to which a CPU 121 is connected by a CPU host bus 122 and a memory 123 is connected. PCI Express 126a and an I / O hub 127 having a conversion function are connected by PCI Express 126b. For example, a storage 129 is connected to the I / O hub 127 by a Serial ATA 128, a local I / O 131 is connected by an LPC 130, and a USB 2.0 132 and a PCI bus slot 133 are connected. Furthermore, a switch 134 is connected to the I / O hub 127 by a PCI Express 126c. The switch 134 is connected to the mobile dock 135, Gigabit Ethernet (Ethernet is a registered trademark) 136, and an add-in by PCI Express 126d, 126e, and 126f, respectively. A card 137 is connected.

  That is, in the PCI Express system, the conventional PCI, PCI-X, AGP bus is replaced with PCI Express, and a bridge is used to connect an existing PCI / PCI-X device. Connection between chipsets is also PCI Express connection, and existing buses such as IEEE1394, Serial ATA, and USB 2.0 are connected to PCI Express by an I / O hub.

[Components of PCI Express]
A. Port / Lane / Link
FIG. 4 shows the structure of the physical layer. A port is a set of transmitters / receivers that are physically in the same semiconductor and form a link, and logically means an interface that connects components one-to-one (point-to-point). The transfer rate is, for example, one-way 2.5 Gbps (in the future, 5 Gbps or 10 Gbps is assumed). The lane is, for example, a set of 0.8 V differential signal pairs, and includes a transmission-side signal pair (two) and a reception-side signal pair (two). A link is a collection of lanes connecting two ports and the two ports, and is a dual simplex communication bus between components. The “xN link” is composed of N lanes, and N = 1, 2, 4, 8, 16, 32 are defined in the current standard. The illustrated example is an x4 link example. For example, as shown in FIG. 5, by changing the lane width N connecting the devices A and B, a scalable bandwidth can be configured.

B. Root Complex
The root complex 112 is located at the highest level of the I / O structure, and connects the CPU and the memory subsystem to the I / O. In a block diagram or the like, as shown in FIG. 3, it is often described as “memory hub”. The root complex 112 (or 124) has one or more PCI Express ports (root ports) (indicated by squares in the root complex 112 in FIG. 2), and each port is an independent I / O hierarchical domain. Form. The I / O hierarchical domain is a simple endpoint (for example, the example of the endpoint 115a side in FIG. 2), or is formed from a large number of switches and endpoints (for example, the endpoint in FIG. 2). 115b and switches 117b and 115c side).

C. End point
The endpoint 115 is a device having a configuration space header of type 00h (specifically, a device other than a bridge), and is divided into a legacy endpoint and a PCI Express endpoint. The major difference between the two is that the PCI Express endpoint basically does not request I / O port resources in the BAR (base address register), and therefore does not request an I / O request. PCI Express endpoints also do not support lock requests.

D. Switch
The switch 117 (or 134) couples two or more ports and performs packet routing between the ports. From the configuration software, the switch is recognized as a collection of virtual PCI-PCI bridges 141 as shown in FIG. In the figure, double-headed arrows indicate PCI Express links 114 (or 126), and 142a to 142d indicate ports. Of these, the port 142a is an upstream port closer to the root complex, and the ports 142b to 142d are downstream ports farther from the root complex.

E. PCI Express 114e-PCI bridge 119
Provides connection from PCI Express to PCI / PCI-X. Thereby, an existing PCI / PCI-X device can be used on the PCI Express system.

[Hierarchical architecture]
As shown in FIG. 7A, the conventional PCI architecture has a structure in which protocols and signaling are closely related and has no concept of hierarchy. In PCI Express, as shown in FIG. 7B, Like general communication protocols and InfiniBand, it has an independent hierarchical structure, and specifications are defined for each layer. In other words, the transaction layer 153, the data link layer 154, and the physical layer 155 are provided between the uppermost software layer 151 and the lowermost mechanism (mechanical) unit 152. Thereby, the modularity of each layer is ensured, and it becomes possible to provide scalability and reuse the module. For example, when adopting a new signal coding method or transmission medium, it is possible to cope with only changing the physical layer without changing the data link layer or the transaction layer.

  The core of the PCI Express architecture is a transaction layer 153, a data link layer 154, and a physical layer 155, each having the following roles described with reference to FIG.

A. Transaction layer 153
The transaction layer 153 is located at the highest level and has a function of assembling and disassembling a transaction layer packet (TLP). The transaction layer packet (TLP) is used for transmission of transactions such as read / write and various events. The transaction layer 153 performs flow control using credits for transaction layer packets (TLP). An outline of a transaction layer packet (TLP) in each of the layers 153 to 155 is shown in FIG. 9 (details will be described later).

B. Data link layer 154
The main role of the data link layer 154 is to guarantee data integrity of the transaction layer packet (TLP) by error detection / correction (retransmission) and link management. Packets for link management and flow control are exchanged between the data link layers 154. This packet is called a data link layer packet (DLLP) to distinguish it from a transaction layer packet (TLP).

C. Physical layer 155
The physical layer 155 includes circuits necessary for interface operations such as a driver, an input buffer, a parallel-serial / serial-parallel converter, a PLL, and an impedance matching circuit. It also has interface initialization / maintenance functions as logical functions. The physical layer 155 also serves to make the data link layer 154 / transaction layer 153 independent of the signaling technology used in the actual link.

  The PCI Express hardware configuration uses a technology called embedded clock, there is no clock signal, the clock timing is embedded in the data signal, and the receiving side is based on the crosspoint of the data signal. The clock is extracted.

[Configuration space]
PCI Express has a configuration space like conventional PCI, but its size is expanded to 4096 bytes as shown in FIG. 10, whereas conventional PCI has 256 bytes. As a result, sufficient space is secured in the future even for devices (such as host bridges) that require a large number of device-specific register sets. In PCI Express, the configuration space is accessed by accessing a flat memory space (configuration read / write), and the bus / device / function / register number is mapped to a memory address.

  The first 256 bytes of the space can be accessed as a PCI configuration space by a method using an I / O port from a BIOS or a conventional OS. The function of converting the conventional access to the access by PCI Express is implemented on the host bridge. From 00h to 3Fh, it is a PCI2.3 compatible configuration header. As a result, a conventional OS and software can be used as they are except for functions extended by PCI Express. That is, the software layer in PCI Express inherits a load / store architecture (a method in which a processor directly accesses an I / O register) that is compatible with the existing PCI. However, in order to use functions expanded by PCI Express (for example, functions such as synchronous transfer and RAS (Reliability, Availability and Serviceability)), it is necessary to make it possible to access a 4 Kbyte PCI Express expansion space.

  Various form factors (shapes) are conceivable as PCI Express. Examples of specific examples include add-in cards, plug-in cards (Express Cards), and Mini PCI Express.

[PCI Express architecture details]
The transaction layer 153, data link layer 154, and physical layer 155, which are the core of the PCI Express architecture, will be described in detail.

A. Transaction layer 153
The main role of the transaction layer 153 is to assemble and disassemble transaction layer packets (TLP) between the upper software layer 151 and the lower data link layer 154 as described above.

a. Address space and transaction type
In PCI Express, memory space (for data transfer with memory space), I / O space (for data transfer with I / O space), and configuration space (device configuration and setup) supported by conventional PCI In addition to message space (in-band event notification between PCI Express devices and general message transmission (exchange) ... Interrupt requests and confirmations are communicated by using the message as a "virtual wire" And four address spaces are defined. Transaction types are defined for each space (memory space, I / O space, configuration space is read / write, and message space is basic (including vendor definition)).

b. Transaction layer packet (TLP)
PCI Express performs communication in units of packets. In the transaction layer packet (TLP) format shown in FIG. 9, the header length of the header is 3DW (DW is an abbreviation of double word; total 12 bytes) or 4DW (16 bytes), and the transaction layer packet (TLP) format ( Information such as header length and presence / absence of payload), transaction type, traffic class (TC), attribute, and payload length are included. The maximum payload length in the packet is 1024 DW (4096 bytes).

  ECRC is an end-to-end data integrity guarantee and is a 32-bit CRC of the transaction layer packet (TLP) portion. This is because when an error occurs in the transaction layer packet (TLP) inside the switch or the like, the LCRC (link CRC) cannot detect the error (because the LCRC is recalculated with the TLP in error).

  Some requests do not require a completion packet, and some requests.

c. Traffic class (TC) and virtual channel (VC)
Upper software can differentiate (prioritize) traffic by using a traffic class (TC). For example, video data can be transferred with priority over network data. There are eight traffic classes (TC) from TC0 to TC7.

  A virtual channel (VC) is an independent virtual communication bus (a mechanism that uses a plurality of independent data flow buffers sharing the same link), each having resources (buffers and queues) As shown in FIG. 11, independent flow control is performed. Thereby, even if the buffer of one virtual channel becomes full (full), the transfer of another virtual channel can be performed. In other words, it can be used effectively by physically dividing one link into a plurality of virtual channels. For example, as shown in FIG. 11, when a route link is divided into a plurality of devices via a switch, the priority of traffic of each device can be controlled (arbitration means). VC0 is indispensable, and other virtual channels (VC1 to VC7) are mounted in accordance with the cost performance trade-off. The solid line arrow in FIG. 11 indicates the default virtual channel (VC0), and the broken line arrow indicates the other virtual channels (VC1 to VC7).

  Within the transaction layer, a traffic class (TC) is mapped to a virtual channel (VC). One or more traffic classes (TC) can be mapped to one virtual channel (VC) (when the number of virtual channels (VC) is small). In a simple example, it can be considered that each traffic class (TC) is mapped to each virtual channel (VC) on a one-to-one basis, and all traffic classes (TC) are mapped to the virtual channel VC0. The mapping of TC0-VC0 is essential / fixed, and the other mappings are controlled from the upper software. The software can control the priority of the transaction by using the traffic class (TC).

d. Flow control Flow control (FC) is performed to avoid the overflow of the reception buffer and establish the transmission order. Flow control is done point-to-point between links, not end-to-end. Therefore, it cannot be confirmed that the packet has reached the final partner (completer) by flow control.

  PCI Express flow control is performed on a credit basis (a mechanism that confirms the buffer availability on the receiving side before starting data transfer and prevents overflow and underflow). That is, the receiving side notifies the transmitting side of the buffer capacity (credit value) at the time of link initialization, and the transmitting side compares the credit value with the length of the packet to be transmitted, and transmits the packet only when there is a certain remaining. There are six types of credits.

  Flow control information exchange is performed using data link layer packets (DLLP) in the data link layer. The flow control is applied only to the transaction layer packet (TLP) and not to the data link layer packet (DLLP) (DLLP can always be transmitted / received).

B. Data link layer 154
The main role of the data link layer 154 is to provide a reliable transaction layer packet (TLP) exchange function between two components on the link, as described above.

a. Handling of transaction layer packet (TLP) For the transaction layer packet (TLP) received from the transaction layer 153, a 2-byte sequence number at the beginning and a 4-byte link CRC (LCRC) at the end are added to the physical layer. To 155 (see FIG. 9). The transaction layer packet (TLP) is stored in the retry buffer and retransmitted until a reception confirmation (ACK) is received from the partner. When the transmission of the transaction layer packet (TLP) continues to fail, it is determined that the link is abnormal, and the physical layer 155 is requested to retrain the link. If link training fails, the state of the data link layer 154 transitions to inactive.

  The transaction layer packet (TLP) received from the physical layer 155 is inspected for the sequence number and the link CRC (LCRC). If normal, the transaction layer packet (TLP) is passed to the transaction layer 153.

b. Data link layer packet (DLLP)
A packet generated by the data link layer 154 is called a data link layer packet (DLLP), and is exchanged between the data link layers 154. Data link layer packet (DLLP)
-Ack / Nak: TLP reception confirmation, retry (retransmission)
-InitFC1 / InitFC2 / UpdateFC: Flow control initialization and update-DLLLP for power management
There are different types.

  As shown in FIG. 12, the length of the data link layer packet (DLLP) is 6 bytes. From the DLLP type (1 byte) indicating the type, the information specific to the type of DLLP (3 bytes), and CRC (2 bytes) Composed.

C. Physical layer-logical sub-block 156
The main role of the physical layer 155 in the logical sub-block 156 shown in FIG. 8 is to convert the packet received from the data link layer 154 into a format that can be transmitted by the electrical sub-block 157. It also has a function of controlling / managing the physical layer 155.

a. Data encoding and parallel-serial conversion
PCI Express uses 8B / 10B conversion for data encoding so that consecutive “0” s and “1” s do not continue (in order not to maintain a state where there is no cross point for a long period of time). The converted data is serial-converted and transmitted from the LSB onto the lane as shown in FIG. Here, when there are a plurality of lanes (FIG. 13 illustrates the case of x4 link), data is allocated to each lane in units of bytes before encoding. In this case, it looks like a parallel bus at first glance, but since the transfer is performed independently for each lane, the skew which is a problem with the parallel bus is greatly reduced.

b. Power management and link state As shown in Table 1, a link state of L0 / L0s / L1 / L2 is defined in order to keep the power consumption of the link low.

  L0 is a normal mode, and power consumption is reduced from L0s to L2, but it takes time to return to L0. As shown in FIG. 14, by actively performing active state power management in addition to software power management, it is possible to reduce power consumption as much as possible.

D. Physical layer—Electric sub-block 157
The main role of the physical layer 155 in the electrical sub-block 157 is to transmit the data serialized in the logical sub-block 156 onto the lane, and to receive the data on the lane and pass it to the logical sub-block 156. is there.

a. AC coupling On the transmission side of the link, a capacitor for AC coupling is mounted. This eliminates the need for the DC common mode voltage on the transmission side and the reception side to be the same. For this reason, it is possible to use different designs, semiconductor processes, and power supply voltages on the transmission side and the reception side.

b. De-emphasis
In PCI Express, as described above, processing is performed so that continuous “0” and “1” do not continue as much as possible by 8B / 10B encoding, but continuous “0” and “1” may continue (maximum). 5 times). In this case, it is specified that the transmission side must perform de-emphasis transfer. When bits of the same polarity are consecutive, it is necessary to increase the noise margin of the signal received on the receiving side by dropping the differential voltage level (amplitude) from the second bit by 3.5 ± 0.5 dB. . This is called de-emphasis. Due to the frequency-dependent attenuation of the transmission line, there are many high-frequency components in the case of changing bits, and the waveform on the receiving side becomes small due to attenuation. Becomes larger. For this reason, de-emphasis is performed in order to make the waveform on the receiving side constant.

[Image forming system]
The data transfer apparatus according to the present embodiment includes an image output apparatus such as a printer, an image input apparatus such as a scanner, a digital copier having both of these, an image forming apparatus such as an MFP, and other various devices and devices. Is used as a high-speed serial interface in an image forming system including an appropriate combination of the above, and conforms to the PCI Express standard as described above.

  An example of an image forming system to which the data transfer apparatus of this embodiment is applied will be described with reference to FIG. FIG. 15 is a block diagram showing an outline of connections of devices, devices, etc. of an image forming system to which the data transfer apparatus of this embodiment is applied. The image forming system 1 uses a PCI Express standard bus system for serial data transfer. That is, a CPU 11 that centrally controls each part of the image forming system 1 and a system memory 12 that is a work area of the CPU 11 are connected to a root complex 13 of the PCI Express standard. A root complex 13 and a PCI Express standard switch (or switch network) 14 are connected via a PCI Express standard general-purpose bus 15. The PCI Express standard switch (or switch network) 14 is connected to various devices and devices serving as PCI Express standard end points. That is, a hard disk (HDD) unit 21 for storing image data, an image memory unit 22 and a memory unit 23, an image processing unit 24 for performing various image processing, a high-speed network 25 for communicating with an external network, A scanner 26 as an input engine, a plotter 27 as an image output engine, an image input engine, another multifunction device 28 having an image output engine, and the like.

[Arbitration standard]
In such an image forming system, since the data transfer rate required for each device / device is different, it is necessary to adjust the data transfer rate with high accuracy. As a standard for this purpose, priority is given to issuing packet data for each virtual channel VC by using virtual channel means for transmitting packet data of a plurality of traffic by using the serial bus as described above in a time division manner for each virtual channel VC. There is a function to arbitrate (arbitration means).

  FIG. 16 is a schematic block diagram showing a configuration example of a conventional serial transmission circuit (data transfer device) configured according to the arbitration function of the PCI Express standard. The illustrated example shows an example defined in a 4-channel configuration among a maximum of 8 virtual channels VC. The serial transmission circuit 31 receives data 1 to 4 for each channel from the device, and generates packet data 1 to 4 and virtual data for temporarily storing the generated packet data 1 to 4 for each virtual channel VC. The channel buffers (virtual channel means) 33a to 33d and the packet data 1 to 4 stored in the virtual channel buffers 33a to 33d are arbitrated according to the priority defined in advance for each virtual channel VC, and passed through the serial output buffer 34. And an arbitration circuit (arbitration means) 36 for outputting to the signal output circuit 35.

  The illustrated example illustrates the case of an arbitration algorithm for issuing packet data with equal frequency for each virtual channel VC. According to the arbitration, a packet is transmitted from the signal output circuit 35 of the serial transmission circuit 31 to the serial bus. Data 1 to 4 are output equally as shown.

  However, as described above, just by specifying the priority of the packet data issuance frequency for each virtual channel VC as in the arbitration of the virtual channel VC of the PCI Express standard, the degree of freedom of priority control is low, and multiple traffic It is difficult to control the data transfer rate with high accuracy for packet data.

[Data transfer device]
Therefore, in the serial transmission circuit (data transfer apparatus) of the present embodiment, paying attention to the payload size of packet data transmitted for each virtual channel VC, the payload size of the packet data to be issued can be arbitrarily designated for each virtual channel VC. Packet data having a payload size designated for each virtual channel VC is generated and output to the arbitration circuit 36.

  FIG. 17 is a schematic block diagram showing a configuration example of the serial transmission circuit (data transfer device) 37 of the present embodiment. The same parts as those shown in FIG. 16 are denoted by the same reference numerals, and description thereof is also omitted. In the serial transmission circuit 37 of the present embodiment, a payload size determination circuit (payload size determination means) 38 having a logic configuration that specifies the payload size of packet data to be transmitted for each virtual channel VC is added. The packet generation circuit 32 is provided as packet generation means for generating packet data for each virtual channel VC according to the payload size specified by the determination of the payload size determination circuit 38 and outputting the packet data to the arbitration circuit 36. Here, “payload size” means the size of the data portion other than the header information in the size of the entire packet data. The arbitration circuit 36 is provided with means (not shown) for detecting the packet issuance frequency for each virtual channel VC, and the payload size determination circuit stores information on the detected packet issuance frequency for each virtual channel VC. 38 to the output.

  The means for detecting the packet issuance frequency is assumed to be the PCI Express standard round robin or the way as an algorithm for each virtual channel VC of the arbitration circuit 36 when the PCI Express standard is assumed as in this embodiment. A means for detecting whether Ted Round Robin (Weighted Round Robin) or Strict (details will be described later) is used, and in particular, Weighted Round Robin (WRR) is used. Is detected, the packet issue frequency for each virtual channel VC is detected with reference to the arbitration table 39 for each virtual channel defined by the PCI Express standard. Since the example shown in FIG. 17 assumes a round robin (RR) with an issuance frequency equal to an even number, the arbitration table 39 shows an example of an even table with a round robin (RR) (that is, each The data examples 1234, 1234,... Issued in the order of 1, 2, 3, and 4 in the order of 1, 2, 3, and 4 are shown. However, in the case of weighted round robin (WRR), 1111, 1212 are shown. , 1213, 1234,...

  For the payload size determination circuit 38, a desired priority setting value of the data transfer rate of the packet data for each virtual channel VC can be appropriately designated by an input operation from an external operation unit or the like. For example, in the case of 4 channels, the priority setting values of the packet data 1 to 4 are specified by a ratio such as data 1: data 2: data 3: data 4 = w: x: y: z.

  In the payload size determination circuit 38, the ratio between the virtual channels VC of the integrated value of the packet issue frequency for each detected virtual channel VC and the payload size of the packet data issued for each virtual channel is designated from the outside. The payload size of the packet data is determined for each virtual channel VC so as to be a value closest to the ratio w: x: y: z of the priority setting value of the data transfer rate for each virtual channel VC. It has a function. In the illustrated example, the payload size of the packet data 1 to 4 for each virtual channel VC is determined and specified as packet data 1> 2> 3> 4 by the payload size determination circuit 38 as indicated by the difference in the square size. It is assumed that The payload size determination process by the payload size determination circuit 38 or the like may be realized by a program process by the CPU.

  FIG. 18 is a schematic flowchart illustrating an example of payload size determination processing for each virtual channel. Here, the ratio of the desired priority setting values of the respective packet data 1 to 4 is designated as data 1: data 2: data 3: data 4: data w = x: y: z by an external operation. It is assumed that Also, assume that the virtual channel is an example of 4 channels, and the payload sizes of the virtual channels 1 to 4 are set as A, B, C, and D.

First, the detection means provided for the arbitration circuit 36 detects the packet issue frequency for each virtual channel VC (steps S1 and S2). This process is basically the detection of the arbitration algorithm method as described above, but in the case of weighted round robin (WRR), the arbitration table 39 for each virtual channel is read (S1), and from this table. By calculating the number of packet issuances for each virtual channel (S2), the packet issuance frequency for each virtual channel VC is detected. Next, the integrated value of the calculated issuance count (detected packet issuance frequency) and the payload size of the packet data is used as the data transfer amount Sum for each of the virtual channels 1 to 4. A, B, C, D A = Issuance count 1 x A
Sum B = number of issuances 2 x B
Sum C = number of issues 3 x C
Sum D = number of issues 4 x D
The ratio of these data transfer amounts (integrated values) between virtual channels Sum A: Sum B: Sum C: Sum D is the ratio between the virtual channels of the priority setting values, 1: data 2: data 3: data 4 = w: x: y: z, that is,
w: x: y: z = Sum A: Sum B: Sum C: Sum D
Payload sizes A, B, C, and D are determined for each of the virtual channels 1 to 4 (S3). In this determination process, it may be a fraction with respect to the ratio, so it does not always match exactly. Therefore, the point is to determine the closest value.

  The thus determined payload sizes A, B, C, and D for the virtual channels 1 to 4 are notified to the packet generation circuit 32 (S4), and the packet generation circuit 32 determines for each of the virtual channels 1 to 4. Data transfer is started by generating payload size packet data and outputting it to the arbitration circuit 36 (S5).

  Therefore, according to the example shown in FIG. 17, in addition to the arbitration algorithm for prioritization by round robin (RR) for issuing packet data with equal frequency for each virtual channel VC, the determination of the payload size of the packet data The serial bus output example in the case of including adjustment according to the above is shown. From the signal output circuit 35 of the serial transmission circuit 37 to the serial bus, the packet data 1 to 4 is a ratio between the virtual channels of the priority setting values, that is, Data 1: Data 2: Data 3: Data 4: = According to w: x: y: z, the data transfer rate is controlled and output so that the data transfer amount is given priority in the order of packet data 1> 2> 3> 4 The

  That is, when a plurality of virtual channels VC are used in each link, the payload size of the packet data for each virtual channel VC is set to the priority specified from the outside with respect to the algorithm for prioritizing arbitration for each virtual channel VC. By appropriately determining the combination for matching the set value, it is possible to control the data transfer rate with high accuracy as desired between the devices and devices.

  FIG. 19 is a block diagram illustrating a simple configuration example of the image forming system, and FIG. 20 is an explanatory diagram illustrating a state of transfer rate adjustment accompanying a payload size change. The effect of the present embodiment will be described with reference to a simple example shown in FIG. In FIG. 19, a connection engine 43 having two plotters 41 and 42 and a controller 44 are connected via a switch 14 by a single link 15 (high-speed serial bus) (for different ports 0 and 1 of the switch 14). The connection engine 43 and the controller 44 are each physically connected by one port A and B), and it is necessary to adjust the packet data transfer rate between the connection engine 43 and the controller 44. is there. Note that the plotter 41 is a device having a different print processing speed, such as a laser printer, and a plotter 42 is an inkjet printer, for example, and means a device having a different data transfer rate in the same direction of packet data transfer.

  In this case, as the arbitration algorithm of the virtual channel VC, even if only the round robin (RR) that issues packet data with an equal frequency is supported by the standard, as described above, the controller 44 side By determining the payload size of the packet data transferred to the plotters 41 and 42 to match the ratio of the desired priority setting value and transferring the data from the controller 44 side, the desired data with high accuracy is obtained. The transfer rate can be controlled. That is, by using the data transfer device as described above for each virtual channel of each port, when plotter data having different speeds is simultaneously transferred to the plurality of plotters 41 and 42 as packet data, according to the speed ratio, By designating the priority setting value for each virtual channel, the payload size is automatically adjusted in the payload size determination circuit 38, and the data transfer rate can be adjusted with high accuracy.

  For example, FIG. 20A shows that the ratio of the priority setting values between the plotters 41 and 42 is 4: 1 under the condition that only the round robin (RR) is supported by the standard as the arbitration algorithm of the virtual channel VC. Is specified (when the plotter 41 is four times faster than the plotter 42), the payload size determination circuit 38 sets the payload size of the virtual channel for the plotter 41 to the payload size of the virtual channel for the plotter 42. In other words, it is possible to transfer data that is four times the data transfer amount to the plotter 42 per unit time as desired.

  Further, FIG. 20B shows that the ratio of the priority setting values between the plotters 41 and 42 is 2: 1 under the condition that only the round robin (RR) is supported by the standard as the arbitration algorithm of the virtual channel VC. Is specified (when the plotter 41 is twice as fast as the plotter 42), the payload size determination circuit 38 sets the payload size of the virtual channel for the plotter 41 to the payload size of the virtual channel for the plotter 42. It is shown that the data can be transferred twice as much as the data transfer amount to the plotter 42 per unit time as desired.

  By the way, in the above description, the arbitration algorithm of the virtual channel VC has been described as an example of the round robin (RR) of the PCI Express standard. However, as the arbitration algorithm, the frequency weighted for each virtual channel is also used. Packet data issuance method (weighted round robin (WRR if the PCI Express standard is used), packet data is issued with a fixed priority for each virtual channel (strict if the PCI Express standard is used) (Strict)) The arbitration algorithm of these virtual channels VC will be described.

  FIG. 21 is a characteristic diagram showing an example of basic characteristics of each system of these arbitration algorithms. In addition, since it is necessary to observe the dynamic fluctuation | variation for the measurement result of arbitration characteristic, in FIG. 21, it shows as a data integration figure. In the figure, the horizontal axis represents time, and the vertical axis represents the amount of transferred data (integrated value). Note that the payload size is a measurement example under the condition that all four types are fixed to 128 bytes (about 8000). FIG. 21A shows a strict characteristic, which is an algorithm for simply flowing data in order. FIG. 21 (b) shows the round robin (RR) characteristic, which is an algorithm for flowing four types of data while dividing them evenly in order. In the drawing, the four types of characteristics are represented by overlapping one characteristic. ing. FIG. 21 (c) shows an example of characteristics when weighted round robin (WRR) characteristics are set so that data transfer is performed at a ratio of 1: 2: 4: 8 for the four types. Data transfer of one traffic class Is completed, the data is transferred while changing the ratio of the remaining traffic class, such as 8: 4: 2 and further 8: 4.

  FIG. 22 shows the basic characteristics of the payload when measured by the strict algorithm. FIG. 22 shows an example in which the designation of the payload size of each traffic is changed in order from the left side, such as 8, 16, 32, and 64 Bytes. According to FIG. 22, paying attention to the inclinations of the four traffics, it can be seen that the smaller the payload size, the slower the transfer rate, and the larger the payload size, the larger the transfer rate. Such payload characteristics are the same when other arbitration algorithms are used. That is, it can be seen that the traffic adjustment can be performed more finely by combining the setting of the arbitration algorithm of the virtual channel VC and the designation of the payload size.

  FIG. 23 is a characteristic diagram for explaining the interaction between the payload size and the arbitration algorithm of the virtual channel VC. As described above, since the transfer rate changes depending on the combination of the payload size and the arbitration algorithm of the virtual channel VC, they affect each other. The influence will be described with reference to a typical example shown in FIG.

  FIG. 23A shows a case where the arbitration algorithm is round robin (RR) and the payload size is fixed at 8 Bytes, and FIG. 23B shows the arbitration algorithm is round robin (RR) and the payload size is in order. FIG. 23 (c) shows a weighted round robin (WRR) weighted with an arbitration algorithm of 1: 2: 4: 8. This shows a case where the payload size is specified non-uniformly in order, such as 8, 16, 32, and 64 bytes.

  First, FIG. 23 (a) and FIG. 23 (b) show an example in which only the payload size of the traffic allocated to the four virtual channels VC is different, but there is a great difference in the characteristics. In particular, in the setting example shown in FIG. 23B, although the arbitration algorithm is round robin (RR), the weighted round robin (WRR), which is an arbitration algorithm when the payload size of each traffic is the same, is used. This is equivalent to the case characteristics.

  FIG. 23B and FIG. 23C show an example in which only the arbitration algorithm is different, but the characteristics are clearly different in each 8 kB data transfer section.

  Contrary to the above case, the parameter settings are completely different, but may have similar characteristics. FIG. 23 (a) and FIG. 23 (c) show examples in which the payload size and arbitration algorithm are different. That is, although all of the settings are separate, the slopes of the four traffics are almost equal (although, in the example shown in FIG. 23C, a difference corresponding to the header overhead occurs).

  As described above, there are a plurality of methods as a determination method for obtaining a target average data transfer rate that is a priority setting value designated from the outside. By effectively utilizing this degree of freedom of selection, even if there are other structural design constraints (for example, buffer size, number of tag stages, etc.), target traffic control can be performed. In order to change the arbitration algorithm setting of the virtual channel VC, it is necessary to change the arbitration table of the virtual channel VC with config write. However, depending on how the payload size is determined, depending on how the user logic is created. Fast change is possible. As a result, for example, a dynamic average rate change is handled by a payload size determination change that can be handled at high speed, and a static average rate change is handled by a change in the arbitration algorithm of the virtual channel VC. Is possible.

  Another embodiment of the data transfer circuit will be described with reference to FIGS. FIG. 24 is a schematic block diagram showing a configuration example of the serial transmission circuit (data transfer device) 51 of the present embodiment. The same parts as those shown in FIG. 17 are denoted by the same reference numerals, and description thereof is also omitted. In the serial transmission circuit 51 of the present embodiment, in addition to the packet issue frequency detection circuit 52 as means for detecting the packet issue frequency for each virtual channel, means for detecting the payload size of the packet data issued for each virtual channel The data transfer rate between virtual channels is provided by feedback control based on the packet issuance frequency for each virtual channel detected by these detection circuits 52 and 53 and the payload size of the packet data. Payload size determination circuit 54 determines the modified payload size of the packet data for each virtual channel so that the ratio of the packet data approaches the ratio between the virtual channels of the priority setting value of the data transfer rate for each virtual channel specified from the outside Is the payload size determination means It is provided. The payload size determination processing by the payload size determination circuit 54 or the like may be realized by program processing by the CPU.

  FIG. 25 is a schematic flowchart illustrating an example of feedback control of payload size determination processing for each virtual channel. Here, as the ratio of the desired priority setting values of the respective packet data 1 to 4, as in the case of the above-described embodiment, data 1: data 2: data 3: data by an input operation from the outside. It is assumed that the ratio is specified as 4 = w: x: y: z. The virtual channel is an example of 4 channels, and the payload size of each virtual channel set at a certain time is A, B, C, and D.

  First, the packet generation circuit 32 causes the arbitration circuit 36 to issue packet data for each of the virtual channels 1 to 4 (S11), and the packet data is actually issued according to the priority set by the arbitration circuit 36 (S12). ). When the packet data is issued, the packet issue frequency detection circuit 52 sequentially receives the virtual channel number from which the packet data was issued, thereby detecting the packet issue frequency for each virtual channel, and for each issued virtual channel. The payload size is detected by sequentially receiving the payload size of the packet data in the payload size detection circuit 53 (S13).

The sum of the data transfer amounts for each of the virtual channels 1 to 4 is summed. When A, B, C, and D are set, the payload size at that time is sequentially accumulated for each of the received virtual channel numbers 1 to 4 (S14). That is, if the virtual channel number is 1, Sum A = Sum Summation processing of A + A, if the virtual channel number is 2, Sum B = Sum B + B integration process, if the virtual channel number is 3, Sum C = Sum Summation process of C + C, if the virtual channel number is 4, Sum D = Sum Integration processing of D + D is performed. By such an integration process, the data transfer rate ratio Sum between the virtual channels 1 to 4 A: Sum B: Sum C: Sum D is calculated. Subsequently, the ratio Sum between virtual channels of these calculated data transfer amounts (integrated values) A: Sum B: Sum C: Sum By comparing D with the ratio data 1: data 2: data 3: data 4: data 4 = w: x: y: z of the priority setting value, the current priority for each virtual channel (transfer rate) Is determined (S15). A process of relatively correcting the size relationship of the payload size is performed in accordance with the result of the priority as the determination result, and the payload size for each virtual channel is determined (S16).

  That is, as a result of the comparison determination, if there is a virtual channel having a transfer rate lower than the priority setting value w: x: y: z, the payload size of the packet data issued from the virtual channel is determined at that time. Modify to be larger than the set payload size (current value). Conversely, when there is a virtual channel with a transfer rate higher than the priority setting value w: x: y: z, the payload size of the packet data issued from the virtual channel is smaller than the current value. Modify to be.

  The correction of the payload size in step S16 is relative between the virtual channels. For example, as a result of the comparison determination, a virtual channel having a lower transfer rate than the priority setting value w: x: y: z If it exists, the payload size of the packet data issued from other virtual channels other than the virtual channel is corrected to be smaller than the current value, or conversely, the priority setting value w: x : If there is a virtual channel with a transfer rate higher than y: z, the payload size of packet data issued from a virtual channel other than the virtual channel is modified to be larger than the current value. Also good. Furthermore, when there is a virtual channel with a lower transfer rate than the priority setting value w: x: y: z, the payload size of the packet data issued from the virtual channel is larger than the current value. At the same time, the payload size of packet data issued from other virtual channels other than the virtual channel may be modified to be smaller than the current value. Also, when there is a virtual channel with a transfer rate higher than the priority setting value w: x: y: z, the payload size of packet data issued from the virtual channel is made smaller than the current value. Simultaneously with the correction, the payload size of packet data issued from a virtual channel other than the virtual channel may be corrected to be larger than the current value.

  In any case, according to such a processing result, the values of the payload sizes A, B, C, and D for each virtual channel are updated and notified to the packet generation circuit 32 (S17). The packet generation circuit 32 issues packet by generating packet data of the payload size determined for each of the virtual channels 1 to 4 and outputting the packet data to the arbitration circuit 36 (S11).

  According to the present embodiment, by determining the payload size of the packet data while dynamically correcting based on feedback control so as to obtain the priority setting value of the required data transfer rate specified from the outside, Compared with the case where the data transfer rate is adjusted only by priority arbitration by the arbitration circuit 36, it is possible to control the data transfer rate with high accuracy with a higher degree of freedom.

It is a block diagram which shows the structural example of the existing PCI system. FIG. 2 is a block diagram illustrating a configuration example of a PCI Express system. It is a block diagram which shows the structural example of the PCI Express platform in desktop / mobile. It is a schematic diagram which shows the structural example of the physical layer in the case of x4. It is a schematic diagram which shows the example of lane connection between devices. It is a block diagram which shows the logical structural example of a switch. (A) is a block diagram showing an existing PCI architecture, and (b) is a block diagram showing a PCI Express architecture. It is a block diagram which shows the hierarchical structure of PCI Express. It is explanatory drawing which shows the format example of a transaction layer packet. It is explanatory drawing which shows the configuration space of PCI Express. It is a schematic diagram for demonstrating the concept of a virtual channel. It is explanatory drawing which shows the format example of a data link layer packet. It is a schematic diagram which shows the byte striping example in x4 link. It is a time chart which shows the example of control of active state power management. 1 is a block diagram schematically showing a configuration example of an image forming system of an embodiment. It is a schematic block diagram which shows the structural example of the conventional serial transmission circuit comprised according to the arbitration function of the PCI Express specification. It is a schematic block diagram which shows the structural example of the serial transmission circuit of this Embodiment. It is a schematic flowchart which shows the payload size determination process example for every virtual channel. 1 is a block diagram illustrating a simple configuration example of an image forming system. It is explanatory drawing which shows the mode of the transfer rate adjustment accompanying a payload size change. It is a characteristic view which shows the example of a basic characteristic of each system of the algorithm of arbitration. It is a basic characteristic diagram of a payload when measured by a strict algorithm. It is a characteristic view for demonstrating interaction with a payload size and the arbitration algorithm of virtual channel VC. It is a schematic block diagram which shows the structural example of the serial transmission circuit of another embodiment. It is a schematic flowchart which shows the example of feedback control of the payload size determination process for every virtual channel.

Explanation of symbols

32 packet generation means 33a-33d virtual channel means 36 arbitration means 37 data transfer device 38 payload size determination means 41, 42 device 43 engine 44 controller 51 data transfer device 52 means for detecting packet issue frequency 53 means for detecting payload size 54 Payload size determination means

Claims (14)

In a data transfer apparatus having virtual channel means for transmitting packet data of a plurality of traffics by using a serial bus in a time division manner in units of virtual channels, and arbitration means for arbitrating the priority for issuing packet data for each virtual channel,
Means for detecting a packet issue frequency for each virtual channel;
A designation means for designating a setting value of a data transfer rate for each virtual channel;
The ratio between the virtual channels of the integrated value of the detected packet issue frequency for each virtual channel and the payload size of the packet data issued for each virtual channel is determined for each virtual channel specified by the specifying unit. Payload size determination means for determining the payload size of packet data for each virtual channel so as to be a value that approaches the ratio of the setting value of the data transfer rate ;
Packet generation means for generating packet data of a payload size determined for each virtual channel and outputting the packet data to the arbitration means;
A data transfer device comprising: In a data transfer apparatus having virtual channel means for transmitting packet data of a plurality of traffics by using a serial bus in a time division manner in units of virtual channels, and arbitration means for arbitrating the priority for issuing packet data for each virtual channel,
Means for detecting a packet issue frequency for each virtual channel;
A designation means for designating a setting value of a data transfer rate for each virtual channel;
Means for detecting a payload size of packet data issued for each virtual channel;
By the feedback control based on the detected packet issuance frequency for each virtual channel and the payload size of the detected packet data for each virtual channel, the ratio of the data transfer rate between the virtual channels is specified by the specifying unit. Payload size determination means for determining a modified payload size of packet data for each virtual channel so as to approach a ratio of a set value of a data transfer rate for each virtual channel;
Packet generation means for generating packet data of a payload size determined for each virtual channel and outputting the packet data to the arbitration means;
A data transfer device comprising: The payload size determining means includes
Means for calculating a ratio of a data transfer rate between the virtual channels by an integration process of the detected packet issue frequency for each virtual channel and the payload size of the detected packet data for each virtual channel;
It calculated the level of priority for each of the virtual channels as compared to the ratio between the virtual channels of the set value of the data transfer rate for each virtual channel a ratio of the data transfer rate is specified from the outside between the virtual channels Means for determining
Means for determining the payload size for each virtual channel by relatively correcting the magnitude relation of the payload size of the packet data between the virtual channels according to the determined priority level result for each virtual channel; ,
The data transfer apparatus according to claim 2, further comprising: Said means for determining is the determined said high and low priority for each virtual channel a result, when the low virtual channel priority than the set value is present, the payload of the packet data to which the virtual channel is issued 4. The data transfer apparatus according to claim 3, wherein the size is corrected so as to be larger than a current value. Said means for determining is the determined said high and low priority for each virtual channel a result, when the low virtual channel priority than the set value is present, the other virtual channels other than the virtual channel 4. The data transfer apparatus according to claim 3, wherein the payload size of the packet data to be issued is corrected so as to be smaller than a current value. Said means for determining is the determined said high and low priority for each virtual channel a result, when the low virtual channel priority than the set value is present, the payload of the packet data to which the virtual channel is issued 4. The data transfer according to claim 3, wherein the size is larger than the current value, and the payload size of packet data issued by another virtual channel other than the virtual channel is modified to be smaller than the current value. apparatus. Said means for determining is the determined said high and low priority for each virtual channel a result, when the high virtual channel priority than the set value is present, the payload of the packet data to which the virtual channel is issued 7. The data transfer device according to claim 3, wherein the size is corrected so as to be smaller than a current value. Said means for determining is the determined said high and low priority for each virtual channel a result, when the high virtual channel priority than the set value is present, the other virtual channels other than the virtual channel 7. The data transfer device according to claim 3, wherein the payload size of the packet data to be issued is corrected so as to be larger than a current value. Said means for determining is the determined said high and low priority for each virtual channel a result, when the high virtual channel priority than the set value is present, the payload of the packet data to which the virtual channel is issued 7. The size of the packet data issued by another virtual channel other than the virtual channel is corrected so that the size is smaller than the current value and larger than the current value. A data transfer apparatus according to any one of the above.   10. The data transfer device according to claim 1, wherein the serial bus is a PCI Express standard serial bus.   11. The algorithm for each virtual channel (Virtual Channel) of the arbitration means is the PCI Express standard round robin or weighted round robin. Data transfer device.   The means for detecting the packet issuance frequency is an algorithm for each virtual channel of the arbitration means, either the round robin of the PCI Express standard or the weighted round robin. The data transfer apparatus according to claim 11, wherein the data transfer apparatus is means for detecting whether or not is used.   The means for detecting the packet issue frequency is when detecting that the weighted round robin of the PCI Express standard is used as an algorithm for each virtual channel of the arbitration means. 13. The data transfer apparatus according to claim 12, wherein the packet transfer frequency for each virtual channel is detected by referring to an arbitration table for each virtual channel defined by the PCI Express standard.   An engine having a plurality of devices having different data transfer rates required in the same packet data transfer direction, a controller for controlling and driving the engine, and one controller between these controllers and the devices in the engine 14. An image forming system comprising: an interface by a serial data transfer device according to claim 1 connected by a serial bus using a link of

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