JP4459969B2 - PLL synthesizer - Google Patents

Description

  The present invention relates to a PLL synthesizer used in a transmission / reception apparatus.

  FIG. 8 shows a configuration example of a conventional integer frequency division type PLL synthesizer. In FIG. 8, an integer frequency division type PLL synthesizer includes a reference oscillator 1, a reference frequency divider 2, a phase comparator 3, a loop filter 4, a voltage controlled oscillator (VCO) 5, a frequency divider that outputs a highly accurate reference frequency signal. It is composed of a variable integer frequency divider 6A having a variable circumferential ratio and an integer.

  The output signal of the voltage controlled oscillator 5 is branched and input to the variable integer frequency divider 6A, and frequency-divided and fed back as one input of the phase comparator 3. The reference frequency signal output from the reference oscillator 1 is frequency-divided by the reference frequency divider 2 and provided as the other input of the phase comparator 3. The phase comparator 3 compares the phases of the two input signals, gives the output signal to the voltage controlled oscillator 5 via the loop filter 4, and controls the oscillation frequency to correspond to the reference frequency.

In the PLL synthesizer having such a configuration, it is necessary to increase the output frequency of the reference frequency divider 2 in order to shorten the pull-in time. Here, the initial output frequency of the reference frequency divider 2 is set to fr = Δf, and the frequency dividing ratios taken by the variable integer frequency divider 6A are..., N−1, N, N + 1,.
Then, the output frequency of the voltage controlled oscillator 5 after the pull-in is
..., (N-1)? F, N? F, (N + 1)? F, ...
Thus, there are frequency channels with an interval Δf.

In order to shorten the pull-in time, the output frequency of the reference frequency divider 2 is set to fr = LΔf which is L times (L is an integer), and the frequency division ratio taken by the variable integer frequency divider 6A is ..., N / L-1 , N / L, N / L + 1,.
Then (N / L is an integer), the output frequency of the voltage controlled oscillator 5 after the pull-in is
..., (N-L) Δf, NΔf, (N + L) Δf, ...
It becomes. At this time, since the frequency changes with the interval LΔf, there is a frequency channel that cannot be used for the frequency channel with the interval Δf, and there is a problem that the convergence time cannot be necessarily shortened.

  FIG. 9 shows a configuration example of a conventional fractional frequency division (fractional N) PLL synthesizer. The difference from the integer frequency division type PLL synthesizer shown in FIG. 8 is that a variable fractional frequency divider 6B is used instead of the variable integer frequency divider 6A.

The output frequency of the reference frequency divider 2 is set to fr = LΔf which is L times (L is an integer), and the division ratios taken by the variable fractional divider 6B are N / L, (N + 1) / L, (N + 2) / L , ...
Then, the output frequency of the voltage controlled oscillator 5 after the pull-in is
NΔf, (N + 1) Δf, (N + 2) Δf,...
Since the frequency changes at the interval Δf, all frequency channels can be used.

  As described above, the fractional frequency division (synchronization type) PLL synthesizer can increase the output frequency of the reference frequency divider 2 without increasing the variable frequency step width, so that the integer frequency division type PLL synthesizer can be used. The pull-in time can be shortened compared to.

However, in this method, since the output of the phase comparator 3 changes with periodicity, the control voltage of the voltage controlled oscillator 5 has periodicity, and the output of the voltage controlled oscillator 5 causes spurious. This spurious is undesirable because it causes interchannel interference in a steady state where the frequency of the PLL synthesizer is constant. As a method for reducing this spurious, a method using a phase error diffusion circuit has been proposed (Non-Patent Document 1).
Toshifumi Adachi, et al., "High-speed frequency switching synthesizer using fractional frequency division", IEICE Transactions C-1, Vol.J76-C-1, No.11, pp.445-452, 1993 11 Moon

  Since a PLL synthesizer using a fractional frequency divider can increase the output frequency of the reference frequency divider without increasing the variable frequency step width, the pull-in time can be shortened and high-speed activation can be realized. However, there is a problem that the output is spurious due to the periodicity of the control voltage of the voltage controlled oscillator. On the other hand, when the phase error diffusion circuit is used, although a spurious reduction effect can be expected, there is a problem that a large-scale circuit configuration is required and power consumption increases. As described above, there is no conventional PLL synthesizer that simultaneously satisfies the following three points: (1) high-speed startability, (2) low power consumption, and (3) low spurious property in a steady state.

  An object of the present invention is to provide a PLL synthesizer that can simultaneously satisfy high-speed startability, low power consumption, and low spurious performance in a steady state, and that optimizes parameters that affect performance.

In the first invention, a voltage-controlled oscillator that outputs a signal having an oscillation frequency corresponding to an input control signal and an output signal of the voltage-controlled oscillator are branched and input, and the frequency is divided by a variable division ratio. A variable frequency divider that outputs, a reference oscillator that outputs a high-precision reference frequency signal, a reference frequency divider that divides the reference frequency signal by a predetermined frequency division ratio, and an output signal of the reference frequency divider And a phase comparator that outputs the phase difference signal by inputting the output signal of the variable frequency divider, and a loop filter that smoothes the phase difference signal and gives it to the voltage controlled oscillator as a control signal, The phase-locked loop (PLL) configuration that feeds back the output signal of the voltage controlled oscillator to the phase comparator through the variable frequency divider allows the frequency and phase of the output signal of the voltage controlled oscillator to be compared with the output signal of the reference frequency divider. Sync pull In the PLL synthesizer, the variable frequency divider functions as a variable integer frequency divider whose integer division ratio is an integer and a variable fractional frequency divider whose average frequency division ratio per clock is represented by a fraction. The switchable variable frequency divider includes means for switching the functions of the two frequency dividers according to an external switching signal. The reference frequency divider can be switched with a frequency division ratio by an external switching signal. Type reference frequency divider, which makes the switchable variable frequency divider function as a variable fractional frequency divider, and the frequency of the output signal of the switchable reference frequency divider becomes greater than the frequency channel interval of the output signal of the voltage controlled oscillator The fractional frequency dividing mode for setting the frequency dividing ratio and the switching type variable frequency divider function as a variable integer frequency divider, and the frequency of the output signal of the switching type reference frequency divider is the output signal of the voltage controlled oscillator. Equal to the frequency channel spacing of So as to generate a switching signal for switching between the integral dividing mode for setting the division ratio, comprising a switching control circuit for delivering to the switching type variable frequency divider and switching type reference divider, the switching control circuit, The convergence time Tacq from the time of PLL startup to the convergence is set, and the convergence time Tacq is determined with respect to the braking coefficient ζ, the natural frequency ω _n , and the initial frequency difference Ω ₀ .
Tacq = Ω ₀ ² / (2ζω _n ³ )… (a)
Is expressed as
0.5 ≦ ζ ≦ 1
The frequency division ratio of the fractional frequency division mode is set so that the natural frequency ω _n satisfies the equation (a) when the PLL is started, and the loop filter is switched at the timing Ts (= Tacq) when the frequency error is considered to have converged. Instead, the frequency division ratio is switched to the integer frequency division mode.

In the second invention, in the same configuration as the first invention, the switching control circuit sets a convergence time Tacq from the time of PLL startup until convergence, and the convergence time Tacq is determined by the braking coefficient ζ and the natural frequency ω. _n , for the initial frequency difference Ω ₀ and the phase error φf that is considered converged,
Tacq = (1 / ζω _n ) ln (Ω ₀ / (φfω _n )) (b)
Is expressed as
0.5 ≦ ζ ≦ 1
And set the frequency division ratio of the fractional frequency division mode so that the natural frequency ω _n satisfies the equation (b) when the PLL is started, and switch the loop filter at the timing Ts (= Tacq) when the frequency error is considered to have converged. Instead, the frequency division ratio is switched to the integer frequency division mode.

According to a third aspect of the present invention, in the same configuration as the first aspect, the switching control circuit sets a convergence time Tacq from the start of the PLL to the convergence, and the convergence time Tacq is determined by the braking coefficient ζ and the natural frequency ω. _n , for the initial frequency difference Ω ₀ ,
Tacq = Ω ₀ ² / (2ζω _n ³ )… (a)
Is expressed as
0.5 ≦ ζ ≦ 1
When the PLL is activated, the frequency division ratio of the fractional frequency division mode is set so that the natural frequency ω _n satisfies the equation (a), and the convergence time Tacq is determined at the timing Ts1 (<Tacq) at which the frequency error is considered to be reduced. For the braking coefficient ζ, natural frequency ω _n , initial frequency difference Ω ₀ , and phase error φf that is considered converged,
Tacq = (1 / ζω _n ) ln (Ω ₀ / (φfω _n )) (b)
Is expressed as
0.5 ≦ ζ ≦ 1
The division ratio of the fractional frequency division mode is set so that the natural frequency ω _n satisfies the equation (b), and an integer is obtained without switching the loop filter at timing Ts2 (= Tacq) at which the frequency error is considered to have converged. In this configuration, the frequency division ratio is switched to the frequency division ratio.

  The PLL synthesizer of the present invention can be operated as a fractional frequency division type during a period from the time of PLL activation to the transition to a steady state in synchronous pull-in, and thereafter can be operated as an integer frequency division type. In particular, by switching the mode from fractional frequency division type to integer frequency division type and performing self-adjustment of parameters by switching the frequency divider without switching the loop filter, high speed start-up performance and low spurious performance in steady state are realized. can do. In addition, since the switching control can be realized with a simple configuration, low power consumption can also be realized.

(Embodiment of PLL Synthesizer of the Present Invention)
FIG. 1 shows an embodiment of a PLL synthesizer of the present invention. 1, the PLL synthesizer of this embodiment includes a reference oscillator 1 that outputs a highly accurate reference frequency signal, a switchable reference frequency divider 11 that can switch a frequency division ratio, a phase comparator 3, a loop filter 4, Voltage controlled oscillator (VCO) 5, switching type variable frequency divider 12 capable of switching between fractional frequency division mode and integer frequency division mode, and switching timing of switching type variable frequency divider 12 are controlled and corresponding to the switching timing The switching control circuit 13 switches the frequency dividing ratio of the switching type reference frequency divider 11. Note that a frequency divider 7 may be provided at the output stage of the voltage controlled oscillator 5, and the output signal of the voltage controlled oscillator 5 may be divided and extracted.

  Here, the frequency of the output signal of the reference oscillator 1 is fr, and the switching type reference frequency divider whose frequency dividing ratio is set corresponding to the setting of the fractional frequency dividing mode or the integer frequency dividing mode of the switching type variable frequency divider 12 The frequency of the output signal of 11 is assumed to be ff or fi (ff> fi), and the frequency of the output signal of the voltage controlled oscillator 5 is assumed to be fv.

  The basic operation of the PLL synthesizer in this embodiment is the same as that of the conventional configuration. That is, the output signal (fv) of the voltage controlled oscillator 5 is branched and input to the switching variable frequency divider 12, and frequency-divided and fed back as one input of the phase comparator 3. The output signal of the reference oscillator 1 (reference frequency signal (fr)) is frequency-divided by the switching-type reference frequency divider 11, and is given as the other input (phase comparison signals (ff, fi)) of the phase comparator 3. The phase comparator 3 compares the phases of the two input signals, gives the output signal to the voltage controlled oscillator 5 via the loop filter 4, and controls it to have a predetermined oscillation frequency.

  A control procedure characteristic of the present embodiment will be described with reference to FIG. The switching control circuit 13 of the PLL synthesizer of this embodiment switches the start state (fractional frequency division mode) from the PLL start time (at the start of pull-in) to the steady state and the steady state (integer frequency division mode). Is controlled by a timer, and the fractional frequency dividing mode is switched to the integer frequency dividing mode at a preset switching time Ts. This will be described in detail below.

First, in the fractional frequency dividing mode (S1 to S3) from when the PLL is started until the switching time ts elapses, the switching control circuit 13 sets the frequency dividing ratio of the switching type reference frequency divider 11 to fr / ff, and the reference A phase comparison signal (ff) is generated from the frequency signal (fr). The frequency ff of the phase comparison signal is larger than the frequency channel interval of the output signal (fv) of the voltage controlled oscillator 5. Further, the switching control circuit 13 uses the switching type variable frequency divider 12 as a fractional frequency divider, and the frequency dividing ratio is fv / ff = Nv + n / m.
Set to. Nv is an integer, and n / m <1.

  In the fractional frequency dividing mode, the synchronous pull-in operation is performed from the PLL startup to the switching time Ts. When the switching time Ts elapses, the switching control circuit 13 shifts from the fractional frequency dividing mode to the integer frequency dividing mode. In the integer frequency dividing mode (S2, S4, S5), the frequency dividing ratio of the switchable reference frequency divider 11 is switched to fr / fi, and the phase comparison signal (fi) is generated from the reference frequency signal (fr). The frequency fi of the phase comparison signal at this time is equal to the frequency channel interval of the output signal (fv) of the voltage controlled oscillator 5. That is, when the switching time Ts elapses, the frequency division ratio of the switchable reference frequency divider 11 is switched so that the frequency of the phase comparison signal becomes a frequency fi equal to the frequency channel interval of the frequency fv. Further, the switching control circuit 13 uses the switching variable frequency divider 12 as an integer frequency divider and switches the frequency dividing ratio N to fv / fi to perform the phase and frequency synchronization operation.

By the way, in the PLL synthesizer, the time required for convergence when the initial frequency difference and the phase error are large (convergence time) Tacq occupies most of the time for pulling in during the cycle slip as shown in FIG. When configured with a general low-pass filter (RC circuit) and a charge pump circuit as shown in 1) to (3), with respect to the braking coefficient ζ, natural frequency ω _n , and initial frequency difference Ω ₀ ,
Tacq = Ω ₀ ² / (2ζω _n ³ ) (1)
(A. Blanchard, “Phase-locked loops, application to coherent receiver design”, John Wiley & Sons, pp. 241-278, 1975). In FIG. 3, the horizontal axis represents phase, and the vertical axis represents frequency.

Here, if the gain Kp of the phase comparator 3, the conversion gain Kv of the voltage controlled oscillator 5, the gain K ₁ of the loop filter 4 shown in FIG. 4, the capacitor C, the resistor R ₂ , and the gain g _m of the charge pump circuit, braking is performed. The coefficient ζ and the natural frequency ω _n are
_{ζ = (τ 2/2)} ω n ... (2)
ω _n = (2πK ₁ KpKv / τ ₁ N) ^1/2 (3)
τ ₁ = C / g _m (time constant)
τ ₂ = R ₂ C (Time constant)
It is expressed. In _order to enable rapid convergence under a condition where the natural frequency ω _n is constant, it is common to set the braking coefficient ζ to 0.5 to 1.

However, in the conventional integer frequency division type PLL synthesizer, the frequency fi of the phase comparison signal can be set only to the frequency channel interval of the output signal (fv) of the voltage controlled oscillator 5, and the natural frequency ω _n is also the phase comparison signal. Since it is about 1/10 of the frequency fi (translated by Tadahiro Kuroda, “RF Microelectronics”, Maruzen, p.289, 2002), the natural frequency ω _n cannot be set in accordance with the desired convergence time.

Therefore, in the frequency division mode switching type PLL synthesizer of the present embodiment, a convergence time Tacq from the start of the PLL (at the start of synchronization) to the convergence is set, and braking is performed in the fractional frequency division mode with respect to the convergence time Tacq. The frequency division ratio N is set so that the coefficient ζ is 0.5 to 1 and the natural frequency ω _n satisfies the equation (1). That is, from the equations (1) and (3), ω _n = Ω ₀ ² / (2ζTacq) ^1/3 (4)
N = 2πK ₁ KpKv / (τ ₁ ω _n ² ) (5)
The frequency division ratio N is set based on the above.

Then, as shown in FIG. 5, the division ratio N of the switchable variable frequency divider 12 is divided by an integer without switching the loop filter 4 at the switching time Ts (= Tacq) at which the frequency error is considered to have converged. By switching to fv / fi in the mode, the braking coefficient ζ and the natural frequency ω _n in the steady state are self-adjusted.

In the PLL synthesizer of the present embodiment, as described above, the synchronous pull-in operation is initially performed in the fractional frequency division mode, and the integer frequency division mode is entered at the elapse timing of the switching time Ts (Tacq) that the frequency is considered to have converged to a constant value. Switch. Thus, by operating in the fractional frequency division mode from the time of PLL startup to the switching time Ts, the time for the frequency to converge to a constant value can be shortened, and the braking coefficient ζ and the natural frequency ω _n in the steady state after the switching time Ts. By self-adjusting, high-speed synchronization becomes possible, and spurious generation can be suppressed by operating in the integer frequency division mode. That is, low power consumption, high speed start-up, and low spurious in a steady state can be achieved at the same time.

(Second Embodiment)
In the first embodiment, the frequency division mode switching time Ts is set to be equal to the convergence time Tacq from the PLL start-up (synchronization start) to the convergence, but in this embodiment,
Ts <Tacq
Therefore, Ts and Tacq are set respectively. Then, the braking coefficient ζ is set as large as possible in the fractional frequency dividing mode, that is, about several times the braking coefficient ζ (0.5 ≦ ζ ≦ 1) in the integer frequency dividing mode, and the equations (1), (3) ((4 ), (5)), the frequency division ratio N is set.

As a result, the frequency error is switched to the integer frequency dividing mode as shown in FIG. 6 and the switching is performed without switching the loop filter 4 at the timing switching time Ts at which the frequency error is reduced to a sufficiently convergent level (before convergence). By switching the frequency division ratio N of the variable frequency divider 12 to fv / fi in the integer frequency division mode, the braking coefficient ζ and the natural frequency ω _n in the steady state are self-adjusted (0.5 ≦ ζ ≦ 1) and quickly It can be converged.

(Third embodiment)
In the PLL synthesizer of the first embodiment, the initial frequency difference and the phase error are large. However, in this embodiment, it is assumed that the initial frequency and the phase error are small and it is clear that the cycle slip is small. To do.

The time required for convergence (convergence time) Tacq in this case is constituted by a general low-pass filter (RC circuit) and a charge pump circuit as shown in FIGS. 4 (1) to (3). When the braking coefficient ζ, natural frequency ω _n , initial frequency difference Ω ₀ , and phase error φf considered to have converged,
Tacq = (1 / ζω _n ) ln (Ω ₀ / (φfω _n )) (6)
(K. Kishine and H. Onodera, "Acquisition-time estimation for over 10 Gbit / s clock and data recovery ICs", Electronics Letters Vol.41, No.23, Nov.2005 ).

In the PLL synthesizer of the present embodiment, a convergence time Tacq from the PLL startup (synchronization start) to convergence is set, and the braking coefficient ζ is set to 0.5 to 1 in the fractional frequency division mode with respect to the convergence time Tacq. The frequency division ratio N is set so that the frequency ω _n satisfies the expressions (6) and (5).

Then, as shown in FIG. 5, the division ratio N of the switchable variable frequency divider 12 is divided by an integer without switching the loop filter 4 at the switching time Ts (= Tacq) at which the frequency error is considered to have converged. By switching to fv / fi in the mode, the braking coefficient ζ and the natural frequency ω _n in the steady state are self-adjusted. As a result, high-speed synchronization is possible, and spurious generation can be suppressed by operating in the integer frequency division mode. That is, low power consumption, high speed start-up, and low spurious in a steady state can be achieved at the same time.

(Fourth embodiment)
In the PLL synthesizer of the first embodiment, the initial frequency difference and the phase error are large, but even in that case, the frequency difference and the phase error pass through a small state until convergence. In the second embodiment, the fractional frequency division mode is switched to the integer frequency division mode at the switching time Ts in the relationship of Ts <Tacq. In the present embodiment, the switching time is the first switching time Ts1 (<Tacq), and the fractional frequency division mode is used with respect to the convergence time Tacq from the PLL startup (synchronization start) to the first switching time Ts1. The frequency division ratio N is set so that the braking coefficient ζ is 0.5 to 1 and the natural frequency ω _n satisfies the equations (4) and (5).

Next, at the first switching time Ts1 (<Tacq), the frequency division ratio N is switched so that the natural frequency ω _n satisfies the expression (6) as in the third embodiment while maintaining the fractional frequency division mode. Then, as shown in FIG. 7, at the timing Ts2 (= Tacq) when the frequency error is considered to have converged, the frequency division ratio N of the switchable variable frequency divider 12 is changed to fv in the integer frequency division mode without switching the loop filter 4. By switching to / fi, the braking coefficient ζ and the natural frequency ω _n in the steady state are self-adjusted. As a result, high-speed synchronization is possible, and spurious generation can be suppressed by operating in the integer frequency division mode. That is, low power consumption, high speed start-up, and low spurious in a steady state can be achieved at the same time.

The figure which shows embodiment of the PLL synthesizer of this invention. The flowchart which shows the control procedure characterized by the PLL synthesizer of this invention. The figure which shows the locus | trajectory of the phase and frequency in the synchronization process of a PLL synthesizer. The figure which shows the structural example of the loop filter 4 of a PLL synthesizer. 4 is a time chart showing an example of change in the VCO control voltage in the synchronization process of the first and third embodiments. 10 is a time chart showing an example of change in the VCO control voltage in the synchronization process of the second embodiment. 10 is a time chart showing an example of change in the VCO control voltage in the synchronization process of the fourth embodiment. The figure which shows the structural example of the conventional integer frequency division type PLL synthesizer. The figure which shows the structural example of the conventional fractional frequency division type PLL synthesizer.

Explanation of symbols

1 Reference Oscillator 2 Reference Divider 3 Phase Comparator 4 Loop Filter 5 Voltage Controlled Oscillator (VCO)
6A Variable integer frequency divider 6B Variable fractional frequency divider 7 Frequency divider 11 Switchable reference frequency divider 12 Switchable variable frequency divider 13 Switching control circuit

Claims (3)

A voltage-controlled oscillator that outputs a signal having an oscillation frequency corresponding to the input control signal;
A variable frequency divider for branching and inputting the output signal of the voltage controlled oscillator, dividing the output signal by a variable division ratio, and outputting it,
A reference oscillator that outputs a high-precision reference frequency signal;
A reference frequency divider for dividing and outputting the reference frequency signal by a predetermined frequency division ratio;
A phase comparator for inputting the output signal of the reference frequency divider and the output signal of the variable frequency divider to perform phase comparison, and outputting the phase difference signal;
A loop filter that smoothes the phase difference signal and provides the voltage controlled oscillator as the control signal;
An output signal of the voltage controlled oscillator with respect to an output signal of the reference frequency divider by a phase locked loop (PLL) configuration that feeds back an output signal of the voltage controlled oscillator to the phase comparator via the variable frequency divider In a PLL synthesizer that pulls in the frequency and phase of
The variable frequency divider has a function as a variable integer frequency divider whose integer frequency division ratio is an integer and a variable fraction frequency divider whose average frequency division ratio per clock is represented by a fraction. A switching type variable frequency divider including means for switching the functions of the two frequency dividers by a switching signal;
The reference frequency divider is a switching type reference frequency divider capable of switching a frequency division ratio by a switching signal from the outside,
The switchable variable frequency divider is made to function as the variable fractional frequency divider, and the frequency of the output signal of the switchable reference frequency divider is made larger than the frequency channel interval of the output signal of the voltage controlled oscillator. A fractional frequency dividing mode for setting a frequency ratio, the switching variable frequency divider functioning as the variable integer frequency divider, and the frequency of the output signal of the switching type reference frequency divider is an output signal of the voltage controlled oscillator The switching control for generating the switching signal for switching between the integer frequency dividing mode for setting the frequency dividing ratio so as to be equal to the frequency channel interval of the switching frequency and sending the switching signal to the switching variable frequency divider and the switching type reference frequency divider With a circuit,
The switching control circuit sets a convergence time Tacq from the start of the PLL to the convergence, and the convergence time Tacq corresponds to the braking coefficient ζ, the natural frequency ω _n , and the initial frequency difference Ω ₀ .
Tacq = Ω ₀ ² / (2ζω _n ³ )… (a)
Is expressed as
0.5 ≦ ζ ≦ 1
The frequency division ratio of the fractional frequency division mode is set so that the natural frequency ω _n satisfies the equation (a) when the PLL is activated, and the loop filter is used at the timing Ts (= Tacq) at which the frequency error is considered to have converged. The PLL synthesizer is configured to switch to the division ratio in the integer frequency division mode without switching. A voltage-controlled oscillator that outputs a signal having an oscillation frequency corresponding to the input control signal;
A variable frequency divider for branching and inputting the output signal of the voltage controlled oscillator, dividing the output signal by a variable division ratio, and outputting it,
A reference oscillator that outputs a high-precision reference frequency signal;
A reference frequency divider for dividing and outputting the reference frequency signal by a predetermined frequency division ratio;
A phase comparator for inputting the output signal of the reference frequency divider and the output signal of the variable frequency divider to perform phase comparison, and outputting the phase difference signal;
A loop filter that smoothes the phase difference signal and provides the voltage controlled oscillator as the control signal;
An output signal of the voltage controlled oscillator with respect to an output signal of the reference frequency divider by a phase locked loop (PLL) configuration that feeds back an output signal of the voltage controlled oscillator to the phase comparator via the variable frequency divider In a PLL synthesizer that pulls in the frequency and phase of
The variable frequency divider has a function as a variable integer frequency divider whose integer frequency division ratio is an integer and a variable fraction frequency divider whose average frequency division ratio per clock is represented by a fraction. A switching type variable frequency divider including means for switching the functions of the two frequency dividers by a switching signal;
The reference frequency divider is a switching type reference frequency divider capable of switching a frequency division ratio by a switching signal from the outside,
The switchable variable frequency divider is made to function as the variable fractional frequency divider, and the frequency of the output signal of the switchable reference frequency divider is made larger than the frequency channel interval of the output signal of the voltage controlled oscillator. A fractional frequency dividing mode for setting a frequency ratio, the switching variable frequency divider functioning as the variable integer frequency divider, and the frequency of the output signal of the switching type reference frequency divider is an output signal of the voltage controlled oscillator The switching control for generating the switching signal for switching between the integer frequency dividing mode for setting the frequency dividing ratio so as to be equal to the frequency channel interval of the switching frequency and sending the switching signal to the switching variable frequency divider and the switching type reference frequency divider With a circuit,
The switching control circuit sets a convergence time Tacq from the start of the PLL to the convergence, and the convergence time Tacq is determined to be a braking coefficient ζ, a natural frequency ω _n , an initial frequency difference Ω ₀ , and a phase error φf Against
Tacq = (1 / ζω _n ) ln (Ω ₀ / (φfω _n )) (b)
Is expressed as
0.5 ≦ ζ ≦ 1
The frequency division ratio of the fractional frequency division mode is set so that the natural frequency ω _n satisfies the equation (b) when the PLL is started, and the loop filter is used at the timing Ts (= Tacq) at which the frequency error is considered to have converged. The PLL synthesizer is configured to switch to the division ratio in the integer frequency division mode without switching. A voltage-controlled oscillator that outputs a signal having an oscillation frequency corresponding to the input control signal;
A variable frequency divider for branching and inputting the output signal of the voltage controlled oscillator, dividing the output signal by a variable division ratio, and outputting it,
A reference oscillator that outputs a high-precision reference frequency signal;
A reference frequency divider for dividing and outputting the reference frequency signal by a predetermined frequency division ratio;
A phase comparator for inputting the output signal of the reference frequency divider and the output signal of the variable frequency divider to perform phase comparison, and outputting the phase difference signal;
A loop filter that smoothes the phase difference signal and provides the voltage controlled oscillator as the control signal;
An output signal of the voltage controlled oscillator with respect to an output signal of the reference frequency divider by a phase locked loop (PLL) configuration that feeds back an output signal of the voltage controlled oscillator to the phase comparator via the variable frequency divider In a PLL synthesizer that pulls in the frequency and phase of
The variable frequency divider has a function as a variable integer frequency divider whose integer frequency division ratio is an integer and a variable fraction frequency divider whose average frequency division ratio per clock is represented by a fraction. A switching type variable frequency divider including means for switching the functions of the two frequency dividers by a switching signal;
The reference frequency divider is a switching type reference frequency divider capable of switching a frequency division ratio by a switching signal from the outside,
The switchable variable frequency divider is made to function as the variable fractional frequency divider, and the frequency of the output signal of the switchable reference frequency divider is made larger than the frequency channel interval of the output signal of the voltage controlled oscillator. A fractional frequency dividing mode for setting a frequency ratio, the switching variable frequency divider functioning as the variable integer frequency divider, and the frequency of the output signal of the switching type reference frequency divider is an output signal of the voltage controlled oscillator The switching control for generating the switching signal for switching between the integer frequency dividing mode for setting the frequency dividing ratio so as to be equal to the frequency channel interval of the switching frequency and sending the switching signal to the switching variable frequency divider and the switching type reference frequency divider With a circuit,
The switching control circuit sets a convergence time Tacq from the start of the PLL to the convergence, and the convergence time Tacq corresponds to the braking coefficient ζ, the natural frequency ω _n , and the initial frequency difference Ω ₀ .
Tacq = Ω ₀ ² / (2ζω _n ³ )… (a)
Is expressed as
0.5 ≦ ζ ≦ 1
The frequency division ratio of the fractional frequency division mode is set so that the natural frequency ω _n satisfies the equation (a) when the PLL is started, and the convergence time Tacq at timing Ts1 (<Tacq) at which the frequency error is considered to be reduced. Is the braking coefficient ζ, natural frequency ω _n , initial frequency difference Ω ₀ , and phase error φf
Tacq = (1 / ζω _n ) ln (Ω ₀ / (φfω _n )) (b)
Is expressed as
0.5 ≦ ζ ≦ 1
And setting the frequency division ratio of the fractional frequency division mode so that the natural frequency ω _n satisfies the equation (b), and switching the loop filter at the timing Ts2 (= Tacq) when the frequency error is considered to have converged. The PLL synthesizer is configured to switch to the division ratio in the integer division mode.

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