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JP4451790B2 - Semiconductor device, semiconductor device manufacturing method, and card-type recording medium - Google Patents

Semiconductor device, semiconductor device manufacturing method, and card-type recording medium Download PDF

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JP4451790B2
JP4451790B2 JP2005001256A JP2005001256A JP4451790B2 JP 4451790 B2 JP4451790 B2 JP 4451790B2 JP 2005001256 A JP2005001256 A JP 2005001256A JP 2005001256 A JP2005001256 A JP 2005001256A JP 4451790 B2 JP4451790 B2 JP 4451790B2
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semiconductor chip
memory
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JP2006190808A (en
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学 五閑
剛史 東條
英信 西川
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Panasonic Corp
Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Description

本発明は、基板に複数の半導体チップを接合した半導体装置、その製造方法およびこれを用いたカード型記録媒体に関する。   The present invention relates to a semiconductor device in which a plurality of semiconductor chips are bonded to a substrate, a manufacturing method thereof, and a card-type recording medium using the same.

基板に複数の半導体チップを接合した半導体装置は、従来から知られている(例えば特許文献1参照)。図7は、従来の半導体装置90の正面図である。半導体装置90はメモリ基板93を備える。このメモリ基板93の両面には、ベアICチップ91、92がバンプ98を介してメモリ基板93の上下面パターンにそれぞれフリップチップ実装される。メモリ基板93のベアICチップ92側に、メモリ基板96が配置される。メモリ基板96の両面には、ベアICチップ94、95がバンプ98を介してメモリ基板96の上下面パターンにそれぞれフリップチップ実装される。ベアICチップ94はベアICチップ92に対向する位置に配置される。メモリ基板93とメモリ基板96との間に銅等からなる複数の導体ボール97が設けられる。この導体ボール97はメモリ基板93とメモリ基板96とを略平行に保持するとともにメモリ基板93の上下面パターンとメモリ基板96の上下面パターンとを電気的に接合する。   A semiconductor device in which a plurality of semiconductor chips are bonded to a substrate is conventionally known (see, for example, Patent Document 1). FIG. 7 is a front view of a conventional semiconductor device 90. The semiconductor device 90 includes a memory substrate 93. Bare IC chips 91 and 92 are flip-chip mounted on the upper and lower surface patterns of the memory substrate 93 via bumps 98 on both surfaces of the memory substrate 93, respectively. A memory substrate 96 is disposed on the bare IC chip 92 side of the memory substrate 93. On both surfaces of the memory substrate 96, bare IC chips 94 and 95 are flip-chip mounted on the upper and lower surface patterns of the memory substrate 96 via bumps 98, respectively. The bare IC chip 94 is disposed at a position facing the bare IC chip 92. A plurality of conductive balls 97 made of copper or the like are provided between the memory substrate 93 and the memory substrate 96. The conductor balls 97 hold the memory substrate 93 and the memory substrate 96 substantially in parallel, and electrically connect the upper and lower surface patterns of the memory substrate 93 and the upper and lower surface patterns of the memory substrate 96.

また、基板の表面に設けた凹部内にチップサイズパッケージ(CSP)されたCSPメモリICを実装し、且つ、左右にのみリード線を持つ薄型スモールアウトラインパッケージ(TSOP)によりパッケージされたTSOPメモリICを、CSPメモリIC及び凹部の上側にそれを覆うように基板上に実装する構成が知られている(特許文献2参照)。   In addition, a CSP memory IC packaged in a chip size package (CSP) is mounted in a recess provided on the surface of the substrate, and a TSOP memory IC packaged by a thin small outline package (TSOP) having lead wires only on the left and right sides. A configuration is known in which a CSP memory IC and a recess are mounted on a substrate so as to cover the upper side of the recess (see Patent Document 2).

さらに、複数の半導体チップを収納し、これらの半導体チップが、バンプにより所定の電気配線パターンを有する電気絶縁基板に電気的に接続されてなるマルチチップモジュールにおいて、電気絶縁基板に多段式凹部を形成し、各半導体チップを該凹部に上下方向に相互に離間して収容する構成が知られている(特許文献3参照)。
特開2002−207986号公報(図7) 特開2002−204053号公報(図1) 特開平5−275611号公報(図1〜図4)
Furthermore, in a multi-chip module in which a plurality of semiconductor chips are accommodated and these semiconductor chips are electrically connected to an electrical insulating substrate having a predetermined electrical wiring pattern by bumps, a multistage recess is formed in the electrical insulating substrate. In addition, a configuration is known in which each semiconductor chip is accommodated in the recess in the vertical direction so as to be spaced apart from each other (see Patent Document 3).
Japanese Patent Laid-Open No. 2002-207986 (FIG. 7) JP 2002-204053 A (FIG. 1) JP-A-5-275611 (FIGS. 1 to 4)

しかしながら図7に示す両面にベアICチップを実装したメモリモジュール間を導体ボールで接合する半導体装置を、所定の寸法が規定されている小型メモリカードに実装しようとすると、その厚みに制約が生じ、半導体装置をさらに薄くする必要があるが、導体ボールの径はさらに小さくすることが困難であり、またベアICチップの多ピン化により導体ボールの数が増えてコストが増大するという問題がある。   However, when a semiconductor device in which the memory modules having the bare IC chips mounted on both sides shown in FIG. 7 are joined with a conductive ball is mounted on a small memory card having a predetermined size, the thickness is limited, Although it is necessary to make the semiconductor device thinner, there is a problem that it is difficult to further reduce the diameter of the conductor ball, and that the number of conductor balls increases due to the increase in the number of pins of the bare IC chip, resulting in an increase in cost.

また特許文献2および特許文献3の構成のように、基板の片面に設けた凹部内にICチップを収容する構成では、ICチップを3層以上積層しようとした場合に、ICチップの電気配線パターンの構成が複雑になるという問題がある。   Further, in the configuration in which the IC chip is accommodated in the recess provided on one side of the substrate as in the configurations of Patent Document 2 and Patent Document 3, when three or more IC chips are to be stacked, the electrical wiring pattern of the IC chip There is a problem that the configuration of the system becomes complicated.

本発明の目的は、上記従来例の問題点を解決し得る半導体装置、半導体装置の製造方法およびカード型記録媒体を提供することにある。   An object of the present invention is to provide a semiconductor device, a method for manufacturing the semiconductor device, and a card-type recording medium that can solve the problems of the conventional example.

本発明の半導体装置は、長辺方向の両側部を中央部に比較して厚肉に形成することにより上下面の中央部に、前記長辺方向に沿って両端面間を縦通する凹部を構成した基板と、基板の上側凹部内に収容されて基板の凹部上面パターンにバンプを介し接合される第1半導体チップと、第1半導体チップの上側に配置されて基板の両側部上面パターンに両側部上面においてバンプを介し接合される第2半導体チップと、基板の下側凹部内に収容されて基板の凹部下面パターンにバンプを介し接合される第3半導体チップと、第3半導体チップの下側に配置されて基板の両側部下面パターンに両側部下面においてバンプを介し接合される第4半導体チップとを備え、第1、第2半導体チップの組と、第3、第4半導体チップの組と、の少なくとも前者において、第2半導体チップは、基板の上面に垂直な方向から見て第1半導体チップを覆い、かつ、第1及び第2半導体チップは、基板の上面に垂直な方向から見て、共に長方体形状を有し、それらの長手方向が互いに交差する方向に配置されたことを特徴とする。 The semiconductor device of the present invention has a concave portion that vertically passes between both end surfaces along the long side direction at the central portion of the upper and lower surfaces by forming both side portions in the long side direction thicker than the central portion. A configured substrate; a first semiconductor chip housed in an upper recess of the substrate and bonded to a recess upper surface pattern of the substrate via a bump; and disposed on both sides of the upper surface pattern on both sides of the substrate disposed above the first semiconductor chip. A second semiconductor chip bonded via a bump on the upper surface of the part; a third semiconductor chip housed in a lower concave portion of the substrate and bonded to the lower surface pattern of the concave portion of the substrate via the bump; and a lower side of the third semiconductor chip And a fourth semiconductor chip which is bonded to the lower surface pattern on both sides of the substrate via bumps on the lower surface of both sides, and a set of first and second semiconductor chips, a set of third and fourth semiconductor chips, At least before The second semiconductor chip covers the first semiconductor chip when viewed from the direction perpendicular to the upper surface of the substrate, and the first and second semiconductor chips are both longer when viewed from the direction perpendicular to the upper surface of the substrate. It has a body shape and is arranged in a direction in which the longitudinal directions intersect each other .

この構成によれば、まず、基板の長辺方向の両側部を中央部に比較して厚肉に形成することにより上下面の中央部に、前記長辺方向に沿って両端面間を縦通する凹部を構成した
ので、基板の上側凹部内に収容した第1半導体チップの上側に第2半導体チップを配置し、基板の下側凹部内に収容した第3半導体チップの下側に第4半導体チップを配置することができる。このため、積層後の半導体装置を薄くすることができる。また基板の両面に4個の半導体チップを2個ずつに分けてバンプを介し接合し積層するので、基板の片面に4個の半導体チップを積層する構成のように配線が密になることがない。
According to this configuration, first, the both sides in the long side direction of the substrate are formed thicker than the central part, thereby vertically passing between both end surfaces along the long side direction in the central part of the upper and lower surfaces. since it is configured a recess for the fourth semiconductor on the lower side of the third semiconductor chip second semiconductor chip is arranged on the upper side of the first semiconductor chip accommodated in the upper recess of the substrate, it was housed within a lower recess of the substrate A chip can be placed. For this reason, the semiconductor device after lamination can be thinned. In addition, since four semiconductor chips are divided into two pieces on each side of the substrate and bonded and laminated via bumps , the wiring does not become dense unlike the configuration in which four semiconductor chips are laminated on one side of the substrate. .

また、第2半導体チップは、基板の上面に垂直な方向から見て第1半導体チップを覆うように配置しているので、半導体チップの形状が大小異なる場合でも、形状の小さい方を第1半導体チップとして上側凹部内に収容し、大きい方を第2半導体チップとして第1半導体チップを覆うように配置することができ、第1及び第2半導体チップを狭い面積内で高密度に配置することができる。 The second semiconductor chip, since the disposed so as to cover the first semiconductor chip when viewed in the direction perpendicular to the upper surface of the substrate, even if the shape of the semiconductor chip are different sizes, the first semiconductor a smaller shape The chip can be accommodated in the upper concave portion, the larger one can be disposed as the second semiconductor chip so as to cover the first semiconductor chip, and the first and second semiconductor chips can be disposed at a high density within a small area. it can.

さらに、少なくとも第1及び第2半導体チップの組は、基板の上面に垂直な方向から見て、共に長方体形状を有し、それらの長手方向が互いに交差する方向に配置しているので、半導体チップの形状が同一の場合でも、一部を重ねる構成となって、半導体装置を薄くすることができる。 Further, at least a first and a second set semiconductor chip, when viewed from the direction perpendicular to the upper surface of the substrate, both have a cuboid shape, since their longitudinal direction are arranged in a direction intersecting with each other, even when the shape of the semiconductor chip are the same, and is configured to overlap a part, it is possible to thin the semiconductor device.

基板の両側部は、上側凹部内にそれぞれ段差部を有し、第1半導体チップ上面が段差部上面にワイヤーボンディングで接合されることが好ましい。段差部を設けることにより、上側凹部内の上面パターンに第1半導体チップをワイヤーボンディングで容易に接合することができる。   Preferably, both side portions of the substrate have step portions in the upper concave portions, and the upper surface of the first semiconductor chip is bonded to the upper surface of the step portion by wire bonding. By providing the step portion, the first semiconductor chip can be easily bonded to the upper surface pattern in the upper concave portion by wire bonding.

段差部上面の高さは、第1半導体チップ上面の高さよりも低いことが好ましい。ワイヤーボンディングで第1半導体チップを段差部に容易に接合できるからである。   The height of the upper surface of the stepped portion is preferably lower than the height of the upper surface of the first semiconductor chip. This is because the first semiconductor chip can be easily joined to the step portion by wire bonding.

第1半導体チップ上に設けられて第2半導体チップを支持する第1補強部材を有することが好ましい。基板の上側凹部を跨いで配置される第2半導体チップの強度を補強するためである。   It is preferable to have a first reinforcing member that is provided on the first semiconductor chip and supports the second semiconductor chip. This is to reinforce the strength of the second semiconductor chip disposed across the upper concave portion of the substrate.

基板の上側凹部底面上に設けられて第1半導体チップを支持する第2補強部材を有することが好ましい。ワイヤーボンディングで段差部に接合された第1半導体チップを支持することができるからである。   It is preferable to have a second reinforcing member provided on the bottom surface of the upper concave portion of the substrate and supporting the first semiconductor chip. This is because the first semiconductor chip bonded to the step portion can be supported by wire bonding.

本発明の半導体装置の製造方法は、長辺方向の両側部を中央部に比較して厚肉に形成することにより上下面の中央部に、前記長辺方向に沿って両端面間を縦通する凹部を構成した基板の上側凹部内に第1半導体チップをそれらの長手方向が一致するように収容して基板の凹部上面パターンにバンプを介し接合し、第2半導体チップを基板の下側凹部内にそれらの長手方向が一致するように収容して基板の凹部下面パターンにバンプを介し接合し、第3半導体チップを第1半導体チップの上側に配置して基板の両側部上面パターンに両側部上面においてバンプを介し接合し、第4半導体チップを第3半導体チップの下側に配置して基板の両側部下面パターンに両側部下面においてバンプを介し接合するのに、第1、第2半導体チップの組と、第3、第4半導体チップの組と、の少なくとも前者において、第2半導体チップが、基板の上面に垂直な方向から見て第1半導体チップを覆い、かつ、共に長方体形状を有した第1及び第2半導体チップは、基板の上面に垂直な方向から見て、それらの長手方向が互いに交差する方向に配置することを特徴とする。 In the method of manufacturing a semiconductor device according to the present invention, both side portions in the long side direction are formed thicker than the central portion, thereby vertically passing between both end surfaces along the long side direction in the central portion of the upper and lower surfaces. The first semiconductor chip is accommodated in the upper concave portion of the substrate that constitutes the concave portion so that the longitudinal directions thereof coincide with each other, and joined to the concave upper surface pattern of the substrate via the bump , and the second semiconductor chip is bonded to the lower concave portion of the substrate. Are accommodated so that their longitudinal directions coincide with each other, bonded to the concave bottom surface pattern of the substrate via bumps , and the third semiconductor chip is disposed on the upper side of the first semiconductor chip so that both side portions are formed on the upper surface pattern on both sides of the substrate. bonded via the bumps on the upper surface, to the fourth semiconductor chip disposed on the lower side of the third semiconductor chip bonded via the bumps on both sides the lower surface on both the lower surface pattern of the substrate, first, second semiconductor chip Pair and the second , At least in the former of the fourth semiconductor chip set, the second semiconductor chip covers the first semiconductor chip when viewed from the direction perpendicular to the upper surface of the substrate, and both have a rectangular parallelepiped shape. The second semiconductor chips are arranged in a direction in which their longitudinal directions intersect each other when viewed from a direction perpendicular to the upper surface of the substrate .

この構成によれば、基板の長辺方向の両側部を中央部に比較して厚肉に形成することにより上下面の中央部に、前記長辺方向に沿って両端面間を縦通する凹部を構成したので、基板の上側凹部内に収容した第1半導体チップの上側に第3半導体チップを配置し、基板の下側凹部内に収容した第2半導体チップの下側に第4半導体チップを配置することができる。このため、積層後の半導体装置を薄くすることができる。また基板の両面に4個の半導体チップを2個ずつに分けてバンプを介し接合して積層するので、基板の片面に4個の半導体チップを積層する構成のように配線が密になることがない。また、第2半導体チップは、基板の上面に垂直な方向から見て第1半導体チップを覆うように配置しているので、半導体チップの形状が大小異なる場合でも、形状の小さい方を第1半導体チップとして上側凹部内に収容し、大きい方を第2半導体チップとして第1半導体チップを覆うように配置することができ、第1及び第2半導体チップを狭い面積内で高密度に配置することができる。さらに、少なくとも第1及び第2半導体チップの組は、基板の上面に垂直な方向から見て、共に長方体形状を有し、それらの長手方向が互いに交差する方向に配置しているので、半導体チップの形状が同一の場合でも、一部を重ねる構成となって、半導体装置を薄くすることができる。 According to this configuration, by forming both side portions in the long side direction of the substrate thicker than the central portion, the concave portion that vertically passes between both end surfaces along the long side direction in the central portion of the upper and lower surfaces. Therefore, the third semiconductor chip is disposed above the first semiconductor chip accommodated in the upper concave portion of the substrate, and the fourth semiconductor chip is disposed below the second semiconductor chip accommodated in the lower concave portion of the substrate. Can be arranged. For this reason, the semiconductor device after lamination can be thinned. Also, since four semiconductor chips are divided into two pieces on each side of the substrate and bonded and laminated via bumps , the wiring may be dense as in the configuration where four semiconductor chips are laminated on one side of the substrate. Absent. In addition, since the second semiconductor chip is disposed so as to cover the first semiconductor chip when viewed from the direction perpendicular to the upper surface of the substrate, even if the shape of the semiconductor chip is different, the smaller one is used as the first semiconductor chip. The chip can be accommodated in the upper concave portion, the larger one can be disposed as the second semiconductor chip so as to cover the first semiconductor chip, and the first and second semiconductor chips can be disposed at a high density within a small area. it can. Furthermore, since at least the first and second semiconductor chip sets have a rectangular shape when viewed from the direction perpendicular to the upper surface of the substrate, and their longitudinal directions are arranged in a direction crossing each other, Even when the shape of the semiconductor chip is the same, the semiconductor device can be thinned by overlapping parts.

本発明のカード型記録媒体は、長辺方向の両側部を中央部に比較して厚肉に形成することにより上下面の中央部、前記長辺方向に沿って両端面間を縦通する凹部を構成したメモリ基板と、メモリ基板の上側凹部内に互いの長手方向が一致するように収容されてメモリ基板の凹部上面パターンにバンプを介し接合される第1メモリチップと、第1メモリチップの上側に配置されてメモリ基板の両側部上面パターンに両側部上面においてバンプを介し接合される第2メモリチップと、メモリ基板の下側凹部内に互いの長手方向が一致するように収容されてメモリ基板の凹部下面パターンにバンプを介し接合される第3メモリチップと、第3メモリチップの下側に配置されてメモリ基板の両側部下面パターンに両側部下面においてバンプを介し接合される第4メモリチップとを備え、第第1、第2半導体チップの組と、第3、第4半導体チップの組と、の少なくとも前者において、2半導体チップは、基板の上面に垂直な方向から見て第1半導体チップを覆い、かつ、第1及び第2半導体チップは、基板の上面に垂直な方向から見て、共に長方体形状を有し、それらの長手方向が互いに交差する方向に配置されたメモリモジュールをベース基板の一方の面に実装するとともに、このベース基板の他方の面に第1乃至第4メモリチップの動作を制御するICチップを実装し、全体をパッケージ内に収納したことを特徴とする。 The card-type recording medium of the present invention has a concave portion that vertically passes between both end surfaces along the long side direction by forming both side portions in the long side direction thicker than the central portion. A first memory chip which is accommodated in the upper concave portion of the memory substrate so that their longitudinal directions coincide with each other and bonded to the upper surface pattern of the concave portion of the memory substrate via bumps, and A second memory chip disposed on the upper side and bonded to the upper surface pattern on both sides of the memory substrate via bumps on the upper surface of both sides, and accommodated in the lower concave portion of the memory substrate so that their longitudinal directions coincide with each other a third memory chip is bonded via bumps to the recess bottom surface pattern of the substrate, bonding via the bumps on both sides lower surface 3 is disposed on the lower side of the memory chips on both sides lower surface pattern of the memory substrate The fourth and a memory chip, a first, a set of the second semiconductor chip, in the third, at least the former of the set of fourth semiconductor chip, the second semiconductor chip, from the direction perpendicular to the upper surface of the substrate The first semiconductor chip covers the first semiconductor chip as viewed, and the first and second semiconductor chips both have a rectangular shape when viewed from the direction perpendicular to the upper surface of the substrate, and their longitudinal directions intersect each other. The arranged memory module is mounted on one surface of the base substrate, and an IC chip for controlling the operation of the first to fourth memory chips is mounted on the other surface of the base substrate, and the whole is housed in a package. It is characterized by that.

この構成によれば、基板の長辺方向の両側部を中央部に比較して厚肉に形成することにより上下面の中央部に、前記長辺方向に沿って両端面間を縦通する凹部を構成したので、メモリ基板の上側凹部内に収容した第1メモリチップの上側に第2メモリチップを配置し、メモリ基板の下側凹部内に収容した第3メモリチップの下側に第4メモリチップを配置することができる。このため、第1乃至第4メモリチップを積層した後のメモリモジュールを薄くすることができ、薄型のカード型記録媒体を得ることができる。またメモリ基板の両面に4個のメモリチップを2個ずつに分けてバンプを介し接合して積層するので、メモリ基板の片面に4個のメモリチップを積層する構成のように配線が密になることがない薄型のカード型記録媒体を得ることができる。また、第2半導体チップは、基板の上面に垂直な方向から見て第1半導体チップを覆うように配置しているので、半導体チップの形状が大小異なる場合でも、形状の小さい方を第1半導体チップとして上側凹部内に収容し、大きい方を第2半導体チップとして第1半導体チップを覆うように配置することができ、第1及び第2半導体チップを狭い面積内で高密度に配置することができる。さらに、少なくとも第1及び第2半導体チップの組は、基板の上面に垂直な方向から見て、共に長方体形状を有し、それらの長手方向が互いに交差する方向に配置しているので、半導体チップの形状が同一の場合でも、一部を重ねる構成となって、半導体装置を薄くすることができる。 According to this configuration, by forming both side portions in the long side direction of the substrate thicker than the central portion, the concave portion that vertically passes between both end surfaces along the long side direction in the central portion of the upper and lower surfaces. The second memory chip is disposed above the first memory chip accommodated in the upper recess of the memory substrate, and the fourth memory is disposed below the third memory chip accommodated in the lower recess of the memory substrate. A chip can be placed. Therefore, the memory module after the first to fourth memory chips are stacked can be thinned, and a thin card type recording medium can be obtained. In addition, four memory chips are divided into two on each side of the memory substrate and bonded and laminated via bumps , so that the wiring is dense as in the configuration in which four memory chips are stacked on one side of the memory substrate. A thin card-type recording medium that does not occur can be obtained. In addition, since the second semiconductor chip is disposed so as to cover the first semiconductor chip when viewed from the direction perpendicular to the upper surface of the substrate, even if the shape of the semiconductor chip is different, the smaller one is used as the first semiconductor chip. The chip can be accommodated in the upper concave portion, the larger one can be disposed as the second semiconductor chip so as to cover the first semiconductor chip, and the first and second semiconductor chips can be disposed at a high density within a small area. it can. Furthermore, since at least the first and second semiconductor chip sets have a rectangular shape when viewed from the direction perpendicular to the upper surface of the substrate, and their longitudinal directions are arranged in a direction crossing each other, Even when the shape of the semiconductor chip is the same, the semiconductor device can be thinned by overlapping parts.

本発明によれば、厚みが薄く低コストで簡単な構成の半導体装置を提供することができる。   According to the present invention, it is possible to provide a semiconductor device having a small thickness and a simple configuration at low cost.

図1は本実施の形態に係る小型メモリカード200のケースを除いた状態での概略斜視図であり、図2(a)は小型メモリカード200に設けられたメモリモジュール100の要部平面図であり、図2(b)はその正面図であり、図3は小型メモリカード200の側面断面図である。   FIG. 1 is a schematic perspective view of the small memory card 200 according to the present embodiment with the case removed, and FIG. 2A is a plan view of the main part of the memory module 100 provided in the small memory card 200. 2B is a front view thereof, and FIG. 3 is a side sectional view of the small memory card 200. FIG.

小型メモリカード200は、ベース基板モジュール23を備える。このベース基板モジュール23は長方形状のベース基板10を有し、その上面11上に形成された上面パターン39にメモリモジュール100が実装される。メモリモジュール100およびベース基板モジュール23は、上ケース15A、下ケース15Bからなるパッケージ14に収納される。ベース基板10の下面12には、ASIC用ICチップ13とマイクロプロセッサ用ICチップ13Aとが、互いに所定の間隔を空けてベース基板10の下面パターンに接合されている。ベース基板10の上面11には、チップコンデンサ34、チップ抵抗35がベース基板10の上面パターンに接合されている。   The small memory card 200 includes a base substrate module 23. The base substrate module 23 has a rectangular base substrate 10, and the memory module 100 is mounted on an upper surface pattern 39 formed on the upper surface 11. The memory module 100 and the base substrate module 23 are accommodated in a package 14 including an upper case 15A and a lower case 15B. On the lower surface 12 of the base substrate 10, an ASIC IC chip 13 and a microprocessor IC chip 13A are bonded to the lower surface pattern of the base substrate 10 at a predetermined interval. A chip capacitor 34 and a chip resistor 35 are bonded to the upper surface pattern of the base substrate 10 on the upper surface 11 of the base substrate 10.

ベース基板10の各長辺に沿って貫通孔24が多数形成され、メモリモジュール100のメモリ基板5には各貫通孔24に対向する貫通孔25がそれぞれ多数形成されている。ベース基板10の各貫通孔24とメモリ基板5の各貫通孔25とをそれぞれ貫通する多数の導電性ワイヤ26が設けられている。導電性ワイヤ26は、ベース基板10の上下面パターンとメモリ基板5の上下面パターンとを電気的に接続する。   A large number of through holes 24 are formed along each long side of the base substrate 10, and a large number of through holes 25 facing the through holes 24 are formed in the memory substrate 5 of the memory module 100. A number of conductive wires 26 penetrating through the through holes 24 of the base substrate 10 and the through holes 25 of the memory substrate 5 are provided. The conductive wires 26 electrically connect the upper and lower surface patterns of the base substrate 10 and the upper and lower surface patterns of the memory substrate 5.

ベース基板10の下面12に小型メモリカードのカード電極36が、上ケース15A、下ケース15Bから露出して設けられている。   A card electrode 36 of a small memory card is provided on the lower surface 12 of the base substrate 10 so as to be exposed from the upper case 15A and the lower case 15B.

メモリ基板5は、両側部29を中央部30に比較して肉厚に形成することにより上下面3、4の中央部30にそれぞれ上側凹部1、下側凹部2を構成する。上側凹部1および下側凹部2は長辺方向に沿ってメモリ基板5の両端面27をそれぞれ貫通する。   The memory substrate 5 is formed with the upper side recesses 1 and the lower side recesses 2 in the central portions 30 of the upper and lower surfaces 3 and 4 by forming both side portions 29 thicker than the central portion 30. The upper concave portion 1 and the lower concave portion 2 respectively penetrate the both end surfaces 27 of the memory substrate 5 along the long side direction.

メモリ基板5の上側凹部1内には2個のメモリチップ6が長辺方向に沿って収容され、メモリ基板5の凹部上面パターン37にバンプ28を介して接合される。メモリチップ6を覆うようにメモリチップ8が、両側部29に形成された両側部上面パターン38にバンプ31を介して接合される。   Two memory chips 6 are accommodated in the upper side recess 1 of the memory substrate 5 along the long side direction, and are joined to the recess upper surface pattern 37 of the memory substrate 5 via bumps 28. The memory chip 8 is bonded to both side surface upper surface patterns 38 formed on the both side portions 29 via the bumps 31 so as to cover the memory chip 6.

メモリ基板5の下側凹部2内には、2個のメモリチップ7がメモリチップ6に対応して収容され、メモリ基板5の凹部下面パターンにバンプ32を介して接合される。メモリチップ7を覆うようにメモリチップ9が、両側部29に形成された両側部下面パターンにバンプ33を介して接合される。   In the lower recess 2 of the memory substrate 5, two memory chips 7 are accommodated corresponding to the memory chip 6, and are joined to the recess lower surface pattern of the memory substrate 5 via bumps 32. The memory chip 9 is bonded to both side portion lower surface patterns formed on both side portions 29 via bumps 33 so as to cover the memory chip 7.

このように構成された小型メモリカード200は以下のようにして製造される。まず、メモリ基板5の上側凹部1内の凹部上面パターン37にメモリチップ6を接合する。そしてメモリチップ7を下側凹部2内の凹部下面パターンに接合する。次にメモリチップ8を両側部29の両側部上面パターン38に接合する。その後メモリチップ9を両側部29の両側部下面パターンに接合してメモリモジュール100を完成する。   The small memory card 200 configured as described above is manufactured as follows. First, the memory chip 6 is bonded to the recess upper surface pattern 37 in the upper recess 1 of the memory substrate 5. Then, the memory chip 7 is bonded to the recess lower surface pattern in the lower recess 2. Next, the memory chip 8 is bonded to the upper surface patterns 38 on both side portions 29. Thereafter, the memory chip 9 is bonded to the lower surface patterns on both side portions 29 to complete the memory module 100.

そして、ベース基板10の上面11にメモリモジュール100、チップコンデンサ34及びチップ抵抗35を接合し、ベース基板10の下面12にASIC用ICチップ13、マイクロプロセッサ用ICチップ13A及びカード電極36を実装する。次に、パッケージ14の上ケース15A、下ケース15Bを、カード電極36を露出させて略全体を覆うようにベース基板10に取り付けて、小型メモリカード200を完成させる。   Then, the memory module 100, the chip capacitor 34, and the chip resistor 35 are joined to the upper surface 11 of the base substrate 10, and the ASIC IC chip 13, the microprocessor IC chip 13A, and the card electrode 36 are mounted on the lower surface 12 of the base substrate 10. . Next, the upper case 15 </ b> A and the lower case 15 </ b> B of the package 14 are attached to the base substrate 10 so that the card electrode 36 is exposed and substantially entirely covered, thereby completing the small memory card 200.

図4は、本実施の形態に係る第1変形例の要部平面図である。図4に示すように、同一の長方体形状を有する2個のメモリチップ8Aを互いに直交する方向に配置して、上側凹部1の凹部上面パターンおよび両側部29の両側部上面パターンにそれぞれ接合してもよい。   FIG. 4 is a main part plan view of a first modification according to the present embodiment. As shown in FIG. 4, two memory chips 8A having the same rectangular shape are arranged in a direction orthogonal to each other, and bonded to the concave upper surface pattern of the upper concave portion 1 and the upper surface patterns on both side portions of the both side portions 29, respectively. May be.

図5は、本実施の形態に係る第2変形例の正面図である。図5に示すように、メモリチップ6上にメモリチップ8を支持する補強部材21を設けてもよい。またメモリチップ7上に補強部材21を設けてメモリチップ9を支持するようにしてもよい。   FIG. 5 is a front view of a second modification according to the present embodiment. As shown in FIG. 5, a reinforcing member 21 that supports the memory chip 8 may be provided on the memory chip 6. Further, a reinforcing member 21 may be provided on the memory chip 7 to support the memory chip 9.

図6は、本実施の形態に係る第3変形例の正面図である。メモリ基板5の上側凹部1の底面19上には、メモリチップ6Aを支持する補強部材22が設けられる。メモリ基板5の両側部29は、上側凹部1側にそれぞれ段差部16を有する。メモリチップ6Aの上面は、段差部16の上面17の凹部上面パターンにワイヤーボンディングの導体線18で接合される。段差部16の上面17の高さH1は、メモリチップ6Aの上面の高さH2よりも低い。メモリチップ6A上にメモリチップ8Bを支持する補強部材21Aが設けられる。メモリチップ8Bの上面は、両側部29の両側部上面パターンにワイヤーボンディングの導体線18で接合される。両側部29の下側についても図6に示すように上側と同様に構成される。   FIG. 6 is a front view of a third modification according to the present embodiment. A reinforcing member 22 that supports the memory chip 6 </ b> A is provided on the bottom surface 19 of the upper recess 1 of the memory substrate 5. Both side portions 29 of the memory substrate 5 have step portions 16 on the upper concave portion 1 side. The upper surface of the memory chip 6 </ b> A is joined to the concave upper surface pattern of the upper surface 17 of the stepped portion 16 by a conductor wire 18 for wire bonding. The height H1 of the upper surface 17 of the stepped portion 16 is lower than the height H2 of the upper surface of the memory chip 6A. A reinforcing member 21A for supporting the memory chip 8B is provided on the memory chip 6A. The upper surface of the memory chip 8B is joined to the upper surface patterns on both side portions 29 by the wire 18 of wire bonding. The lower side of both side portions 29 is configured in the same manner as the upper side as shown in FIG.

本発明は、基板に複数の半導体チップを接合した半導体装置、その製造方法およびこれを用いたカード型記録媒体に適用することができる。   The present invention can be applied to a semiconductor device in which a plurality of semiconductor chips are bonded to a substrate, a manufacturing method thereof, and a card-type recording medium using the same.

本実施の形態に係る小型メモリカードのケースを除いた状態での概略斜視図である。It is a schematic perspective view in the state except the case of the small memory card concerning this embodiment. (a)は本実施の形態に係る小型メモリカードに設けられたメモリモジュールの要部平面図であり、(b)はその正面図である。(A) is a principal part top view of the memory module provided in the small memory card based on this Embodiment, (b) is the front view. 本実施の形態に係る小型メモリカードの側面断面図である。It is side surface sectional drawing of the small memory card based on this Embodiment. 本実施の形態に係る第1変形例の要部平面図である。It is a principal part top view of the 1st modification concerning this Embodiment. 本実施の形態に係る第2変形例の正面図である。It is a front view of the 2nd modification concerning this embodiment. 本実施の形態に係る第3変形例の正面図である。It is a front view of the 3rd modification concerning this embodiment. 従来の半導体装置の正面図である。It is a front view of the conventional semiconductor device.

符号の説明Explanation of symbols

1 上側凹部
2 下側凹部
3 上面
4 下面
5 メモリ基板
6、7、8、9 メモリチップ
10 ベース基板
11 上面
12 下面
13 ICチップ
14 パッケージ
15A 上ケース
15B 下ケース
16 段差部
17 上面
18 導体線
19 底面
20 上面
21、22 補強部材
23 ベース基板モジュール
37 凹部上面パターン
38 両側部上面パターン
100 メモリモジュール
200 小型メモリカード
DESCRIPTION OF SYMBOLS 1 Upper side recessed part 2 Lower side recessed part 3 Upper surface 4 Lower surface 5 Memory substrate 6, 7, 8, 9 Memory chip 10 Base substrate 11 Upper surface 12 Lower surface 13 IC chip 14 Package 15A Upper case 15B Lower case 16 Step part 17 Upper surface 18 Conductor wire 19 Bottom surface 20 Upper surface 21, 22 Reinforcing member 23 Base substrate module 37 Recessed surface pattern 38 Both side surface pattern 100 Memory module 200 Small memory card

Claims (7)

長辺方向の両側部を中央部に比較して厚肉に形成することにより上下面の中央部に、前記長辺方向に沿って両端面間を縦通する凹部を構成した基板と、基板の上側凹部内にそれらの長手方向が一致するように収容されて基板の凹部上面パターンにバンプを介し接合される第1半導体チップと、第1半導体チップの上側に配置されて基板の両側部上面パターンに両側部上面においてバンプを介し接合される第2半導体チップと、基板の下側凹部内にそれらの長手方向が一致するように収容されて基板の凹部下面パターンにバンプを介し接合される第3半導体チップと、第3半導体チップの下側に配置されて基板の両側部下面パターンに両側部下面においてバンプを介し接合される第4半導体チップとを備え、第1、第2半導体チップの組と、第3、第4半導体チップの組と、の少なくとも前者において、第2半導体チップは、基板の上面に垂直な方向から見て第1半導体チップを覆い、かつ、第1及び第2半導体チップは、基板の上面に垂直な方向から見て、共に長方体形状を有し、それらの長手方向が互いに交差する方向に配置されたことを特徴とする半導体装置。 By forming both side portions in the long side direction thicker than the center portion, a substrate having a concave portion that vertically passes between both end surfaces along the long side direction in the central portion of the upper and lower surfaces, and A first semiconductor chip that is accommodated in the upper concave portion so that their longitudinal directions coincide with each other and bonded to the concave upper surface pattern of the substrate via bumps, and an upper surface pattern on both sides of the substrate that is disposed on the upper side of the first semiconductor chip A second semiconductor chip bonded to the upper surface of both sides via bumps, and a third semiconductor chip which is accommodated in the lower concave portion of the substrate so that their longitudinal directions coincide with each other and bonded to the concave pattern of the concave portion of the substrate via the bumps . A semiconductor chip; and a fourth semiconductor chip disposed below the third semiconductor chip and bonded to the lower surface patterns on both sides of the substrate via bumps on the lower surfaces of both sides, and a set of first and second semiconductor chips, The second In at least the former of the fourth semiconductor chip set, the second semiconductor chip covers the first semiconductor chip when viewed from the direction perpendicular to the upper surface of the substrate, and the first and second semiconductor chips are formed on the substrate. A semiconductor device characterized in that when viewed from a direction perpendicular to the upper surface, both have a rectangular shape and are arranged in a direction in which their longitudinal directions intersect each other . 基板の両側部は、上側凹部内にそれぞれ段差部を有し、第1半導体チップ上面が段差部上面にワイヤーボンディングで接合される請求項記載の半導体装置。 2. The semiconductor device according to claim 1 , wherein both side portions of the substrate have step portions in the upper recesses, and the upper surface of the first semiconductor chip is bonded to the upper surface of the step portion by wire bonding. 段差部上面の高さは、第1半導体チップ上面の高さよりも低い請求項記載の半導体装置。 The height of the stepped portion upper surface, a semiconductor device of low claim 2 than the height of the first semiconductor chip top surface. 第1半導体チップ上に設けられて第2半導体チップを支持する第1補強部材を有する請求項1乃至の何れかに記載の半導体装置。 The semiconductor device according to any one of claims 1 to 3 having a first reinforcement member that supports the second semiconductor chip provided on the first semiconductor chip. 基板の上側凹部底面上に設けられて第1半導体チップを支持する第2補強部材を有する請求項1乃至の何れかに記載の半導体装置。 The semiconductor device according to any one of claims 1 to 4 having a second reinforcing member that supports the first semiconductor chip provided on the upper bottom surface of the recess of the substrate. 長辺方向の両側部を中央部に比較して厚肉に形成することにより上下面の中央部に、前記長辺方向に沿って両端面間を縦通する凹部を構成した基板の上側凹部内に第1半導体チップをそれらの長手方向が一致するように収容して基板の凹部上面パターンにバンプを介し接合し、第2半導体チップを基板の下側凹部内にそれらの長手方向が一致するように収容
して基板の凹部下面パターンにバンプを介し接合し、第3半導体チップを第1半導体チップの上側に配置して基板の両側部上面パターンに両側部上面においてバンプを介し接合し、第4半導体チップを第3半導体チップの下側に配置して基板の両側部下面パターンに両側部下面においてバンプを介し接合するのに、第1、第2半導体チップの組と、第3、第4半導体チップの組と、の少なくとも前者において、第2半導体チップが、基板の上面に垂直な方向から見て第1半導体チップを覆い、かつ、共に長方体形状を有した第1及び第2半導体チップは、基板の上面に垂直な方向から見て、それらの長手方向が互いに交差する方向に配置することを特徴とする半導体装置の製造方法。
In the upper concave portion of the substrate, in which both side portions in the long side direction are formed thicker than the central portion, thereby forming a concave portion that vertically passes between both end surfaces along the long side direction in the central portion of the upper and lower surfaces. The first semiconductor chips are accommodated in such a manner that their longitudinal directions coincide with each other and bonded to the concave upper surface pattern of the substrate via bumps, and the second semiconductor chips are arranged in the lower concave portion of the substrate so that their longitudinal directions coincide with each other. accommodated by joining via the bumps in the recess bottom surface pattern of the substrate, is bonded via the bumps on both sides the upper surface of the third semiconductor chip on both sides the upper surface pattern of the substrate is disposed above the first semiconductor chip, the fourth A semiconductor chip is disposed below the third semiconductor chip and joined to the lower surface patterns on both sides of the substrate via bumps on the lower surfaces of both sides, and a set of first and second semiconductor chips, and third and fourth semiconductors A small set of chips In at least the former, the second semiconductor chip covers the first semiconductor chip when viewed from the direction perpendicular to the upper surface of the substrate, and both the first and second semiconductor chips having a rectangular shape are the upper surface of the substrate. A method of manufacturing a semiconductor device, characterized in that the semiconductor devices are arranged in a direction in which their longitudinal directions intersect each other when viewed from a direction perpendicular to the vertical direction .
長辺方向の両側部を中央部に比較して厚肉に形成することにより上下面の中央部、前記長辺方向に沿って両端面間を縦通する凹部を構成したメモリ基板と、メモリ基板の上側凹部内に互いの長手方向が一致するように収容されてメモリ基板の凹部上面パターンにバンプを介し接合される第1メモリチップと、第1メモリチップの上側に配置されてメモリ基板の両側部上面パターンに両側部上面においてバンプを介し接合される第2メモリチップと、メモリ基板の下側凹部内に互いの長手方向が一致するように収容されてメモリ基板の凹部下面パターンにバンプを介し接合される第3メモリチップと、第3メモリチップの下側に配置されてメモリ基板の両側部下面パターンに両側部下面においてバンプを介し接合される第4メモリチップとを備え、第1、第2半導体チップの組と、第3、第4半導体チップの組と、の少なくとも前者において、第2半導体チップは、基板の上面に垂直な方向から見て第1半導体チップを覆い、かつ、第1及び第2半導体チップは、基板の上面に垂直な方向から見て、共に長方体形状を有し、それらの長手方向が互いに交差する方向に配置されたメモリモジュールをベース基板の一方の面に実装するとともに、このベース基板の他方の面に第1乃至第4メモリチップの動作を制御するICチップを実装し、全体をパッケージ内に収納したことを特徴とするカード型記録媒体。 A memory substrate having a central portion on the upper and lower surfaces by forming both side portions in the long side direction thicker than the central portion , and a concave portion vertically passing between both end surfaces along the long side direction; and a memory substrate A first memory chip that is accommodated in the upper recess of the memory substrate so that their longitudinal directions coincide with each other and bonded to the upper surface pattern of the recess of the memory substrate via bumps, and both sides of the memory substrate disposed on the upper side of the first memory chip a second memory chip to be bonded via the bumps at both sides an upper surface part upper surface pattern, is accommodated so as to lower the recess of the memory substrate longitudinal mutual match via the bumps in the recess bottom surface pattern of the memory substrate Bei third memory chip to be joined, and a fourth memory chips are bonded via the bumps on both sides the lower surface on both the lower surface pattern of the memory substrate is arranged below the third memory chip , First, a set of the second semiconductor chip, third, the set of fourth semiconductor chip, at least the former, the second semiconductor chip covers the first semiconductor chip when viewed in the direction perpendicular to the upper surface of the substrate The first and second semiconductor chips each have a rectangular shape when viewed from the direction perpendicular to the upper surface of the substrate, and the memory modules arranged in directions in which the longitudinal directions intersect with each other are used as the base substrate. A card-type recording characterized in that an IC chip for controlling the operation of the first to fourth memory chips is mounted on the other surface of the base substrate, and the whole is housed in a package. Medium.
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