JP4433702B2 - Solid-state imaging device and driving method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a solid-state imaging device and a driving method thereof, and more particularly to a solid-state imaging device and a driving method thereof that read out signals of pixels from a pixel unit in parallel in units of rows.
[0002]
[Prior art]
In recent years, a CMOS image sensor has attracted attention as a solid-state imaging device that replaces a CCD (Charge Coupled Device) image sensor that has been the mainstream until now. This is because the CCD image sensor requires a dedicated process for its manufacture, requires a plurality of power supply voltages for its operation, and needs to operate in combination with a plurality of peripheral ICs, which makes the system very complicated. This is because the CMOS image sensor overcomes these problems.
[0003]
That is, the CMOS image sensor can be manufactured by using a manufacturing process similar to that of a general CMOS integrated circuit produced all over the world, and can be driven by a single power source. Since analog circuits and logic circuits using processes can be mixed in the same chip, it has a plurality of very significant advantages such as the number of peripheral ICs can be reduced.
[0004]
While the output circuit of a CCD image sensor is mainly a 1ch output using an FD (Floating Diffusion) amplifier, the CMOS image sensor has an FD amplifier for each pixel, and the pixels are two-dimensionally arranged in a matrix. A column parallel output type in which a certain row in the pixel array is selected and read out in the column direction is the mainstream (see, for example, Patent Document 1). This is because it is difficult to obtain a sufficient driving capability with an FD amplifier arranged in a pixel, so it is necessary to lower the data rate, and parallel processing is advantageous for this purpose.
[0005]
As shown in FIG. 9, the output circuit of this parallel output type CMOS image sensor has a capacitor array C11 to C, in which signals read in parallel in the column direction are prepared for the number of columns below or above the pixel array (sensor cell). Transfer to C1n where it is sampled and held. Thereafter, the charges are sequentially transferred in the horizontal direction using the charge integration type amplifier OP. Since the serial output is 1ch from here, the data rate increases rapidly.
[0006]
[Patent Document 1]
JP 11-69231 A
[0007]
[Problems to be solved by the invention]
In the case of a CMOS image sensor, if a charge integration amplifier OP using CMOS analog circuit technology can be integrated in the same chip as the pixel array and a sufficiently wide-band amplifier can be designed, it can be transferred at a high data rate in the horizontal direction. It is possible to follow. However, with the recent increase in the number of pixels in the image sensor, the data rate is constantly increasing, and the design of the charge integrating amplifier OP has become very difficult.
[0008]
There are several factors that hinder the broadbanding of the charge integrating amplifier OP. In the first place, one of the factors is that circuits using MOS transistors are not good at wide band. As a circuit factor, since the charge integrating amplifier OP requires a reset operation, the operation sequence becomes two phases of reset and read, and a frequency band twice as high as that of a normal one is required.
[0009]
Further, since the switch elements S11 to S1n are connected to the horizontal signal line HL for transmitting a signal from the capacitance arrays C11 to C1n to the charge integrating amplifier OP, the number of the switching elements S11 to S1n is connected, so that there are many parasitic capacitances Cp. This is because the band of the charge integrating amplifier OP is limited. With the recent increase in the number of pixels in an image sensor, not only the data rate but also the parasitic capacitance Cp is steadily increasing, and the design of the charge integrating amplifier OP is becoming more and more difficult.
[0010]
Therefore, a method is conceivable in which a plurality of charge integration amplifiers OP themselves are provided and output from a plurality of channels to reduce the data rate per channel. However, when outputting with a plurality of channels, a plurality of channels are required up to the AD converter at the subsequent stage. Therefore, there is a problem that it is difficult to match between channels due to variations in differential errors and integration errors of the AD converter.
[0011]
In addition, in a CMOS image sensor, pixel addition for adding signals between pixels can be performed relatively easily. There are various pixel addition methods. A pixel addition method in the conventional output circuit will be described with reference to FIG.
[0012]
Signals from the pixels are output to the capacitor arrays C11 to C1n, sampled and held. Normally, when a signal is read by the charge integrating amplifier OP, one of the switch elements S11 to S1n that connects the capacitor holding the signal to be read and the horizontal signal line HL is selected, and the capacitor and the horizontal What is necessary is just to connect the signal line HL. Since the pixel signal is held as a charge in the capacitor, the addition is relatively simple. That is, when adding the signals of two pixels, if two switch elements (for example, S11 and S12) are simultaneously turned on, they are automatically added when read by the charge integrating amplifier OP. If three are read simultaneously, the signals of the three pixels are added.
[0013]
Since pixel addition can increase the signal amount, it has an advantage in terms of S / N. However, in the addition method using this charge integration amplifier OP, noise generated by the charge integration amplifier OP itself cannot be reduced. Therefore, in practice, there is a problem that the S / N is not improved so much.
[0014]
Here, the relationship between pixel addition and noise of the charge integration amplifier OP will be described in detail with reference to FIG. FIG. 10 is a circuit diagram showing the output circuit of FIG. 9 in a simplified manner. In FIG. 10, the signal source VnIn represents noise generated by the charge integrating amplifier OP1 in terms of input.
[0015]
In a CMOS image sensor having a pixel array P1 and a pixel signal readout circuit R1 that reads out signals from the pixel array P1 in column parallel, the output circuit includes capacitive elements C1, C2 that hold signals read out by the pixel signal readout circuit R1. A charge integrating amplifier OP1 having the reference voltage Vref as a non-inverting (+) input, a horizontal signal line HL1 connected to the inverting (−) input terminal of the charge integrating amplifier OP1, capacitive elements C1 and C2, and a horizontal signal line HL1. Switch elements S1 and S2, which are selectively connected to each other, feedback capacitors C0 and C0 ′ of the charge integrating amplifier OP, a switch element S0 that selectively connects the feedback capacitor C0 ′ to the feedback capacitor C0 in parallel, and a feedback capacitor It has a configuration having a reset switch Srst for resetting C0. Here, for the sake of simplicity, the influence of the parasitic capacitance of the horizontal signal line HL1 is ignored.
[0016]
Next, the circuit operation of the output circuit having the above configuration will be described. First, it is assumed that the switch element S0 is off (open). In this state, when only the switch element S1 is turned on (closed) and the signal held in the capacitive element C1 is read, the gain G1 applied to the signal is determined only by the capacitance ratio of the capacitive elements C0 and C1. That is, the gain G1 is
G1 = −C1 / C0
It becomes.
[0017]
The noise of the charge integrating amplifier OP is expressed as an input converted value VnIn in FIG. 10, but the gain when this is transmitted to the output terminal Vout of the charge integrating amplifier OP is inversely proportional to the feedback amount β of the charge integrating amplifier OP. Therefore, the output noise VnOUT of the output terminal Vout is
VnOUT = VnIn / β
It becomes.
[0018]
Here, the feedback amount β is
β = C0 / (C0 + C1)
It is. Therefore, the output noise VnOUT is
VnOUT = VnIn (C0 + C1) / C0
It becomes. The input converted value VnIn is a standard deviation value of random noise generated by the charge integrating amplifier OP, and the output noise VnOUT obtained by converting the standard value is also a standard deviation value.
[0019]
On the other hand, when pixel addition is performed between two adjacent pixels in the horizontal direction by simultaneously turning on the switch elements S1 and S2 and simultaneously reading out the capacitive elements C1 and C2, the gain G2 applied to the signal is
G2 =-(C1 + C2) / C0
Thus, if the capacitance values of the capacitive elements C1 and C2 are the same, they are read with a double gain. However, in this state, the read gain becomes too large and the signal may not be within the range of the power supply voltage. Therefore, the switch element S0 is turned on and the feedback capacitor C0 'is connected in parallel with the feedback capacitor C0. In most cases, the read gain is kept constant.
[0020]
In this case, the signal readout gain G2 ′ is
G2 '=-(C1 + C2) / (C0 + C0')
If C1 = C2 and C0 = C0 ′,
G2 '=-C1 / C0
Thus, the read gain G2 'is the same as that when no addition is performed. In this case, the noise VnIn of the charge integrating amplifier OP is transmitted to the output terminal Vout in inverse proportion to the feedback amount β, but the feedback amount β is
β = (C0 + C0 ′) / (C0 + C0 ′ + C1 + C2)
= C0 / (C0 + C1)
Thus, it is not different from the one pixel readout at all. Therefore, the noise output from the charge integrating amplifier OP is constant regardless of whether or not the pixels are added.
[0021]
This occurs because the gain rebating action performed in order to keep the signal gain at the time of addition constant before the readout by the charge integrating amplifier OP due to the problem of the signal range that can be handled with the power supply voltage. (Or while reading). Therefore, if it can be divided after reading by the charge integrating amplifier OP, in principle, the noise of the charge integrating amplifier OP itself should be reduced.
[0022]
As described above, in the CMOS image sensor according to the conventional example, even if pixel addition is performed, noise of the charge integration amplifier OP cannot be reduced, but noise generated by the pixel itself (thermal noise of the FD amplifier, KT / C noise and other fixed pattern noise) can be reduced by pixel addition. Here, it is considered which of the noise of the pixel itself and the noise of the charge integrating amplifier OP is dominant. The noise of the charge integrating amplifier OP has been increasing steadily due to the increase in the data rate accompanying the increase in the number of pixels of the image sensor in recent years and the demand for low power consumption accompanying the mounting in the portable information terminal. On the other hand, as the pixel development progresses, pixel noise has improved dramatically. Therefore, the noise of the charge integrating amplifier OP is no longer dominant.
[0023]
Therefore, the present invention provides a solid-state imaging capable of reducing the data rate per channel without considering matching between channels when outputting the signals of each pixel read out in parallel in units of rows from the pixel unit in multiple channels. Providing apparatus and driving method thereof Purpose And
[0025]
[Means for Solving the Problems]
In order to achieve the above object, in the present invention, pixels including photoelectric conversion elements are two-dimensionally arranged in a matrix, and a signal charge photoelectrically converted by each photoelectric conversion element is converted into an electric signal and output in parallel In the solid-state imaging device configured to read out the signal of each pixel in parallel from the unit, the read signal of each pixel is output in a plurality of channels, and each signal of the plurality of channels is output by a multiplexer. at the same time Take in Addition And this Added analog Signal with one A / D converter Digital signal The structure to convert is taken.
[0026]
Multiple-channel signals are sequentially taken into a multiplexer, multiplexed and output as a single-channel signal, so that only one AD converter is required at the subsequent stage of the multiplexer. Therefore, the data rate per channel can be reduced without considering matching between channels.
[0029]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0030]
[First Embodiment]
FIG. 1 is a block diagram illustrating a configuration example of a solid-state imaging device according to the first embodiment of the present invention. Here, a case of a CMOS image sensor will be described as an example. In FIG. 1, a pixel unit 11 includes two-dimensionally arranged pixels including photoelectric conversion elements and FD amplifiers that convert light incident through a color filter (not shown) into an electrical signal. A row selection line is provided for each row, and a vertical signal line is provided for each column, so that signals of pixels for one row are read simultaneously.
[0031]
The vertical drive circuit 12 selects each pixel of the pixel unit 11 in units of rows, and operates transfer, readout, and reset of signals accumulated in the pixels in the selected row in units of rows. The pixel signal readout circuit 13 reads out the signal of each pixel in the row selected by the vertical scanning by the vertical drive circuit 12 in column parallel. Here, the number of pixels in the horizontal direction in the pixel unit 11 is n. Capacitance elements C1 to Cn (hereinafter also referred to as “capacitance arrays C1 to Cn”) are connected between each of the signal output lines L1 to Ln of the pixel signal readout circuit 13 and the ground, and the pixel signal readout circuit. 13 holds the signal read out in parallel in the column.
[0032]
The switch elements S1 to Sn are alternately connected between the terminal ends of the signal output lines L1 to Ln of the pixel signal readout circuit 13 and a plurality (two in this example) of horizontal signal lines HSL1 and HSL2. Specifically, the switch elements S1, S3, S5,... Are connected between the odd-numbered signal output lines L1, L3, L5,... And the horizontal signal line HSL1, and the switch elements S2, S4, S6,. Are connected between the signal output lines L2, L4, L6,... Of the even columns and the horizontal signal line HSL2.
[0033]
Here, the case where there are two horizontal signal lines is shown as an example, so that the switch elements S1 to Sn have two cycles in the horizontal direction with respect to the two horizontal signal lines HSL1 and HSL2. Although the connections are made alternately, if the number of horizontal signal lines HSL is three, they are connected in order in three cycles, in the case of four in four cycles, and so on. Become.
[0034]
The output terminals of the horizontal signal lines HSL1 and HSL2 are connected to the inverting (−) terminals of the operational amplifiers OP1 and OP2. The operational amplifier OP1 uses the reference voltage Vref as a non-inverting (+) input, and forms a charge integrating amplifier 14-1 together with a feedback capacitor C01 and a switching element Srst1 connected in parallel between the inverting input terminal and the output terminal. . Similarly, the operational amplifier OP2 uses the reference voltage Vref as a non-inverting input, and forms a charge integrating amplifier 14-2 together with the feedback capacitor C02 and the switch element Srst2 connected in parallel between the inverting input terminal and the output terminal.
[0035]
The charge integrating amplifiers 14-1 and 14-2 read each signal read from each of the capacitor arrays C 1 to Cn through the switch elements S 1 to Sn, and each of the capacitors of the capacitor arrays C 1 to Cn and the capacitors of the feedback capacitors C 01 and C 02. Amplified with a gain determined by the capacity ratio of the output. In these charge integrating amplifiers 14-1 and 14-2, the switch elements Srst1 and Srst2 reset the charges of the feedback capacitors C01 and C02. Each output of the charge integrating amplifiers 14-1 and 14-2 becomes two inputs of the multiplexer (MPX) 15.
[0036]
Here, the capacitance arrays C1 to Cn, the switch elements S1 to Sn, the horizontal signal lines HSL1 and HSL2, and the charge integration amplifiers 14-1 and 14-2 receive the signals of the pixels read in parallel from the pixel unit 11 in units of rows. , Output means for outputting in a plurality of channels (in this example, 2 channels) is configured. Of course, the number of output channels is not limited to two.
[0037]
The multiplexer 15 receives the outputs of the charge integrating amplifiers 14-1 and 14-2, and sequentially takes in and outputs them, thereby collecting signals input in two channels into one channel. The AD converter (analog-digital converter) 16 converts the analog image signal output from the multiplexer 15 into digital image data.
[0038]
Next, each operation of the charge integrating amplifiers 14-1 and 14-2 in the solid-state imaging device according to the first embodiment having the above-described configuration will be described with reference to the timing chart of FIG. The following description of the operation relates to the horizontal readout period (horizontal output period).
[0039]
First, in a state where all of the odd-numbered switch elements S1, S3, S5,... Connected to the horizontal signal line HSL1 are turned off, the switch element Srst1 of the charge integrating amplifier 14-1 is turned on by the reset pulse φSrst1, thereby returning the feedback capacitance. The charge of C01 is reset (reset operation). Next, the switch element S1 is turned on by the horizontal scanning pulse φS1, thereby reading the signal held in the capacitive element C1 to the charge integrating amplifier 14-1 through the horizontal signal line HSL1.
[0040]
Before the reading of the capacitive element C1, the half of the readout period is reached and this time, the charge of the feedback capacitor C02 is reset by turning on the switch element Srst2 of the charge integrating amplifier 14-2 by the reset pulse φSrst2. Further, at the next timing, the switch element S2 is turned on by the horizontal scanning pulse φS2, thereby reading the signal held in the capacitive element C2 to the charge integrating amplifier 14-2 through the horizontal signal line HSL2. At this point in time, the reading of the capacitive element C1 has not been completed, but when the charge integrating amplifier 14-2 has just reached about half of the reading period, the charge integrating amplifier 14-1 has finished reading the capacitive element C1 first. To do.
[0041]
After the reset operation is performed again in the charge integrating amplifier 14-1, the switch element S3 is turned on by the horizontal scanning pulse φS3 to start reading the signal held in the capacitive element C3. At this time, the reading of the capacitive element C2 has not been completed. However, when the reading of the capacitive element C3 has been completed approximately half, the reading of the capacitive element C2 is completed, and after the reset operation is started again, this time the capacitive element C4 Move on to reading. Thereafter, similar operations are sequentially repeated.
[0042]
In this way, the two charge integrating amplifiers 14-1 and 14-2 operate at a timing shifted from each other by half, and are stored in the capacitor arrays C1 to Cn connected to the two through the horizontal signal lines HSL1 and HSL2, respectively. The read signal is read out. The outputs QVOUT1 and QVOUT2 of the charge integrating amplifiers 14-1 and 14-2 are supplied to the multiplexer 15. The multiplexer 15 combines the back half of one pixel period of the outputs QVOUT1 and QVOUT2 of the charge integration amplifiers 14-1 and 14-2 that are shifted by half, thereby operating the charge integration amplifiers 14-1 and 14-2. It is possible to generate a signal of one system at twice the speed of the signal and input it to the AD converter 16.
[0043]
FIG. 3 shows an example of the configuration of the 2-input multiplexer 15. The multiplexer 15 according to this example transfers the sampled signals to the switch elements SH1 and SH2 and the capacitive elements Csh1 and Csh2 that sample the outputs QVOUT1 and QVOUT2 of the charge integrating amplifiers 14-1 and 14-2, and to the preamplifier OP3. Switch elements TR1 and TR2 for switching, and a switch element Srstm for resetting the parasitic capacitance Cpm present at the input of the preamplifier OP3 to an appropriate voltage Vm.
[0044]
The operation of the multiplexer 15 having the above configuration will be described with reference to the timing chart of FIG.
[0045]
The outputs QVOUT1 and QVOUT2 of the charge integrating amplifiers 14-1 and 14-2 are sampled when the switching elements SH1 and SH2 are sequentially turned on by the sampling pulses φSH1 and φSH2 shifted by ½ period, respectively, and the capacitive elements Csh1, Held in Csh2. The signals held in the capacitive elements Csh1 and Csh2 are sequentially transferred to the preamplifier OP3 when the switch elements TR1 and TR2 are sequentially turned on by the transfer pulses φTR1 and φTR2 that are also shifted by ½ period.
[0046]
However, the parasitic capacitance Cpm is usually present at the input of the preamplifier OP3, and color mixing occurs with the previous data as it is. Therefore, the switching element Srstm is normally turned on by the reset pulse φSrstm, so that the parasitic capacitance Cpm is set. An operation to reset the remaining signal is necessary. The switch element Srstm is turned on within a period from when the transfer pulse φTR1 is turned off to when the transfer pulse φTR2 is turned on, and within a period from when the transfer pulse φTR2 is turned off to when the transfer pulse φTR1 is turned on.
[0047]
The preamplifier OP3 sequentially outputs the transferred signals to the AD converter 16. The output signal MPXOUT of the preamplifier OP3 has a signal waveform as shown in FIG. 4, and the data rate is twice the operation period of the charge integrating amplifiers 14-1 and 14-2. However, the output signal MPXOUT of the preamplifier OP3 includes reset noise due to the reset pulse φSrstm.
[0048]
As described above, a plurality of (two in this example) charge integrating amplifiers 14-1 and 14-2 are used to read out signals on a plurality of channels (multi-channel output), and signals on the plurality of channels are sequentially received by the multiplexer 15. By taking in, multiplexing, and outputting as a single-channel signal, it is only necessary to provide one AD converter 16, so there is no need to consider matching between channels due to variations in differential error and integral error of the AD converter. Also, the data rate per channel can be reduced.
[0049]
[Second Embodiment]
FIG. 5 is a block diagram showing a configuration example of a solid-state imaging device according to the second embodiment of the present invention. In FIG. 5, the same parts as those in FIG. Also in the solid-state imaging device according to the present embodiment, the case of a CMOS image sensor will be described as an example.
[0050]
5, the configuration of the pixel unit 11, the vertical drive circuit 12 (omitted in FIG. 5), the pixel signal readout circuit 13, the capacitor arrays C1 to Cn, and the switch elements S1 to Sn are the solid-state imaging device according to the first embodiment. The configuration is the same. For example, as shown in FIG. 5, the pixel unit 11 includes G, R, G, R, G, R,..., Or B, G, B, G, B, G, in the row direction (horizontal direction). A primary color Bayer array color filter having a repetition of 2 pixels in the horizontal direction and a repetition of 2 pixels in the vertical direction (column direction) is arranged. However, the present invention is not limited to this color coding.
[0051]
In the solid-state imaging device according to the first embodiment, two horizontal signal lines HSL (HSL1, HSL2) are provided, whereas in the solid-state imaging device according to the present embodiment, for example, four horizontal signal lines HSL (HSL1) are provided. To HSL4). The switch elements S1 to Sn are connected to the four horizontal signal lines HSL1 to HSL4 in a cycle of four. Specifically, the switch elements S1, S5,... Are on the horizontal signal line HSL1, the switch elements S2, S6,... Are on the horizontal signal line HSL3, the switch elements S3, S7,. , S8,... Are connected to the horizontal signal line HSL4.
[0052]
The output terminals of the horizontal signal lines HSL1 to HSL4 are connected to the inverting terminals of the operational amplifiers OP1 to OP4. The operational amplifier OP1 uses the reference voltage Vref as a non-inverting input, and constitutes a charge integrating amplifier 14-1 together with the feedback capacitor C01 and the switch element Srst1 connected in parallel between the inverting input terminal and the output terminal. Similarly, the operational amplifier OP2 uses the reference voltage Vref as a non-inverting input, and forms a charge integrating amplifier 14-2 together with the feedback capacitor C02 and the switch element Srst2 connected in parallel between the inverting input terminal and the output terminal.
[0053]
Similarly, the operational amplifier OP3 uses the reference voltage Vref as a non-inverting input, and constitutes a charge integrating amplifier 14-3 together with the feedback capacitor C03 and the switch element Srst3 connected in parallel between the inverting input terminal and the output terminal. Similarly, the operational amplifier OP4 uses the reference voltage Vref as a non-inverting input, and forms a charge integrating amplifier 14-4 together with the feedback capacitor C04 and the switch element Srst4 connected in parallel between the inverting input terminal and the output terminal.
[0054]
The charge integrating amplifiers 14-1 to 14-4 read the signals read from the capacitor arrays C1 to Cn through the switch elements S1 to Sn, and the capacitors of the capacitor arrays C1 to Cn and the capacitors of the feedback capacitors C01 to C04. Amplified with a gain determined by the capacity ratio of the output. In these charge integrating amplifiers 14-1 to 14-4, the switch elements Srst1 to Srst4 reset the charges of the feedback capacitors C01 to C04. Each output of the charge integrating amplifiers 14-1 and 14-2 becomes two inputs of the multiplexer 15-1, and each output of the charge integrating amplifiers 14-3 and 14-4 becomes two inputs of the multiplexer 15-4.
[0055]
.., Odd-numbered switch elements S1, S3, S5, S7,..., Horizontal signal lines HSL1, HSL2, and charge integrating amplifiers 14-1, 14-2. Constitutes a first output means for outputting a signal of pixels of the same color read out in parallel from the pixel unit 11 in units of rows for each channel in a plurality of channels (in this example, 2 channels). The even-numbered capacitive elements C2, C4, C6, C8,..., The even-numbered switch elements S2, S4, S6, S8,..., The horizontal signal lines HSL3, HSL5 and the charge integrating amplifiers 14-3, 14-4 The second output unit is configured to output the signals of the pixels of the same color (colors different from the first output unit) read out in parallel from the unit 11 in units of rows by a plurality of channels. Of course, the number of output channels is not limited to two.
[0056]
The multiplexer 15-1 is provided corresponding to the first output means, receives the outputs of the charge integrating amplifiers 14-1 and 14-2, and sequentially captures and outputs them in two channels. The read signals are combined into one channel. The multiplexer 15-2 is provided corresponding to the second output means, receives the outputs of the charge integrating amplifiers 14-3 and 14-4, and sequentially takes them in and outputs them, so that two channels are provided. The read signals are combined into one channel. As is clear from FIG. 5, the multiplexers 15-1 and 15-2 have the same configuration as that in FIG. The AD converters 16-1 and 16-2 convert the analog image signals output from the multiplexers 15-1 and 15-2 into digital image data.
[0057]
Next, each operation of the charge integrating amplifiers 14-1 to 14-4 in the solid-state imaging device according to the second embodiment having the above configuration will be described with reference to the timing chart of FIG. The following description of the operation relates to the horizontal readout period (horizontal output period).
[0058]
First, in a state where the switch elements S1, S5,... Connected to the horizontal signal line HSL1 are all turned off, the charge of the feedback capacitor C01 is reset by turning on the switch element Srst1 of the charge integrating amplifier 14-1 by the reset pulse φSrst1. To do. Next, the switch element S1 is turned on by the horizontal scanning pulse φS1, whereby the signal held in the capacitive element C1 is read out to the charge integrating amplifier 14-1 through the horizontal signal line HSL1.
[0059]
Before the reading of the capacitive element C1 is finished, at the time when it has just reached ¼ of the reading period, this time, the switching element Srst3 of the charge integrating amplifier 14-3 is turned on by the reset pulse φSrst3, thereby charging the feedback capacitor C03. And the switch element S2 is turned on by the horizontal scanning pulse φS2 at the next timing, whereby the signal held in the capacitive element C2 is read out to the charge integrating amplifier 14-3 through the horizontal signal line HSL3.
[0060]
Before the reading of the capacitive element C2 is finished, at the time when it has just reached ¼ of the reading period, this time, by turning on the switching element Srst2 of the charge integrating amplifier 14-2 by the reset pulse φSrst2, the charge of the feedback capacitor C02 And the switch element S3 is turned on by the horizontal scanning pulse φS3 at the next timing, so that the signal held in the capacitive element C3 is read out to the charge integrating amplifier 14-2 through the horizontal signal line HSL2.
[0061]
Before the reading of the capacitive element C3 is completed, at the time when it has just reached ¼ of the reading period, the switching element Srst4 of the charge integrating amplifier 14-4 is turned on by the reset pulse φSrst4 to thereby charge the feedback capacitor C04. And the switch element S4 is turned on by the horizontal scanning pulse φS4 at the next timing, whereby the signal held in the capacitive element C4 is read out to the charge integrating amplifier 14-4 through the horizontal signal line HSL4.
[0062]
When the readout period of the capacitive element C4 has just reached about ¼, the readout of the capacitive element C1 is finally finished, the charge of the feedback capacitor C01 is reset again, and this time the operation of reading the signal of the capacitive element C5 is started. Transition. As described above, the charge integrating amplifiers 14-1, 14-2, 14-3, and 14-4 operate at a timing shifted by a quarter period, and sequentially read out signals.
[0063]
Here, looking at the charge integrating amplifiers 14-1 and 14-2, it can be seen that these outputs QVOUT 1 and QVOUT 2 are each shifted by ½ period. This signal is input to the multiplexer 15-1 as it is, and is sampled by turning on the switch elements SH1 and SH2 by the sampling pulses φSH1 and φSH2 which are shifted by ½ period, and is held in the capacitive elements Csh1 and Csh2.
[0064]
The signals held in the capacitive elements Csh1 and Csh2 are sequentially transferred to the preamplifier OP5 when the switch elements TR1 and TR2 are turned on by the transfer pulses φTR1 and φTR2 that are also shifted by ½ period. The preamplifier OP5 sequentially outputs the transferred signals to the AD converter 16-1. Similarly, the outputs QVOUT3 and QVOUT4 of the charge integrating amplifiers 14-3 and 14-4 are multiplexed and transferred to the preamplifier OP6. The output signals MPXOUT1 and MPXOUT2 of the preamplifiers OP5 and OP6 have signal waveforms as shown in FIG.
[0065]
When the pixel signals in a certain row (for example, the PL1 row in FIG. 5) of the pixel unit 11 are read out by the series of operations described above, only the G (Green) pixel signal is read out to the horizontal signal lines HSL1 and HSL2. Thus, only the signal of the B (Blue) pixel is read out to the horizontal signal lines HSL3 and HSL4. Further, when the next row of the PL1 row is read, only the R (Red) pixel signal is read out on the horizontal signal lines HSL1 and HSL2, and only the G pixel signal is read out on the horizontal signal lines HSL3 and HSL4. Will come.
[0066]
As described above, a plurality of (two in this example) output means for outputting the signals of the pixels read in parallel from the pixel unit 11 in units of rows in a plurality of channels (two in this example) are provided, and these outputs are provided. A plurality of multiplexers are provided corresponding to each of the means, and a plurality of output means outputs a signal of a pixel of the same color for each channel, so that when a row is read, the same horizontal signal line Only pixels of the same color are read out.
[0067]
The multiplex after being read by the charge integration amplifiers 14-1 to 14-4 is referred to as a charge integration amplifier 14-1, a charge integration amplifier 14-2, a charge integration amplifier 14-3, and a charge integration amplifier 14-4. By limiting the same color to each other, even if the parasitic capacitors Cpm5 and Cpm6 exist in the multiplexers 15-1 and 15-2, there is no concern about color mixing, so that the reset period can be omitted from the operation of the multiplex. Thus, further speedup can be achieved. In addition, since reset noise can be removed from the output waveforms of the preamplifiers OP5 and OP6 after multiplexing, a margin is created in the capture timing of the AD converters 16-1 and 16-2, and the speed margin can be increased.
[0068]
Furthermore, when performing multiplexing of a plurality of channels, there is a concern that the operation speeds of the preamplifiers OP5 and OP6 are very high compared to the operation speeds of the charge integration amplifiers 14-1 to 14-4. Therefore, the operation speed of the preamplifiers OP5 and OP6 should be faster than the optical frequency determined by the resolution of the lens that guides incident light to the solid-state imaging device and the pixel pitch. Further, since the optical frequency is usually not so high, the operation speed of the preamplifiers OP5 and OP6 can be suppressed. In this way, by performing readout-multiplexing for each color, it becomes possible to further increase the speed.
[0069]
[Third Embodiment]
The solid-state imaging device according to the third embodiment is based on the configuration of the solid-state imaging device according to the first embodiment shown in FIG. 1, and in this configuration, signals of a plurality of channels (here, two channels) are supplied as charge integration amplifiers. The pixel addition is performed by simultaneously transferring the data from 14-1 and 14-2 to the multiplexer 15. Also in this embodiment, the multiplexer 15 having the configuration shown in FIG. 3 is used, for example.
[0070]
The specific operation of the solid-state imaging device according to the third embodiment will be described below with reference to the timing chart of FIG. The following description of the operation relates to the horizontal readout period (horizontal output period).
[0071]
First, in a state where all the switch elements S1 to Sn connected to the horizontal signal lines HSL1 and HSL2 are turned off, the switch elements Srst1 and Srst2 of the charge integrating amplifiers 14-1 and 14-2 are turned on by the reset pulses φSrst1 and φSrst2. The charge of the feedback capacitors C01 and C02 is reset. Next, the switch elements S1 and S2 are turned on by the horizontal scanning pulses φS1 and φS2, so that the signals held in the capacitive elements C1 and C2 are supplied to the charge integrating amplifiers 14-1 and 14- through the horizontal signal lines HSL1 and HSL2. Read to 2 simultaneously.
[0072]
The read signal is input to the multiplexer 15 shown in FIG. Then, the switching elements SH1 and SH2 are simultaneously turned on by the in-phase sampling pulses φSH1 and φSH2, and are sampled and held in the capacitive elements Csh1 and Csh2. Next, the switching element Srstm is turned on by the reset pulse φSrstm to reset the parasitic capacitance Cpm to an appropriate voltage Vm, and then the switching elements TR1 and TR2 are simultaneously turned on by the in-phase transfer pulses φTR1 and φTR2. The signals held in the capacitive elements Csh1 and Csh2 are transferred to the preamplifier OP3.
[0073]
At this time, when the signal voltages held in the capacitive elements Csh1 and Csh2 are V1 and V2, the voltage V3 input to the preamplifier OP3 is
V3 = V1 {Csh1 / (Csh1 + Csh2 + Cpm)}
+ V2 {Csh2 / (Csh1 + Csh2 + Cpm)}
+ Vm {Cpm / (Csh1 + Csh2 + Cpm)}
It becomes.
[0074]
If Csh1 = Csh2 and Cpm << Csh1,
V3 = (V1 + V2) / 2
Thus, the average voltage of the signal voltages V1 and V2 is obtained. This means that the signals held in the capacitive element C1 and the capacitive element C2 are added.
[0075]
As described in the description of the prior art, in the case of the addition method in which two capacitive elements are simultaneously connected to the horizontal signal line when reading to the charge integrating amplifier, the read gain is doubled, and the signal range Therefore, it is necessary to increase the feedback capacity so that the read gain does not change. On the other hand, the solid-state imaging device according to this embodiment has an advantage that the read gain can be kept constant even if nothing is done if the influence of the parasitic capacitance Cpm is sufficiently small.
[0076]
Now consider noise. The input conversion noises of the charge integrating amplifiers 14-1 and 14-2 in FIG. 1 are Vn1 and Vn2, respectively. For simplicity, the influence of the parasitic capacitances of the horizontal signal lines HSL1 and HSL2 and the parasitic capacitance Cpm of the multiplexer 15 will be ignored.
[0077]
Since the output noises Vn1OUT and Vn2OUT of the charge integrating amplifiers 14-1 and 14-2 are inversely proportional to the feedback amount β as described in the conventional example,
Vn1OUT = Vn1 (C01 + C1) / C01
Vn2OUT = Vn2 (C02 + C2) / C02
It becomes. Since this is sampled and held in the capacitive elements Csh1 and Csh2 together with the signal, the signal values held in the capacitive elements Csh1 and Csh2 are:
Csh1: V1 + Vn1OUT
Csh2: V2 + Vn2OUT
In this way, the signal and noise overlap. However, the input conversion noises Vn1 and Vn2 handled here are standard deviation values, and the output noises Vn1OUT and Vn2OUT which are the conversion values are also standard deviation values.
[0078]
Thereafter, when the switch elements TR1 and TR2 are simultaneously turned on by the in-phase transfer pulses φTR1 and φTR2 and multiplexed, the signal value V3 transmitted to the preamplifier OP3 is Csh1 = Csh2.
V3 = (V1 + V2) / 2 + √ (Vn1OUT ² + Vn2OUT ² ) / 2
It becomes.
[0079]
Although both noise and signal have two average values, since the noise represents its magnitude by standard deviation, the average value is calculated not by addition averaging but by square averaging. Furthermore, for simplicity, when V1 = V2 and Vn1OUT = Vn2OUT, the signal value V3 is
V3 = V1 + (Vn1OUT / √2)
It becomes. It can be seen that the S / N is improved by the amount of noise 1 / √2 compared with the value obtained when the capacitance element Csh1 is sampled before the addition.
[0080]
Thus, when pixel addition is performed when multiplexing is performed, there is an advantage that noise of the charge integrating amplifier can be reduced. This is different from the case of adding when reading with the charge integration amplifier as in the conventional example. Since the addition is performed after reading with the charge integration amplifier, the noise generated by the charge integration amplifier is also added and averaged together. Because it is done.
[0081]
In the present embodiment, the case where signals held in adjacent capacitive elements such as the capacitive element C1 and the capacitive element C2 are added has been described as an example, but the capacitive arrays C1 to Cn and the horizontal signal lines are added. By maintaining the arrangement of the switch elements S1 to Sn connecting HSL1 and HSL2 or by devising the drive timing of the horizontal scanning pulses φS1 to φSn that drive the switch elements S1 to Sn, the capacitance elements are not adjacent to each other. It is also possible to add the signals that have been processed. For example, it is also possible to add signals skipping one pixel and add signals that have passed through a color filter of the same color.
[0082]
Further, in the present embodiment, the case where the two-pixel addition is performed using the two charge integration amplifiers 14-1 and 14-2 has been described as an example. However, the present invention is not limited to the two-pixel addition. It is possible to perform 4-pixel addition using four charge integration amplifiers, and it is also possible to drive such that reading is performed at a double data rate while adding two pixels each using four charge integration amplifiers.
[0083]
In all of the solid-state imaging devices according to the three embodiments of the present invention described above, the signals of the respective pixels read out in parallel in units of rows from the pixel unit 11 are output in a plurality of channels using a plurality of charge integration amplifiers. However, it is also possible to adopt a configuration in which an ordinary voltage follower is used instead of the charge integrating amplifier to output in a plurality of channels, or a non-inverting amplifier is used to output in a plurality of channels.
[0084]
Further, as the multiplexers 15, 15-1 and 15-2, it is possible to use a configuration as shown in FIG. 8 in addition to the configuration shown in FIG. 3. The multiplexer 25 having such a configuration uses the sampling capacitors Csh1 and Csh2 as they are for the feedback capacitor of the preamplifier OP3, and has the advantage that it is not affected by the parasitic capacitance Cpm.
[0085]
The multiplexer 25 having the configuration shown in FIG. 8 can be used similarly to the multiplexer 15 having the configuration shown in FIG. For the drive, timing pulses other than the reset pulse φSrstm in the timing chart of FIG. 4 are used.
[0086]
In FIG. 8, switch elements SH1 and SH2 operate at the timing of sampling pulses φSH1 and φSH2 in FIG. 4, respectively, and switch elements TR1 and TR2 operate at the timing of transfer pulses φTR1 and φTR2, respectively. Further, the switch elements TR1r and TR2r operate at the same timing as the switch elements TR1 and TR2, respectively, and the switch elements xTR1r and xTR2r perform the inversion operation of the switch elements TR1r and TR2r, respectively.
[0087]
Vref1, Vref2, and Vref3 are reference voltages that are set appropriately, and the three voltages may be the same voltage or different voltages. The multiplexer having the configuration shown in FIG. 8 does not require a reset operation, so that it is high speed and there is no fear of color mixing. Moreover, in the solid-state imaging device according to the third embodiment, even when the multiplexers 15-1 and 15-2 are used, the pixel addition operation can be performed in the same manner. The same applies to the effect of averaging the noise.
[0088]
In each of the above embodiments, the case where the present invention is applied to a CMOS image sensor has been described as an example. However, the present invention is not limited to the application to a CMOS image sensor, and XY represented by a MOS image sensor. In general, address-type solid-state imaging devices, and further, a signal detector photoelectrically converted by a pixel is transferred by a vertical transfer unit arranged for each vertical pixel column, and a charge detection unit provided at the subsequent stage of the vertical transfer unit for each vertical column Therefore, the present invention can also be applied to a so-called horizontal scan type solid-state imaging device that converts the signal into an electrical signal and outputs the signal by horizontal scanning.
[0089]
【The invention's effect】
As described above, according to the present invention, pixels including photoelectric conversion elements are two-dimensionally arranged in a matrix, and the signal charges photoelectrically converted by each photoelectric conversion element are converted into electric signals and output in parallel. In the solid-state imaging device configured to read out the signal of each pixel in parallel from the unit, the read signal of each pixel is output in a plurality of channels, and each signal of the plurality of channels is output by a multiplexer. at the same time Take in Addition As a result, only one AD converter is required after the multiplexer. Therefore, the data rate per channel can be set without considering matching between channels due to variations in differential and integral errors of the AD converter. Can be reduced.
[0090]
Further, in a solid-state imaging device configured to read out the signal of each pixel in parallel in a row unit from a pixel portion in which pixels including photoelectric conversion elements are two-dimensionally arranged in a matrix, a signal of each read pixel is Outputs in multiple channels using a charge integration amplifier, and simultaneously captures each signal of this multiple channel with a multiplexer and performs pixel addition, so that not only the noise inherent in the pixel signal but also the signal of each pixel is output in multiple channels S / N can be improved because the noise itself generated in the system can be averaged.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration example of a solid-state imaging apparatus according to a first embodiment of the present invention.
FIG. 2 is a timing chart for explaining the operation of the charge integrating amplifier in the solid-state imaging device according to the first embodiment.
FIG. 3 is a circuit diagram showing a configuration example of a multiplexer.
4 is a timing chart for explaining the operation of the multiplexer of FIG. 3;
FIG. 5 is a block diagram illustrating a configuration example of a solid-state imaging apparatus according to a second embodiment of the present invention.
FIG. 6 is a timing chart for explaining the operation of the charge integrating amplifier in the solid-state imaging device according to the second embodiment.
FIG. 7 is a timing chart for explaining the operation of the charge integrating amplifier in the solid-state imaging device according to the third embodiment.
FIG. 8 is a circuit diagram showing another configuration example of the multiplexer.
FIG. 9 is a circuit diagram showing a configuration of an output circuit of a parallel output type CMOS image sensor.
FIG. 10 is a circuit diagram showing the output circuit of FIG. 9 in a simplified manner in order to explain the problems of the prior art.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 11 ... Pixel part, 12 ... Vertical drive circuit, 13 ... Pixel signal readout circuit, 14-1 to 14-4 ... Charge integration amplifier, 15, 15-1, 15-2, 25 ... Multiplexer, 16, 16-1, 16-2 ... AD converter

Claims (3)

Pixel units including photoelectric conversion elements are arranged two-dimensionally in a matrix, and a pixel unit that converts signal charges photoelectrically converted by each photoelectric conversion element into an electric signal and outputs the electric signal in parallel;
Output means for outputting a signal of each pixel read in parallel from the pixel unit in units of rows in a plurality of channels;
A multiplexer that simultaneously captures and adds each signal output from the output means on the plurality of channels;
A solid-state imaging device comprising: an A / D converter that is provided for the multiplexer and converts an analog signal that is added and output by the multiplexer into a digital signal . A plurality of the output means are provided, and a plurality of the multiplexers are provided corresponding to each of the plurality of output means,
2. The solid-state imaging device according to claim 1, wherein each of the plurality of output units outputs a signal of a pixel of the same color read in parallel from the pixel unit in a row unit for each channel. Pixels including photoelectric conversion elements are two-dimensionally arranged in a matrix, and the signal charges photoelectrically converted by the respective photoelectric conversion elements are converted into electric signals and output in parallel. reading,
Output the read signal of each pixel in multiple channels,
Each signal of these multiple channels is simultaneously captured by a multiplexer and added .
A method for driving a solid-state imaging device, wherein the added analog signal is converted into a digital signal by one A / D converter.

Images