JP4428248B2 - Manufacturing method of semiconductor device - Google Patents

Description

The present invention relates to the manufacture how semiconductor equipment.

  As a product structure for reducing the size of a semiconductor device, a semiconductor device whose package matches or approximates the size of a semiconductor chip, a so-called chip size package (hereinafter referred to as CSP) is known (for example, Patent Documents 1 and 2). .

  The semiconductor device of Patent Document 1 is a CSP whose chip size is the size of the semiconductor device, and has a BGA (Ball Grid Array) structure in which external electrode terminals are conductive balls. The semiconductor device according to this example has a structure in which the wire connecting the electrode on the surface of the chip and the electrode pad of the circuit board is covered with resin. The circuit board part which connects a wire is made thin, and the device which makes the loop of a wire low is made | formed. The surface of the resin covering the wire is higher than the surface of the circuit board.

  Patent Document 2 is a CSP in which a ceramic substrate constituting a semiconductor device is larger than a semiconductor chip. Also in this semiconductor device, a part of the ceramic substrate is lowered, a metal pattern is formed in the lower part to connect the metal wire, and the metal wire is covered with a sealing agent by coating. The surface of the sealing agent covering the wire has a height corresponding to the surface of the ceramic substrate.

  On the other hand, as a semiconductor device capable of reducing the mounting height, an LGA (Land Grid Array) is known in which electrodes (external electrode terminals) disposed on the lower surface of a package are flat electrodes (for example, Patent Document 3).

JP-A-11-54556 JP 2000-307032 A JP 2002-254434 A

  Electronic devices such as portable electronic devices have been reduced in size and weight. For this reason, it is necessary to further reduce the size and weight of semiconductor devices incorporated in these electronic devices. The CSP that matches the planar outer dimension of the semiconductor device with the outer dimension of the semiconductor chip can reduce the mounting area. Further, by reducing the height (thickness) of the semiconductor device, the mounting height can be reduced, and the electronic device can be made thinner.

  In the LGA type semiconductor device, since the electrode (external electrode terminal) on the lower surface of the semiconductor device (package) has a thin flat plate shape of about 20 to 50 μm, for example, the diameter is about 0.2 to 0.3 mm. As compared with the BGA type semiconductor device formed by using the balls, the mounting height can be further reduced.

  Since the LGA type semiconductor device has an electrode thickness as thin as about 20 to 50 μm as described above, if foreign matter enters between the mounting substrate and the package, the package is lifted by the presence of the foreign matter, and the external electrode terminal May not be securely connected to the land of the mounting board.

  In addition, since the LGA type semiconductor device is connected to the external electrode terminals on the lower surface of the package, it is difficult to directly see the connected portion, and it is difficult to check the quality of the mounted state by visual observation or the like. Therefore, further countermeasures against contamination by foreign matters are taken at the mounting site of the LGA type semiconductor device.

  On the other hand, the external electrode terminal of the BGA type semiconductor device is thicker than that of the LGA type semiconductor device. However, the inclusion of a larger foreign substance causes poor electrode connection and reduced mounting reliability.

  Although the conventional semiconductor device can reduce the size of the semiconductor device by adopting the structure shown in the above-mentioned patent document, no consideration is given to improving the mounting reliability due to such contamination.

  That is, as can be seen from the patent document, the sealing body made of an insulating resin covering the wire is the same as the surface of the wiring board (circuit board) constituting the semiconductor device or a structure protruding from the wiring board (circuit board). It has become. For this reason, when a foreign substance is mixed between the mounting board and the wiring board, the semiconductor device is lifted by the foreign substance. As a result, some of the external electrode terminals float without being in close contact with the land, and connection with an adhesive such as solder becomes impossible, or the connection area is reduced and connection reliability is lowered.

An object of the present invention is to provide a manufacturing how the reliable small semiconductor equipment implementation.
Another object of the present invention is to provide a manufacturing how semiconductor equipment of reliable implementation thin.
Another object of the present invention is to provide a manufacturing how semiconductor equipment of small and thin that reduction in manufacturing cost can be achieved.
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

Semiconductors devices are manufactured by a manufacturing method having the following steps. This manufacturing method is
(A) preparing a semiconductor wafer having a circuit element is aligned formed in a matrix and electrode of the circuit element on the first surface,
(B) said I step der preparing a wiring mother substrate having a wiring block portion which is aligned formed in a matrix so as to correspond to each circuit element, the wiring mother substrate, the first surface and the first surface of a second surface on the opposite face, said first face Ri flat surfaces der, the wiring block section, first part made of an insulating flat plate, and extending life-and-death from said first portion A second portion that is thinner than the first portion, wherein the first portion and the first surface of the second portion are located on the same plane and are opposite to the first surface; Each of the second surfaces of the second part has a plurality of conductor layers, and the predetermined conductor layers of the first part and the predetermined conductor layers of the second part are interposed via conductors provided therein. a step ing an electrically connected structure Te,
(C) connecting the first surface of the wiring mother board to the first surface of the semiconductor wafer with an insulating adhesive ;
; (D) first said electrode conductor layers of the second part of the wiring mother substrate surface I step der of connecting a conductive wire, a loop of the wire the first part of the semiconductor wafer Forming a lower surface than the second surface ;
(E) the first surface of the semiconductor wafer, said second part and said wire I step der of forming the resin layer is covered with an insulating resin, the surface of the resin layer of the first part Forming a predetermined height lower than the surface of 2 ;
(F) and having a step of forming a plurality of semiconductor devices with the wiring mother substrate and the semiconductor wafer is cut lengthwise and crosswise so as to divide each said circuit element.

Further, in the step of preparing a distribution Senhaha substrate (b), extending the wiring block section along the parallel department direction, one groove which penetrates the wiring mother board in a central portion of each wiring block unit Forming the wiring block pattern so that the tip of the second part extends from both sides toward the groove,
The wiring mother substrate in a state of being bonded to the semiconductor wafer so as to position the electrode of the semiconductor wafer in the groove.

Further, in the step of preparing a distribution Senhaha substrate (b), extending the wiring block section along the parallel department direction, one formed between the wiring block portions adjacent the groove which penetrates the wiring motherboard And forming the wiring block pattern so that the tip of the second part extends from both sides toward the groove,
In a state where the wiring mother board and the semiconductor wafer are bonded, two or more electrodes of the semiconductor wafer are positioned in the groove.

Further, in the step of forming a tree fat layer (e), bonding was below the semiconductor wafer and the wiring mother board to cover the second surface of the wiring mother substrate of a deformable sheet, mold them The resin layer is formed by injecting a resin from one end side of the groove by transfer molding in a state where the mold is clamped between the mold and the upper mold and the sheet is inserted into the groove to a predetermined depth.

Further, in the step of preparing a distribution Senhaha substrate (b), the conductive layer of the first part previously formed in a plate shape, to produce a semiconductor device as a land grid array terminals.

A semiconductor chip having a first surface having electrodes, a second surface opposite to the first surface, and a plurality of side surfaces connecting these surfaces;
A first portion made of an insulator and a second portion extending from the first portion and being thinner than the first portion; and the first surfaces of the first portion and the second portion are on the same plane. The first surface is bonded to the first surface of the semiconductor chip that is out of the position of the electrode via an insulating adhesive, and is opposite to the first surface. Each of the second surface of the first part and the second part has a plurality of conductor layers, and the predetermined conductor layer of the first part and the predetermined conductor layer of the second part are provided inside. A wiring block having a structure electrically connected through a conductor,
A conductive wire connecting the predetermined conductor layer of the second part of the wiring block and the predetermined electrode of the semiconductor chip;
A semiconductor device having a first surface of the semiconductor chip, the second portion of the wiring block, and an insulating sealing body covering the wires;
A mounting substrate having a land on an upper surface corresponding to the conductor layer of the first part of the wiring block of the semiconductor device;
The semiconductor device is an electronic device in which the conductor layer of the first part is connected to the land via a conductive adhesive,
The surface of the sealing body has a predetermined height lower than the second surface of the first part of the wiring block.
The conductor layer of the first part is formed in a flat plate shape and serves as a land grid array type terminal.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
According to the means of (1), (a) in the manufacture of a semiconductor device, the resin layer formed so as to cover the first surface of the semiconductor wafer, the second portion of the wiring block portion, and the wire is used as a sheet. Since it is formed by transfer molding, the surface of the resin layer used as a sealing body is a surface recessed about 100 μm or less from the second surface of the wiring motherboard. Therefore, when a semiconductor device is mounted on the mounting substrate, even if foreign matter is mixed between the mounting substrate and the semiconductor device, the foreign matter does not enter the retracted portion of the sealing body and lift the semiconductor device, or Since the floating amount is reduced, the bonding of the electrode (external electrode terminal) of the semiconductor device and the land of the mounting substrate by the adhesive is surely performed, and the mounting yield is improved and the mounting reliability is increased. As a result, the reliability of an electronic device incorporating this semiconductor device is increased.

(B) By using the wiring block, the electrode arrangement of the semiconductor chip can be rearranged into a plurality of rows of external electrode terminal arrangements, and the semiconductor device can be downsized.
(C) Since the external electrode terminal formed of the conductor layer is an LGA type, the semiconductor device can be thinned. As a result, the mounting height of the semiconductor device is reduced, and an electronic device incorporating the semiconductor device can be made thinner.
(D) Since the planar size of the semiconductor device is the size of the semiconductor chip itself, it becomes a CSP structure, and the semiconductor device can be miniaturized.
(E) According to the above (b) to (d), the weight of the semiconductor device can be reduced by making the semiconductor device thin and small.

  (F) Since the retracted sealing body is formed by transfer molding using a sheet, it is possible to perform a mold in which the retracting amount is always constant with good reproducibility, and it is possible to improve product quality and yield. As a result, the manufacturing cost of the semiconductor device can be reduced.

  (G) Since the semiconductor device can be manufactured by wire bonding, resin layer formation, and separation, starting with the bonding of the wiring mother board and the semiconductor wafer, the manufacturing cost of the semiconductor device can be reduced by simplifying the mass production and the manufacturing process. .

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment of the invention, and the repetitive description thereof is omitted.

  1 to 16 are diagrams relating to a semiconductor device according to a first embodiment of the present invention. 1 to 4 are diagrams related to the structure of the semiconductor device, FIG. 5 is a cross-sectional view showing a mounted state of the semiconductor device, and FIGS. 6 to 16 are diagrams related to a method for manufacturing the semiconductor device.

  The semiconductor device 1 according to the first embodiment has a structure as shown in FIGS. 1 is a perspective view of the semiconductor device, FIG. 2 is a cross-sectional view taken along line AA of FIG. 1, FIG. 3 is a bottom view of the semiconductor device, and FIG. 4 is a bottom view of the semiconductor device from which a sealing body covering the chip surface is removed. FIG.

  As shown in FIGS. 1 to 3, the semiconductor device 1 according to the first embodiment is a hexahedron (cuboid), and the upper surface is formed by the second surface 2 b of the semiconductor chip 2. The semiconductor chip 2 is a rectangular body, and is not particularly limited, but has a rectangular shape. An electrode 3 is disposed on the first surface 2 a which is the opposite surface of the second surface 2 b of the semiconductor chip 2. The first surface 2a faces downward as shown in FIG. The semiconductor chip 2 has a center pad structure, and the electrodes 3 are arranged in a line along the longitudinal direction of the semiconductor chip 2 and along the center. A pair of wiring blocks 4 are arranged with this electrode 3 in between. The first surface 4 a of the wiring block 4 is bonded to the first surface 2 a of the semiconductor chip 2 via an insulating adhesive 5.

  The wiring block 4 is made of an insulating flat plate and has a wiring board structure. For example, the wiring block 4 has a wiring board structure in which two wirings (conductor layers) obtained by bonding two glass epoxy resins are two layers. That is, the above-mentioned conductor layers located above and below by two conductors formed by bonding two glass epoxy resin plates each having a predetermined pattern of conductor layer formed on the same surface side and penetrating through one glass epoxy resin plate Are electrically connected.

  As shown in FIGS. 1 to 4, the wiring block 4 has a first part 4e made of an insulating flat plate and a second part 4f extending from the first part 4e and thinner than the first part 4e. ing. The first portion 4e is a portion where two glass epoxy resin plates are bonded together, and the second portion 4f is a portion formed by one glass epoxy resin plate. One glass epoxy resin plate extends over the first portion 4e and the second portion 4f, and another glass epoxy resin plate overlaps with the first portion 4e. In other words, the wiring block 4 is lowered in a stepped manner on one surface, and this lower portion has a structure constituting the second portion 4f. Accordingly, one surface (first surface 4a) of the first portion 4e and the second portion 4f is located on the same plane, but the second surface 4b, which is the opposite surface of the second surface 4b, is stepped. The second surface 4b of the second part 4f is a surface (lower surface) that is recessed than the second surface 4b of the first part 4e.

  A conductor layer 6e serving as an external electrode terminal is formed on the second surface 4b (lower surface in FIG. 2) of the first portion 4e of the wiring block 4, and the conductor layer 6f is formed on the second surface 4b of the second portion 4f. Is formed. Since the wiring block 4 is formed by bonding two glass epoxy resin plates, and the conductor layer 6f is formed so as to enter the inside of the wiring block 4, the conductor layer 6f is formed inside the wiring block 4. Extend to. The conductor layer 6f is electrically connected to the conductor layer 6e by a conductor 6j provided through a single glass epoxy resin plate. In the figure, the first glass epoxy resin plate and the second glass epoxy resin plate are not distinguished from each other, and are shown in a sectional view in which the wiring block 4 is integrated.

  Also, the conductor layer 6f disposed on the second surface 4b of the second portion 4f is disposed in parallel as shown in FIG. 4, and one end of the conductive wire 7 is connected to the tip thereof. It has become. The conductor layers 6e provided on the second surface 4b of the first part 4e are arranged in two rows along the longitudinal direction of the wiring block 4, as shown in FIGS. As shown in FIG. 3, the outer ends of the conductor layers 6f are located corresponding to the conductor layers 6e, and the outer ends of the conductor layers 6e and 6f are electrically connected by the conductors 6j. Also, the conductor layer 6f connected to the outer conductor layer 6e arranged in two rows and the conductor layer 6f connected to the inner conductor layer 6e are not in contact with each other as shown in FIG. Further, it is formed in a bent pattern.

  The conductor layers 6e and 6f are formed of a copper layer. The surface portion of the conductor layer 6f to which the wire is connected and the surface of the conductor layer 6e have a desired metal plating film so that the wettability with the adhesive (solder or the like) during wire connection or mounting is improved. Is formed. This metal plating film is, for example, a Ni layer-Au layer (the lower layer is Ni: the thickness is 5 μm for the Ni layer and 0.5 μm for the Au layer). The wire connection portion may be an Ag plating film. In addition, it is good also as a structure which covers the periphery etc. of the conductor layer 6e and the conductor layer 6f with a soldering resist. In the first embodiment, the manufacturing cost of the semiconductor device 1 can be reduced by not forming the solder resist.

  As shown in FIGS. 2 and 4, the semiconductor device 1 is arranged such that the thin second portion 4 f of the pair of wiring blocks 4 is on the inside and the thick first portion 4 e is on the outside. The electrode 3 on the first surface 2 a of the semiconductor chip 2 exposed between the pair of wiring blocks 4 and the conductor layer 6 f of the second portion 4 f of the wiring block 4 are connected by a conductive wire 7. Moreover, the hollow part between a pair of wiring blocks 4 is filled with the sealing body 8 formed with an insulating resin. The sealing body 8 has a structure that covers the first surface 2 a of the semiconductor chip 2, the second portion 4 f of the wiring block 4, and the wires 7.

  This is one of the features of the present invention. The surface 8a of the sealing body 8 is lower than the first surface 4a of the first part 4e of the wiring block 4 by a predetermined dimension. For example, the surface 8a of the sealing body 8 is recessed by 0.1 mm from the first surface 4a of the first part 4e. This retracting means that when a semiconductor device is mounted on a mounting substrate, if a foreign object is mixed between the mounting substrate and the semiconductor device, the semiconductor device is lifted by the foreign material and mounting by an adhesive such as solder becomes incomplete. It is for preventing.

  As will be described later, the semiconductor device 1 is formed by bonding a semiconductor wafer in which circuit elements are arranged vertically and horizontally and a wiring mother board in which wiring block portions are arranged in vertical and horizontal directions corresponding to the circuit elements. For example, a plurality of semiconductor devices are manufactured by forming a resin layer and cutting the stacked semiconductor wafer and wiring mother board vertically and horizontally. Therefore, the size of the semiconductor device 1 in the planar direction is the size of the semiconductor chip 2, a CSP structure, and a small size. Further, as shown in FIG. 2, the semiconductor device 1 has an LGA (Land Grid Array) structure in which a flat conductor layer 6 f protrudes from the lower surface of the wiring block 4.

  Since the semiconductor device 1 is manufactured by cutting the wiring mother board, the semiconductor wafer, and the resin layer vertically and horizontally as described above, the upper surface of the semiconductor device 1 is the second of the semiconductor chip 2 as shown in FIG. The lower surface is formed by the wiring block 4 and the sealing body 8 as shown in FIG. Further, as shown in FIG. 1, both sides of the semiconductor device 1 are formed by the semiconductor chip 2 and the first portion 4 e of the wiring block 4. As shown in FIG. 1, the end face of the semiconductor device 1 is formed by the semiconductor chip 2, the first part 4 e and the second part 4 f of the wiring block 4, and the sealing body 8. In the first embodiment, the external electrode terminal has a circular shape, but may have another shape, for example, a square shape.

  Here, some dimensions of the semiconductor device 1 will be described. The wiring block 4 formed by laminating two glass epoxy resin plates to which a copper foil having a thickness of about 35 μm is attached has a thickness of about 0.2 to 0.5 mm including the conductor layer 6e. Further, although the semiconductor chip 2 has a thickness of 100 to 400 μm, depending on the product, it becomes a thin LGA type semiconductor device 1 with a thickness of 0.3 to 0.9 mm.

  FIG. 5 is a cross-sectional view showing a state in which the semiconductor device is mounted on the mounting substrate. On the upper surface of the mounting substrate 10, there is a land 11 corresponding to the conductor layer 6 e serving as the external electrode terminal of the semiconductor device 1. Therefore, in mounting, the semiconductor device 1 is positioned and placed on the mounting substrate 10, and the adhesive 12 such as solder previously formed on the land 11 or the adhesive 12 such as solder applied to the conductor layer 6e is reflowed. (Reheating) to fix (mount) the semiconductor device 1 to the mounting substrate 10.

  At this time, if a foreign material larger than the gap is mixed between the mounting substrate 10 and the semiconductor device 1, the semiconductor device 1 is lifted by the foreign material, and a part of the conductor layer 6 e is separated from the land 11 and reliably adhered by the adhesive 12. Connection may not be possible. However, in the case of the present Example 1, since the surface 8a of the sealing body 8 is recessed rather than the 2nd surface 4b of the 1st part 4e in which the conductor layer 6e is provided, it does not lift by a foreign material and is reliable. Can be mounted (connected). Further, even if the lifting occurs, the lifting amount is reduced by the retraction, so that the connection with the adhesive 12 becomes possible.

  In the mounting substrate 10, since the semiconductor device 1 has a CSP structure and is small, the mounting area becomes small. As a result, the mounting substrate can be reduced in size, and the electronic device in which the mounting substrate is incorporated can be reduced in size. Further, in the case of an electronic device in which a large number of semiconductor devices 1 are mounted, the area of a vacant area that is not used increases due to a reduction in the mounting area of the semiconductor device 1. Therefore, it is possible to mount the semiconductor device 1 and other electronic components in the empty area. As a result, it is possible to achieve further multi-functionality and performance improvement of the electronic device. In addition, since the semiconductor device 1 has an LGA structure and is thin, the mounting height is also reduced, and the electronic device can be made thinner accordingly.

Next, a method for manufacturing the semiconductor device 1 will be described with reference to FIGS. As shown in the flowchart of FIG. 6, the semiconductor device 1 includes a wiring board (wiring mother board) / semiconductor wafer preparation (S01), a wiring board (wiring mother board) / semiconductor wafer bonding (S02), and wire bonding (S03). It is manufactured through the steps of resin layer formation (S04), separation (tape support state: S05), and tape removal (S06).
In the manufacture of the semiconductor device 1, as shown in FIGS. 7A, 7B and 8, a semiconductor wafer 20 and a wiring mother board (wiring board) 21 are prepared (S01).

  The semiconductor wafer 20 is made of, for example, a silicon substrate, and circuit elements are already formed. Here, the circuit element is a circuit in which one or a plurality of active elements such as transistors are formed, and is an entire circuit formed on a semiconductor chip. The outline of the circuit element 22 is indicated by a dotted line in FIG. 10. The circuit element 22 is a rectangular portion, the length of the short side is d, and the length of the long side is e. As shown in FIG. 10, the semiconductor wafer 20 has an orientation flat 20c in which one edge is cut out linearly, and a plurality of the circuit elements 22 are arranged in alignment vertically and horizontally with reference to the orientation flat 20c. . Finally, cutting is performed at the outline portion of the circuit element 22, and the semiconductor wafer 20 becomes the semiconductor chip 2 constituting the semiconductor device 1.

  7A and 12 show the electrode 3 of the circuit element 22. The electrodes 3 are provided on the first surface 20a of the semiconductor wafer 20, and are arranged in a line along the center of the circuit element to constitute a center pad structure. The second surface 20b, which is the opposite surface to the first surface 20a, is a flat surface.

  As shown in FIGS. 8 and 10, the wiring mother board 21 is a rectangular body having a size that overlaps the entire semiconductor wafer 20. The wiring mother board 21 is overlaid so that one side thereof coincides with the orientation flat 20 c of the semiconductor wafer 20. Wiring block portions 25 are aligned and formed vertically and horizontally with respect to the one side. When the wiring mother board 21 is overlaid on the semiconductor wafer 20, each wiring block portion 25 overlaps with each circuit element 22 of the semiconductor wafer 20. That is, the wiring block portion 25 is also rectangular, the short side is d, and the long side is e. Finally, cutting is performed at the outline portion of the wiring block portion 25, and the wiring block portion 25 becomes a pair of wiring blocks 4 constituting the semiconductor device 1.

  Further, as shown in FIG. 8, grooves 26 are formed in the wiring mother board 21 in parallel. The groove 26 is disposed along the center of the wiring block portion 25, and the electrode 3 of the semiconductor wafer 20 is positioned along the center of the groove 26 when the semiconductor wafer 20 is bonded to the wiring mother board 21. (See FIGS. 11 and 12). The groove 26 extends along the long side of the wiring block portion 25. As shown in FIG. 9, the groove 26 has a T-shaped cross section, a thin groove on the first surface 21a of the wiring motherboard 21, and a second surface that is the opposite surface of the first surface 21a. 21b is wider than the narrow groove.

  The wiring mother board 21 is formed by forming a conductor layer having a predetermined pattern on the same surface side and bonding two glass epoxy resin plates each having a groove, so that the groove of one glass epoxy resin plate is formed on the other side. If formed wider than the glass epoxy resin plate, the groove 26 having the above-mentioned T-shaped cross section can be formed. If a conductor 6j that penetrates a predetermined portion of the glass epoxy resin plate having a wide groove width is formed, a conductor layer 6e provided on one surface of the glass epoxy resin plate having a wide groove width and a glass epoxy resin having a narrow groove width. The conductor layer 6f provided on one surface of the plate can be electrically connected by bonding two glass epoxy resin plates. Since the structure of the pair of wiring blocks 4 in the wiring block unit 25 has already been described, a description thereof will be omitted. The entire wiring mother board 21 is the first part 4e, and only the part facing the groove 26 is the second part 4f thinner than the first part 4e. Further, a guide hole 21j used for transferring or positioning the wiring mother board 21 is provided in the peripheral portion of the wiring mother board 21. In the figure, the boundary line between the two glass epoxy resin plates is omitted.

  Next, as shown in FIG. 7B, the first surface 20 a of the semiconductor wafer 20 is bonded to the first surface 21 a of the wiring mother board 21 via the insulating adhesive 5. At this time, alignment is performed so that the circuit element 22 of the semiconductor wafer 20 and the wiring block portion 25 of the wiring mother board 21 coincide and overlap each other. As a result, as shown in FIG. 11, the electrode 3 provided on the first surface 20 a of the semiconductor wafer 20 is positioned in the groove 26. In FIG. 7 and the subsequent process cross-sectional views, the conductor layer 6f, the conductor 6j, and the like are omitted for easy understanding of the drawing.

  Next, as shown in FIGS. 7C, 10, and 11, the electrode 3 (see FIGS. 11 and 12) provided on the first surface 20 a of the semiconductor wafer 20 in each wiring block unit 25. The inner end of the conductor layer 6 f of the wiring block portion 25 is connected by the conductive wire 7. The loop height of the wire 7 is set lower than the second surface 21 b of the thick first part 4 e of the wiring mother board 21. The wire 7 is then covered with a resin layer, and the surface of the resin layer is also made lower than the second surface 21b of the thick first portion 4e of the wiring motherboard 21. In consideration of mounting of the semiconductor device 1, the surface of the resin layer is, for example, 100 μm or less lower than the second surface 21 b of the thick first portion 4 e. In consideration of the sealing performance (for example, moisture resistance) of the resin layer covering the wire 7, that is, the sealing body 8, the height of the loop of the wire 7 so that the thickness of the resin on the wire 7 becomes 100 μm. Decide. In wire bonding, since the first bonding point is the surface of the electrode 3 of the semiconductor wafer 20 and the second bonding point is the surface of the conductor layer 6f, it is easy to reduce the height of the wire loop from the conductor layer 6f. It is.

  Next, as shown in FIG. 7D, a resin is injected into each groove 26 of the wiring mother board 21 to form a resin layer 27 that covers the thin second portion 4 f and the wires 7. As described above, the resin layer 27 is formed lower than the second surface 21b of the thick first portion 4e of the wiring motherboard 21. For example, it is formed to be 100 μm or less lower than the second surface 21b of the thick first portion 4e of the wiring motherboard 21.

  The resin layer 27 may be formed by printing, potting, or the like. However, in the first embodiment, the resin layer 27 is formed by a transfer molding method using a sheet that can determine the surface height with good reproducibility.

  In FIG. 13, the upper and lower surfaces of the semiconductor wafer 20 attached to the wiring mother board 21 are covered with resin (elastic body) sheets 28 and 29, and sandwiched between the lower mold 30 and the upper mold 31 of the mold, and Shows the state of mold clamping. The lower mold 30 and the upper mold 31 form a gate 32 for injecting resin on one end side of the groove 26 and an air vent 33 for releasing air on the other end side. The groove 26 becomes a cavity 34 by the upper die 31. A liquid resin 35 is injected from the gate 32 into the cavity 34.

  The upper surface of the cavity 34 is formed of a sheet 28, and the sheet 28 bites into the groove 26 by tightening the lower mold 30 and the upper mold 31, so that the surface of the resin layer 27 is the first portion 4e of the wiring mother board 21. Retract from the second surface 21b. The amount of biting (depth) is the depth of the surface 8 a of the resin layer 27. Accordingly, the depth (amount) of retraction can be changed by changing the thickness of the sheet. As the resin for forming the resin layer 27, for example, an epoxy resin is used. After filling the resin, the resin layer 27 is formed by curing at a predetermined temperature to cure the resin. Even in this cure, the resin layer 27 is small but hardens and shrinks. If necessary, the resin layer 27 is formed in consideration of the amount of curing shrinkage. FIG. 16 is an enlarged cross-sectional view showing the wiring mother board 21 and the like on which the resin layer 27 having the recessed surface 8a is formed. When the semiconductor wafer 20 and the wiring mother board 21 are cut vertically and horizontally, the resin layer 27 is also cut, and the resin layer 27 forms the sealing body 8 constituting the semiconductor device 1.

  FIG. 14 is a plan view showing an overlapping state between the transfer molding die and the wiring mother board 21 and the like. In FIG. 14, the resin flow path formed by the lower mold 30 and the upper mold 31 will be described. It consists of two circular culls 39 for extruding the melted resin, a runner 40 that guides the resin connected to the cull 39, and a gate 32 and a cavity 34 that follow the runners 40. Further, an air vent 33 is disposed on the tip side of the groove 26. Sheets 28 and 29 having a thickness of 50 μm are used.

  When the resin layer 27 is formed, as shown in FIG. 15, one end side of the groove 26 of the wiring mother board 21 is removed to a predetermined depth to form a groove 41, and this groove 41 is used as the gate 32. For example, as shown in FIG. 15, the surface of the upper mold 31 corresponding to the gate 32 can be a flat surface. As a result, the flow of the resin 35 is not stepped as in the case of FIG. 13, but becomes flat, so that the resin 35 can be injected more stably and the generation of bubbles (voids) can be reduced. it can. This not only increases the reliability of the product but also improves the yield. Further, when the upper die 31 is made flat, it is not necessary to form the gate 32 as shown in FIG. 13 in the upper die 31, thereby reducing the manufacturing cost of the mold and reducing the manufacturing cost of the semiconductor device.

  Next, as illustrated in FIG. 7E, a tape 45 serving as a support member is attached to the second surface 20 b side that is the exposed surface of the semiconductor wafer 20. Thereafter, separation grooves 46 are formed vertically and horizontally so as to reach the surface of the tape 45 from the upper surface of the wiring mother board 21. The groove 46 is formed by cutting with a dicing blade 47. In the cutting by the dicing blade 47, the wiring mother board 21, the semiconductor wafer 20 and the resin layer 27 are completely divided, but the tape 45 is not divided, and the tip of the dicing blade is controlled to the tape surface or halfway depth. To do.

  Further, by cutting the dicing blade 47, the wiring mother board 21 has the thick first portion 4e and the thin second portion 4f facing the second portion 4f as shown in FIGS. A pair is formed. Further, by cutting, the resin layer 27 becomes the sealing body 8, the semiconductor wafer 20 becomes the semiconductor chip 2, and a plurality of semiconductor devices 1 attached to the tape 45 are formed. The tape 45 may be affixed to the wiring mother board 21 and then the semiconductor wafer 20 and the wiring mother board 21 may be cut from the semiconductor wafer 20 side.

  Next, by removing the tape 45, as shown in FIG. 7G, a plurality of semiconductor devices 1 having the structure shown in FIG. 1 are manufactured. For example, as shown in FIG. 7 (f), the tape 45 is removed by pushing up a plurality of push-up needles 48 from below the tape 45 to separate the semiconductor device 1 on the tape 45 from the tape 45. The semiconductor device 1 may be vacuum-sucked and held by the pickup tool 49 from above, and the pickup tool 49 may be moved and stored in a storage tray or the like. The pick-up tool 49 holds the surface 8a of the flat sealing body 8 by vacuum suction.

  FIGS. 17 to 19 are modifications of the first embodiment and relate to a semiconductor device in which a semiconductor chip having pads on both sides is incorporated. 17 is a cross-sectional view of the semiconductor device, FIG. 18 is a bottom view of the semiconductor device, and FIG. 19 is a cross-sectional view showing a mounted state of the semiconductor device.

  As shown in FIGS. 17 and 18, the semiconductor device 1 according to this modification has a structure in which the electrodes 3 are arranged on both sides in place of the center pad chip in the manufacture of the semiconductor device 1 of the first embodiment. The semiconductor chip 2 is used.

  In the case of the first embodiment, the cutting is performed between the groove 26 and the groove 26. However, in the case of the modification, the cutting position of the wiring mother board 21 is cut at the center of the groove. In this case, the electrodes 3 are arranged on both sides of the cutting line, and the wiring block 4 formed by cutting is formed of a single rectangular body, and both sides are thin second portions 4f. Since the sealing body 8 is arranged along the both sides of the semiconductor device 1, the resin layer 27 for forming the sealing body 8 can be formed by transfer molding, which improves productivity. Improvements can be made.

The first embodiment has the following effects.
(1) In the manufacture of the semiconductor device 1, the sheets 28 and 29 are used for the resin layer 27 formed so as to cover the first surface 20 a of the semiconductor wafer 20, the second portion 4 f of the wiring motherboard 21, and the wires 7. Since the surface is formed by transfer molding, the surface 8 a of the resin layer 27 to be the sealing body 8 is a surface recessed about 100 μm or less from the second surface 21 b of the wiring mother board 21. Therefore, when the semiconductor device 1 is mounted on the mounting substrate 10, even if foreign matter is mixed between the mounting substrate 10 and the semiconductor device 1, the foreign matter enters the portion where the sealing body 8 is retracted, and the semiconductor device 1 is lifted. Therefore, the conductive layer 6e serving as an electrode (external electrode terminal) of the semiconductor device 1 and the land 11 of the mounting substrate 10 are reliably bonded to each other by the adhesive 12 to improve the mounting yield. Improves the reliability of mounting. It is more effective if the amount of retraction is 10 to 100 μm. As a result, the reliability of the electronic device incorporating the semiconductor device 1 is increased.

(2) By using the wiring block 4, it is possible to rearrange and wire the electrode array of the semiconductor chip 2 into a plurality of rows of external electrode terminal arrays, and the semiconductor device 1 can be downsized.
(3) Since the external electrode terminal formed of the conductor layer 6e is an LGA type, the semiconductor device 1 can be thinned. As a result, the mounting height of the semiconductor device 1 is reduced, and the electronic device incorporating the semiconductor device 1 can be thinned.
(4) Since the planar size of the semiconductor device 1 is the size of the semiconductor chip 2 itself, a CSP structure is formed, and the semiconductor device 1 can be reduced in size.
(5) According to the above (2) to (4), the weight of the semiconductor device can be reduced by making the semiconductor device thin and small.

  (6) Since the retracted sealing body 8 is formed by transfer molding using the sheets 28 and 29, a mold in which the retracted amount is always constant can be performed with good reproducibility, and product quality and yield are improved. Can be planned. As a result, the manufacturing cost of the semiconductor device 1 can be reduced.

  (7) Since the semiconductor device 1 can be manufactured by wire bonding, resin layer formation, and separation, starting with the bonding of the wiring mother board 21 and the semiconductor wafer 20, the manufacturing cost of the semiconductor device can be reduced by simplifying mass production and manufacturing processes. Can be achieved.

  (8) According to the above (1) to (7), a thin, small, and lightweight semiconductor device with high mounting reliability can be manufactured at low cost. In addition, an electronic device incorporating this semiconductor device can be reduced in thickness, size and weight, and the cost of the electronic device can be reduced by incorporating an inexpensive semiconductor device.

  20 to 23 are diagrams relating to a semiconductor device which is Embodiment 2 of the present invention. 20 is a flowchart showing a method for manufacturing a semiconductor device, FIG. 21 is a process sectional view showing a method for manufacturing a semiconductor device, FIG. 22 is an enlarged sectional view of a part of FIG. 21 (e), and FIG. It is sectional drawing which shows the mounting state of a semiconductor device.

  In the second embodiment, in the method for manufacturing the semiconductor device 1 of the first embodiment, after the resin layer 27 is formed, the conductive film 55 is formed on the surface of the conductor layer 6e, and the resin layer 27 is cut. The level difference between the surface 8a of the sealing body 8 and the surface of the coating 55 serving as the surface of the external electrode terminal is increased by the thickness of the coating 55 compared to the semiconductor device 1 of the first embodiment.

  The manufacturing process of the semiconductor device 1 of the first embodiment is S01 to S06 as shown in the flowchart of FIG. 6, but in the method of manufacturing the semiconductor device of the second embodiment, the resin layer 27 is formed (S04). Next, plating film formation (S11) is performed, and separation of Example 1 (tape support state: S05) is performed again. Therefore, after manufacturing the resin layer 27 of FIG. 21D, which is a sectional view of the manufacturing process of the semiconductor device 1, a film 55 is formed on the surface of the conductor layer 6e as shown in FIG. In FIG. 21E and subsequent figures, the coating 55 is shown in black. FIG. 22 shows an enlarged coating 55 provided on the surface of the conductor layer 6e. Thereafter, the grooves 46 are formed by the dicing blade 47 as shown in FIG. FIGS. 21 (f) to 21 (h) correspond to FIGS. 7 (e) to 7 (g).

  When the semiconductor device 1 according to the second embodiment is mounted on the mounting substrate 10 as shown in FIG. 23, the distance from the surface of the mounting substrate 10 to the surface 8a of the sealing body 8 is equal to the thickness of the coating 55. Therefore, the mounting defect due to the contamination is less likely to occur, and the mounting quality and the mounting yield can be improved.

  As a method of forming the coating 55 on the surface of the conductor layer 6e, a method of forming the conductive coating 55 on the surface of the conductor layer 6e by plating, printing, or the like when the wiring mother board 21 is formed can be employed.

  24 to 32 are diagrams relating to a semiconductor device which is Embodiment 3 of the present invention. 24 to 27 are views showing the structure of the semiconductor device, FIG. 28 is a cross-sectional view showing the mounting state of the semiconductor device, and FIGS. 29 to 32 are views relating to a method for manufacturing the semiconductor device.

  As shown in FIGS. 24 to 27, the semiconductor device 1 according to the third embodiment is similar to the semiconductor device 1 according to the first embodiment in that a ball electrode (projection electrode) 60 is formed on the surface of the conductor layer 6e. The semiconductor device 1 has array type terminals (external electrode terminals).

  The manufacturing process of the semiconductor device 1 of Example 1 is S01 to S06 as shown in the flowchart of FIG. 6, but in the method of manufacturing the semiconductor device of Example 3, the resin layer 27 is formed (S04). Next, bump electrode formation (S22) is performed, and separation of Example 1 (tape support state: S05) is performed again. Therefore, after manufacturing the resin layer 27 of FIG. 30D, which is a sectional view of the manufacturing process of the semiconductor device 1, the ball electrode 60 is formed on the surface of the conductor layer 6e as shown in FIG.

  FIG. 31 is an enlarged plan view of a part of the wiring mother board 21 and the like after the wire bonding in FIG. FIG. 32 is an enlarged plan view of a part of the wiring mother board 21 and the like in which the ball electrode 60 is formed on the conductor layer 6e of FIG. The ball electrode 60 is formed by attaching a solder ball having a diameter of 250 to 430 μm, for example.

  After the formation of the ball electrode 60, the groove 46 is formed by the dicing blade 47 as shown in FIG. FIG. 30 (f) corresponds to FIG. 7 (e), and FIG. 30 (g) corresponds to FIG. 7 (g). In FIG. 30, a process cross-sectional view corresponding to FIG.

  Since the semiconductor device 1 of the third embodiment is a ball grid array type terminal, as compared to the semiconductor device 1 having the land grid array type terminal of the first embodiment, as shown in FIG. When mounted on the mounting substrate 10, the distance between the mounting substrate 10 and the surface 8 a of the sealing body 8 becomes wide. However, even in this case, the semiconductor device 1 may be lifted due to foreign matter mixing and mounting may be insufficient. However, in the semiconductor device 1 of the third embodiment, the surface 8a of the sealing body 8 is the first of the wiring block 4. Since the structure is retracted from the second surface 4b of the part 4e, when the foreign matter is located in the retracted portion, the semiconductor device 1 does not lift up and can be mounted satisfactorily.

  The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Nor.

1 is a perspective view showing an appearance of a semiconductor device that is Embodiment 1 of the present invention. It is sectional drawing which follows the AA line of FIG. 2 is a bottom view of the semiconductor device of Example 1. FIG. It is a bottom view of the said semiconductor device which removed the sealing body which covers a chip | tip surface. FIG. 6 is a cross-sectional view illustrating a mounting state of the semiconductor device according to the first embodiment. 3 is a flowchart illustrating a method for manufacturing the semiconductor device according to the first embodiment. FIG. 6 is a process cross-sectional view illustrating the method for manufacturing the semiconductor device according to Example 1; 3 is a plan view showing a first surface of a wiring board (wiring mother board) used for manufacturing the semiconductor device of Example 1. FIG. It is a partial expanded sectional view which follows the AA line of FIG. FIG. 6 is a plan view showing a state in which a semiconductor wafer is bonded to a wiring motherboard in the manufacture of the semiconductor device of the first embodiment. FIG. 3 is an enlarged cross-sectional view of a part of the wiring mother board and the like showing a state in which the wiring mother board is bonded to the semiconductor wafer and wire bonding is performed in the manufacture of the semiconductor device of the first embodiment. It is an enlarged plan view which shows a part of semiconductor wafer and wiring motherboard which performed the said wire bonding. FIG. 5 is a schematic cross-sectional view showing a mold die or the like for forming a resin layer by transfer molding in manufacturing the semiconductor device of the first embodiment. It is a schematic diagram which shows the cull, runner, gate part, etc. which inject | pour resin in the said transfer molding. It is typical sectional drawing which shows the other structure of the said mold metal mold | die. FIG. 3 is an enlarged cross-sectional view of a part of a wiring mother board or the like on which the resin layer is formed. It is sectional drawing of the semiconductor device which incorporated the semiconductor chip which has a pad on both sides which is a modification of the present Example 1. FIG. It is a bottom view of the semiconductor device of the modification. It is sectional drawing which shows the mounting state of the semiconductor device of the said modification. It is a flowchart which shows the manufacturing method of the semiconductor device which is Example 2 of this invention. FIG. 10 is a process cross-sectional view illustrating the method for manufacturing the semiconductor device according to Example 2; It is a partial expanded sectional view of FIG.21 (e). It is sectional drawing which shows the mounting state of the semiconductor device of the present Example 2. It is a perspective view which shows the external appearance of the semiconductor device which is Example 3 of this invention. It is sectional drawing which follows the AA line of FIG. FIG. 10 is a bottom view of the semiconductor device of Example 3. It is a bottom view of the semiconductor device of the present Example 3 which removed the sealing body which covers a chip | tip surface. It is sectional drawing which shows the mounting state of the semiconductor device of the present Example 3. 10 is a flowchart illustrating a method for manufacturing the semiconductor device according to the third embodiment. It is process sectional drawing which shows the manufacturing method of the semiconductor device of the present Example 3. FIG. 31 is an enlarged plan view showing a part of a semiconductor wafer and a wiring mother board after wire bonding in the state of FIG. FIG. 31 is an enlarged plan view showing a part of a wiring mother board on which a ball electrode in the state of FIG. 30 (e) is formed.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 2 ... Semiconductor chip, 2a ... 1st surface, 2b ... 2nd surface, 3 ... Electrode, 4 ... Wiring block, 4a ... 1st surface, 4b ... 2nd surface, 4e ... 1st 1 part, 4f ... 2nd part, 5 ... adhesive, 6e ... conductor layer, 6f ... conductor layer, 6j ... conductor, 7 ... wire, 8 ... sealing body, 8a ... surface, 10 ... mounting substrate, 11 ... land , 12 ... Adhesive, 20 ... Semiconductor wafer, 20a ... First surface, 20b ... Second surface, 20c ... Orientation flat, 21 ... Wiring mother board (wiring substrate), 21a ... First surface, 21b ... First 2 side, 21j ... guide hole, 22 ... circuit element, 25 ... wiring block part, 26 ... groove, 27 ... resin layer, 28, 29 ... sheet, 30 ... lower mold, 31 ... upper mold, 32 ... gate, 33 ... Air vent, 34 ... Cavity, 35 ... Resin, 39 ... Cull, 40 ... Runner, 41 ... , 45 ... tape, 46 ... groove, 47 ... dicing blade 48 ... push-up needle, 49 ... pick-up tool, 55 ... coating, 60 ... ball electrode.

Claims (10)

(A) preparing a semiconductor wafer having a circuit element is aligned formed in a matrix and electrode of the circuit element on the first surface,
(B) said I step der preparing a wiring mother substrate having a wiring block portion which is aligned formed in a matrix so as to correspond to each circuit element, the wiring mother substrate, the first surface and the first surface of a second surface on the opposite face, said first face Ri flat surfaces der, the wiring block section, first part made of an insulating flat plate, and extending life-and-death from said first portion A second portion that is thinner than the first portion, wherein the first portion and the first surface of the second portion are located on the same plane and are opposite to the first surface; Each of the second surfaces of the second part has a plurality of conductor layers, and the predetermined conductor layers of the first part and the predetermined conductor layers of the second part are interposed via conductors provided therein. a step ing an electrically connected structure Te,
(C) a first surface of the wiring mother substrate to the first surface of the semiconductor wafer and the step of connecting with an insulating adhesive,
; (D) first said electrode conductor layers of the second part of the wiring mother substrate surface I step der of connecting a conductive wire, a loop of the wire the first part of the semiconductor wafer forming lower than the second surface of,
(E) the first surface of the semiconductor wafer, said second part and said wire I step der of forming the resin layer is covered with an insulating resin, the surface of the resin layer of the first part Forming a predetermined height lower than the surface of 2;
(F) a method of manufacturing a semiconductor device characterized by having the steps of forming a plurality of semiconductor devices with the wiring mother substrate and the semiconductor wafer is cut lengthwise and crosswise so as to divide each said circuit element. In the step of preparing a distribution Senhaha substrate (b), extending the wiring block section along the parallel department direction, one formed in a central portion of the wiring mother board each wiring block portion a groove which penetrates the , Forming the wiring block pattern so that the tip of the second part extends from both sides toward the groove,
The method of manufacturing a semiconductor device according to claim 1 in a state adhered to the semiconductor wafer and the wiring mother board, characterized in that so as to the electrodes position of the semiconductor wafer in the groove. In the step of preparing a distribution Senhaha substrate (b), the extended wiring block section along the parallel department direction, one formed between the wiring block portions adjacent the groove which penetrates the wiring motherboard, Forming the wiring block pattern so that the tip of the second part extends from both sides toward the groove;
The method of manufacturing a semiconductor device according to claim 1 in a state adhered to the semiconductor wafer and the wiring mother board, characterized in that so as to be positioned above the semiconductor wafer electrode than two rows in the groove. In the step of forming a resin layer (e), bonding said semiconductor wafer and the wiring mother said wire covering the second surface of the mother substrate in a deformable sheet in the substrate, on which a lower die of the molding die The resin layer is formed by injecting a resin from one end side of the groove by transfer molding in a state where the sheet is clamped between the mold and the sheet is inserted into the groove by a predetermined depth. Item 4. A method for manufacturing a semiconductor device according to Item 2 or 3 . In the step of preparing a wiring mother substrate (b), as a gate portion for injecting the resin in the transfer molding, it sets a recess in the extension of one end of each groove of the wiring mother board,
The method of manufacturing a semiconductor device according to claim 4, said recess, characterized by the use of the resin during the transfer molding as a gate for injecting into said groove. In the step of preparing a wiring mother substrate (b),
2. The method of manufacturing a semiconductor device according to claim 1 , wherein the first portion of the conductor layer is formed in a flat plate shape to manufacture a semiconductor device to be a land-grid array terminal. In the step of preparing a wiring mother substrate (b),
The first portion of the conductor layer is formed in a flat plate shape, and a conductive film is formed on the conductor layer to manufacture a semiconductor device that becomes a land-grid array type terminal. A method for manufacturing a semiconductor device according to claim 1 . In the step of preparing a wiring mother substrate (b), advance the conductive layer of the first part is formed into a flat plate,
After said step of forming a resin layer (e), claim 1, characterized by manufacturing a semiconductor device comprising a terminal surface in a land grid array type to form a conductive film of the conductive layer The manufacturing method of the semiconductor device as described in 2. above. The wiring mother board formed of glass epoxy resin plate insulating said conductor layer and the copper layer, and a nickel plating film that will be formed on the copper layer, the gold layer in which the Ru is formed on the nickel plating film It is formed, and a method of manufacturing a semiconductor device according to claim 7 or claim 8 wherein the coating on said conductor layer is characterized by Rukoto formed by plating or printing. After said step of forming a resin layer (e), according to claim 1, characterized in that to manufacture a semiconductor device by forming a protruding electrode on the surface of the conductive layer becomes a ball grid array type terminal Semiconductor device manufacturing method.

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