JP4425173B2 - Asynchronous data transfer device - Google Patents

Description

  The present invention relates to an asynchronous data transfer apparatus that transfers a data signal between a transfer source apparatus and a transfer destination apparatus that operate asynchronously with each other based on clock signals of different frequencies.

  As an asynchronous data transfer device for transferring data between two circuits operating independently at different clock frequencies as shown in FIG. 5, for example, a two-stage flip-flop as shown in FIG. Circuits are known. However, when a multi-bit data signal is transferred in parallel as shown in FIG. 6B, as shown in FIG. 6C, the data signal Di transferred from the transfer destination device is the data At the change timing, an unstable transient response period occurs due to a change in load capacitance generated between a plurality of wirings due to a change in data potential in each data signal. Therefore, when the two-stage flip-flop circuit inputs the data signal Di based on a clock signal CLKB different from the clock signal CLKA for outputting the data signal Di, the data signal in the unstable transient response period And indefinite data that may be different from the original data signal is output. In order to solve such a problem, an asynchronous data transfer apparatus such as a transfer system using handshaking or a system using a high-speed clock as shown in FIG. 7 has been proposed.

  Examples of two circuits operating independently at different clock frequencies include a data processing circuit having an image processing processor and a process processing circuit having a sequence control processor in a digital copying machine. is there. The data processing circuit performs various kinds of image processing such as gradation correction processing, enlargement / reduction processing, and color conversion processing on image data of a document read by a scanner or the like, and outputs the generated output image data to a laser head or the like. It is a circuit for outputting to the print head. On the other hand, the process processing circuit is a circuit for controlling the mechanical operation of the scanner or printer, and an output signal from an original size sensor installed in the scanner or an output paper size sensor installed in the printer. The size detection based on is also performed. That is, detection data such as the document size and output paper size is transferred from the process processing circuit to the data processing circuit, and the data processing circuit stores image data corresponding to the size read based on the transferred detection data. Processing and so on.

  For example, the data processing circuit is configured to output image data corresponding to a preset paper size when outputting image data to the print head, and the size cannot be initially determined as in manual paper feeding. For the paper, control is performed so that image data corresponding to the maximum length size is output in the paper conveyance direction. At this time, when the process processing circuit detects the size in the longitudinal direction of the paper being conveyed based on the paper size sensor, if the detected size is output to the data processing circuit, the data processing circuit has a length corresponding to the size. Now, control is performed to stop the output of the image data.

Here, the document size, the output paper size, and the like are the time during which the sensor is turned on / off by the original or the output paper conveyed at a predetermined conveyance speed by an infrared sensor or the like installed at a specific part of the digital copying machine. The original and the output paper size data passing over the sensor are transferred from the process processing circuit to the data processing circuit.
JP 2002-269036 A

  In general, the clock frequency, that is, the data processing speed in the data processing circuit is set in a range of about 20 MHz to 80 MHz corresponding to the number of print outputs, that is, the process speed. Since the process processing circuit and the execution program of the sequence control processor must be individually designed for each model with different process speeds, a clock frequency of about 50 MHz from high-speed models to low-speed models is required from the viewpoint of design efficiency. Commonly designed to work with.

  For this reason, when paper size detection data is asynchronously transferred from the process processing circuit to the data processing circuit based on clock signals having different frequencies, if the data processing circuit receives the data as incorrect data, There is a possibility that a correct image may not be output.

  Therefore, it is possible to transfer data reliably by using an asynchronous data transfer device based on the transfer method using the above-described handshake or a method using a high-speed clock, but the circuit configuration becomes complicated and expensive. was there.

  In view of the conventional drawbacks, the present invention is to provide an asynchronous data transfer apparatus that does not generate indefinite data in spite of its simple structure and low cost.

In order to achieve the above object, the first characteristic configuration of the asynchronous data transfer device according to the present invention operates asynchronously with each other based on clock signals of different frequencies as described in claim 1 of the claims. An asynchronous data transfer device that transfers a data signal between the transfer source device and the transfer destination device, and the original data signal output from the transfer source device based on the clock signal of the transfer source device, The first flip-flop circuit that is input based on the clock signal of the transfer destination device, and the output data signal of the first flip-flop circuit that is connected in series to the first flip-flop circuit, and one cycle of the clock signal of the transfer destination device A second flip-flop circuit that is delayed by a delay time, a comparison circuit that compares the output data signals of the first and second flip-flop circuits, and a comparison circuit A switching output circuit to which a result signal is input, and a third flip-flop circuit that inputs an output data signal from the switching output circuit and outputs the output data signal to a subsequent stage. When the output data signal and the output data signal of the third flip-flop circuit are input and the output data signals of the first and second flip-flop circuits are equal based on the comparison result signal input from the comparison circuit, The output data signal input from the second flip-flop circuit is output to the third flip-flop circuit. When the output data signals of the first and second flip-flop circuits are different, the output data signal is input from the third flip-flop circuit. The output data signal is output to the third flip-flop circuit .

According to the above configuration, the switching output circuit, based on the comparison result signal output data signal of the output data signal and the third flip-flop circuit of the second flip-flop circuit type, is input from the comparison circuit, When the output data signals of the first and second flip-flop circuits are equal, the output data signal input from the second flip-flop circuit is output to the third flip-flop circuit, and the first and second flip-flop circuits are output. When the output data signal of the circuit is different, since the output data signal input from the third flip-flop circuit is output to the third flip-flop circuit, the cycle corresponding to the clock frequency of the transfer source device or the transfer destination device In this case, the data whose data changes in a long cycle will be output preferentially. It is possible to cut noise data varies in a short time such transient response period like generated. That is , an asynchronous data transfer device that does not output indefinite data generated in the first and second flip-flop circuits can be obtained. Further, less expensive despite a simple configuration from the first said comparator circuit and the switching output circuit and the third flip-flop circuit, it is possible to asynchronous data transfer device that does not generate undefined data.

  As described above, according to the present invention, it is possible to provide an asynchronous data transfer device that does not generate indefinite data even though it is simple and inexpensive.

Embodiments of an asynchronous data transfer apparatus according to the present invention will be described below. As shown in FIG. 1, the asynchronous data transfer device 01 receives an original data signal Di output from the transfer source device 02 based on its own clock signal CLKA based on the clock signal CLKB at the transfer destination device 03. The flip-flop circuit 04 of the stage and the two output data signals different from each other by a predetermined period output from each stage of the flip-flop circuit 04 are compared, and when the two output data signals are equal, the output data signal is And an output data adjustment circuit that outputs the output data signal output last time when the two output data signals are different.

  Here, as shown in FIG. 2, the transfer source device 02 is, for example, a process processing circuit 02a in a digital copying machine, and the transfer destination device 03 is, for example, a data processing circuit 03a in a digital copying machine, Paper size detection data such as the original size and output paper size is transferred from the process circuit to the data processing circuit, and processing of image data read by the data processing circuit based on the transferred paper size detection data is performed. Configured to do.

  Returning to FIG. 1, the two-stage flip-flop circuit 04 inputs the original data signal Di output based on the clock signal CLKA based on the clock signal CLKB, and inputs the input original data signal Di to the clock signal. A first flip-flop circuit 04a that outputs the data signal Do (t) based on the signal CLKB, and a data signal Do (t) that is output from the first flip-flop circuit 04a based on the clock signal CLKB. And a second flip-flop circuit 04b that outputs the input data signal Do (t) as a data signal Do (t-1) delayed by one cycle based on the clock signal CLKB. Yes.

The output data adjustment circuit 05 uses the data signal Do (t) output from the first flip-flop circuit 04a and the data signal Do (t-1) output from the second flip-flop circuit 04b. and comparison means 05a as a comparison circuit that compares a switching output circuit 05b to output only one of two predetermined input signal based on the comparison result signal by the comparing means 05a as the data signal Q (t), A third flip-flop circuit 05c that receives the data signal Q (t) output from the switching output circuit 05b based on the CLKB and outputs the data signal Q (t-1) delayed by one cycle; Configured.

The comparing means 05a compares the data signal Do (t) output from the first flip-flop circuit 04a with the data signal Do (t-1) output from the second flip-flop circuit 04b, when the data signal Do (t) and the data signal Do (t-1) are equal, the comparison result is set to compare flag FC as a signal, the data signal Do (t) and the data signal Do (t The comparison flag FC is reset when -1) differs.

  The switching output circuit 05b includes a data signal Do (t-1) output from the second flip-flop circuit 04b and a data signal Q (t-1) output from the third flip-flop circuit 05c. When the comparison flag FC is set by the comparison means 05a, the data signal Do (t-1) is output as the data signal Q (t), and the comparison flag FC is reset. Sometimes, the data signal Q (t-1) is output as the data signal Q (t).

  Hereinafter, the operation of the asynchronous data transfer device 01 will be described with reference to the flowchart of FIG. 3 and the timing chart of FIG. When the original data signal Di output based on the clock signal CLKA is transferred from the transfer destination device 02, the first flip-flop circuit 04a uses the original data signal Di based on the clock signal CLKB. Input (SA1), and the input original data signal Di is output as a data signal Do (t) based on the clock signal CLKB (SA2).

  The second flip-flop circuit 04b receives the data signal Do (t) output from the first flip-flop circuit 04a based on the clock signal CLKB (SA3), and inputs the data signal Do ( t) is output as a data signal Do (t-1) delayed by one cycle based on the clock signal CLKB (SA4).

  The comparing means 05a compares the data signal Do (t) output from the first flip-flop circuit 04a with the data signal Do (t-1) output from the second flip-flop circuit 04b. (SA5) If the data signal Do (t) and the data signal Do (t-1) match (SA6), the comparison flag FC is set (SA7). The switching output circuit 05b outputs the data signal Do (t-1) input to the switching output circuit 05b based on the comparison flag FC as the data signal Q (t) (SA8). That is, when the data signal Do (t) is equal to the data signal Do (t−1), the original data signal Di is a data signal in which the same data is continuous for a long time. The selected data is selected and output.

  On the other hand, if the data signal Do (t) is different from the data signal Do (t-1) (SA6), the comparison unit 05a resets the comparison flag FC (SA9). The switching output circuit 05b outputs the data signal Q (t−1) input to the switching output circuit 05b based on the comparison flag FC as a data signal Q (t) (SA10). That is, when the data signal Do (t) and the data signal Do (t−1) are different, the data in the original data signal Di has changed, so that the long-time continuous data output also in the previous time is changed. The selected data is output, and the indefinite data generated when the data in the original data signal Di is shifted is prevented from being output.

  The third flip-flop circuit 05c receives the data signal Q (t) output from the switching output circuit 05b based on the CLKB (SA11), and the data signal Q (t−1) delayed by one cycle. (SA12). The output data signal Q (t−1) is input to the transfer destination device 03 and to the switching output circuit 05b.

  In the case of transfer of paper size detection data from the process circuit to the data processing circuit in the digital copying machine, that is, the same data is a continuous data signal for a long time, In the case of data transfer in which data is particularly important data, the output of the indefinite data can be prevented by increasing the output priority of the same data that occupies most of the transfer data for a long time. Thus, it is possible to reliably transfer the same data continuously for a long time.

  In the above description, the case where the frequency of the clock signal CLKA in the transfer source apparatus is lower than the frequency of the clock signal CLKB in the transfer destination apparatus has been described with reference to FIG. However, it may be higher than the frequency of the clock signal CLKB in the transfer destination device.

Explanatory drawing of the asynchronous data transfer device in the present invention Explanatory diagram of the relationship between the process processing circuit, data processing circuit, and asynchronous data transfer apparatus of the present invention in a digital copying machine The flowchart for demonstrating operation | movement of the asynchronous data transfer apparatus in this invention Timing chart for explaining the operation of the asynchronous data transfer apparatus according to the present invention Illustration of the concept of asynchronous data transfer BRIEF DESCRIPTION OF THE DRAWINGS It is explanatory drawing of the asynchronous data transfer apparatus in a prior art, (a) is explanatory drawing in the case of transferring a 1-bit data signal with a two-stage flip-flop circuit, (b) is multi-bit with a two-stage flip-flop circuit. (C) is an explanatory diagram of indefinite data generated when a multi-bit data signal is transferred by a two-stage flip-flop circuit. Explanatory diagram of asynchronous data transfer device in the prior art

01: Asynchronous data transfer device 02: Transfer source device 03: Transfer destination device 04: Two-stage flip-flop circuit 04a: First flip-flop circuit 04b: Second flip-flop circuit 05: Output data adjustment circuit 05a: Comparison means 05b: switching output circuit 05c: third flip-flop circuit

Claims (1)

An asynchronous data transfer device that transfers a data signal between a transfer source device and a transfer destination device that are operating asynchronously with each other based on clock signals of different frequencies,
A first flip-flop circuit that inputs an original data signal output from the transfer source device based on the clock signal of the transfer source device based on the clock signal of the transfer destination device;
A second flip-flop circuit connected in series to the first flip-flop circuit and delaying the output data signal of the first flip-flop circuit by one cycle of the clock signal of the transfer destination device;
A comparison circuit for comparing output data signals of the first and second flip-flop circuits;
A switching output circuit to which a comparison result signal is input from the comparison circuit;
A third flip-flop circuit that inputs an output data signal from the switching output circuit and outputs it to the subsequent stage, and
The switching output circuit receives the output data signal of the second flip-flop circuit and the output data signal of the third flip-flop circuit, and based on the comparison result signal input from the comparison circuit, the first and second flip-flops Output data signals input from the second flip-flop circuit are output to the third flip-flop circuit, and the output data signals of the first and second flip-flop circuits are different. An asynchronous data transfer device that outputs an output data signal input from the third flip-flop circuit to the third flip-flop circuit .