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JP4422326B2 - Borderless via with a patterned metal layer gap-filled with HSQ - Google Patents

Borderless via with a patterned metal layer gap-filled with HSQ Download PDF

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Publication number
JP4422326B2
JP4422326B2 JP2000516371A JP2000516371A JP4422326B2 JP 4422326 B2 JP4422326 B2 JP 4422326B2 JP 2000516371 A JP2000516371 A JP 2000516371A JP 2000516371 A JP2000516371 A JP 2000516371A JP 4422326 B2 JP4422326 B2 JP 4422326B2
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layer
hsq
metal
containing plasma
conductive
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JP2001520459A (en
JP2001520459A5 (en
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チェン，ロバート・シィ
シールズ，ジェフリー・エイ
ドーソン，ロバート
トラン，カーン
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02134—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material comprising hydrogen silsesquioxane, e.g. HSQ
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
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    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Description

【０００１】
【技術分野】
この発明は信頼性のある配線パターンを備える、高密度の多金属層半導体装置に関する。この発明は、特に、０．２５ミクロン以下の設計部分を備える、高密度の多金属層半導体装置の製造に適用できる。
【０００２】
【背景分野】
超大規模集積半導体装置に関する高密度化および高性能への要求の高まりによって、０．１８ミクロンなどの０．２５ミクロン以下の設計部分、より速いトランジスタおよび回路速度、高い信頼性および増大した製造処理量といったものが必要とされる。設計部分を０．２５ミクロン以下に縮小することは、従来のフォトリソグラフィ、エッチングおよび堆積技術を含む従来の配線技術の限界に挑むことになる。
【０００３】
パターニングされた金属層を形成するための従来の方法は、主な金属パターニング技術として、サブトラクティブ・エッチングまたはエッチバックステップを含む。そのような方法では、典型的には単結晶シリコンの半導体基板の上に第１の絶縁層が形成され、導電性コンタクトがソース／ドレイン領域などの半導体基板上の活性領域への電気的接続として、そこに形成される。アルミニウムまたはアルミニウム合金などの金属層が第１の絶縁層上に堆積され、所望の導電パターンに対応するパターンを有するフォトレジストマスクが金属層上に形成される。金属層はフォトレジストマスクを介してエッチングされ、間に配線スペースを備える複数の金属線などのような、間隙によって隔てられる金属部分を含む導電性パターンが形成される。次に、絶縁層が結果としてできた導電性パターンに加えられ、間隙を充填し、表面が平坦化される。この際、従来のエッチングまたは化学的機械研磨（ＣＭＰ）平坦化技術などが用いられる。
【０００４】
図１および２に示されるように、従来技術は、典型的にはトランジスタ（図示せず）を備える活性領域を含む半導体基板上に形成される絶縁層１０上への金属層１１の堆積を含む。フォトリソグラフィ後、その間に間隙を備える金属部分１１ａ、１１ｂ、１１ｃおよび１１ｄを含むパターニングされた金属層を形成する。典型的には、スピン・オン・ガラス（ＳＯＧ）などの絶縁材料１２が金属部分間の間隙を充填するように堆積され、約３００℃から約３５０℃の温度でベークされ、利用される特定のＳＯＧ材料によるが、最高約１時間の間、約３５０℃から約４００℃で垂直炉の中で硬化されて、平坦化を果たす。プラズマＣＶＤ（ＰＥＣＶＤ）によって別の酸化物が堆積され、ＣＭＰなどによって平坦化が行なわれる。
【０００５】
たとえば金属線および配線スペースの部分の大きさを０．２ミクロン以下に縮小すると、ボイドなしに配線間隔を満足に充填し、適当なステップカバレッジを得ることはますます困難になる。信頼性のある配線構造を形成することもまたますます困難になる。間隙充填のためのスピンオン絶縁材料が唯一の実行可能な解決策のようである。絶縁層にスルーホールが形成され、下部にある金属部分を露出すると、金属部分はスルーホールの底部全体を占める取付け台としての役割を果たす。金属プラグなどの導電性金属でスルーホールを充填して導電性バイアを形成すると、導電性バイアの底部表面全体が金属部分と直接接触する。そのような従来技術は図３に示される。ここでは第１のパターニングされた金属層の金属部分３０が第１の絶縁層３１上に形成され、第２の絶縁層３３中に形成されるスルーホール３２によって露出される。従来技術例によると、金属部分３０がその底部開口部全体を囲むようスルーホール３２が形成され、これによってスルーホール３２を充填して導電性バイア３５を形成する金属プラグ３４にとっての、取付け台としての役割を果たす。このようにして導電性バイア３５の底部表面全体が金属部分３０と直接接触する。導電性バイア３５は、金属部分３０と第２のパターニングされた金属層の一部である金属部分３６とを電気的に接続する。図２および３に示されるように、金属部分または導線の側面端、たとえば３０Ａ、３０Ｂと３６Ａおよび３６Ｂとは、エッチングの結果幾分先細りになる。
【０００６】
設計部分を０．２５ミクロン以下の範囲に縮小することは、著しい高密度化を要求する。導電性バイアの底部表面を完全に囲む取付け台を形成するという従来技術では、半導体チップ上のかなりの貴重なスペースが使用され、これは高まる高密度化要求に反する。さらに、そのような削減された大きさを有するスルーホールをボイドなしに充填することは、極めて困難である。なぜならアスペクト比、すなわちスルーホール直径に対するスルーホールの高さ、が極めて高いからである。したがって従来の改良技術は、アスペクト比を減少させるように、意図的なスルーホールの直径の拡大を含む。その結果、導電性バイアの底部表面が下にある金属部分によって完全に囲まれないという、不整列が起こる。この型のバイアは「ボーダレスバイア」と呼ばれ、チップのスペースを節約する。
【０００７】
しかしながら、ボーダレスバイアの使用は新しい問題を生み出す。たとえば、ＳＯＧの不安定性および低密度によって、不整列のスルーホールが形成されるとき、不整列の結果として、ＳＯＧ間隙充填層がエッチングによって貫通される。そのような貫通の結果、水分とガスが蓄積することによって配線の抵抗が増大する。その上、スパイクが起こり得る。すなわち金属プラグの基板への貫通が短絡をもたらす。図４に言及する。第１の絶縁層４１が基板４０上に形成され、反射防止膜４５Ａを含むたとえば金属線４５などの第１の金属部分を含む第１の金属パターンが、第１の絶縁層４１上に形成され、間隙はＳＯＧ４２で充填される。次に、絶縁層４３が堆積され、そこに形成される不整列のスルーホールが、金属線４５の上部表面の一部および側部表面の少なくとも一部を露出し、ＳＯＧ層４２の一部を貫通して露出する。スルーホールを、典型的には最初は障壁層（図示せず）およびタングステンを含む金属プラグ４４で充填すると、スパイクが起こる。すなわち基板４０への貫通によって短絡が起きる。
【０００８】
この発明では、ＳＯＧをハイドロゲンシラセスキオキサン（ＨＳＱ）に取り替え、これは配線パターンの使用に多くの利点を供する。ＨＳＱは比較的炭素がないことによりポイズンドバイアの問題を回避する。その上、炭素が実質上存在しないため、短絡を回避するように、ＨＳＱを金属線の上部表面より下にエッチバックする必要がない。さらにＨＳＱは、優れた平坦性を示し、従来のスピン・オン装置を利用して０．１５ミクロン未満の配線スペースの間隙を充填することができる。ＨＳＱはおよそ２００℃で溶解相に入るが、高い絶縁性の一定したガラス相に転換するのは、金属間の用途では約４００℃の温度で、プリメタルの用途では約７００℃ないし約８００℃に達してからである。１９９８年８月３１日出願の同時係属中の出願連続番号ＰＣＴ／ＵＳ９８／１８０１２号において、金属部分に隣接する堆積されたＨＳＱ層の部分を選択的に加熱し、ボーダレスバイア用の不整列のスルーホールをエッチングするときに、隣接する部分を貫通しにくくさせる方法が、開示されている。
【０００９】
しかしながら、ＨＳＱは加工中に劣化を受けやすく、ボーダレスバイアの形成時のボイドなどのさまざまな問題に至る。たとえば、ボーダレスバイアを形成するとき、フォトレジストマスクが堆積され、不整列のスルーホールがエッチングされると、金属線の上部表面の一部および側部表面の一部を露出し、ＨＳＱ層を貫通して露出する。次に、典型的には酸素（Ｏ2）含有プラズマを利用して、フォトレジストマスクが除去される。ボーダレスバイアを含む配線パターンにおける間隙充填のためのＨＳＱ利用の実行可能性を評価する実験中、フォトレジストマスクを除去するために利用されたＯ2含有プラズマが、ＨＳＱ層を劣化させることが判明した。窒化チタンまたはチタン−窒化チタンなどの障壁材料などで不整列のスルーホールをその後充填すると、スパイクが起こった。すなわち、障壁材料がＨＳＱ層を抜けて基板または下にある導電性部分まで貫通した。
【００１０】
ＨＳＱは、典型的には、約７０％ないし約９０％のＳｉ−Ｈ結合を含有する。しかしながら、Ｏ2含有プラズマへさらすと、かなりの数のＳｉ−Ｈ結合が破壊され、Ｓｉ−ＯＨ結合が形成される。Ｏ2含有プラズマで処理すると、堆積されたＨＳＱ膜内に約２０％ないし約３０％ものＳｉ−Ｈ結合が残った。さらに、Ｏ2含有プラズマにさらすと、堆積された直後のＨＳＱ膜の水分含有量およびその水分を吸収する傾向が増大した。Ｓｉ−Ｈ結合が減少しＳｉ−ＯＨ結合が高いＨＳＱ膜は、周囲から水分を吸収する傾向があり、水分が後の障壁金属堆積中気化放出される。このようにして、その後のたとえば、チタン−窒化チタンおよびタングステンなどの障壁および金属堆積中、気化放出が起こり、それによってボイドを生じ不完全な電気的接続に至ることが判明した。
【００１１】
ＨＳＱの明白な利点を鑑みると、ボーダレスバイアを含む配線パターンの形成において、ボイドのない間隙充填のためにＨＳＱが利用され得る技術を提供する必要がある。
【００１２】
【発明の開示】
この発明の目的は、０．２５ミクロン以下の設計部分および完成度の高いボーダレスバイアを含む配線パターンを備える高密度多金属層半導体装置の製造方法である。
【００１３】
この発明の他の目的は、完成度の高いボーダレスバイアを含む配線パターンを含む、０．２５ミクロン以下の設計部分を備える高密度多金属層半導体装置である。
【００１４】
この発明のさらなる目的、利点および他の特徴は、以下の明細書において部分的に説明され、かつ以下の検討により当業者には部分的に明らかになるか、または、この発明の実施から習得される。添付の特許請求の範囲において特に指摘されるように、この発明の目的と利点とは実現され獲得され得る。
【００１５】
この発明によれば、前記および他の目的は以下のものを含む半導体装置の製造方法によって部分的に達成される。すなわち、Ｓｉ−Ｈ結合を含有するハイドロゲンシラセスキオキサン（ＨＳＱ）を含む絶縁層を堆積するステップと、Ｈ2含有プラズマで堆積されたＨＳＱ層を処理し、Ｓｉ−Ｈ結合数を増加させるステップとを含む。
【００１６】
この発明の他の局面は、以下のものを有する配線パターンを含む半導体装置である。すなわち、第１の下部金属部分と第２の上部金属部分との間に電気的接続を形成する導電性材料で充填された開口部と、第１の金属部分および導電性材料に隣接するハイドロゲンシラセスキオキサン（ＨＳＱ）の層とを含み、ＨＳＱの層は約７０％を超えるＳｉ−Ｈ結合を含む。
【００１７】
この発明のさらなる目的と利点とは、この発明を実施するために意図された最良の形態を単に例示することによりこの発明の好ましい実施例のみが示され記載される以下の詳細な説明から、当業者には、容易に明らかとなるであろう。この発明は他の異なる実施が可能であり、そのいくつかの詳細は、この発明から全く逸脱することなく、さまざまな明らかな点において修正が可能であることが理解される。したがって、図面と明細書は全く例示的であり、限定的でないものとみなされる。
【００１８】
【発明を実施する最良の形態】
この発明によって、ＨＳＱ層の劣化より派生する悪影響を被ることなく、パターニングされた金属層の間隙を充填するＨＳＱを利用して、０．２５ミクロン以下の設計部分を有する高密度の多金属層半導体装置の形成において、信頼性の高いボーダレスバイアの有効な使用が可能となる。たとえば、チタン−窒化チタンまたは窒化チタンなど、最初に障壁材料を含む複合プラグでスルーホールを充填する前に、レジスト除去中、Ｏ2含有プラズマに晒すと、堆積されたＨＳＱは劣化される。
【００１９】
ＨＳＱは、従来のスピン・オン装置を利用して、優れた平坦性と間隙充填能力を示すという点で、非常に所望される間隙充填のための絶縁材料である。ＨＳＱは容易に、たとえば約０．１５ミクロ未満の配線スペースの間隙を充填し得る。その上、無炭素高分子前駆物質の使用により、ポイズンドバイアの問題に直面せず、ＨＳＱは金属線の上部表面より下にエッチバックされる必要がない。ＨＳＱの一つの形状が、フロワブル・オキサイド（Flowable OxideTMまたはFox TM）の製品名でダウ・コーニング社（Dow Corning Corp.）により商業的入手が可能である。
【００２０】
ＨＳＱは、主に、たとえば約７０％ないし約９０％のＳｉ−Ｈ結合を含有する。しかしながら、ＨＳＱは処理中に劣化されやすく、それによって、Ｓｉ−Ｈ結合の数が大きく減少する。たとえばフォトレジスト除去中、Ｏ2含有プラズマに晒すと、約２０％から約３０％だけ、ＨＳＱのＳｉ−Ｈ結合の数が減少し、Ｓｉ−ＯＨ結合数が増加する。その結果、そのような劣化したＨＳＱは周囲から水分を吸収するという性質を示す。従来のＨＩ−ＶＡＣスパッタ・チャンバ内でチタン−窒化チタン障壁層をスパッタ堆積するときのように、その後にスルーホールを充填してボーダレスバイアを形成する間、そのような吸収された水分は気化放出され、それによってボイドが生じ、装置の信頼性を低下させる。たとえば、１９９７年１２月１８日出願の係属中の米国特許出願連続番号第０８／９９２，４３０号に開示される方法などによる化学的気相蒸着によって、窒化チタンを堆積するときにも、気化放出は起こる。
【００２１】
この発明によると、Ｏ2含有プラズマへの露出により起こる堆積された直後のＨＳＱの劣化は、実質的に逆転される、すなわち、劣化したＨＳＱはＨ2含有プラズマで処理することにより、その堆積された直後の状態へ実質的に回復される。たとえば、劣化したＨＳＱをＨ2／Ｎ2含有プラズマなどのＨ2含有プラズマで処理すると、Ｓｉ−Ｈ結合の数は、約７０％を超え、たとえば約８７％ないし約９０％、約８０％を超えて、実質的に増加することが判明した。劣化したＨＳＱをＨ2／Ｎ2含有プラズマ中で処理すると、結果として、Ｏ2含有プラズマへの露出中に破壊または減少したＳｉ−Ｈ結合が実質的に回復することも判明した。劣化したＨＳＱをＨ2／Ｎ2プラズマで処理すると、Ｏ2含有プラズマへの露出によって生じるＳｉ−ＯＨ結合が、実質的に減少することも、さらに判明した。堆積された直後の状態へ実質的に回復すると、この発明によるＨ2含有プラズマで処理されたＨＳＱは、周囲から水分を吸収するという重大な性質を示さない。
【００２２】
このようにして、この発明によると、劣化したＨＳＱで間隙充填された層は、実質的に元のＳｉ−Ｈ結合含有量に回復され、周囲から多くの水分を吸収するという性質はもはやない。したがって、その後の導電性材料でのスルーホールの充填の際に気化放出およびボイドが起こらない。
【００２３】
従来は、Ｈ2／Ｎ2プラズマ処理を利用して、化学気相蒸着法（ＣＶＤ）によって堆積された窒化チタン膜を処理し、炭素含有量を減少させてきた。たとえば、１９９７年１２月１８日出願の、同時係属中の米国特許出願連続番号第０８／９９２，４３０号を参照。また、エイ・ジェイ・コノクニ（A. J. Konecni）らによる「障壁／接着層適用のための、安定したプラズマ処理されたＣＶＤ窒化チタン膜」第１８１−１８３頁、１９９６年６月１８日−２０日、ＶＭＩＣ大会、１９９６ＩＳＭＩＣと、キム（Kim）らによる「テトラキス−ジメチルアミノチタンを用いる化学気相蒸着法によるＴｉＮ膜の安定性」、電気化学学会誌、第１４３巻第９号、１９９６年９月、第Ｌ１８８頁−Ｌ１９０頁と、ジェイ・ラコポニ（J. Lacoponi）らによる「その場的窒素プラズマによるＣＶＤＴｉＮの抵抗性向上および低抵抗多層配線におけるその応用」、１９９５年、ＵＬＳＩ応用のための先進メタライゼーションおよび配線システム、とを参照。
【００２４】
この発明によるＨ2含有プラズマ処理を行なう際、当業者は関連するパラメータを最適化し、堆積されたＨＳＱ膜のＳｉ−Ｈ結合の数を増加させ、生じたＳｉ−ＯＨ結合の数を減少させるという、開示された目的を達成することができる。たとえば、ＣＶＤ窒化チタン膜の処理において、その炭素含有量と抵抗とを減少させるのに利用されるパラメータおよび条件は、劣化したＨＳＱを処理してＳｉ−Ｈ結合の数を増加させ、発生したＳｉ−ＯＨ結合の数を減少させるのに有効である。したがって、１９９７年１２月１８日出願の米国特許出願連続番号第０８／９９２，４３０号に開示されるパラメータ、同様に、前記コノクニら、キムら、ラコポニらによる刊行物に開示されるパラメータがこの発明に利用され得る。この発明によって劣化したＨＳＱ層をＨ2／Ｎ2プラズマで処理する際、ＨＳＱの膜の厚さによるが、約３００ｓｃｃｍの水素フロー、約２００ｓｃｃｍの窒素フロー、約４５０℃の温度、約１．３Ｔｏｒｒの気圧、約７５０ＷのＲＦ出力および約２５から約４５秒の時間を利用することが好適であることが判明している。
【００２５】
この発明の実施例によるボーダレスバイアの形成方法は、半導体基板上の第１の絶縁層を形成するステップと、第１の絶縁層上の第１の金属層をパターニングして配線スペースによって隔てられる金属線などの、間隙によって隔てられる金属部分を形成するステップとを含む。次にＳＯＧに利用される従来のスピン装置を用いてスピンなどして、たとえば約２００℃の適当な温度で、ＨＳＱを堆積することにより、間隙が充填される。ＨＳＱは、０．１５ミクロン未満の間隙さえも、完全にボイドなしに容易に充填することができる。次に、第２の絶縁層が第１のパターニングされた金属層およびＨＳＱ層上に堆積される。次に、不整列のスルーホールが第２の絶縁層中に形成され、部分的にＨＳＱ層を貫通して、第１の金属層の側面表面の少なくとも一部および上部表面の一部とＨＳＱ層の一部とを露出する。
【００２６】
第２の絶縁層上にフォトレジストマスクを堆積し、フォトレジストマスクおよびＨＳＱ層の一部を介してエッチングすることによって、スルーホールは、形成される。フォトレジストマスクは、従来の方法で、Ｏ2含有プラズマを利用して除去され、これによりＨＳＱ層は劣化する。劣化したＨＳＱ層は、劣化していない堆積された直後のＨＳＱ層に比べて、著しく少ないＳｉ−Ｈ結合と著しく多いＳｉ−ＯＨ結合とを含む。さらに、Ｏ2含有プラズマに晒されると、劣化したＨＳＱ膜は水分の含有量の増加を示し、周囲から水分を吸収することにより水分含有量は増加し続ける。
【００２７】
Ｏ2含有プラズマでフォトレジストマスクを除去した後、劣化したＨＳＱ層はＨ2／Ｎ2含有プラズマで処理され、これによりＳｉ−Ｈ結合の数は著しく増加し、Ｓｉ−ＯＨ結合の数は著しく減少する。さらに、Ｈ2含有プラズマでの処理中、ＨＳＱの水分含有量は減少し、処理されたＨＳＱは水分を吸収するという重大な性質を示さない。Ｏ2含有プラズマへ晒すことによってもたらされる劣化を逆転することによって、ＨＳＱ層を実質的に回復して次に、不整列のスルーホールは、たとえば複合プラグなどの導電性材料で充填される。最初に、チタン、窒化チタン、チタン−タングステンまたはチタン−窒化チタンの障壁が堆積され、これが、主なプラグ材料の構成要素となる、その後に堆積されるタングステンにとっての付着促進物の役割を果たす。従来のスパッタリング装置を利用して、たとえば、チタン−窒化チタンの障壁材料はスパッタ堆積される。
【００２８】
この発明の別の実施例では、１９９７年１２月１８日出願の米国特許出願連続番号第０８／９９２，４３０号に開示される方法に従って、ＣＶＤ−ＴｉＮ障壁層が堆積される。この実施例の利点は、ＨＳＱ膜のＨ2／Ｎ2プラズマ処理および堆積されたＣＶＤ−ＴｉＮ膜のＨ2／Ｎ2プラズマ処理が同じチャンバ内で行なわれ得ることである。
【００２９】
この発明の実施例の概略図が図５に示される。パターニングされた金属層の金属部分５１は、絶縁層５０上に堆積され、その上に反射防止膜５１を備える。金属部分間の間隙は、ＨＳＱ５２で充填される。次に、酸化物５３、典型的にはＴＥＯＳ（テトラエチルオルソシリケート）から得られる酸化物が堆積され、ＣＭＰが行なわれる。次に、第２の絶縁層５４が堆積され、その上にフォトレジストマスクが形成される。次に、エッチングが行なわれ、不整列のスルーホール５５を形成し、これはＨＳＱ層５２を貫通し金属部分５１の側面表面の一部を露出させる。スルーホール５５の形成後、利用されたフォトレジストマスクが、Ｏ2含有プラズマを用いるような従来の方法で除去され、それにより、ＨＳＱ層５２が劣化する。劣化は、典型的には、多くのＳｉ−Ｈ結合の減少、かなりの数のＳｉ−ＯＨ結合の形成および水分を吸収するという不所望の傾向を特徴とし、これによって、導電性材料でスルーホールを充填する際、気化放出によってボイドが発生する。
【００３０】
この発明では、劣化したＨＳＱ層はＨ2含有プラズマに晒され、それによって、Ｓｉ−Ｈ結合の数を著しく増加させ、Ｓｉ−ＯＨ結合の数を著しく減少させることにより、劣化したＨＳＱ層を回復させる。さらに、回復されたＨＳＱは周囲からあまり水分を吸収しなくなる。次に、タングステン５６にとっての付着促進物としての役割を果たす障壁層５７を最初に堆積するなどして、スルーホール５５は複合プラグで充填される。障壁層は、典型的には、チタン、窒化チタン、チタン−タングステンまたはチタン−窒化チタンなどの高融点金属である。
【００３１】
導電性バイア５７を形成した後、第２のパターニングされた金属層が第２の絶縁層５４上に形成される。この第２の金属層は、その上に反射防止膜５８Ａを備える金属部分５８を含み、導電性バイア５７を介して金属部分５１に電気的に接続される。たとえば、５層の金属層などの、所望の数のパターニングされた金属層が形成され、間隙が充填されるまで、ＨＳＱを利用して第２のパターニングされた金属層を間隙充填し、Ｈ2含有プラズマ処理を行なうことにより、この方法が繰返される。
【００３２】
この発明に利用される金属層は、従来例と一致し、典型的にはアルミニウムまたはアルミニウム合金を含む。この発明の実施例は、最初にはタングステン、チタンまたは窒化チタンなどの高融点金属層と、中間のアルミニウムまたはアルミニウム合金層と、チタン−窒化チタンなどの上部反射防止膜とを含む、複合のパターニングされた金属層の形成を含む。この発明では、従来のＣＶＤ技術によって、タングステンが堆積される。
【００３３】
この発明は、半導体装置のさまざまな型、特に微細部分、特に、０．２５ミクロン以下の微細部分を備える高密度多金属のパターニングされた層に適用でき、高速特徴および向上した信頼性を示す。この発明は、ＨＳＱの有利な利用を可能にし、Ｏ2含有プラズマへの露出などによって起こる、処理によって誘発される劣化という悪影響なしに、パターニングされた金属層を間隙充填することができる。このようにして、この発明は、ボーダレスバイア形成中のＨＳＱにおけるボイド形成の問題を解決する。この発明は費用効率が高く従来の加工および装置に容易に統合され得る。
【００３４】
この発明の実施例の実施においては、金属層は、アルミニウム、アルミニウム合金、銅、銅合金、金、金合金、銀、銀合金、高融点金属、高融点金属合金および高融点金属化合物などの半導体装置製造に典型的に利用されるいかなる金属からも、形成され得る。この発明の金属層は、半導体装置の製造に従来利用されるいかなる技術によっても形成され得る。たとえば、金属層は、従来の物理気相蒸着法（ＰＶＤ）または化学気相蒸着法（ＣＶＤ）およびたとえば銅および銅合金の電気めっきなどの従来のメタライゼーション技術によって形成され得る。
【００３５】
以上の説明では、この発明の完全な理解を提供するために、具体的な材料、構造、化学製品、方法などの多くの具体的な詳細が述べられる。しかしながら、当業者なら理解するであろう通り、この発明は、具体的に述べられる詳細に頼ることなく、実施され得る。他の場合には、この発明を不必要に不明瞭にしないために周知の加工構成は記載されない。
【００３６】
この発明の好ましい実施例のみおよびその多様性の一例がこの開示に示され述べられる。この発明は、さまざまな他の組合せと環境において使用が可能であり、ここに表わされるような発明の概念の範囲内で変更や変形が可能であることが、理解されるべきである。
【図面の簡単な説明】
【図１】 従来のパターニングされた金属層の間隙充填を例示する概略図である。
【図２】 従来のパターニングされた金属層の間隙充填を例示する概略図である。
【図３】 従来の金属プラグバイア配線を例示する概略図である。
【図４】 ボーダレスバイアにおけるスパイクを例示する概略図である。
【図５】 この発明によって形成されるボーダレスバイアを例示する概略図である。[0001]
【Technical field】
The present invention relates to a high-density multi-metal layer semiconductor device having a reliable wiring pattern. The present invention is particularly applicable to the manufacture of a high-density multi-metal layer semiconductor device having a design portion of 0.25 microns or less.
[0002]
[Background]
Higher density and higher performance requirements for ultra-large scale integrated semiconductor devices have resulted in sub-0.25 micron design features such as 0.18 micron, faster transistors and circuit speeds, higher reliability and increased manufacturing throughput. Is required. Reducing the design portion to 0.25 microns or less challenges the limitations of conventional wiring technologies, including conventional photolithography, etching and deposition techniques.
[0003]
Conventional methods for forming a patterned metal layer include a subtractive etch or etchback step as the main metal patterning technique. In such a method, a first insulating layer is typically formed on a single crystal silicon semiconductor substrate, and the conductive contacts serve as electrical connections to active regions on the semiconductor substrate, such as source / drain regions. Formed there. A metal layer such as aluminum or aluminum alloy is deposited on the first insulating layer, and a photoresist mask having a pattern corresponding to the desired conductive pattern is formed on the metal layer. The metal layer is etched through a photoresist mask to form a conductive pattern including metal portions separated by a gap, such as a plurality of metal lines with wiring spaces in between. Next, an insulating layer is added to the resulting conductive pattern, filling the gaps and planarizing the surface. At this time, a conventional etching or chemical mechanical polishing (CMP) planarization technique is used.
[0004]
As shown in FIGS. 1 and 2, the prior art typically includes the deposition of a metal layer 11 on an insulating layer 10 formed on a semiconductor substrate that includes an active region comprising a transistor (not shown). . After photolithography, a patterned metal layer including metal portions 11a, 11b, 11c and 11d with gaps between them is formed. Typically, an insulating material 12 such as spin-on-glass (SOG) is deposited to fill the gaps between the metal parts, baked at a temperature of about 300 ° C. to about 350 ° C. Depending on the SOG material, it is cured in a vertical furnace at about 350 ° C. to about 400 ° C. for up to about 1 hour to achieve planarization. Another oxide is deposited by plasma CVD (PECVD), and planarization is performed by CMP or the like.
[0005]
For example, if the size of the metal wire and the wiring space is reduced to 0.2 microns or less, it becomes more difficult to satisfactorily fill the wiring interval without voids and obtain appropriate step coverage. It is also increasingly difficult to form a reliable wiring structure. A spin-on insulating material for gap filling appears to be the only viable solution. When a through hole is formed in the insulating layer and a lower metal portion is exposed, the metal portion serves as a mounting base that occupies the entire bottom of the through hole. When a conductive via is formed by filling a through hole with a conductive metal such as a metal plug, the entire bottom surface of the conductive via is in direct contact with the metal portion. Such prior art is shown in FIG. Here, the metal portion 30 of the first patterned metal layer is formed on the first insulating layer 31 and is exposed by the through hole 32 formed in the second insulating layer 33. According to the prior art example, a through hole 32 is formed so that the metal portion 30 surrounds the entire bottom opening, thereby providing a mounting base for the metal plug 34 that fills the through hole 32 to form a conductive via 35. To play a role. In this way, the entire bottom surface of the conductive via 35 is in direct contact with the metal portion 30. The conductive via 35 electrically connects the metal portion 30 and the metal portion 36 that is part of the second patterned metal layer. As shown in FIGS. 2 and 3, the side edges of the metal portion or conductor, such as 30A, 30B and 36A and 36B, are somewhat tapered as a result of the etching.
[0006]
Reducing the design portion to a range of 0.25 microns or less requires a significant increase in density. The prior art of forming a mount that completely encloses the bottom surface of the conductive vias uses a significant amount of valuable space on the semiconductor chip, which is contrary to increasing density requirements. Furthermore, it is extremely difficult to fill through holes having such a reduced size without voids. This is because the aspect ratio, that is, the height of the through hole with respect to the through hole diameter is extremely high. Thus, conventional improved techniques include intentional through-hole diameter enlargement to reduce the aspect ratio. As a result, misalignment occurs where the bottom surface of the conductive via is not completely surrounded by the underlying metal portion. This type of via is called a “borderless via” and saves chip space.
[0007]
However, the use of borderless vias creates new problems. For example, when misaligned through holes are formed due to SOG instability and low density, the SOG gap fill layer is etched through as a result of misalignment. As a result of such penetration, the resistance of the wiring increases due to the accumulation of moisture and gas. In addition, spikes can occur. That is, the penetration of the metal plug into the substrate causes a short circuit. Reference is made to FIG. A first insulating layer 41 is formed on the substrate 40, and a first metal pattern including a first metal portion such as a metal wire 45 including an antireflection film 45A is formed on the first insulating layer 41. The gap is filled with SOG42. Next, an insulating layer 43 is deposited, and the misaligned through-holes formed therein expose a portion of the upper surface and the side surface of the metal wire 45 to expose a portion of the SOG layer 42. It is exposed through. When a through hole is initially filled with a metal plug 44 that typically includes a barrier layer (not shown) and tungsten, a spike occurs. That is, a short circuit occurs due to penetration into the substrate 40.
[0008]
In the present invention, SOG is replaced with hydrogen silsesquioxane (HSQ), which provides many advantages for the use of wiring patterns. HSQ avoids the poison via problem by being relatively carbon-free. Moreover, since there is virtually no carbon, it is not necessary to etch back the HSQ below the top surface of the metal line to avoid short circuits. Furthermore, HSQ exhibits excellent flatness and can fill gaps in the wiring space of less than 0.15 microns using conventional spin-on devices. HSQ enters the melt phase at approximately 200 ° C., but converts to a highly insulating constant glass phase at temperatures of about 400 ° C. for intermetallic applications and about 700 ° C. to about 800 ° C. for premetal applications. It is after reaching. In co-pending application serial number PCT / US98 / 18012 filed Aug. 31, 1998, selectively heats a portion of the deposited HSQ layer adjacent to a metal portion to provide an unaligned slew for a borderless via. A method for making it difficult to penetrate adjacent portions when etching holes is disclosed.
[0009]
However, HSQ is susceptible to degradation during processing, leading to various problems such as voids during the formation of borderless vias. For example, when forming a borderless via, when a photoresist mask is deposited and misaligned through holes are etched, a portion of the top and side surfaces of the metal lines are exposed and penetrate the HSQ layer And exposed. Next, the photoresist mask is removed, typically using an oxygen (O 2 ) containing plasma. During an experiment evaluating the feasibility of using HSQ for gap filling in wiring patterns including borderless vias, it was found that the O 2 containing plasma used to remove the photoresist mask degrades the HSQ layer. . Spikes occurred when subsequently filling misaligned through holes, such as with a barrier material such as titanium nitride or titanium-titanium nitride. That is, the barrier material penetrated through the HSQ layer to the substrate or underlying conductive portion.
[0010]
HSQ typically contains about 70% to about 90% Si-H bonds. However, exposure to an O 2 containing plasma destroys a significant number of Si—H bonds and forms Si—OH bonds. Treatment with an O 2 containing plasma left about 20% to about 30% Si—H bonds in the deposited HSQ film. Furthermore, exposure to O 2 containing plasma increased the moisture content of the HSQ film immediately after deposition and its tendency to absorb the moisture. HSQ films with reduced Si-H bonds and high Si-OH bonds tend to absorb moisture from the surroundings, and moisture is vaporized and released during subsequent barrier metal deposition. In this way, it was found that during subsequent barrier deposition and metal deposition such as, for example, titanium-titanium nitride and tungsten, vaporization emission occurred, thereby creating voids and leading to incomplete electrical connections.
[0011]
In view of the obvious advantages of HSQ, there is a need to provide a technique in which HSQ can be utilized for void-free gap filling in the formation of wiring patterns including borderless vias.
[0012]
DISCLOSURE OF THE INVENTION
An object of the present invention is a method for manufacturing a high-density multi-metal layer semiconductor device having a wiring pattern including a design portion of 0.25 microns or less and a borderless via having a high degree of perfection.
[0013]
Another object of the present invention is a high-density multi-metal layer semiconductor device having a design portion of 0.25 microns or less, including a wiring pattern including a borderless via having a high degree of completion.
[0014]
Additional objects, advantages and other features of the invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art from the following discussion or may be learned from practice of the invention. The The objects and advantages of the invention may be realized and obtained as particularly pointed out in the appended claims.
[0015]
According to the present invention, the above and other objects are partially achieved by a method of manufacturing a semiconductor device including the following. A step of depositing an insulating layer containing hydrogen silsesquioxane (HSQ) containing Si—H bonds; a step of treating the HSQ layer deposited with H 2 containing plasma to increase the number of Si—H bonds; including.
[0016]
Another aspect of the present invention is a semiconductor device including a wiring pattern having the following. That is, an opening filled with a conductive material that forms an electrical connection between a first lower metal portion and a second upper metal portion, and a hydrogen silice adjacent to the first metal portion and the conductive material. A layer of skioxane (HSQ), the layer of HSQ containing more than about 70% Si-H bonds.
[0017]
Further objects and advantages of this invention will become apparent from the following detailed description, in which only preferred embodiments of the invention are shown and described, merely by way of illustration of the best mode contemplated for carrying out the invention. It will be readily apparent to the merchant. It will be understood that the invention is capable of other different implementations, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and specification are to be regarded as illustrative in nature and not as restrictive.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
The present invention provides a high density multi-metal layer semiconductor having a design portion of 0.25 microns or less utilizing HSQ that fills the gaps in the patterned metal layer without incurring the adverse effects derived from degradation of the HSQ layer. A highly reliable borderless via can be used effectively in forming the device. For example, exposure to an O 2 containing plasma during resist removal prior to filling the through hole with a composite plug that initially includes a barrier material, such as titanium-titanium nitride or titanium nitride, degrades the deposited HSQ.
[0019]
HSQ is a highly desired insulating material for gap filling in that it uses a conventional spin-on device and exhibits excellent flatness and gap filling capability. HSQ can easily fill gaps in wiring space, for example, less than about 0.15 micron. Moreover, due to the use of carbon-free polymer precursors, the poison via problem is not encountered and the HSQ does not need to be etched back below the upper surface of the metal line. One form of HSQ are possible commercially available by flowable Oxide Dow Corning under the product name (Flowable Oxide TM or Fo x TM) (Dow Corning Corp. ).
[0020]
HSQ mainly contains, for example, about 70% to about 90% Si—H bonds. However, HSQ is prone to degradation during processing, thereby greatly reducing the number of Si-H bonds. For example, exposure to an O 2 -containing plasma during photoresist removal reduces the number of Si—H bonds in HSQ by about 20% to about 30% and increases the number of Si—OH bonds. As a result, such degraded HSQ exhibits the property of absorbing moisture from the surroundings. Such absorbed moisture is vaporized and released during subsequent filling of the through-holes to form borderless vias, such as when sputter depositing a titanium-titanium nitride barrier layer in a conventional HI-VAC sputter chamber. Thereby creating voids that reduce the reliability of the device. For example, vapor deposition may also occur when depositing titanium nitride by chemical vapor deposition, such as by the method disclosed in pending US patent application Ser. No. 08 / 992,430, filed Dec. 18, 1997. Will happen.
[0021]
According to the present invention, the degradation of HSQ immediately after deposition caused by exposure to an O 2 containing plasma is substantially reversed, ie, the degraded HSQ is deposited by treatment with an H 2 containing plasma. It is substantially recovered to the state immediately after. For example, when degraded HSQ is treated with an H 2 containing plasma, such as an H 2 / N 2 containing plasma, the number of Si—H bonds exceeds about 70%, for example about 87% to about 90%, about 80%. Beyond that, it was found to increase substantially. It has also been found that treatment of degraded HSQ in a H 2 / N 2 containing plasma results in substantial recovery of broken or reduced Si—H bonds during exposure to the O 2 containing plasma. If the degraded HSQ is treated with H 2 / N 2 plasma, Si-OH bonds caused by exposure to O 2 containing plasma, also be substantially reduced, further proved. Upon substantial recovery to the state immediately after deposition, the HSQ treated with the H 2 containing plasma according to the present invention does not exhibit the critical property of absorbing moisture from the surroundings.
[0022]
Thus, according to the invention, the gap-filled layer with degraded HSQ is substantially restored to its original Si-H bond content and no longer has the property of absorbing much moisture from the surroundings. Therefore, vaporization emission and void do not occur during subsequent filling of the through hole with the conductive material.
[0023]
Conventionally, a titanium nitride film deposited by chemical vapor deposition (CVD) has been treated using H 2 / N 2 plasma treatment to reduce the carbon content. See, for example, co-pending US Patent Application Serial No. 08 / 992,430, filed December 18, 1997. Also, AJ Konecni et al., “Stable Plasma Treated CVD Titanium Nitride Films for Barrier / Adhesive Layer Application,” pages 181-183, June 18-20, 1996. VMIC Convention, 1996 ISMIC, and Kim et al., “Stability of TiN Films by Chemical Vapor Deposition Using Tetrakis-Dimethylamino Titanium”, Journal of Electrochemical Society, Vol. 143, No. 9, September 1996, Pp. L188-L190 and J. Lacoponi et al., “In-situ nitrogen plasma enhanced resistance of CVDTiN and its application in low resistance multilayer interconnects”, 1995, Advanced Meta for ULSI applications. See also Rization and Wiring System.
[0024]
When performing containing H 2 plasma treatment according to the present invention, as those skilled in the art to optimize the related parameters, increasing the number of Si-H bonds of the deposited HSQ film, reducing the number of the resulting Si-OH bonds The disclosed object can be achieved. For example, in the processing of CVD titanium nitride films, the parameters and conditions utilized to reduce the carbon content and resistance are such that the degraded HSQ is processed to increase the number of Si-H bonds and the generated Si Effective for reducing the number of —OH bonds. Therefore, the parameters disclosed in U.S. Patent Application Serial No. 08 / 992,430 filed December 18, 1997, as well as those disclosed in the publications by Konokuni et al., Kim et al., Lakoponi et al. Can be used in the invention. When the HSQ layer deteriorated according to the present invention is treated with H 2 / N 2 plasma, depending on the thickness of the HSQ film, the hydrogen flow is about 300 sccm, the nitrogen flow is about 200 sccm, the temperature is about 450 ° C., and the temperature is about 1.3 Torr. It has been found that it is preferable to utilize a pressure of about 750 W, an RF power of about 750 W and a time of about 25 to about 45 seconds.
[0025]
A method for forming a borderless via according to an embodiment of the present invention includes a step of forming a first insulating layer on a semiconductor substrate, and a metal separated by a wiring space by patterning the first metal layer on the first insulating layer. Forming a metal portion separated by a gap, such as a line. Next, the gap is filled by depositing HSQ, for example, at a suitable temperature of about 200 ° C., for example, by spinning using a conventional spin device utilized for SOG. HSQ can easily fill even gaps less than 0.15 microns completely without voids. Next, a second insulating layer is deposited on the first patterned metal layer and HSQ layer. Next, misaligned through holes are formed in the second insulating layer and partially penetrate the HSQ layer to form at least part of the side surface and part of the upper surface of the first metal layer and the HSQ layer. To expose a part of.
[0026]
Through-holes are formed by depositing a photoresist mask on the second insulating layer and etching through the photoresist mask and part of the HSQ layer. The photoresist mask is removed using O 2 containing plasma in a conventional manner, thereby degrading the HSQ layer. A degraded HSQ layer contains significantly fewer Si—H bonds and significantly more Si—OH bonds than an intact, freshly deposited HSQ layer. Further, when exposed to O 2 containing plasma, the degraded HSQ film shows an increase in moisture content, and the moisture content continues to increase by absorbing moisture from the surroundings.
[0027]
After removing the photoresist mask with O 2 containing plasma, the degraded HSQ layer is treated with H 2 / N 2 containing plasma, which significantly increases the number of Si—H bonds and significantly increases the number of Si—OH bonds. Decrease. Furthermore, during treatment with H 2 containing plasma, the moisture content of HSQ is reduced and the treated HSQ does not exhibit the critical property of absorbing moisture. By reversing the degradation caused by exposure to the O 2 containing plasma, the HSQ layer is substantially recovered and then the misaligned through holes are filled with a conductive material, such as a composite plug. Initially, a titanium, titanium nitride, titanium-tungsten or titanium-titanium nitride barrier is deposited, which serves as an adhesion promoter for subsequently deposited tungsten, which is a component of the main plug material. For example, a titanium-titanium nitride barrier material is sputter deposited using conventional sputtering equipment.
[0028]
In another embodiment of the invention, a CVD-TiN barrier layer is deposited according to the method disclosed in US Patent Application Serial No. 08 / 992,430, filed December 18, 1997. The advantage of this embodiment is that the H 2 / N 2 plasma treatment H 2 / N 2 plasma treatment and deposited CVD-TiN film of HSQ film may be made in the same chamber.
[0029]
A schematic diagram of an embodiment of the present invention is shown in FIG. The metal portion 51 of the patterned metal layer is deposited on the insulating layer 50 and has an antireflection film 51 thereon. The gap between the metal parts is filled with HSQ52. Next, an oxide 53, typically an oxide obtained from TEOS (tetraethylorthosilicate), is deposited and CMP is performed. Next, a second insulating layer 54 is deposited and a photoresist mask is formed thereon. Etching is then performed to form misaligned through-holes 55 that penetrate the HSQ layer 52 and expose a portion of the side surface of the metal portion 51. After the formation of the through hole 55, the used photoresist mask is removed by a conventional method using an O 2 containing plasma, thereby degrading the HSQ layer 52. Degradation is typically characterized by the loss of many Si-H bonds, the formation of a significant number of Si-OH bonds and the undesired tendency to absorb moisture, thereby allowing through holes in conductive materials. When filling, voids are generated by vaporization release.
[0030]
In this invention, the degraded HSQ layer is exposed to an H 2 containing plasma, thereby recovering the degraded HSQ layer by significantly increasing the number of Si—H bonds and significantly decreasing the number of Si—OH bonds. Let Furthermore, the recovered HSQ does not absorb much moisture from the surroundings. Next, the through hole 55 is filled with a composite plug, such as by first depositing a barrier layer 57 that serves as an adhesion promoter for tungsten 56. The barrier layer is typically a refractory metal such as titanium, titanium nitride, titanium-tungsten or titanium-titanium nitride.
[0031]
After forming the conductive via 57, a second patterned metal layer is formed on the second insulating layer. The second metal layer includes a metal portion 58 having an antireflection film 58A thereon, and is electrically connected to the metal portion 51 through a conductive via 57. For example, HSQ is used to gap fill the second patterned metal layer until a desired number of patterned metal layers, such as five metal layers, are formed and the gap is filled, and H 2 This method is repeated by performing the plasma treatment.
[0032]
The metal layer utilized in this invention is consistent with the prior art and typically includes aluminum or an aluminum alloy. Embodiments of the present invention include a composite patterning that initially includes a refractory metal layer such as tungsten, titanium or titanium nitride, an intermediate aluminum or aluminum alloy layer, and a top antireflective coating such as titanium-titanium nitride. Forming a formed metal layer. In this invention, tungsten is deposited by conventional CVD techniques.
[0033]
The present invention can be applied to various types of semiconductor devices, especially fine portions, particularly high density multi-metal patterned layers with fine portions of 0.25 microns or less, exhibiting high speed features and improved reliability. The present invention allows for advantageous utilization of HSQ and can gap fill a patterned metal layer without the deleterious effects of process induced degradation, such as caused by exposure to an O 2 containing plasma. Thus, the present invention solves the problem of void formation in HSQ during borderless via formation. The invention is cost effective and can be easily integrated into conventional processes and equipment.
[0034]
In the embodiment of the present invention, the metal layer is made of a semiconductor such as aluminum, aluminum alloy, copper, copper alloy, gold, gold alloy, silver, silver alloy, refractory metal, refractory metal alloy and refractory metal compound. It can be formed from any metal typically utilized in device manufacture. The metal layer of the present invention can be formed by any technique conventionally used in the manufacture of semiconductor devices. For example, the metal layer can be formed by conventional metallization techniques such as conventional physical vapor deposition (PVD) or chemical vapor deposition (CVD) and electroplating of copper and copper alloys, for example.
[0035]
In the above description, numerous specific details are set forth such as specific materials, structures, chemical products, methods, etc., in order to provide a thorough understanding of the present invention. However, as will be appreciated by one skilled in the art, the invention may be practiced without resorting to the details specifically set forth. In other instances, well known processing features have not been described in order not to unnecessarily obscure the present invention.
[0036]
Only the preferred embodiment of the invention and an example of its versatility are shown and described in this disclosure. It should be understood that the invention can be used in a variety of other combinations and environments, and that changes and modifications can be made within the scope of the inventive concept as presented herein.
[Brief description of the drawings]
FIG. 1 is a schematic diagram illustrating gap filling of a conventional patterned metal layer.
FIG. 2 is a schematic diagram illustrating gap filling of a conventional patterned metal layer.
FIG. 3 is a schematic view illustrating a conventional metal plug via wiring.
FIG. 4 is a schematic diagram illustrating spikes in a borderless via.
FIG. 5 is a schematic diagram illustrating a borderless via formed according to the present invention.

Claims (18)

半導体基板上に第１の絶縁層を形成するステップと、
前記第１の絶縁層上に間隙を有する第１のパターニングされた金属層を形成するステップであって、前記第１のパターニングされた金属層は上部表面および側部表面を有する第１の金属部分を含むステップと、
Ｓｉ−Ｈ結合を含有するハイドロゲンシラセスキオキサン（ＨＳＱ）層を堆積して前記間隙を充填するステップと、前記第１のパターニングされた層およびＨＳＱ層上に第２の絶縁層を堆積するステップと、
スルーホールを前記第２の絶縁層中に形成して前記第１の金属部分の上部表面の一部と、前記第１の金属部分の側部表面の少なくとも一部と、を露出させ、前記ＨＳＱ層の一部を貫通し、露出させるステップと、
前記ＨＳＱ層をＨ2含有プラズマで処理しＳｉ−Ｈ結合の数を増加させるステップと、
前記スルーホールを導電性材料で充填しボーダレスバイアを形成するステップとを含む、半導体装置の製造方法。Forming a first insulating layer on a semiconductor substrate;
Forming a first patterned metal layer with a gap on the first insulating layer, the first patterned metal layer having a top surface and a side surface; Including steps,
Depositing a hydrogen silsesquioxane (HSQ) layer containing Si-H bonds to fill the gap; and depositing a second insulating layer over the first patterned layer and the HSQ layer; ,
A through hole is formed in the second insulating layer to expose a portion of the upper surface of the first metal portion and at least a portion of the side surface of the first metal portion, and the HSQ Penetrating and exposing a portion of the layer;
Treating the HSQ layer with a H 2 containing plasma to increase the number of Si—H bonds;
Filling the through hole with a conductive material to form a borderless via. Ｈ2含有プラズマでＨＳＱ層を処理する前に、ＨＳＱ層における開口部を形成し、導電性構造の一部を露出するステップと、堆積されたＨＳＱ層をＨ2含有プラズマで処理した後、導電性材料で開口部を充填し、前記導電性構造との電気的接続を形成するステップとを含む、請求項１記載の方法。Prior to treating the HSQ layer with the H 2 containing plasma, forming an opening in the HSQ layer to expose a portion of the conductive structure, and treating the deposited HSQ layer with the H 2 containing plasma, Filling the opening with a conductive material to form an electrical connection with the conductive structure. 前記第２の絶縁層上にフォトレジストマスクを形成するステップと、
エッチングしてスルーホールを形成するステップと、
フォトレジストマスクを除去するステップと、
フォトレジストマスク除去後に前記ＨＳＱ層をＨ2含有プラズマで処理するステップとを含む、請求項１に記載の方法。Forming a photoresist mask on the second insulating layer;
Etching to form a through hole; and
Removing the photoresist mask;
Treating the HSQ layer with an H 2 containing plasma after removing a photoresist mask. Ｏ2含有プラズマを用いて前記フォトレジストマスクを除去するステップを含む、請求項３に記載の方法。The method of claim 3, comprising removing the photoresist mask using an O 2 containing plasma. 前記Ｏ2含有プラズマによるフォトレジスト除去は、堆積された状態のＨＳＱ層のＳｉ−Ｈ結合の数を減少させ、ＨＳＱ層中にＳｉ−ＯＨ結合を形成させ、前記Ｈ2含有プラズマ処理はＨＳＱ層のＳｉ−ＯＨ結合の数を減少させる、請求項４に記載の方法。The removal of the photoresist by the O 2 -containing plasma reduces the number of Si—H bonds in the deposited HSQ layer and forms Si—OH bonds in the HSQ layer, and the H 2 -containing plasma treatment is performed by the HSQ layer. The method according to claim 4, wherein the number of Si—OH bonds of the compound is reduced. 前記Ｈ2含有プラズマ処理が、前記Ｏ2含有プラズマによるフォトレジスト除去によって減少したＳｉ−Ｈ結合の数を実質的に回復する、請求項５に記載の方法。The method of claim 5, wherein the H 2 -containing plasma treatment substantially recovers the number of Si—H bonds reduced by photoresist removal with the O 2 -containing plasma. 前記Ｏ2含有プラズマによるフォトレジスト除去が、堆積された状態のＨＳＱ層の水分含有量を増加させ、前記Ｈ2含有プラズマ処理がＨＳＱ層の水分含有量を減少させる、請求項５に記載の方法。The O 2 containing plasma by photoresist removal, increasing the water content of the HSQ layer of deposited state, the containing H 2 plasma treatment decreases the water content of the HSQ layer, The method of claim 5 . 前記Ｈ2含有プラズマ処理が、前記Ｏ2含有プラズマによるフォトレジスト除去によって減少したＳｉ−Ｈ結合のすべてを実質的に回復する、請求項５に記載の方法。The method of claim 5, wherein the H 2 -containing plasma treatment substantially recovers all of the Si—H bonds reduced by photoresist removal with the O 2 -containing plasma. 前記Ｈ2含有プラズマが窒素をさらに含む、請求項１に記載の方法。The method of claim 1, wherein the H 2 containing plasma further comprises nitrogen. 前記スルーホールを複合導電性プラグで充填するステップを含む、請求項１に記載の方法。  The method of claim 1, comprising filling the through hole with a composite conductive plug. 第２の導電層のための付着促進物として働く第１の導電性障壁層を堆積するステップを含む、請求項１０に記載の方法。The method of claim 10 , comprising depositing a first conductive barrier layer that serves as an adhesion promoter for the second conductive layer. 前記第１の導電層がチタン、窒化チタン、チタン−タングステンまたはチタン−窒化チタンを含み、前記第２の導電層がタングステンを含む、請求項１１に記載の方法。The method of claim 11 , wherein the first conductive layer comprises titanium, titanium nitride, titanium-tungsten or titanium-titanium nitride, and the second conductive layer comprises tungsten. 前記第１の金属層が、下部の高融点金属層と、アルミニウムまたはアルミニウム合金の中間層と、
上部の反射防止膜とを含む複合物である、請求項１に記載の方法。The first metal layer comprises a lower refractory metal layer, an intermediate layer of aluminum or aluminum alloy,
The method of claim 1, which is a composite comprising an upper antireflective coating. 前記第２の絶縁層上に第２のパターニングされた金属層を形成するステップを含み、前記第２のパターニングされた金属層は、前記ボーダレスバイアによって前記第１の金属構造に電気的に接続される第２の金属構造を含む、請求項１に記載の方法。  Forming a second patterned metal layer on the second insulating layer, wherein the second patterned metal layer is electrically connected to the first metal structure by the borderless via. The method of claim 1, comprising a second metal structure. 前記第１の金属構造が金属配線を含み、前記間隙が配線スペースを含む、請求項１に記載の方法。  The method of claim 1, wherein the first metal structure includes metal wiring and the gap includes wiring space. 半導体基板上の第１の絶縁層と、
前記第１の絶縁層上に形成される間隙を有する第１のパターニングされた金属層であって、上部表面および側部表面を有する第１の下部金属構造を含む金属層と、
前記間隙を充填するハイドロゲンシラセスキオキサン（ＨＳＱ）の層と、
前記第１のパターニングされた金属層上および前記ＨＳＱ層上に形成される第２の絶縁層と、
前記第２の絶縁層中に形成され、前記第１の下部金属構造の上部表面の一部と、前記第１の下部金属構造の側部表面の少なくとも一部と、を露出させ、前記ＨＳＱ層の一部を貫通し、露出させるスルーホールと、
前記スルーホールを充填することによりボーダレスバイアを形成し、前記第１の下部金属部分と第２の上部金属部分との間に電気的接続を形成する、導電性材料とを含み、
前記ＨＳＱ層は前記第１の金属部分および前記導電性材料に隣接し、
前記スルーホールは、
前記第２の絶縁層上にフォトレジストマスクを堆積し、
エッチングし、
前記ＨＳＱ層のＳｉ−Ｈ結合の数の削減を引き起こすＯ2含有プラズマを用いて前記フォトレジストマスクを除去することによって形成され、
前記スルーホールを導電性材料で充填する前に、前記ＨＳＱ層をＨ 2 含有プラズマで処理してＳｉ−Ｈ結合の数を増加させる、配線パターンを備える半導体装置。A first insulating layer on a semiconductor substrate;
A first patterned metal layer having a gap formed on the first insulating layer, the metal layer comprising a first lower metal structure having an upper surface and a side surface;
A layer of hydrogen silsesquioxane (HSQ) filling the gap;
A second insulating layer formed on the first patterned metal layer and on the HSQ layer;
An HSQ layer formed in the second insulating layer, exposing a portion of an upper surface of the first lower metal structure and at least a portion of a side surface of the first lower metal structure; A through hole that penetrates and exposes a portion of
A conductive material that forms a borderless via by filling the through-hole and forms an electrical connection between the first lower metal portion and the second upper metal portion;
The HSQ layer is adjacent to the first metal portion and the conductive material;
The through hole is
Depositing a photoresist mask on the second insulating layer;
Etched,
Formed by removing the photoresist mask using an O 2 containing plasma that causes a reduction in the number of Si—H bonds in the HSQ layer;
A semiconductor device comprising a wiring pattern in which the HSQ layer is treated with H 2 containing plasma to increase the number of Si—H bonds before filling the through holes with a conductive material . 前記導電性材料が、第２の導電層にとっての接着促進物として働く第１の導電性障壁層を含む複合物である、請求項１６に記載の半導体装置。The semiconductor device according to claim 16 , wherein the conductive material is a composite including a first conductive barrier layer that serves as an adhesion promoter for the second conductive layer. 前記第１の導電層がチタン、窒化チタン、チタン−タングステン、またはチタン−窒化チタンを含み、前記第２の導電層がアルミニウムまたはアルミニウム合金を含む、請求項１７に記載の半導体装置。The semiconductor device according to claim 17 , wherein the first conductive layer includes titanium, titanium nitride, titanium-tungsten, or titanium-titanium nitride, and the second conductive layer includes aluminum or an aluminum alloy.
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