JP4417533B2 - Intermediate frequency circuit for TV receiver - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an intermediate frequency circuit used in a TV receiver, and more particularly to a circuit in which VCO free-run frequency is not adjusted.
[0002]
[Prior art]
In a TV receiver, an intermediate frequency circuit using a PLL synchronous detection method is common. FIG. 3 shows an example of the configuration of such an intermediate frequency circuit. Hereinafter, a conventional intermediate frequency circuit will be described with reference to FIG. In this figure, 1 is an antenna for receiving TV radio waves, 2 is a tuner, and B is an intermediate frequency circuit. In the intermediate frequency circuit B, a high frequency signal from an antenna is selected and converted by a tuner 2 provided outside the antenna, and is input to an intermediate frequency amplifier 4 through an intermediate frequency filter 3. The signal amplified by the intermediate frequency amplifier 4 is input to a phase comparator (APC) 5 and an IF detector (DET) 13 respectively. A VCO (voltage controlled oscillator) 6 having an APC 5 and an external LC resonance circuit and a phase shifter 7 form a so-called PLL loop, and an output signal of the VCO 6 via the phase shifter 7 and an intermediate frequency amplifier. The VCO 6 is controlled so that the phase difference of the output signals of 4 is 90 °. Although not shown, a loop filter is connected between the APC 5 and the VCO 6.
[0003]
A specific example of the internal circuit of the VCO 6 is shown in FIG. In this figure, 61 is a current control oscillator, 62 is an external reactance element, 67 is an external variable inductance element, 64 is a constant current source having a fixed value, and 65 is based on a control voltage output from the APC 5 to the VCO. A constant current source having a current value is shown.
The reactance element 62 and the variable inductance element 67 constitute a parallel resonance circuit with respect to the current controlled oscillator (ICO) 61, and the oscillation frequency generated from the ICO 61 can be appropriately adjusted by the variable inductance element 67. It is known that the ICO 61 is composed mainly of a differential amplifier circuit using transistors. Further, the constant current source 65 can also be constituted by a constant current source circuit using transistors, and a control voltage is applied from the APC 5 via the base of the input transistor, and the change of the applied voltage value is changed to the change of the current value. It has been.
[0004]
On the other hand, in the DET 13, the output signal of the VCO 6 through the phase shifter 7 is input together with the signal from the intermediate frequency amplifier, the video synchronous detection is performed, and the video signal is output. This video signal is amplified by a video signal amplifier. Further, an AFT signal is output from the output of the APC 5 by the automatic frequency control (AFT) output circuit 12.
[0005]
[Problems to be solved by the invention]
In the above-described conventional circuit, the VCO free-run frequency, which is the center frequency of the VCO pull-in frequency, needs to be adjusted to vary L of the LC resonance circuit externally attached to the VCO. There was a problem that an intermediate frequency input signal with high accuracy is required and an adjustment error occurs. An object of the present invention is to provide an intermediate frequency circuit for a TV receiver that solves the above-described problems and makes the VCO free-run frequency unadjustable.
[0006]
[Means for Solving the Problems]
An intermediate frequency signal filter that filters an intermediate frequency signal input from the outside, an intermediate frequency amplifier that amplifies the intermediate frequency signal after the filter, a VCO that is controlled by the outputs of the first APC and the second APC, and oscillates at the intermediate frequency, VCO A phase shifter that outputs a phase shift from the first APC and DET with a phase difference of 90 °, a first APC that compares the phase-shifted signal of the VCO oscillation output with the amplified intermediate frequency signal, A DET that performs synchronous detection with a phase-shifted signal of the VCO oscillation output and an amplified intermediate frequency signal, a video signal amplifier that amplifies the DET detection output, and the oscillation output frequency of the VCO to 1 / n for phase comparison. 1 / n frequency divider for dividing, a reference oscillator for oscillating a reference frequency, and 1 for dividing the reference oscillation frequency of the reference oscillator to 1 / m for phase comparison an m frequency divider, a second APC that compares the output of the 1 / n frequency divider and the output of the 1 / m frequency divider, and an AFT output circuit that outputs an AFT signal from the output of the second APC. The response time of the output of the PLL loop composed of 1 APC is set sufficiently faster than the response time of the output of the PLL loop composed of the second APC, and the reference oscillation frequency of the reference oscillator is divided into 1 / m and a phase. The VCO is controlled by the output of the second APC being compared.
[Action]
With this configuration, the VCO frequency is controlled by the second PLL loop so as to match the frequency of the intermediate frequency signal based on the reference oscillator, so that the VCO free-run frequency that is the center frequency of the VCO pull-in frequency is The VCO free-run frequency is not adjusted without being varied by L of the LC resonance circuit externally attached to the VCO and without causing an adjustment error.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to FIGS. 1 and 2. The members and arrangements described below do not limit the present invention and can be variously modified within the scope of the gist of the present invention. First, the configuration of an intermediate frequency circuit for a TV receiver according to an embodiment of the present invention will be described with reference to FIG.
[0008]
This TV receiver intermediate frequency circuit A is provided in the subsequent stage of the tuner 2 that selects a desired TV channel signal from the radio wave received by the antenna 1 and converts it into a predetermined intermediate frequency signal. It has a circuit configuration. This TV receiver intermediate frequency circuit A is first provided with an intermediate frequency filter 3 and an intermediate frequency amplifier 4, and the intermediate frequency signal input from the tuner 2 is filtered by one channel, amplified and output. . The signal amplified by the intermediate frequency amplifier 4 is input to the first APC (APC1) 5 and the IF detector (DET) 13, respectively.
[0009]
The VCO 6 having the first APC 5 and the external LC resonance circuit and the phase shifter 7 form a so-called PLL loop, and the level of the output signal of the VCO 6 and the output signal of the intermediate frequency amplifier via the phase shifter 7. The VCO 6 is controlled so that the phase difference is 90 °. The VCO 6 is also subjected to absolute value control of the intermediate frequency by the reference oscillator 10. A 1 / n divider 8 that divides the oscillation output frequency of the VCO 6 into 1 / n (n is an integer of 1 or more), a reference oscillator (RefOsc) 10 that oscillates a reference frequency, and a reference oscillation frequency of the reference oscillator 10 1 / m frequency divider 11 that divides 1 into 1 / m (m is an integer equal to or greater than 1), and the second APC that compares the output of 1 / n frequency divider 8 with the output of 1 / m frequency divider 11 (APC2) 9 forms a second PLL loop. Although not shown, loop filters are respectively connected between the first APC 5 and the VCO 6 and between the second APC 9 and the VCO 6. The response speed of the second PLL loop is sufficiently slower than the response speed of the first PLL loop so that the oscillation of the VCO 6 does not become unstable. Here, an example is shown.
[0010]
Intermediate frequency: 45.75 MHz, reference oscillator reference frequency: 4 MHz, l / n divider 8 n: 5856, 1 / m divider 11 m: 512, second APC 9 comparison frequency: 7812.5 Hz . In other words, the second PLL loop operates to have a desired intermediate frequency that does not depend on the frequency of the input intermediate frequency signal. If there is an offset in the frequency of the input intermediate frequency signal, the AFT signal is output from the output of the second APC 9 by the AFT output circuit 12, so that feedback is applied to the tuner 2 so that the desired intermediate frequency is obtained. The response speed of the second PLL at this time was 1000 times slower than the response speed of the first PLL.
[0011]
A specific example of the internal circuit of the VCO 6 is shown in FIG. In this figure, 63 is an inductance element, 65 is a constant current source having a control current value based on the control voltage from the first APC 5, and 66 is a constant current source having a control current value based on the control voltage from the second APC 9. These constant current sources 65 and 66 can be constituted by transistor circuits as described in the conventional example, and current values are determined in accordance with control voltages output from the first APC 5 and the second APC 9 respectively.
[0012]
As described above, in this embodiment, the PLL synchronous detection control for the normal input intermediate frequency signal is performed by the first PLL loop, and the absolute frequency control of the VCO 6 using the reference oscillator 10 is performed by the second PLL loop. In the embodiment, an LC circuit is externally attached to the VCO, but a VCO 6 having no external LC circuit may be used.
Further, the following method in which the operation of the second PLL loop is limited may be used. Only when the power is turned on or when the channel is switched, the operation of the first PLL loop is stopped and only the second PLL loop is operated and stabilized. Then, the VCO control by the second PLL loop is fixed, and then the first PLL is fixed. Start the loop operation. That is, during normal operation other than when the power is turned on or when the channel is switched, the control of the VCO by the second PLL loop is fixed and only the operation of the first PLL loop is performed. This can be easily performed by controlling the operation / non-operation of the first and second APCs 5 and 9 with a microcontroller or the like. For example, when the power is turned on or when the channel is switched, the first APC 5 is not operated and only the second APC 9 is operated. Then, after the operation of the VCO 6 is stabilized, the control voltage from the second APC 9 is fixed to a voltage value when the VCO 6 is stably operated, so that the second APC 9 is not substantially operated. Thereafter, the first APC 5 may be operated.
[0013]
【The invention's effect】
As described above, according to the present invention, the PLL synchronous detection control for the normal input intermediate frequency signal is performed in the intermediate frequency circuit, and the absolute frequency control of the VCO using the reference oscillator is performed in the first PLL loop. By adopting a configuration in which a PLL loop is used, the VCO free-run frequency can be made non-adjustable without being varied by L of the LC resonance circuit externally attached to the VCO and without causing an adjustment error. it can. Furthermore, since it is not necessary to adjust the free-run frequency, it is possible to use a VCO without an external LC circuit, and it is possible to obtain a stable oscillation of the VCO that is not affected by external noise from the outside. In addition, no VCO oscillation noise is generated through an external connection.
[Brief description of the drawings]
FIG. 1 is a diagram showing an embodiment of the present invention.
FIG. 2 is a diagram showing a specific example of a VCO according to the present invention.
FIG. 3 is a diagram showing a conventional example.
FIG. 4 is a diagram showing a specific example of a VCO according to a conventional example.
[Explanation of symbols]
1: antenna, 2: tuner, 3: intermediate frequency filter, 4: intermediate frequency amplifier, 5: phase comparator (first phase comparator), 6: VCO, 7: phase shifter, 8: 1 / n frequency division 9: second phase comparator, 10: reference oscillator, 11: 1 / m frequency divider, 12: automatic frequency control output circuit, 13: IF detector, 14: video signal amplifier, 61: current controlled oscillator, 62: reactance element, 63: inductance element, 64: constant current source (fixed), 65, 66: constant current source (variable), 67: variable inductance element

Claims (2)

An intermediate frequency signal filter that filters the intermediate frequency signal input from the outside, an intermediate frequency amplifier that amplifies the filtered intermediate frequency signal, and the outputs of the first phase comparator and the second phase comparator are controlled at the intermediate frequency. The VCO that oscillates and the oscillation output of the VCO are amplified with a phase shifter that outputs a phase shift of 90 ° to the first phase comparator and the IF detector, and a signal that is a phase shift of the oscillation output of the VCO. A first phase comparator for comparing intermediate frequency signals, an IF detector for performing synchronous detection with a signal obtained by shifting the phase of the VCO oscillation output and the amplified intermediate frequency signal, and a video for amplifying the detection output of the IF detector A signal amplifier, a 1 / n divider that divides the oscillation output frequency of the VCO by 1 / n (n is an integer of 1 or more) for phase comparison, a reference oscillator that oscillates a reference frequency, and a phase comparison Compare the output of the 1 / m divider that divides the reference oscillation frequency of the reference oscillator to 1 / m (m is an integer of 1 or more), the output of the 1 / n divider, and the output of the 1 / m divider. A second phase comparator to perform and an AFT output circuit for outputting an AFT signal from the output of the second phase comparator, and the response time of the output of the PLL loop formed by the first phase comparator is the oscillation time of the VCO. The second phase is set faster than the response time of the output of the PLL loop composed of the second phase comparator so as not to become unstable, and the phase is compared with the frequency obtained by dividing the reference oscillation frequency of the reference oscillator by 1 / m. An intermediate frequency circuit for a TV receiver, wherein a VCO is controlled by an output of a comparator. The second phase comparator operates only when the power is turned on or when the channel is switched, and after the operation of the VCO is stabilized, the control voltage from the second phase comparator is fixed to the voltage value when the operation of the VCO is stable, 2. The intermediate frequency circuit for a TV receiver according to claim 1, wherein the operation of the first phase comparator starts thereafter.

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