JP4403359B2 - Switching regulator - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a switching regulator that supplies constant power to a load by monitoring an output voltage to the load, and more particularly to a switching regulator that is suitable for use as a power supply device for a small electronic device.
[0002]
[Prior art]
The synchronous step-down switching regulator is configured to pulse by turning on / off a DC voltage power supply at high speed by turning on / off a semiconductor switch or the like, and control an output voltage according to the pulse width. Such a switching regulator performs conversion with a low voltage when the pulse width is narrowed, and a high voltage when the pulse width is widened. The conversion efficiency is good, the power supply can be downsized, and used for power supply devices of small electronic devices. There are many.
[0003]
FIG. 12 shows an example of a conventional switching regulator. A basic configuration of a general synchronous switching regulator includes a pair of switching elements SWP and SWN connected in series between a voltage input terminal Vin supplied with a power supply input and a grounded reference potential terminal, and these switching elements. The drive circuit 10 includes an inductor element L disposed between an output node n1 that connects the source of SWP and a drain of SWN and an output terminal 13 that connects a load, and an output capacitor Co that determines an output voltage Vout. By switching on and off the switching elements SWP and SWN, the voltage of the power supply input is converted and output to the output capacitor Co. The magnitude of the output voltage Vout is fed back to the comparator 11 and further compared with a triangular wave signal generated by the oscillator 12, thereby controlling the on / off cycle of the switching elements SWP and SWN. At this time, the inductor current i itself flowing through the inductor element L via the output node n1 increases or decreases almost linearly with respect to time and does not become a constant current, but the magnitude of the current flowing through the load connected to the output terminal 13 is , And can be set as an average value of the inductor current i.
[0004]
FIG. 13 is a diagram illustrating an analysis model including parasitic capacitance of the switching regulator of FIG.
As shown here, in the switching regulator, the parasitic capacitance Cp is present on the power input side of the inductor element L as an impedance component that cannot actually be ignored, and a sudden current change due to switching of the switching elements SWP and SWN occurs in this portion. As a result, the high-frequency power supply voltage fluctuates on the input / output side. The switching elements SWP and SWN can be configured by switching transistors such as N-channel and P-channel MOSFETs, respectively. In that case, D1 and D2 shown in FIG. 13 are parasitic diodes of the respective switching transistors. In general, the parasitic capacitance of the entire switching regulator can be integrated into one and represented as a parasitic impedance component Cp at the output node n1.
[0005]
Here, regarding the inductor current i flowing through the inductor element L, a current flowing in the direction of the output terminal 13 (indicated by an arrow) is considered as a positive value, and a current flowing in the opposite direction is considered as a negative value.
[0006]
The P driver 1 and the N driver 2 that drive the switching elements SWP and SWN correspond to the drive circuit 10 shown in FIG. Here, in order to prevent the through current from flowing between the voltage input terminal Vin and the ground (reference potential) when the switching elements SWP and SWN are simultaneously turned on, between the ON signals of the P driver 1 and the N driver 2, A dead time for turning off both the switching elements SWP and SWN is provided. Therefore, the operation of the switching regulator shown in FIG. 13 can be considered by classifying it into three modes M1, M2 and M3 described below according to the combination of ON / OFF of the switching elements SWP and SWN.
[0007]
14 is a diagram showing a voltage waveform of the output node when the bottom current of the switching regulator of FIG. 12 is a positive value, and FIG. 15 is a diagram of the output node when the bottom current of the switching regulator of FIG. 12 is a negative value. It is a figure which shows a voltage waveform.
[0008]
In mode M3 (SWP on, SWN off), the potential at the output node n1 of the switching regulator (output node voltage Vn) is equal to the potential of the voltage input terminal Vin. When the switching element SWP is switched from on to off at timing t0 and enters a dead time state of mode M2 (SWP off, SWN off), the output node voltage Vn rapidly decreases and overshoots to the negative side. Next, when the switching element SWN is turned on at the timing t1, the output node voltage Vn approaches zero, but when the inductor current i is always positive and the bottom current is a positive value, again at the timing t2. When the dead time state of the mode M2 is entered, a large discharge current flows from the parasitic inductor component Cp to the inductor element L. For this reason, as shown in FIG. 14, the output node voltage Vn overshoots to the negative side and a ripple is generated, which becomes transient power supply noise. When the bottom current has a negative value, the output node voltage Vn becomes positive by the timing t2 when the switching element SWN is turned off, as shown in FIG. For this reason, the ripple is suppressed in the voltage waveform of the output node voltage Vn at the timing t2 when the mode M1 (SWP off, SWN on) is switched to the mode M2.
[0009]
Hereinafter, the ripple generated in these voltage waveforms will be considered in more detail. FIG. 16 is a diagram showing an equivalent circuit of the switching regulator for explaining the operation of the mode M1.
[0010]
In mode M1, switching element SWP is off and switching element SWN is on, and an equivalent circuit thereof is as shown in FIG. Here, when the switching element SWN is formed of an FET, the relationship between the drain current Id and the gate-source voltage Vgs in the non-saturation region can be expressed by the following equation (1).
[0011]
[Expression 1]
Id = 2K {Vgs−Vt− (Vds / 2)} Vds (1)
By solving this equation (1) for the drain-source voltage Vds, Vds can be obtained as in the following equation (2). Here, Vt is a threshold voltage, and K is a constant.
[0012]
[Expression 2]
Vds = (Vgs−Vt) − {(Vgs−Vt)²-(Id / K)}^1/2
... (2)
That is, the output node voltage Vn proportional to the drain-source voltage Vds is a function of the drain current Id flowing through the switching element SWN.
[0013]
Now, in mode M2, the switching elements SWP and SWN are both in an off state, and an equivalent circuit thereof is as shown in FIG. The inductor current i varies linearly according to the parasitic capacitance Cp and the size of the inductor element L unless clamped by the parasitic diodes D1 and D2 of the switching elements SWP and SWN. FIG. 17 shows a state equation of the inductor current i corresponding to the equivalent circuit. In this mode M2, when the inductor current i changes linearly, the magnitude of the bottom current, which is the lowest value, can be determined from this state equation.
[0014]
In mode M3, the switching element SWP is turned on and the switching element SWN is kept off, so that the output node n1 is directly connected to the voltage input terminal Vin, and an equivalent circuit thereof is as shown in FIG.
[0015]
FIG. 19 is a waveform diagram showing the charge / discharge current and the like of the parasitic capacitance when the bottom current is a positive value. Here, in particular, when the switching element SWN is switched on from the mode M1 to the switching element SWP is switched on to the mode M3, the change in the charging / discharging current ip of the parasitic capacitance Cp when the inductor current i is always positive is described in detail. To do.
[0016]
In mode M2, the capacitor Cp is charged in such a direction that the inductor current i is ip and Vn is lowered. The operation according to the state equation in FIG. 17 ends when the output node voltage Vn is clamped by the parasitic diode D2, and Vn is fixed to the clamp voltage. The inductor current i starts to increase after the switching element SWP is turned on. The di / dt related to the switching element SWP at this time becomes very large, and acts on the parasitic inductance and causes noise. . That is, since a parasitic capacitance Cp having a magnitude that cannot be ignored in an actual switching regulator exists on the input power supply side, a sudden current change due to switching occurs in this portion, and thus a high-frequency power supply voltage fluctuation occurs on the input / output side. In a step-down type power supply device using such a switching regulator, the current value flowing in the Nch transistor is conventionally detected, and the Nch transistor is turned off when the current is zero or almost zero, thereby suppressing harmonics. There is something that is intended to. An example of such a technique is described in Patent Document 1 below.
[0017]
The switching regulator described in Patent Document 1 is a line operating type in which an input / output circuit is insulated by a transformer or the like, and performs so-called zero voltage switching (ZCS). This is realized and is slightly different from the above-mentioned chopper type.
[0018]
FIG. 20 is a waveform diagram showing the charge / discharge current and the like of the parasitic capacitance when the bottom current has a negative value. In this case, since the capacitor Cp is charged in the direction in which the inductor current i becomes ip and Vn is increased, Vn can be increased without being clamped by D2, so that it can approach Vin. Further, this movement is in accordance with a linear differential equation, and is not as steep as the moment when the switching element SWP is turned on at t = t3 in FIG.
[0019]
  In this figure, when the switching element SWN is switched from the ON state (mode M1) to the ON state (mode M3) through the dead time state (mode M2), as shown in FIG. As described above, since Vn is close to Vin, di / dt related to the switching element SWP is smaller than that in FIG. However, since the linear operation in the mode M2 ends when the output node voltage Vn is clamped by the parasitic diode D1,As is clear from FIGS. 20A and 20B, when the inductor current i becomes a negative value,Bottom currentvalueWhen the absolute value of is somewhat large, the clamp voltage is higher than the input voltage Vin of the switching element SWP by the drop voltage of the parasitic diode D1.To becomeOvershoot due to this voltage occurs.
[0020]
[Patent Document 1]
JP-A-10-215566
[0021]
[Problems to be solved by the invention]
As described above, the greater the difference between Vn and Vin immediately before the switching element SWP is turned on, the greater the change rate di / dt related to the switching element SWP when the switching element SWP is turned on. Therefore, there is a problem that the input / output power supply voltage fluctuates due to a sudden change in the current flowing through the output semiconductor switch, and noise associated with the switching operation tends to occur.
[0022]
Also, zero current switching is desirable to reduce the energy loss during switching of the switching element SWP, but the value of the inductor current i varies greatly depending on the load. Therefore, the zero current switching due to the return current from the inductor element L is It only happened by chance under limited conditions, and was only possible under narrow load conditions.
[0023]
An object of the present invention is to provide a switching regulator that uses a return current from an inductor over a wide range of load conditions to reduce a change in current flowing through an output semiconductor switch.
[0024]
[Means for Solving the Problems]
  In order to achieve the above object, there is provided a switching regulator that supplies constant power to the load by monitoring an output voltage to the load. The switching regulator includes a pair of switching elements connected in series between a voltage input terminal and a reference potential terminal, and an inductor element disposed between an output node connecting the pair of switching elements to each other and the load. And a signal generating means for generating a triangular wave signal for controlling an on / off period of the switching element, and a current flowing through the switching element on the reference potential terminal sidebottomTiming detection means for detecting the timing when the current becomes negativeAnd a frequency changing means for changing the frequency of the triangular wave signal according to the magnitude of the bottom current at a timing when the bottom current becomes a negative value.It consists of.
[0025]
  In the switching regulator of the present invention, the bottom frequency flowing in the inductor is changed to a current value with a small negative value by changing the switching frequency according to the load current.Change toAs a result, the parasitic capacitance at the output node is resonantly and gently charged to reduce the switching noise. Also, the absolute value of the bottom current can be controlled to prevent output node voltage overshoot.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
(First embodiment)
FIG. 1 is an overall circuit diagram showing a switching regulator according to the present invention.
[0027]
This switching regulator constitutes the same synchronous step-down switching power supply circuit as that of the conventional circuit of FIG. 12, and its basic structure is that a voltage input terminal Vin to which a power supply input is supplied and a reference grounded to the ground. A pair of switching elements SWP and SWN connected in series between the potential terminal and an output terminal 13 to which a load is connected and an output node n1 connecting the source of the switching element SWP and the drain of the switching element SWN. Inductor element L, output capacitor Co for determining output voltage Vout of output terminal 13, drive circuit for controlling on / off of switching elements SWP and SWN, P driver 1 and N driver 2, control circuit 3 such as a PWM comparator, and the like are provided. However, in the switching regulator of the present invention, The oscillation period determining circuit 4 that determines the frequency of the triangular wave signal for controlling the on / off period of the switching elements SWP and SWN, and the timing at which the current value of the current flowing through the switching element SWN on the reference potential terminal (ground) side becomes negative. A bottom current detection circuit 5 is provided.
[0028]
FIG. 2 is a signal waveform diagram illustrating the operation of the switching regulator.
In the control circuit 3 of FIG. 1, a voltage signal obtained by dividing the output voltage Vout by a resistor or the like is fed back, and a difference signal Verr between the voltage signal and the reference voltage Vref is detected by an error amplifier. The triangular wave signal Vosc shown in FIG. 2A is compared with the output Verr of the error amplifier, and the switching element SWP is turned on when the difference signal Verr is larger than the triangular wave signal Vosc (Ton period). In this case, as is well known, the output voltage Vout can be defined between the voltage (Vi) of the voltage input terminal Vin as follows:
[0029]
[Equation 3]
Vout = Ton / (Ton + Toff) Vin (3)
Here, Ton / (Ton + Toff) is a duty ratio.
[0030]
FIG. 2B shows a change in voltage (output node voltage) Vn at the output node n1. If the switching element SWP on the voltage input terminal Vin side is off (Toff period), the output node voltage Vn is approximately equal to the ground potential of the reference potential terminal, but if the switching element SWP is on (Ton period), the output node The voltage Vn rises. On the other hand, as shown in FIG. 4C, this circuit operation is balanced when the average value iave of the current i flowing through the inductor element L becomes equal to the output current io to the load.
[0031]
If PWM control is performed by an ordinary switching regulator, these conditions are automatically satisfied, and the bottom current can be reduced by increasing the period of the triangular wave signal. However, when the bottom current decreases, the maximum value of the inductor current i also increases, whereby the average value iave can be kept constant. That is, the bottom current detection circuit 5 detects the magnitude of the bottom current, and when it is a positive current, the oscillation period determination circuit 4 feeds back the direction of increasing the period of the triangular wave signal Vosc, Make it smaller. On the other hand, if the current is negative, the oscillation period determining circuit 4 should shorten the period of the triangular wave signal Vosc and feed back in the direction of increasing the bottom current. If it is determined that the bottom current is a sufficiently small negative current, the detected small negative current is maintained without changing the period of the triangular wave signal Vosc. As a result, the difference between Vn and Vin immediately before the change from mode M2 to mode M3 is small, and the current is also in a zero current switching state, so that noise during switching of the switching element SWP can be suppressed. .
[0032]
Next, specific circuit configurations of the bottom current detection circuit 5 and the oscillation period determination circuit 4 described above when the switching regulator shown in FIG. 1 is configured will be described.
[0033]
FIG. 3 is a circuit diagram showing a configuration of a bottom current detection circuit and an oscillation cycle determination circuit that constitute the switching regulator of FIG.
In FIG. 3, the PWM comparator 31 is connected to 10 stages of inverters INV1 to INV10 that delay the output signal S0 by a predetermined time, and also connected to the drive circuit 10 driven by the output signal S10 of the final stage inverter INV10. Has been. Here, S0 is a signal that becomes L (corresponding to Ton) when Verr> Vosc, and H (corresponding to Toff) when Verr <Vosc. The NOR circuit NOR1 receives the output signal S4 of the fourth-stage inverter INV4 and the output signal S7 of the seventh-stage inverter INV7.
[0034]
The bottom current detection circuit 5 includes two input terminals 51 and 52 and a comparator CMP1 that determines whether the bottom current is positive or negative. The comparator CMP1 receives the output node voltage Vn from the input terminal 52 and the ground potential, and a bottom current positive / negative determination output P / M (Plus or Minus) signal is output as one output signal of the exclusive OR circuit EOR1. It is supplied to the input terminal. The other input terminal of the exclusive OR circuit EOR1 is connected to the second-stage inverter INV2, and its output signal S2 is supplied.
[0035]
In this bottom current detection circuit 5, the switching circuit 53, the exclusive OR circuit EOR1, the switch SW1, the inverter INV11, the capacitor C10, the switch SW2, the inverter INV12, the capacitor C11, the operational amplifier OPA1, and the reference power source V10 are a kind of switched A capacitor circuit is configured. The exclusive OR circuit EOR1 is connected to the switching circuit 53, and the output signal S12 is supplied to the select terminal s of the switching circuit 53. The output terminal of the switching circuit 53 is connected to the positive electrode of the capacitor C10 via the switch SW1. This switch SW1 is ON / OFF controlled by the output signal S10 of the final stage of the 10-stage inverters INV1 to INV10 and a signal obtained by inverting it with the inverter INV11. The negative electrode of the capacitor C10 is connected to the negative input terminal of the operational amplifier OPA1. In the operational amplifier OPA1, a parallel circuit of a switch SW2 and a capacitor C11 is connected between the negative input terminal and the output terminal. The switch SW2 is ON / OFF controlled by the output signal S0 of the PWM comparator 31 and a signal obtained by inverting it with the inverter INV12. The + input terminal of the operational amplifier OPA1 is connected to the reference power supply V10.
[0036]
In the bottom current detection circuit 5, the switch SW3, the inverter INV13, the capacitor C12, the resistor R1, and the comparator CMP2 constitute a circuit that converts the absolute value of the output node voltage Vn into time. The operational amplifier OPA1 has an output terminal connected to the capacitor C12, the resistor R1, and the + input terminal of the comparator CMP2 via the switch SW3. The switch SW3 is ON / OFF controlled by the output signal S11 of the NOR circuit NOR1 and a signal obtained by inverting it with the inverter INV13. The negative input terminal of the comparator CMP2 is connected to the reference power source V10.
[0037]
The oscillation period determination circuit 4 is a circuit that changes the period of the triangular wave generation circuit based on the detection result of the bottom current. The oscillation cycle determination circuit 4 includes an inverter INV14, a NAND circuit NAND1, a transistor N21, a constant current source i1, a transistor P20, a NAND circuit NAND2, a transistor P21, a constant current source i2, a transistor N20, and a capacitor C13, and an output terminal. 41 is provided.
[0038]
Next, operations of the bottom current detection circuit and the oscillation cycle determination circuit shown in FIG. 3 will be described.
The bottom current positive / negative judgment output signal P / M output from the comparator CMP1 is H when the bottom current is a negative value as shown in FIG. In that case, it is necessary to shorten the period of the triangular wave signal Vosc by the oscillation period determining circuit 4 or to generate a feedback signal in a direction to leave it as it is. Further, when the positive / negative determination output signal P / M is L, the bottom current is a positive value as shown in FIG. 19, and therefore it is necessary to feed back in a direction to increase the period of the triangular wave signal Vosc.
[0039]
The PWM comparator 31 shown in FIG. 3 is connected to 10 stages of inverters INV1 to INV10 as delay elements, and outputs a control signal obtained by delaying the output signal S0 by a predetermined time. These inverters INV1 to INV10 may have a configuration in which the number of stages shown in FIG. Here, as described above, the timing at which the switching element SWN is switched from ON to SWP on is a problem in the process from the mode M1 to the mode M3. Therefore, the switching circuit SWN is switched from ON to OFF from the control circuit 3 to the N driver 2. The following circuit operation will be described with reference to the time when the drive signal for switching to H changes from H to L and the drive signal as a base point.
[0040]
The output signals S1 to S10 of each stage of the inverters INV1 to INV10 are transmitted with a little delay in the output signal S0, and the final stage output signal S10 is supplied to the drive circuit 10. The input terminals 51 and 52 of the bottom current detection circuit 5 are connected to the switching circuit 53 and the comparator CMP1, respectively, and the output node voltage Vn is input thereto.
[0041]
The switched capacitor circuit including the switching circuit 53, the exclusive OR circuit EOR1, the switch SW1, the inverter INV11, the capacitor C10, the switch SW2, the inverter INV12, the capacitor C11, the operational amplifier OPA1, and the reference power supply V10 is output from the operational amplifier OPA1. A signal proportional to the absolute value of the voltage Vn (more precisely, the reference power supply V10 added as a bias) is output as the output signal S13. The operation of this circuit portion differs depending on whether the positive / negative judgment output signal P / M (hereinafter referred to as P / M signal) is H or L, that is, depending on whether the output node voltage Vn is positive or negative. Specifically, the exclusive OR circuit EOR1 takes the exclusive OR of the P / M signal and the output of the inverter INV2, thereby changing the operation of the switching circuit 53 depending on whether the bottom current is positive or negative.
[0042]
After the potential of the output signal S13 of the operational amplifier OPA1 is stabilized, the switch SW3 is turned on for a short time at a timing defined by the NOR circuit NOR1. During this ON period, the capacitor C12 is charged to the potential of the output signal S13. When the switch SW3 is turned off, the charge of the capacitor C12 is discharged by a time constant circuit including the capacitor C12 and the resistor R1. The output signal S15 of the comparator CMP2 becomes H only during the period T from when the capacitor C12 is charged to when the discharge is started until the potential becomes equal to the reference power source V10.
[0043]
Here, since the operational amplifier OPA1 determines the output signal S13 as a function of the absolute value of the output node voltage Vn, the output node voltage Vn is also changed during the period T in which the output signal S15 of the comparator CMP2 is H. It becomes a function. However, in practice, the period T can be calculated by the following equation by ignoring the ON period of the switch SW3.
[0044]
[Expression 4]
T = (C12 * R1) * ln (1+ (| Vn | / V10)) (4)
In the oscillation cycle determination circuit 4, the NAND circuits NAND1 and NAND2 are controlled by the P / M signal, and either the transistor N20 or the transistor P20 is turned on for a period T substantially proportional to the output node voltage Vn, and the capacitor C13 Charging / discharging is performed, and the potential V3 of the output terminal 41 is raised and lowered according to charging / discharging of the capacitor C13. Now, when the P / M signal is H, that is, when the bottom current has a negative value, the transistor P20 is turned on and the capacitor C13 is charged by (i1 * T), thereby raising the potential V3 of the output terminal 41. Further, when the P / M signal is L, that is, when the bottom current is a positive value, the transistor N20 is turned on and the capacitor C13 is discharged only (i2 * T), so the potential V3 of the output terminal 41 is lowered.
[0045]
FIG. 4 is a circuit diagram showing an example of the switching circuit constituting the bottom current detection circuit of FIG.
The switching circuit 53 includes two switches SW11 and SW12, an inverter INV16, input terminals 53a and 53b, a select terminal 53c, and an output terminal 53d that outputs an output signal OUT. When the select signal s (= S12) input to the select terminal 53c is H, the analog signal “1” input to the input terminal 53a is output from the output terminal 53d, and when the select signal s (S12) is L. The analog signal “0” input to the input terminal 53b is output from the output terminal 53d.
[0046]
FIG. 5 is a circuit diagram showing a configuration of a triangular wave signal generation circuit constituting the switching regulator of FIG.
The triangular wave signal generating circuit 32 is connected to the output terminal 41 of the oscillation period determining circuit 4, and a voltage signal V3 output therefrom is input to the input terminal 32a, and a predetermined triangular wave signal Vosc corresponding to the voltage signal V3 is supplied. This is a circuit to be generated. Since the input terminal 32a is connected to the gate of the transistor N22, the drain current i3 flowing through the transistor N22 depends on the voltage signal V3 of the oscillation period determining circuit 4. That is, if the voltage signal V3 increases, the drain current i3 also increases. If the voltage signal V3 decreases, the drain current i3 also decreases.
[0047]
The transistors P22 and P23 are current mirror circuits, and the drain current i4 flowing through the transistor P23 is the ratio of the transistor size of the transistors P22 and P23 to the current i3 ((W of P23 / L of P23) / (W / P22 of P22). L)). In the transistors P22 and P23, parameters other than the transistor size such as the channel width W and the channel length L are the same. Similarly, the current i5 flowing through the transistor N23 is obtained by multiplying the current i3 by the ratio of the transistor sizes of the transistors N22 and N23. The triangular wave signal Vosc generated by charging / discharging the capacitor C20 with these currents i4 and i5 has a magnitude (= i4 / C20) whose slope is proportional to the current i4 and inversely proportional to the capacitance value (= C20) of the capacitor C20. ) To the upper limit value Vhosc, and then decreases to the lower limit value Vlosc with a gradient (= −i5 / C20) proportional to the current i5 and inversely proportional to the capacitance value of the capacitor C20 (= C20).
[0048]
The comparators CMP3 and CMP4 and the NOR circuits NOR2 and NOR3 constitute a flip-flop circuit that receives the triangular wave signal Vosc of the output terminal 32d. Then, the transistors P23 and N24 are alternately turned on by the output of the flip-flop circuit, and the charging period by the drain current i4 and the discharging period by the drain current i5 are switched. In the flip-flop circuit, when the output voltage level of the triangular wave signal Vosc reaches the upper limit value Vhosc or the lower limit value Vlosc, it can be inverted to generate the triangular wave signal Vosc having a predetermined period.
[0049]
Next, the relationship between the period of the triangular wave signal Vosc and the magnitude of the bottom current will be described. When the bottom current has a negative value, the voltage signal V3 output from the oscillation period determination circuit 4 increases according to the magnitude of the absolute value of the bottom current. When the voltage signal V3 rises, the drain current i3 increases, thereby increasing the drain currents i4 and i5, so the charge / discharge time of the capacitor C20 is shortened. Therefore, the period of the triangular wave signal Vosc is shortened.
[0050]
On the other hand, when the bottom current is a positive value, the voltage signal V3 output from the oscillation period determination circuit 4 falls according to the magnitude of the absolute value. When the voltage signal V3 falls, the drain current i3 decreases, thereby decreasing the drain currents i4 and i5, and the charge / discharge time of the capacitor C20 becomes longer. Therefore, the period of the triangular wave signal Vosc becomes long.
[0051]
In this way, the period of the triangular wave signal Vosc can be controlled according to the bottom current. In addition, regarding the magnitude of the current sources i1 and i2 for charging and discharging the capacitor C13 that determines the voltage signal V3 of the oscillation period determining circuit 4, if the current source i2 is made larger (slightly) than the current source i1, the overall operation As a result, the voltage signal V3 is reduced and the period of the triangular wave signal Vosc is increased, so that the operating point when the bottom current is close to zero is balanced on the negative current side.
[0052]
FIG. 6 is a signal waveform diagram for explaining the operation of the bottom current detection circuit of FIG. FIG. 7 is a timing chart for explaining the bottom current determination operation when the bottom current has a negative value, and FIG. 8 is a timing chart for explaining the bottom current determination operation when the bottom current becomes a positive value.
[0053]
FIG. 6A shows the output signal S0 of the PWM comparator 31, which changes from H to L at timing t10. FIG. 4B shows the output signal S2 of the second-stage inverter INV2, which changes from H to L at timing t11 after the timing t10. FIG. 5C shows the output signal S4 of the fourth-stage inverter INV4, which changes from H to L at timing t12 later than timing t11. FIG. 6D shows the output signal S7 of the seventh-stage inverter INV7, which changes from L to H at timing t13 later than timing t12. FIG. 5E shows the output signal S10 of the tenth stage inverter INV10, which rises to H at timing t1 and changes from H to L at timing t2. FIG. 5F shows the output signal S11 of the NOR circuit NOR1, which is H from timing t12 to timing t13.
[0054]
FIG. 7A shows an enlarged output signal S11 of the NOR circuit NOR1 shown in FIG. Although not shown here, the bottom current has a negative value, and the output node voltage Vn immediately before the switching element SWP is turned on is positive. Therefore, the P / M signal maintains the H state.
[0055]
FIG. 7B shows how the output signal S12 of the exclusive OR circuit EOR1 falls from H to L at timing t11. FIG. 5C shows how the charge Q1 on the positive electrode side of the capacitor C10 changes. The positive electrode of the capacitor C10 is connected to the switching circuit 53 while the switch SW1 is turned on, and is switched to the ground side at the timing t11 by the output signal S12 of the exclusive OR circuit EOR1. Therefore, the charge + Q accumulated in the positive electrode of the capacitor C10 is discharged via the switch SW1 and the switching circuit 53 at the timing t11. FIG. 4D shows how the charge Q2 on the negative electrode side of the capacitor C10 changes. At the timing t11, the charge Q2 is charged until the charge becomes zero from the previous -Q state, contrary to the charge Q1 on the positive electrode side.
[0056]
FIG. 7E shows how the charge Q3 on the negative electrode side of the capacitor C11 changes. This charge Q3 (= −Q) is the charge Q2 (= −Q) on the negative electrode side of the capacitor C10 moved at the timing t11. FIG. 5F shows how the charge Q4 on the positive electrode side of the capacitor C11 changes. Since the switch SW2 connected in parallel with the capacitor C11 is turned off at the timing t10, the charge Q4 becomes + Q at the timing t11 at which −Q is generated on the negative electrode side.
[0057]
FIG. 7G shows a potential change with respect to the output signal S13 of the operational amplifier OPA1. The potential of the output signal S13 rises from the potential of the reference power supply V10 (= V10) by a voltage (= | Vn | × C10 / C11) proportional to the magnitude of the output node voltage Vn at timing t11. FIG. 11H shows the potential change for the input signal S14 to the + side terminal of the comparator CMP2. At timing t12, the output signal S11 of the NOR circuit NOR1 becomes H and the switch SW3 is turned on, so that charge is accumulated in the capacitor C12 and the input signal S14 rises to a potential equal to the output signal S13 of the operational amplifier OPA1. However, at the subsequent timing t13, the output signal S11 of the NOR circuit NOR1 falls to L again, and the switch SW3 is turned off, whereby the charge accumulated in the capacitor C12 starts discharging.
[0058]
FIG. 7 (i) shows the output signal S15 of the comparator CMP2. The output signal S15 becomes H at the same timing t12 as the input signal S14, and changes to L at the timing t14 when the input signal S14 becomes equal to or lower than the potential of the reference power supply V10 (= V10). Therefore, the oscillation period determining circuit 4 controls the NAND circuits NAND1 and NAND2 only during the ON period T determined by the above-described equation (4), and allows the current to flow from the constant current source i1 to the output-side transistor P20 to charge the capacitor C13. To do. Thereby, when the bottom current is negative (P / M signal = H), the potential V3 of the output terminal 41 rises in proportion to (T × i1).
[0059]
In FIG. 7, the bottom current detection signal in the case where the bottom current is a negative value has been described by the signal waveforms of the respective parts of the bottom current detection circuit and the oscillation cycle determination circuit constituting the switching regulator. In FIG. The bottom current determination operation when the bottom current becomes a positive value will be described.
[0060]
FIG. 8A shows an enlarged output signal S11 of the NOR circuit NOR1 shown in FIG. Here, when the bottom current becomes a positive value, the output node voltage Vn becomes negative and the P / M signal becomes L.
[0061]
In FIG. 8B, since the P / M signal becomes L, the output signal S12 of the exclusive OR circuit EOR1 rises from L to H at timing t11. FIG. 5C shows how the charge Q1 on the positive electrode side of the capacitor C10 changes. The positive electrode of the capacitor C10 is connected to the switching circuit 53 while the switch SW1 is turned on, and is switched to the input terminal 51 side at the timing t11 by the output signal S12 of the exclusive OR circuit EOR1. Therefore, at timing t11, contrary to the case of FIG. 7, negative charge −Q flows into the positive electrode of the capacitor C10 via the switch SW1 and the switching circuit 53. FIG. 4D shows how the charge Q2 on the negative electrode side of the capacitor C10 changes. The charge Q2 is charged from the ground potential until then to + Q, opposite to the positive charge −Q1.
[0062]
FIGS. 8E and 8F show how the charges Q4 and Q3 on the positive and negative sides of the capacitor C11 change. Here, as in the case of FIGS. 7E and 7F, since the switch SW2 connected in parallel with the capacitor C11 is turned off at the timing t10, the capacitor C11 is turned off at the timing t11 at which −Q is generated on the negative electrode side. The charge Q4 on the positive electrode side changes to + Q.
[0063]
Therefore, as shown in these timing charts, even when the bottom current takes a positive value or a negative value, a signal having a positive voltage value is output as the output signal S13 of the operational amplifier OPA1. Therefore, the output signal S15 of the comparator CMP2 becomes H at the same timing t12 as the input signal S14, and changes to L at the timing t14 when the input signal S14 becomes equal to or lower than the potential (= V10) of the reference power supply V10.
[0064]
FIG. 9 is a diagram illustrating a voltage waveform at the output node when the absolute value of the bottom current is small. FIG. 10 is a diagram illustrating a voltage waveform at the output node when the absolute value of the bottom current is further smaller.
[0065]
Here, the absolute value of the bottom current ib1 in FIG. 9 is smaller than the bottom current ib of the inductor current i shown in FIG. In this case, the output node voltage Vn at the timing t3 when the mode M2 ends is substantially equal to the power supply voltage of the voltage input terminal Vin. Therefore, noise when the switching element SWP is turned on can be suppressed to a minimum magnitude. As shown in FIG. 10, when the absolute value of the bottom current ib1 is further reduced, the inductor current i is inverted to a positive value during the operation of the mode M2, so that the output node voltage Vn starts to oscillate.
[0066]
In the switching regulator described above, the operation when di / dt changes from negative to positive is realized by a linear circuit, and Vn immediately before the switching element SWP is turned on is substantially equal to Vin. As shown in FIG. 10, a switching operation with low noise can be realized.
[0067]
Here, as in the conventional switching regulator, when the current is positive (in the direction of charging the output capacitance Co), even if the operation by the linear circuit of the parasitic capacitance Cp and the inductor element L is started once, immediately. It is not reached until it is clamped by the parasitic diode of the Nch transistor and the direction of the inductor current is reversed. In addition, when the current flowing through the switching element SWN is a small negative current, it is switched off, so that the overshoot of the output node voltage Vn can be removed and the noise can be further reduced. Furthermore, since the switching element SWN is turned off and the switching element SWP is turned on when the absolute value of the inductor current i is substantially zero, zero current switching can also be realized.
[0068]
(Second Embodiment)
FIG. 11 is a circuit diagram showing the oscillation cycle determination circuit of FIG. 3 configured as a digital circuit.
[0069]
In FIG. 11, the oscillation cycle determination circuit 4 from receiving the output signal S13 of the operational amplifier OPA1 to determining the voltage signal V3 of the output terminal 49 is configured using a digital circuit. The configuration of the bottom current detection circuit 5 is basically the same as the configuration of the first embodiment, but differs in that the + input terminal of the operational amplifier OPA1 is grounded.
[0070]
The control circuit 42 is activated by the output signal S11 of the NOR circuit NOR1, and controls the timing of the oscillation cycle determination circuit 4. The AD converter 43 receives the control signal from the control circuit 42 at the lNST port, AD converts the output signal S13 input as an analog signal, and outputs the converted digital signal from the output port OUT. The processor unit 44 is a special arithmetic processing circuit, and obtains output data P2 by executing the following arithmetic expression on the two input data POP1 according to the state of the P / M signal.
[0071]
When P / M = H
[0072]
[Equation 5]
P2 = P1 + P0−α1 (5)
When P / M = L
[0073]
[Formula 6]
P2 = P1-P0 (6)
And However, α1 is a small positive constant.
[0074]
The register circuit 45 stores the output data P2 of the processor unit 44, and the output data is input to the binary decoder 46 and the input port P1 of the processor unit 44. When the bottom current is a negative value, the processor unit 44 executes an operation that shortens the oscillation period of the triangular wave signal until the data in the register circuit 45 is + P0, and then lengthens the oscillation period by a small α1 (> 0). . That is, the processor unit 44 increases the output data P2 at a rate (+ P0) corresponding to the output node voltage Vn, and then outputs it with a slight decrease (−α1).
[0075]
Therefore, when the bottom current is a small negative current, it can be controlled not to be a positive current. When the bottom current is a positive current, the data in the register circuit 45 is reduced at a rate proportional to the magnitude of the bottom current. The output data of the register circuit 45 is converted into a binary code by the binary decoder 46, the switch 48 corresponding to the binary data is selected, and one of the plurality of constant current sources 47a, 47b, 47c,... Is connected to the transistor N25. The As a result, the current i6 flows through the transistor N25 with a magnitude corresponding to the magnitude of the output data of the register circuit 45. The gate and drain of the transistor N25 are short-circuited and connected to the output terminal 49. In this case, in the triangular wave signal generation circuit 32, the transistors N22 and N23 are current mirror circuits for the transistor N25.
[0076]
In this way, the oscillation cycle determination circuit 4 constituted by a digital circuit can control the oscillation cycle of the triangular wave signal based on the value of the bottom current, as in the first embodiment, and has a small negative current. An equilibrium point can be set.
[0077]
In addition, the switching control circuit including the oscillation cycle determination circuit 4 and the bottom current detection circuit 5 can detect the bottom current and change the switching frequency so as to maintain a small negative current. That is, since di / dt is switched from negative to positive not by the switching elements SWP and SWN but by a linear circuit composed of the parasitic capacitance Cp and the inductor element L, di / dt changes smoothly. Then, since Vn immediately before the switching element SWP is turned on becomes approximately equal to Vin, it is possible to reduce noise at the time of switching that occurs in a conventional switching regulator.
[0078]
In the above-described embodiment, the bottom current is directly estimated from the voltage Vn of the output node n1 increased by the on-resistance of the semiconductor switch. However, as another example of the bottom current detection circuit, it is serially connected to the power supply or the output. It is also possible to detect the load current from the voltage value of the inserted minute resistor. From this load current and inductor value, the bottom current value at a specific switching frequency can be estimated.
[0079]
The bottom current detection circuit 5 and the oscillation cycle determination circuit 4 described above are shown as one circuit example for configuring a switching regulator, and the switching frequency is changed so as to keep the bottom current small. If so, a detection circuit or a control circuit having another configuration may be used.
[0080]
【The invention's effect】
As described above, according to the switching regulator of the present invention, the following effects can be realized.
[0081]
First, when the semiconductor switch (SWN) is turned off, the current that flows transiently is set to a small bottom current, so that it is basically zero current switching, and the current change (di / dt) related to the switching element SWN is changed. Thus, the fluctuation of the input / output voltage due to switching can be suppressed.
[0082]
Second, when the semiconductor switch (SWP) is turned on, the current that flows transiently is also kept very small. This is because a so-called zero voltage switching state in which the output node voltage is turned on at a value close to the input power supply voltage can be achieved, and the inductor current value is almost zero. Therefore, the current change (di / dt) related to the switching element SWP can be reduced, and fluctuations in the input / output voltage due to switching can be suppressed.
[0083]
Thirdly, since Vn changes to near Vin due to resonant charging due to the bottom current of the inductor and the parasitic capacitance of the output node, high-frequency components generated in the conventional switching regulator are not included. For this reason, there is an advantage that extra radiation and conduction noise associated with high-speed switching operation do not occur.
[Brief description of the drawings]
FIG. 1 is an overall circuit diagram showing a switching regulator according to the present invention.
FIG. 2 is a signal waveform diagram illustrating the operation of a switching regulator.
3 is a circuit diagram showing a configuration of a bottom current detection circuit and an oscillation cycle determination circuit constituting the switching regulator of FIG. 1; FIG.
4 is a circuit diagram showing an example of a switching circuit constituting the bottom current detection circuit of FIG. 3;
5 is a circuit diagram showing a configuration of a triangular wave generating circuit constituting the switching regulator of FIG. 1. FIG.
6 is a signal waveform diagram illustrating a control signal used for a determination operation in the bottom current detection circuit of FIG.
FIG. 7 is a timing chart illustrating a bottom current determination operation when the bottom current is a negative value.
FIG. 8 is a timing chart illustrating a bottom current determination operation when the bottom current is a positive value.
FIG. 9 is a diagram showing a voltage waveform at the output node when the absolute value of the negative value of the bottom current is small.
FIG. 10 is a diagram illustrating a voltage waveform of the output node when the absolute value of the negative value of the bottom current is further smaller.
11 is a circuit diagram showing the oscillation cycle determination circuit of FIG. 3 configured as a digital circuit.
FIG. 12 is a circuit diagram showing an example of a conventional switching regulator.
13 is a diagram showing an analysis model including parasitic capacitance of the switching regulator of FIG.
14 is a diagram showing a voltage waveform at the output node when the bottom current of the switching regulator of FIG. 12 is a positive value.
15 is a diagram showing a voltage waveform at the output node when the bottom current of the switching regulator of FIG. 12 becomes a negative value.
FIG. 16 is a diagram showing an equivalent circuit of a switching regulator for explaining a circuit operation in mode M1.
FIG. 17 is a diagram showing an equivalent circuit of a switching regulator for explaining a circuit operation in mode M2.
FIG. 18 is a diagram showing an equivalent circuit of a switching regulator for explaining a circuit operation in mode M3.
FIG. 19 is a waveform diagram showing a charge / discharge current and the like of parasitic capacitance when the bottom current is a positive value.
FIG. 20 is a waveform diagram showing charge / discharge current and the like of parasitic capacitance when the bottom current becomes a negative value.
[Explanation of symbols]
1 P driver
2 N driver
3 Control circuits such as PWM comparators
4 Oscillation cycle determination circuit
5 Bottom current detection circuit
10 Drive circuit
13 Output terminal
31 PWM comparator
32 Triangular wave signal generation circuit
41 Output terminal
42 Control circuit
43 AD Converter
44 processor units
45 register circuit
46 Binary decoder
47a, 47b, 47c constant current source
48 switches
51,52 input terminals
53 switching circuit
SWP, SWN Switching element
EOR1 Exclusive OR circuit
SW1-SW3, SW11-SW12 switch
C10 to C13 capacitors
OPA1 operational amplifier
NOR1 NOR circuit
NAND1, NAND2 NAND circuit
N20 to N25, P20 to P24 Transistor
i1, i2 constant current source
Vin voltage input terminal
n1 output node
L Inductor element
Co output capacitor
Vout output voltage
i Inductor current
Cp parasitic capacitance
Vn Output node voltage
Vosc triangular wave signal
INV1 to INV16 inverter
CMP1-CMP4 comparator

Claims (7)

In a switching regulator that supplies constant power to the load by monitoring the output voltage to the load,
A pair of switching elements connected in series between the voltage input terminal and the reference potential terminal;
An inductor element disposed between an output node connecting the pair of switching elements to each other and the load;
Signal generating means for generating a triangular wave signal for controlling the on / off period of the switching element;
Timing detection means for detecting a timing at which a bottom current flowing in the switching element on the reference potential terminal side becomes a negative value;
Frequency changing means for changing the frequency of the triangular wave signal at a timing when the bottom current becomes a negative value according to the magnitude of the bottom current;
A switching regulator comprising: 2. The switching regulator according to claim 1, wherein the frequency changing means maintains the period of the triangular wave signal at a timing when the bottom current becomes a predetermined negative value . Said frequency changing means, the bottom current flowing from the output node connected to said switching element to the reference potential terminal side to the negative values and to so that is the oscillation period determining circuit for determining the frequency of the triangular wave signal The switching regulator according to claim 1. Said timing detecting means, switching regulator of claim 1, wherein the minimum value of the bottom current detect based on the potential in the previous SL output node the timing was reduced to a predetermined negative value. The timing detection means includes the bottom at a specific switching frequency in the switching element based on a current value flowing through a minute resistor connected between the pair of switching elements and the output node and an inductance value of the inductance element. The switching regulator according to claim 1 , wherein the magnitude of the current is estimated .   2. The switching regulator according to claim 1, wherein the power supplied to the voltage input terminal is stepped down to supply a constant power to the load.   The switching regulator according to claim 1, wherein the switching element includes an N-channel and a P-channel switching transistor.

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