JP4395918B2 - Field emission type electron emission device and field emission type display device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a field emission type electron emission device that emits electrons by field emission, and a field emission type display device that performs image display using electrons emitted by field emission.
[0002]
[Prior art]
When a high voltage is applied to the tip of a needle-like conductor or semiconductor, electrons are transmitted through the potential barrier by the tunnel effect and emitted from the tip even at room temperature. Such a phenomenon is called field emission or cold-cathode emission, and an element (member) that emits electrons by this phenomenon is called an emitter or a cold cathode.
[0003]
An element (member) that emits electrons due to such a phenomenon (hereinafter referred to as an “emitter” or an “electron-emitting element”) can effectively emit electrons even at room temperature because of its structure. Since there is no need for heating and the electron emission effect with respect to the applied voltage is high, the electron emission can be performed in response to a minute electric field at a relatively low voltage. Further, such an electron-emitting device also has a characteristic that process consistency with a semiconductor process is good, and a large number of devices can be formed in an array on a plane.
[0004]
In addition, the characteristics of the above-described electron-emitting devices are considered to be particularly suitable for flat panel display devices. A device using an electron-emitting device as a flat panel display device is called a field emission display (hereinafter simply referred to as “FED (Field Emission Display)”). The general configuration of the FED is such that an anode electrode coated with a phosphor that emits light upon collision of electrons is disposed opposite to a plurality of electron-emitting devices. In the FED having such a configuration, a current is selectively supplied to a plurality of electron-emitting devices according to an image to be displayed, and electrons are emitted from the electron-emitting devices to which the current is supplied. The electrons emitted from the electron-emitting device collide with the phosphor to emit light, and a desired image is displayed by the light emission.
[0005]
According to this FED, electrons emitted from the electron-emitting device collide with the phosphor, and the phosphor is excited to emit light. Therefore, unlike a non-light-emitting display device such as a liquid crystal display device, the FED It has the advantage of being able to display images by light emission, and is highly expected as a next-generation display device.
[0006]
10 and 11 are a plan view and a cross-sectional view, respectively, showing a configuration example of a conventional FED. In these figures, as the type of the structure of the emitter, a structure called a Spindt (person name) type having a conical shape is shown as an example. However, as the type of emitter structure, in addition to the Spindt type, the outer shape is formed in a cup-shaped structure, and the electric field is concentrated on the peripheral edge (ridgeline) portion, so that electrons are emitted from the peripheral portion. An emitter called a so-called cup-type structure has also been proposed. This cup-type emitter is also a field emission type device, similar to the Spindt type, in that it emits electrons by field emission. In these figures, however, for simplicity of explanation, the Spindt type is representative of the emitter structure. I will pick up and explain.
[0007]
The FED includes a plurality of emitters 1 arranged in a matrix and an anode electrode 2 arranged to face the plurality of emitters 1. A phosphor layer 4 is formed on the upper or lower surface (upper surface in the example of FIG. 11) of the anode electrode 2 by applying a phosphor. The FED further includes a cathode electrode 3 and a gate electrode (extraction electrode) 5 that are arranged orthogonal to each other. The cathode electrode 3 and the extraction electrode 5 each have a plurality of electrodes arranged at equal intervals, and are arranged orthogonally so as to face each other via the insulating layer 6 (FIG. 11). The emitters 1 are arranged in a matrix in the horizontal direction (X direction in FIG. 10) and the vertical direction (Y direction in FIG. 10) corresponding to the position where the extraction electrode 5 and the cathode electrode 3 cross each other, and the bottom surface. Is electrically connected to the cathode electrode 3. The extraction electrode 5 is provided with a hole 7 corresponding to each emitter 1. The center position of the hole 7 has a positional relationship corresponding to the top vertex of each emitter 1. A scanning driver (scanning drive circuit) 8 is connected to the extraction electrode 5. A data driver (signal drive circuit) 9 is connected to the cathode electrode 3.
[0008]
Although not shown in the drawings, each component of the conventional general FED as described above is formed in a structure that is housed in, for example, a flat tube made of glass or the like and kept in a vacuum. ing.
[0009]
For example, the emitter 1 selectively emits an electric field of about 0.01 V / Å to 0.1 V / Å so that electrons are emitted from the tip by the tunnel effect. Normally, in the FED, a set of a predetermined number (for example, 1000) of emitters 1 corresponds to one pixel. If the phosphor layer 4 is for monochrome image display, the entire phosphor layer 4 is formed of a white light-emitting phosphor. If the phosphor layer 4 is for color image display, phosphor stripes for emitting red (Red = R), green (Green = G) and blue (Blue = B) colors are arranged for each pixel. The
[0010]
For example, a DC voltage of 3 kV is fixedly applied to the anode electrode 2. Further, a DC voltage of 100 V, for example, is applied to the extraction electrode 5 from the scan driver 8. This DC voltage is cyclically applied sequentially from, for example, the upper extraction electrode 5 to the lower extraction electrode 5 (Y direction in FIG. 10). On the other hand, a voltage (for example, a voltage of about 0 V to 10 V) corresponding to an image signal is selectively applied from the data driver 9 to the cathode electrode 3.
[0011]
In the FED having such a configuration, in the emitter 1 positioned at the intersection of the extraction electrode 5 to which a DC voltage of, for example, 100 V is applied and the cathode electrode 3 to which a voltage of, for example, 0 V is selectively applied according to the image signal. Then, field emission occurs, and electrons are emitted toward the anode electrode 2. The electrons emitted from the emitter 1 collide with the phosphor applied to the anode electrode 2 to cause the phosphor to emit light. A desired image is displayed by the emission of the phosphor. Note that the time during which the phosphor emits light by one-time electron emission from the emitter 1 is, for example, about several tens of microseconds.
[0012]
Field emission type electron-emitting devices are considered to be particularly suitable for use in display devices having the above-described structure. However, the field of use of electron-emitting devices is not limited to display devices. For example, use of the electron-emitting device as an information recording device (memory device) has been proposed.
[0013]
An information recording element using this electron-emitting device has a configuration in which a large number of bits are formed by arranging a large number of combinations of emitters and holding means for holding electrons emitted from the emitters, for example. . In such an information recording element, it is possible to hold a 1/0 or high / low state in each bit depending on whether or not electrons are held in the holding means of each bit. Information can be recorded on the basis. That is, in this information recording element, instead of the phosphor in the above-described FED, a holding means for holding electrons emitted from the emitter is provided, and information is recorded by holding the electrons in the holding means. Recording element. Thus, it is considered that the electron-emitting device can be suitably applied to an information recording device.
[0014]
[Problems to be solved by the invention]
By the way, the above-mentioned FED has a physical characteristic that the emission efficiency is high because the emitter has a high electron emission effect on the applied voltage. For this reason, the FED is expected to perform self-luminous display with high luminance. Further, the FED is required to have high luminance stability as well as high luminance. Here, the state where the luminance stability is high is that sufficient luminance necessary for the image to be displayed is maintained in a constant state. In order to ensure the luminance stability of such an FED, it is necessary that electrons are stably emitted from the emitter. Further, in order to stably emit electrons from the emitter, it is necessary that the current supplied to the emitter is stable.
[0015]
Therefore, in the conventional FED, in order to stabilize the current supplied to the emitter, for example, an electric resistor of about 1 MΩ is connected to the cathode electrode, current control by the resistor is performed, and the current flowing through the cathode electrode itself is controlled. A method that aims to stabilize is adopted. However, in the method using this resistor, current is supplied to the emitter 1 through a high resistance of about 1 MΩ, and it is difficult to avoid voltage drop and power loss due to this resistance. There is a problem in that it is necessary to apply a voltage, and a required amount of current increases, resulting in an increase in power consumption.
[0016]
On the other hand, in the conventional FED, besides the method using a resistor, a method for stabilizing the current supplied to the emitter using the rectifying action of a MOS (Metal Oxide Semiconductor) transistor has been proposed. In this method, for example, a MOS transistor is connected between a cathode electrode and a data driver that applies a signal voltage to the cathode electrode. The source of the MOS transistor is connected to the data driver, the drain is connected to the cathode electrode, and the gate is always turned on. Then, a signal is input from the data driver to the source side of the MOS transistor, and a signal from the scan driver is input to the extraction electrode, so that a current flows to the cathode electrode connected to the drain side, and an electron is transmitted from the emitter. Release is made. At this time, the current flowing to the drain side of the MOS transistor is controlled by a preset gate voltage at the gate which is always on.
[0017]
Such a method using a MOS transistor does not require the use of a resistor, and therefore has an advantage that the increase in power consumption is smaller than that in the case of using a resistor. However, this method of using a MOS transistor has a problem that a high voltage (for example, 50 V) for generating a strong electric field from the data driver to the emitter must be applied, which increases the burden on the data driver. . In addition, the method of using the MOS transistor has a problem that the supply current to the emitter is not completely stabilized, and the supply current is reduced.
[0018]
As a method of not applying a high voltage, a large number of Spindt-type emitters having a small Taylor cone with a radius of curvature of 0.05 μm or less are arranged in correspondence with one pixel in correspondence with small holes of 0.1 μm. There is a way to do it. This method has the advantage that the voltage required for electron emission is relatively low because the emitter is very small, but the problem that the manufacturing process becomes difficult and the stability of operation become difficult. There is a problem of becoming.
[0019]
Next, with reference to the drawings, the problem of a decrease in supply current to the emitter in the conventional FED will be described in more detail.
[0020]
FIG. 12 is a diagram schematically showing the structure of an electron emission portion in a conventional FED. The FED shown in this figure is prepared as an experimental sample in order to consider the problem of a decrease in supply current to the emitter. In this FED, a comb-shaped emitter 1 and an extraction electrode (or anode electrode) 2 are arranged to face each other with a gap. The extraction electrode 2 is connected to the output terminal on the high voltage side of the scanning drive circuit 3. The other end of the scanning drive circuit 3 is grounded. The scanning drive circuit 3 is for applying a rectangular wave extraction voltage Vex (= 0 to 250 V) as shown in FIG. 13A to the extraction electrode 2 side, and uses a variable voltage power supply.
[0021]
In this FED, when the potential of the emitter 1 is in a floating state and the extraction voltage Vex = 250 V is applied to the extraction electrode 2, the potential difference between the emitter 1 and the extraction electrode 2 is the so-called electron emission effect during pixel selection. It is comprised so that it may become a potential difference which produces. Further, in the FED, when the extraction voltage Vex = 0 V is applied to the extraction electrode 2, the potential difference between the emitter 1 and the extraction electrode 2 becomes a potential difference that is less than the so-called electron emission threshold value when no pixel is selected. It is configured as follows. In this FED, a voltmeter 4 is connected to the emitter 1 in order to observe the potential Vc of the emitter 1.
[0022]
When an FED of an experimental sample schematically representing such a conventional FED structure is driven with a pulsed applied voltage waveform having a period of 0.1 second as shown in FIG. 13A, the potential Vc of the emitter 1 is driven. As shown in FIG. 13 (B), the result fluctuated greatly. That is, the potential Vc of the emitter 1 rises rapidly to about 10 V at the moment when the pixel (emitter 1) is in a selected state (in other words, the moment when the extraction voltage Vex rises to 250 V). As a result, the voltage dropped to about 1V. Such a decrease in the potential Vc of the emitter 1 causes a decrease in the current supplied to the emitter 1 and decreases the amount of emitted electrons.
[0023]
FIG. 14 is a diagram schematically showing the structure of the FED using the rectifying MOS transistor described above with respect to the FED shown in FIG. Similar to the FED shown in FIG. 12, the FED shown in the figure is prepared as an experimental sample in order to consider the problem of a decrease in supply current to the emitter 1. In this FED, the source side of the MOS transistor 5 is set to the ground potential when a pixel is selected, the drain is connected to the emitter 1, and the gate is always on. In this FED, for example, a signal input from a data driver (not shown) is input to the source side of the MOS transistor 5 and a signal from the scanning drive circuit 3 is input to the extraction electrode, whereby the emitter 1 connected to the drain side. Current can be supplied to the emitter 1 and electrons can be emitted from the emitter 1. In the FED, the current flowing to the drain side of the MOS transistor 5 can be controlled by a preset gate voltage at the gate that is always on. The basic characteristics of the MOS transistor 5 are as shown in FIG. In this FED, it is assumed that the current (that is, the maximum emission current) when the potential difference of 250 V is applied with the emitter 1 directly grounded is 20 μA as shown in FIG.
[0024]
When the FED using the MOS transistor 5 is driven with a pulsed applied voltage waveform having a period of 0.1 second as shown in FIG. 15A, the potential Vc (= drain voltage Vd) of the emitter 1 is Similar to the case shown in FIG. 13, the result showed a large fluctuation as shown in FIG. Moreover, at this time, although the MOS transistor 5 is used to obtain the rectifying effect, the emitter current (= drain current Id) flowing through the emitter 1 suddenly and significantly decreases as the potential Vc of the emitter 1 changes. . That is, in this FED, as shown in FIG. 15C, the emitter current was initially about 1 μA at which sufficient electron emission was possible, but the time t = As a result, after 20 ms, the electron emission decreased to 0.3 μA, which is a substantially insufficient current amount.
[0025]
Such a decrease in the emitter current is considered as follows with reference to the drain current-drain voltage characteristics (Id-Vd characteristics) of the MOS transistor 5 shown in FIG. As shown in FIG. 6A, since the drain voltage Vd = 10 V at the first time (t = 0), 1 μA in the saturation region and a sufficient drain current Id flow to the emitter 1 correspondingly. . On the other hand, when the time t = 20 ms elapses, the voltage drops to the drain voltage Vd = 1 V as described above. Therefore, the emitter 1 corresponds to the drain voltage Vd = 1 V in FIG. As shown in B), only the drain current Id = 0.3 μA in the non-saturated region according to the Id-Vd characteristic of the MOS transistor 5 flows.
[0026]
Thus, although it is considered that it is effective to stabilize the current supplied to the emitter 1 by its rectification by using the MOS transistor 5 as described above, in the conventional FED, as a result, There is a problem that the current supplied to the emitter 1 is reduced due to a sudden change in the potential Vc of the emitter 1 and the amount of emitted electrons is reduced. Furthermore, there is a problem that this decrease in the amount of emitted electrons leads to a decrease in light emission luminance in image display.
[0027]
In order to solve the problem that the current cannot be stabilized even if such a MOS transistor 5 is used, for example, as shown in FIG. 17, the rising characteristic in the non-saturation region is very steep and is saturated at a low voltage. It can be considered that the countermeasure of using a MOS transistor having an Id-Vd characteristic of 0.1V in the figure is effective. That is, if such a MOS transistor can be used, even if the emitter voltage Vc, that is, the drain voltage Vd of the MOS transistor fluctuates (decreases) from 10 V to 0.1 V, the current amount Id is always optimal for electron emission. It is thought that it can be kept at a small value (for example, 1 μA).
[0028]
However, in practice, realizing a MOS transistor having an Id-Vd characteristic that rises very steeply in a narrow region of a low voltage of 0 to 0.1 V as shown in FIG. 17 is a great departure from current LSI technology. Therefore, its realization is extremely difficult or impossible. Therefore, it is practically impossible to stabilize the current Id by using a MOS transistor having an Id-Vd characteristic as shown in FIG.
[0029]
Alternatively, if a MOS transistor having an Id-Vd characteristic capable of flowing a drain current Id = 1 μA at least when the potential Vc = 1 V of the emitter 1 is used, it is necessary even at least after the time t = 20 ms. It is considered that the amount of current can be obtained. However, also in this case, the current Id flowing through the emitter 1 varies greatly depending on the potential Vd, so that the current Id cannot be stabilized.
[0030]
Further, as the MOS transistor, for example, a MOS transistor having such a characteristic that the Id-Vd characteristic rises from a reverse voltage region such as −5 V and is already in a saturation region at Vd = 0 V may be used. However, directly connecting such a MOS transistor that allows application of a reverse voltage to a delicate emitter 1 that is brittle and susceptible to electrostatic disturbances and electrical shocks is provided with this emitter 1. When the apparatus is actually used, it causes an electrostatic breakdown of the emitter 1 and is not preferable.
[0031]
The decrease in the supply current to the emitter as described above leads to a decrease in light emission luminance in image display in the FED. Further, such a decrease in the supply current to the emitter becomes a problem even in an information recording element using the above-described electron-emitting device, for example. That is, in the information recording element, as in the case of the FED, there is a problem that an information recording operation failure occurs due to a large fluctuation of the emitter current caused by the fluctuation of the emitter voltage.
[0032]
The present invention has been made in view of such problems, and a first object of the present invention is to provide a field emission electron capable of stably supplying a current required for electron emission to an electron-emitting device. It is to provide a discharge device.
[0033]
A second object of the present invention is to provide a field emission display device capable of sufficiently and stably obtaining light emission luminance required for image display.
[0034]
[Means for Solving the Problems]
The field emission electron emission device according to the present invention has a structure in which an electron corresponding to an amount of current supplied corresponds to an electric field generated by a potential difference between a fixed voltage application electrode to which a fixed voltage is applied and a fixed voltage application electrode. A plurality of electron-emitting devices that perform emission are electrically connected to one or two or more electron-emitting devices via a drain, and a voltage applied to the gate is changed, so that a current supply amount to the electron-emitting devices can be reduced. It is possible to perform control, and a sufficient current value required for emitting electrons from a plurality of electron-emitting devices is in a non-saturated region defined by the drain current-drain voltage characteristics. And a semiconductor element.
[0035]
In addition, the field emission display device according to the present invention includes an electron corresponding to the amount of current supplied corresponding to an electric field generated by a potential difference between a fixed voltage application electrode to which a fixed voltage is applied and the fixed voltage application electrode. A plurality of electron-emitting devices that emit electrons, and one or two or more electron-emitting devices that are electrically connected to the electron-emitting devices via a drain, and a plurality of electron-emitting devices by changing a voltage applied to the gate. The amount of current supplied to the device can be controlled, and a sufficient current value required for emitting electrons from the plurality of electron-emitting devices is determined by the drain current-drain voltage characteristics. The semiconductor device has a saturation region and a light emitting means for emitting light in response to collision of electrons emitted from the electron emitting device.
[0036]
In the field emission electron emission apparatus according to the present invention, a fixed voltage is applied to a plurality of electron-emitting devices by a fixed voltage application electrode, and one or more electron-emitting devices are electrically connected via a drain. By changing the voltage applied to the gate, it is possible to control the amount of current supplied to the plurality of electron-emitting devices, and it is sufficient to emit electrons from the plurality of electron-emitting devices. A semiconductor element whose current value is in the non-saturated region defined by the drain current-drain voltage characteristic is supplied with a current for emitting electrons to a plurality of electron-emitting devices as necessary. The
[0037]
In the field emission display device according to the present invention, a fixed voltage is applied to the plurality of electron-emitting devices by the fixed voltage application electrode, and one or two or more electron-emitting devices are electrically connected via the drain. By changing the voltage applied to the gate, it is possible to control the amount of current supplied to the electron-emitting device, and it is sufficient to emit electrons from a plurality of electron-emitting devices. A semiconductor element whose current value is in a non-saturated region defined by the drain current-drain voltage characteristic is supplied with a current for emitting electrons as necessary to a plurality of electron-emitting devices, Electrons are emitted from the electron-emitting device supplied with current toward the light emitting means.
[0038]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0039]
[First Embodiment]
FIG. 1 is a block diagram schematically showing the configuration of the main part of the field emission electron emission device according to the first embodiment of the present invention. FIG. 2 is another configuration diagram schematically showing the configuration of the main part of the field emission electron emission device according to the present embodiment. In these figures, as the type of emitter structure, the outer shape is formed in a cup-like structure, and an electric field is concentrated on the peripheral edge (ridgeline) portion to emit electrons from the peripheral portion. A so-called cup type structure is shown as an example. However, as the type of emitter structure, in addition to the cup type, an emitter having a conical shape called a Spindt type has been proposed. It is also possible to use this Spindt-type emitter for the field emission electron emission device according to the present embodiment. However, in the following, for simplicity of explanation, the cup type will be described as a representative example of the emitter structure.
[0040]
The field emission type electron emission device includes a cathode electrode 100 on which a large number of cup-type emitters 101 are formed and a lead electrode 103 disposed so as to face the cathode electrode 100. The extraction electrode 103 is disposed to face the emitter 101 with a predetermined gap. In the emitter 101, a predetermined number of collections constitute one structural unit, and electrons are emitted for each structural unit. In FIG. 2, a portion indicated by reference numeral 102 corresponds to one constituent unit of the emitter 101. The field emission electron emission device generally has a configuration in which a large number of constituent units of the emitter 101 are arranged in a matrix. Note that one structural unit here is a structural unit corresponding to one pixel, for example, when this field emission type electron-emitting device is applied to an FED. The predetermined number here is, for example, the number of emitters 101 corresponding to one pixel when this field emission type electron-emitting device is applied to an FED, for example, 1000. In FIG. 2, the extraction electrode 103 is not shown for the sake of simplicity.
[0041]
Here, the emitter 101 corresponds to a specific example of “electron-emitting device” in the invention. The extraction electrode 103 corresponds to a specific example of “fixed voltage application electrode” in the present invention.
[0042]
The field emission electron emission device is further connected to a plurality of NMOS transistors 200 electrically connected to the cathode electrode 100 for each constituent unit of the emitter 101 and to the gate 202 of the NMOS transistor 200. A gate driving circuit 300 and a fixed voltage power source 400 connected to the extraction electrode 103 are provided. The source 204 of the NMOS transistor 200 is grounded. The drain 201 of the NMOS transistor 200 is connected to the cathode electrode 100. Note that the NMOS transistor 200 may be arranged for each emitter 101 instead of for each constituent unit of the emitter 101.
[0043]
Here, the NMOS transistor 200 corresponds to a specific example of “semiconductor element” in the present invention.
[0044]
The emitter 101 is made of, for example, a material such as carbon, and in response to an electric field generated by a potential difference between the emitter 101 and the extraction electrode 103, electrons are emitted according to the supplied current amount by a tunnel effect. It has become. For example, the emitter 101 emits sufficient electrons when a current of 1 μA flows. Here, in the present embodiment, a strong electric field that always allows electrons to be emitted from the extraction electrode 103 to all the emitters 101 is applied. In order to apply this strong electric field to the emitter 101, a fixed voltage of, for example, 250 V is supplied to the extraction electrode 103 from the fixed voltage power source 400 as the extraction voltage Vex in advance.
[0045]
The gate drive circuit 300 controls the gate voltage Vg applied to the gate 202 of the NMOS transistor 200. The gate driving circuit 300 applies a voltage of, for example, 5 V as the gate voltage Vg to the gate 202 of the NMOS transistor 200 when the emitter 101 emits electrons. Further, the gate driving circuit 300 applies a voltage of, for example, 0 V as the gate voltage Vg to the gate 202 of the NMOS transistor 200 when the emitter 101 does not emit electrons. .
[0046]
FIG. 3 is an explanatory diagram showing drain current-drain voltage characteristics (Id-Vd characteristics) of the NMOS transistor 200. In the example shown in the figure, the current (that is, the maximum emission current) when the emitter 101 is directly grounded and a potential difference of 250 V is applied is assumed to be 20 μA. Further, in the figure, the curve indicated by the symbol G0 is a curve indicating the Id-Vd characteristic of the NMOS transistor 200.
[0047]
The NMOS transistor 200 can control the amount of current supplied to the emitter 101 by changing the gate voltage Vg applied to the gate 202. In the example of the figure, the operating voltage of the NMOS transistor 200 is 5V. In the NMOS transistor 200, in the example shown in the figure, the region where the drain voltage Vd is 0 to 4 V is a non-saturated region defined by the Id-Vd characteristics, and the region exceeding 4 V is a saturated region. The drain current Id in the saturation region of the NMOS transistor 200 is 10 μA.
[0048]
As shown in FIG. 4A, the NMOS transistor 200 is turned off when a signal of 0 V is inputted as the gate voltage Vg from the gate driving circuit 300 to the gate 202, and the source side to the drain side are turned on. The drain current Id flowing through the current becomes zero. Further, as shown in FIG. 5B, the NMOS transistor 200 is turned on when, for example, a signal of 5V is inputted as the gate voltage Vg from the gate driving circuit 300 to the gate 202, and from the source side. A constant drain current Id flows on the drain side. Here, in this embodiment, the emitter 101 emits sufficient electrons when a current of 1 μA flows, but the NMOS transistor 200 obtains a drain current Id of 1 μA. The region to be generated exists in the non-saturated region. In other words, in the present embodiment, the drain voltage Vd and the drain current Id are controlled based on the gate voltage Vg applied to the gate 202 within the non-saturation region defined by the Id-Vd characteristics of the NMOS transistor 200. It is like that. Note that FIG. 3 corresponds to the timing chart shown in FIG. 4 described later, and a signal of 0 V is input as the gate voltage Vg at time t = −1 second ((A) in FIG. 3). In this example, a signal of 5 V is input as the gate voltage Vg at the time t = 0 second ((B) in the figure).
[0049]
Next, the operation of the field emission electron emission device having the above configuration will be described.
[0050]
FIG. 4 is a timing chart showing various drive waveforms for driving the field emission electron emission device according to the present embodiment. In the figure, as an example of the operation, a case where a pulsed applied voltage waveform having a wave height of 5 V is applied from the gate driving circuit 300 to the gate 202 of the NMOS transistor 200 at a cycle of 0.1 second is shown. Yes. In this field emission type electron emission device, as shown in the timing chart of the figure, in order to give the extraction electrode 103 a strong electric field that can emit electrons to the emitter 101, a fixed voltage of 250V is always applied. Is applied as the extraction voltage Vex (FIG. 4A). At this time, the potential Vc on the emitter 101 side is always 0.1 V corresponding to the potential on the extraction electrode 103 side being a fixed voltage (FIG. 4B).
[0051]
Here, when the state of the gate voltage Vg applied from the gate driving circuit 300 to the gate 202 of the NMOS transistor 200 is low level (0 V), the gate 202 of the NMOS transistor 200 is turned off (see FIG. 4 (C) OFF), the drain current Id becomes zero (FIG. 4D, FIG. 3A). Accordingly, at this time, the current flowing through the emitter 101 connected to the drain 201 of the NMOS transistor 200 is zero, and no electrons are emitted from the emitter 101.
[0052]
On the other hand, when the state of the gate voltage Vg applied from the gate drive circuit 300 to the gate 202 of the NMOS transistor 200 is at a high level (5 V), the gate 202 of the NMOS transistor 200 is turned on (FIG. 4 (C) ON). At this time, the drain voltage Vd is maintained at a value of Vd = Vc = 0.1 V, and corresponds to the Id-Vd characteristic of the NMOS transistor 200 corresponding to the drain voltage Vd of 0.1 V. 1 μA flows as the drain current Id (FIGS. 4D and 3B). Accordingly, at this time, the current flowing through the emitter 101 connected to the drain 201 of the NMOS transistor 200 is 1 μA, and electrons are emitted from the emitter 101. Here, in this embodiment, as shown in the figure, the potential Vc (= drain voltage Vd) on the emitter 101 side is always 0.1% corresponding to the potential on the extraction electrode 103 side being a fixed voltage. Since V is V, a drain current Id of 1 μA required for electron emission is stably supplied while electrons are being emitted, and electron emission from the emitter 101 is stably performed. .
[0053]
In the field emission electron emission device of this embodiment, if the current flowing through the emitter 101 is 1 μA, electrons can be emitted from the emitter 101 satisfactorily. It is also possible to pass different currents. For example, by adjusting the extraction voltage Vex applied to the extraction electrode 103 to a voltage value different from the fixed voltage of 250 V described above and adjusting the potential Vc of the emitter 101, that is, the drain voltage Vd, the drain voltage Vd can be handled. A drain current Id, that is, a desired current flowing through the emitter 101 can be obtained.
[0054]
For example, by setting the lead-out voltage Vex to a voltage higher than 250V and setting the voltage Vc = Vd to a voltage value V1 satisfying 0.1 <V1 <4, the voltage value Vd = V1 corresponds to FIG. A drain current Id = I1 μA (1 <I1 <10) in the non-saturation region according to the Id-Vd characteristic as shown in B) can be obtained. Needless to say, the current flowing through the emitter 101 can be controlled to a current lower than 1 μA.
[0055]
[Comparative example]
Next, a comparative example for the field emission electron emission device according to the present embodiment will be described with reference to FIGS.
[0056]
FIG. 18 is a diagram schematically showing the structure of an electron emission portion in a field emission electron emission device as a comparative example. The apparatus of the comparative example shown in this figure is prepared as an experimental sample in order to compare operating characteristics with the field emission electron emission apparatus according to the present embodiment. The device of this comparative example is provided with a cathode electrode 3 on which a large number of cup-type emitters 1 are formed and a lead electrode 2 disposed opposite to the cathode electrode 3. The extraction electrode 2 is disposed opposite to the emitter 1 with a predetermined gap.
[0057]
The device of this comparative example is further connected to the NMOS transistor 5 electrically connected to the cathode electrode 3, a signal drive circuit (not shown) connected to the gate of the NMOS transistor 5, and the extraction electrode 2. And a scanning drive circuit (not shown). The source of the NMOS transistor 5 is grounded. The drain of the NMOS transistor 5 is connected to the cathode electrode 3 via an ammeter 20 for measuring the drain current Id. A voltmeter 4 for measuring the voltage of the cathode electrode 3, that is, the voltage Vc of the emitter 1, is connected to the cathode electrode 3. From a scanning drive circuit (not shown) connected to the extraction electrode 2, a rectangular waveform extraction voltage Vex (= 0 to 250V) as shown in FIG. 19A is applied to the extraction electrode 2 side. .
[0058]
In the device of this comparative example, the gate of the NMOS transistor 5 is always on. Further, in the device of this comparative example, when the potential of the emitter 1 is in a floating state and a voltage of 250 V is applied to the extraction electrode 2 as the extraction voltage Vex, the potential difference between the emitter 1 and the extraction electrode 2 is 1 is a potential difference that causes an electron emission effect. Further, in the device of this comparative example, when a voltage of 0 V is applied to the extraction electrode 2 as the extraction voltage Vex, the potential difference between the emitter 1 and the extraction electrode 2 is less than the electron emission threshold value. It is configured.
[0059]
Thus, in the apparatus of this comparative example, whether to emit electrons from the emitter 1 is switched by switching whether to apply a high voltage of 250 V to the extraction electrode 2. On the other hand, in the field emission electron emission device according to the present embodiment shown in FIG. 1, whether a high voltage of 250 V is always applied to the extraction electrode 103 to cause the emitter 101 to emit electrons. This selection is performed by switching the on / off state of the gate of the NMOS transistor 200.
[0060]
Next, the operation characteristics of the comparative apparatus having such a configuration will be described.
[0061]
FIG. 19 is a timing chart showing various drive waveforms for driving the device of this comparative example. When the device of this comparative example is driven by the extraction electrode 2 with a pulsed extraction voltage Vex having a period of 0.1 second as shown in FIG. 19A, the potential Vc of the emitter 1 (= drain voltage Vd). As a result, as shown in FIG. In addition, at this time, the emitter current (= drain current Id) flowing through the emitter 1 suddenly and significantly decreases as the potential Vc of the emitter 1 changes. That is, in the device of this comparative example, as shown in FIG. 19C, the emitter current was initially about 1 μA at which sufficient electron emission was possible, but in response to the change in the potential Vc, As a result, after the elapse of time t = 20 ms, the electron emission decreased to 0.1 μA, which is a substantially insufficient current amount.
[0062]
Next, such a decrease in the emitter current will be considered with reference to the drain current-drain voltage characteristics (Id-Vd characteristics) of the MOS transistor 5 shown in FIG. In the example shown in the figure, the current (that is, the maximum emission current) when the emitter 1 is directly grounded and a potential difference of 250 V is applied is assumed to be 20 μA. Further, in the example of the figure, the NMOS transistor 5 has a non-saturated region defined by the Id-Vd characteristics in a region where the drain voltage Vd is 0 to 1 V, and a region exceeding 1 V is a saturated region. The drain current Id in the saturation region of the NMOS transistor 5 is 1 μA.
[0063]
In the device of this comparative example, as shown in FIG. 5A, the drain voltage Vd is 1 V at the time of the first (t = 0), so that a sufficient drain of 1 μA in the saturation region is corresponding to this. A current Id flows through the emitter 1. On the other hand, when the time t = 20 ms elapses, the drain voltage Vd drops to 0.1 V. Therefore, the emitter 1 corresponds to the drain voltage Vd of 0.1 V as shown in FIG. As described above, only a drain current Id of about 0.1 μA in the non-saturation region according to the Id-Vd characteristic of the MOS transistor 5 flows.
[0064]
As described above, in the device of this comparative example, the current flowing through the emitter 1 rapidly decreases, and the amount of current that can be accurately (reliably) operated as a field emission type electron-emitting device (here, this embodiment) It was confirmed that 1 μA) could not be obtained as with the emitter 101 in the configuration.
[0065]
As described above, according to the present embodiment, the extraction voltage Vex applied to the extraction electrode 103 is set to a fixed voltage that does not change with time, and whether or not to emit electrons from the emitter 101 is selected. By switching the on / off state of the gate 202 of the NMOS transistor 200, the amount of current supplied to the emitter 101 is controlled and switched, so that the emission of electrons from the emitter 1 is performed as in the comparative example shown in FIG. The drive voltage for causing electron emission can be reduced as compared with the case where selection of whether or not to perform is performed by switching whether or not a high voltage is applied to the extraction electrode 2. In addition, since whether or not to emit electrons from the emitter 101 is selected by switching the ON / OFF state of the gate 202 of the NMOS transistor 200, the electron emission operation is performed as in the comparative example shown in FIG. Accordingly, the potential Vc of the emitter 101 does not fluctuate greatly and can be maintained in a substantially constant state, and is required for emitting electrons to the emitter 101 using the rectifying action of the NMOS transistor 200. Current can be stably supplied. Thus, according to the present embodiment, the amount of current supplied to the emitter 101 can be kept stable, so that the electron emission amount of the emitter 101 can be stabilized in time. Therefore, when the field emission electron emission device according to the present embodiment is applied to, for example, an FED, it is possible to sufficiently and stably obtain light emission luminance required for image display.
[0066]
Further, according to the present embodiment, as the NMOS transistor 200, a sufficient current value (for example, 1 μA) required for emitting electrons from the emitter 101 is defined by the drain current-drain voltage characteristics. Since the characteristics in the non-saturation region are used, the rise characteristic in the non-saturation region as shown in FIG. 17 is very steep and has an Id-Vd characteristic that saturates at a low voltage. In practice, it is possible to keep the amount of current supplied to the emitter 101 stable by suitably using an existing semiconductor element having general electrical characteristics without using a semiconductor element having characteristics that cannot be realized.
[0067]
Furthermore, according to the present embodiment, since the NMOS transistor 200 is used in the non-saturated region, the Id-Vd characteristic in the non-saturated region, which has been a factor that destabilizes the current amount in the conventional technique, is obtained. It is possible to adjust the current amount of the drain current Id supplied to the emitter 101 to a desired current amount by actively utilizing it. For example, by adjusting the extraction voltage Vex applied to the extraction electrode 103 to a voltage value different from the above-described fixed voltage of 250 V and adjusting the potential Vc (= drain voltage Vd) of the emitter 101, the drain voltage Vd can be handled. The drain current Id, that is, the current flowing through the emitter 101 can be changed.
[0068]
[Second Embodiment]
Next, a second embodiment of the present invention will be described. In the following description, the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted as appropriate.
[0069]
In the first embodiment, as described with reference to FIG. 3, a current (maximum emission) in a state where the extraction voltage Vex of 250 V is applied to the extraction electrode 103 and the emitter 101 is directly grounded. Current) is set to 20 μA, and the NMOS transistor 200 having a characteristic that the drain current Id in the saturation region is 10 μA lower than the maximum emission current (= 20 μA) is used. Instead of the NMOS transistor 200 having such characteristics, a transistor having a characteristic that the drain current Id in the saturation region is larger than the maximum emission current is used.
[0070]
FIG. 5 is a characteristic diagram showing Id-Vd characteristics of the NMOS transistor in the field emission electron emission device according to the present embodiment. In the figure, the curve indicated by reference sign G0 'is a curve showing the Id-Vd characteristics of the NMOS transistor in this embodiment. In the NMOS transistor of the present embodiment shown in the figure, the drain current Id in the saturation region is 100 μA which is higher than the maximum emission current (20 μA in the example in the figure). In the present embodiment, the value of the drain current Id in the saturation region may be a value that exceeds the maximum emission current of the emitter 101, and is not limited to a value of 100 μA. Similar to the NMOS transistor 200 having the characteristics shown in FIG. 3, the NMOS transistor can control the amount of current supplied to the emitter 101 by changing the gate voltage Vg applied to the gate. . In the example of the figure, the operating voltage of the NMOS transistor is 5V. Further, in this example of the NMOS transistor, the region where the drain voltage Vd is 0 to 4 V is a non-saturated region defined by the Id-Vd characteristic, and the region exceeding 4 V is a saturated region.
[0071]
The NMOS transistor having the characteristics shown in FIG. 5 is similar to the NMOS transistor 200 having the characteristics shown in FIG. 3 when, for example, a signal of 0V is input to the gate from the gate driving circuit 300 as the gate voltage Vg. In the off state, the drain current Id flowing from the source side to the drain side becomes zero ((A) in the figure). Further, as shown in FIG. 5B, the NMOS transistor is turned on when, for example, a signal of 5 V is inputted as the gate voltage Vg from the gate driving circuit 300 to the gate, and the drain is turned on from the source side. A drain current Id having a constant value flows on the side. FIG. 5 is a diagram corresponding to the timing chart shown in FIG. 4. At time t = −1 second, a signal of 0 V is input as the gate voltage Vg (FIG. 5A). In this example, a signal of 5V is input as the gate voltage Vg at t = 0 seconds ((B) in the figure).
[0072]
By using the NMOS transistor having such characteristics, the maximum emission current of the emitter 101 becomes smaller than the drain current Id in the saturation region, so that the emitter 101 does not change no matter how the drain voltage Vd changes. The drain current Id flowing through the current is always in the non-saturated region. That is, in this embodiment, even if the drain voltage Vd is changed, the drain current Id is always controlled in the non-saturation region by the NMOS transistor.
[0073]
Note that other configurations, operations, and effects in the present embodiment are the same as those in the first embodiment.
[0074]
[Third Embodiment]
Next, a third embodiment of the present invention will be described. In the following description, the same components as those in the first and second embodiments are denoted by the same reference numerals, and description thereof is omitted as appropriate.
[0075]
In the first embodiment and the second embodiment, as shown in FIGS. 3 and 5, the NMOS transistor having the characteristic of the maximum operating voltage of 5V is driven with the same voltage as the maximum operating voltage. However, in this embodiment, an NMOS transistor having a maximum operating voltage higher than that of the NMOS transistor shown in FIGS. 3 and 5 is driven at a voltage lower than the maximum operating voltage. It is.
[0076]
FIG. 6 is a characteristic diagram showing Id-Vd characteristics of an NMOS transistor in the field emission electron emission device according to the present embodiment. In the example shown in the figure, the current (maximum emission current) when the emitter 101 is directly grounded and a potential difference of 250 V is applied is assumed to be 20 μA. The NMOS transistor in the present embodiment shown in the figure has a maximum operating voltage of 50V. When this NMOS transistor is operated at a gate voltage Vg of 50 V, which is the maximum operating voltage, the value of the drain current Id in the saturation region is 1 mA. Even when such an NMOS transistor is driven at an operating voltage lower than the maximum operating voltage, the drain voltage Vd is 0.1 V, for example, as in the NMOS transistor having the characteristics shown in FIGS. Sometimes, a drain current Id of 1 μA sufficient to cause the emitter 101 to emit electrons can be supplied. In the example of FIG. 6, when the gate voltage Vg is 5 V, the drain current Id of 1 μA flows corresponding to the drain voltage Vd of 0.1 V.
[0077]
Further, in the NMOS transistor according to the present embodiment, by changing the gate voltage Vg within the range of 0 <Vg ≦ 50V, various changes based on the Id-Vd characteristic curve corresponding to the change of the gate voltage Vg. It is also possible to obtain a drain current Id having a current value. For example, when a gate voltage Vg of 50 V is applied and the drain voltage Vd is 0.1 V and a drain current Id of I2 μA is obtained, the gate voltage Vg is changed within the range of 0 <Vg ≦ 50V. Correspondingly, a drain current Id in the range of 1 <Id ≦ I2 can be obtained. Thus, by changing the gate voltage Vg, various drain currents Id can be obtained, and the amount of electrons emitted from the emitter 101 can be controlled in accordance with this current.
[0078]
As described above, according to the present embodiment, since the NMOS transistor having a high operating voltage is driven at the maximum operating voltage or a voltage lower than the maximum operating voltage, the gate voltage Vg is changed and the drain is correspondingly changed. The amount of electron emission from the emitter 101 can be changed by changing the current Id. As a result, for example, when the field emission electron emission device according to this embodiment is used for an FED, the light emission amount, that is, the light emission luminance of the pixel is changed (controlled) in accordance with the change in the electron emission amount. It is also possible. Therefore, it is possible to control the gradation by suitably using such an action.
[0079]
Other configurations, operations, and effects in the present embodiment are the same as those in the first and second embodiments.
[0080]
[Fourth Embodiment]
Next, a fourth embodiment of the present invention will be described. In the following description, the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted as appropriate.
[0081]
FIG. 7 is a configuration diagram showing a configuration of a main part of an FED as a field emission type electron emission device according to the fourth embodiment of the present invention. FIG. 8 is a cross-sectional view showing the configuration of the main part of the FED according to the present embodiment. The FED according to this embodiment uses a field emission type electron-emitting device as described in each of the above embodiments as a display device. In this FED, one screen is constituted by a collection of a plurality of pixels arranged in a matrix array. In the FED, a plurality of emitters 101 are arranged in a matrix corresponding to a plurality of pixels. In FIG. 7, the plurality of emitters 101 in the portion indicated by reference numeral 700 correspond to the emitter 101 for one pixel. Although not shown, each component of the FED is housed in a flat tube made of, for example, glass, and the inside is kept in a vacuum.
[0082]
This FED is electrically connected to the cathode electrode 100 having a large number of emitters 101 arranged on the surface thereof, an extraction electrode 103 (FIG. 8) arranged to face the cathode electrode 100, and the cathode electrode 100 for each pixel. And a plurality of NMOS transistors 200 connected to each other. The configurations of the emitter 101, the cathode electrode 100, the extraction electrode 103, and the NMOS transistor 200 are the same as those shown in FIG. The sources 204 of the NMOS transistors 200 are connected together by the same signal wiring 701 for each column. The gates 202 of the NMOS transistors 200 are connected together by the same scanning wiring 709 for each row.
[0083]
The FED further includes an anode electrode 104 disposed to face the cathode electrode 100 as shown in FIG. A phosphor layer 800 is formed on the upper or lower surface (upper surface in the example of FIG. 8) of the anode electrode 104 by applying the phosphor. If the phosphor layer 800 is for monochrome image display, the entire phosphor layer 800 is formed of a white light-emitting phosphor. Further, if the phosphor layer 800 is for color image display, phosphor stripes for R, G, and B color emission are arranged for each pixel. A fixed voltage for generating a strong electric field that causes the emitter 101 to emit a field together with the extraction electrode 103 is always applied to the anode electrode 104.
[0084]
Here, the phosphor layer 800 corresponds to a specific example of “light emitting means” in the present invention. In the present embodiment, the anode electrode 104 and the extraction electrode 103 correspond to a specific example of “fixed voltage application electrode” in the present invention.
[0085]
The FED further includes a plurality of NMOS transistors 702 having drains 703 connected to the source 204 of the NMOS transistor 200 for each column by a signal wiring 701, and a positive electrode side (positive potential side) grounded and a negative electrode A negative voltage side output terminal is connected to the source 704 of the NMOS transistor 702, a signal drive circuit 707 connected to the gate 706 of the NMOS transistor 702, and the scanning wiring 709. And a scan driving circuit 708 to which the gate 202 of each NMOS transistor 200 is connected. Note that the NMOS transistor 702 is arranged for each column.
[0086]
Here, the NMOS transistor 702 and the signal driving circuit 707 correspond to a specific example of “current control means” in the present invention. The NMOS transistor 702 corresponds to a specific example of “a semiconductor element for current control” in the present invention.
[0087]
The NMOS transistor 702 is provided for current control in order to absorb the difference in electrical characteristics of the plurality of NMOS transistors 200 and control the value of the current flowing through the drain 201 of the NMOS transistor 200 to a predetermined value. It is a thing. The current control action of the NMOS transistor 702 on the NMOS transistor 200 will be described in detail later with reference to the drawings.
[0088]
The signal driving circuit 707 applies a signal voltage to the gate 706 of the NMOS transistor 702 as necessary, and controls conduction between the source 704 and the drain 703 of the NMOS transistor 702. The scan driving circuit 708 applies one scan selection period as one cycle, and applies one scan pulse as the gate voltage Vg to the NMOS transistor 200 for each row for each cycle. In the present embodiment, a signal for turning on the gate 202 of the NMOS transistor 200 is applied from the scan driving circuit 708 and a signal for turning on the gate 706 of the NMOS transistor 702 is applied from the signal driving circuit 707. When applied, a current corresponding to the characteristics of the NMOS transistor 200 and the NMOS transistor 702 is supplied to the emitter 101, and electrons corresponding to the current are emitted.
[0089]
Next, the operation of the FED configured as described above will be described.
[0090]
In this FED, a fixed electric voltage is constantly applied to the anode electrode 104 and the extraction electrode 103, so that a strong electric field that can enable electron emission in advance is fixedly applied to the surface of the emitter 101. More specifically, the fixed voltage applied to the anode electrode 104 and the extraction electrode 103 is such that when both the NMOS transistor 200 and the NMOS transistor 702 are turned on, the potential at the emitter 101 causes the electrons from the emitter 101 to emit electrons. The voltage is such that it can be discharged.
[0091]
The signal driving circuit 707 applies a signal voltage to the gate 706 of the NMOS transistor 702 and controls conduction between the source 704 and the drain 703 of the NMOS transistor 702. On the other hand, the scan driving circuit 708 sets one scan selection period to one cycle (for example, 0.1 second), and uses one scan pulse as the gate voltage Vg for each cycle to the gate 202 of the NMOS transistor 200 for each row. Apply. While a high level voltage (for example, 5 V) is applied from the scan driving circuit 708 to the gate 202 of the NMOS transistor 200, the NMOS transistor 200 is turned on, and the source 204 and drain of the NMOS transistor 200 are turned on. 201 is in a conductive state.
[0092]
When the NMOS transistor 200 and the NMOS transistor 702 are turned on, a current corresponding to a voltage applied from a constant voltage power source 705 connected to the source of the NMOS transistor 702 causes the NMOS transistor 702 and the NMOS transistor 200 to be turned on. To the emitter 101. At this time, since the emitter 101 is given in advance a strong electric field that can enable electron emission from the anode electrode 104 and the extraction electrode 103, field emission occurs on the surface of the emitter 101 in accordance with the current flowing through the emitter 101. Occurs and electrons are emitted toward the anode electrode 104. The electrons emitted from the emitter 101 collide with the phosphor of the phosphor layer 800 (FIG. 8) applied to the anode electrode 104, and cause the phosphor to emit light. A desired image is displayed by the emission of the phosphor.
[0093]
Here, since the FED according to the present embodiment is configured using the field emission electron emission devices according to the first to third embodiments, the amount of current supplied to the emitter 101 is stabilized. In addition, the electron emission amount of the emitter 101 is stabilized in terms of time. Therefore, with the FED according to the present embodiment, the light emission luminance required for image display can be obtained sufficiently and stably.
[0094]
Next, the current control action by the NMOS transistor 702 for current control will be described in more detail.
[0095]
FIG. 9 is a diagram for explaining the action of current control by the NMOS transistor 702. FIGS. 9A and 9B show the Id-Vd characteristics of the NMOS transistor 200. In particular, FIG. 9B shows the ideal Id-Vd characteristics of the NMOS transistor 200. FIG. Show.
[0096]
For example, when the Id-Vd characteristics vary among the plurality of NMOS transistors 200, even if each NMOS transistor 200 is driven under the same conditions, the drain current Id varies, and each emitter 101 Variations occur in the current supplied. Variations in current supplied to each emitter 101 appear as luminance variations as a result, which is not preferable. Curves G1 and G2 shown in FIG. 9A indicate two NMOs having different Id-Vd characteristics, respectively.
An example of characteristics of the S-type transistor 200 is shown. In the example shown in the figure, the drain current Id when the drain voltage Vd is 0.1 V differs between the curves G1 and G2 by 1 and 2 μm, respectively, at a ratio of 2 times.
[0097]
In the present embodiment, the variation in the drain current Id caused by the variation in the electrical characteristics of the NMOS transistor 200 is absorbed by using the NMOS transistor 702, and the amount of electron emission for each pixel varies. It does not occur.
[0098]
FIG. 9C shows an example of Id-Vd characteristics of the NMOS transistor 702. As shown in the figure, the NMOS transistor 702 has a characteristic that, for example, when the gate voltage Vg is 5 V and the drain voltage Id is 0 V, the drain current Id becomes 1 μA and becomes saturated. . Thus, as the NMOS transistor 702, for example, a transistor having a characteristic that a current value (for example, 1 μA) required for the NMOS transistor 200 to be controlled is in its saturation region is used. Then, the NMOS transistor 702 is operated in the saturation region defined by the Id-Vd characteristic (that is, the conduction between the source / drain is controlled in the saturation region of the Id-Vd characteristic). By doing so, even if the electrical characteristics of the NMOS transistor 200 vary as shown in FIG. 9A, the amount of current flowing through the source 204 of the NMOS transistor 200 is always the NMOS transistor. Since the current is controlled to be constant within the saturation region 702, the drain current Id of the NMOS transistor 200 is always constant.
[0099]
Here, in order to obtain the Id-Vd characteristics as shown in FIG. 9C, for example, a method of applying a positive bias voltage to the substrate of the NMOS transistor 702 in advance is used. it can. Even when such a bias voltage, that is, a voltage that can be regarded as a reverse bias with respect to the positive drain voltage Vd is applied to the substrate of the NMOS transistor 702, the NMOS transistor 702 does not have the emitter 101. Since the other NMOS transistor 200 is directly connected to the emitter 101, there is no inconvenience that a reverse voltage is applied to the emitter 101.
[0100]
For example, the source voltage of the NMOS transistor 200 is changed by changing the gate voltage Vg applied to the NMOS transistor 702 in accordance with the display data input from the outside or the gradation display in the image display in the signal driving circuit 707. It is also possible to change the amount of electron emission from the emitter 101 indirectly by controlling the current flowing to the 204 side.
[0101]
As described above, according to the present embodiment, the field emission type electron-emitting device having the effects as described in the first to third embodiments is used. The current required for electron emission can be stably supplied, and the electron emission amount of the emitter 101 can be stabilized in terms of time. Therefore, according to the FED according to the present embodiment, the light emission luminance required for image display can be obtained sufficiently and stably.
[0102]
Further, according to the present embodiment, the current supplied to the NMOS transistor 200 connected to the emitter 101 side is controlled by the NMOS transistor 702 for current control. Even if the electrical characteristics vary, the voltage applied to the emitter 101 and the amount of current to flow can be made uniform.
[0103]
Furthermore, according to the present embodiment, for example, by changing the gate voltage Vg applied to the NMOS transistor 702 corresponding to the gradation display, it is also possible to indirectly change the electron emission amount at the emitter 101. Therefore, even in an FED that performs gradation display, it is possible to perform favorable gradation display with high gradation reproducibility.
[0104]
In addition, the other structure, an effect | action, and effect in this Embodiment are the same as that of the said 1st-3rd embodiment.
[0105]
In addition, this invention is not limited to said each embodiment, A various deformation | transformation implementation is possible. For example, in the fourth embodiment, the field emission electron emission device of the present invention is applied to the FED. However, the field emission electron emission device of the present invention can be applied to other devices. It is. For example, in place of the phosphor in the above-described FED, a holding means for holding electrons emitted from the emitter 101 is provided, and the information recording apparatus records information by holding the electrons in the holding means. In contrast, the field emission electron emission device of the present invention can be applied.
[0106]
In each of the above-described embodiments, the example in which the NMOS transistor 200 is used as the semiconductor element has been described. However, for example, another semiconductor element such as a PMOS transistor may be used.
[0107]
【The invention's effect】
As described above, according to the field emission electron emission device of any one of claims 1 to 6, a fixed voltage is applied to the plurality of electron-emitting devices by the fixed voltage application electrode, and the gate The amount of current supplied to the electron-emitting device can be controlled by changing the voltage applied to the electron-emitting device, and a sufficient current value required to discharge electrons from the electron-emitting device has a sufficient value. Since a semiconductor element that is in a non-saturated region defined by the current-drain voltage characteristics is supplied with a current for emitting electrons as needed to a plurality of electron-emitting elements, The effect is that the current required for electron emission can be stably supplied to the emission element, and the required amount of electron emission can be stably obtained. Achieve the.
[0108]
The field emission display device according to any one of claims 7 to 16, wherein a fixed voltage is applied to the plurality of electron-emitting devices by a fixed voltage application electrode, and a voltage applied to the gate is changed. By changing, it is possible to control the amount of current supplied to the electron-emitting device, and a sufficient current value required for emitting electrons from the plurality of electron-emitting devices is drain current-drain. An electron-emitting device to which a current for supplying electrons is supplied to a plurality of electron-emitting devices as needed by a semiconductor device that is in a non-saturated region defined by voltage characteristics. Since electrons are emitted from the light source toward the light emitting means, the current required for electron emission can be stably supplied to the electron-emitting device. Et stably can emit electrons. Thereby, there is an effect that the light emission luminance required for image display can be obtained sufficiently and stably.
[0109]
Particularly, according to the field emission electron emission device according to claim 5 or the field emission display device according to claim 12, since the current control means for controlling the current supplied to the source of the semiconductor element is provided, For example, even if the electrical characteristics of the semiconductor element are different from the required characteristics, the difference in the characteristics is absorbed and the voltage applied to the electron-emitting device and the amount of current to flow are set to desired values. There is an effect that can be.
[0110]
According to the field emission display device according to claim 9, in the field emission display device according to claim 8, the voltage value applied to the gate of the semiconductor element is changed corresponding to the gradation display in the image display. Thus, there is an effect that gradation can be controlled by changing the gate voltage of the semiconductor element.
[0111]
Furthermore, according to the field emission display device according to claim 13, in the field emission display device according to claim 12, the current control means supplies the source of the semiconductor element in correspondence with the gradation display in the image display. Since the current flowing to the source side of the semiconductor element is controlled, it is possible to indirectly change the amount of electron emission in the electron-emitting device, and a good gradation reproducibility is obtained. There is an effect that tone display can be performed.
[Brief description of the drawings]
FIG. 1 is a configuration diagram schematically showing a configuration of a main part of a field emission electron emission device according to a first embodiment of the present invention.
FIG. 2 is another configuration diagram schematically showing the configuration of the main part of the field emission electron emission device according to the first embodiment of the present invention.
FIG. 3 is a characteristic diagram showing Id-Vd characteristics of an NMOS transistor in the field emission electron emission device shown in FIG.
4 is an explanatory diagram showing drive waveforms for driving the field emission electron emission device shown in FIG. 1; FIG.
FIG. 5 is a characteristic diagram showing Id-Vd characteristics of an NMOS transistor in a field emission electron emission device according to a second embodiment of the present invention.
FIG. 6 is a characteristic diagram showing Id-Vd characteristics of an NMOS transistor in a field emission electron emission device according to a third embodiment of the present invention.
FIG. 7 is a configuration diagram showing a configuration of a main part of a field emission electron emission device according to a fourth embodiment of the present invention.
8 is a cross-sectional view showing a cross-sectional structure of a main part of the field emission electron emission device shown in FIG.
9 is an explanatory diagram showing the operation of an NMOS transistor for current control in the field emission electron emission device shown in FIG. 7;
FIG. 10 is a plan view showing a configuration example of a conventional FED.
FIG. 11 is a cross-sectional view showing a configuration example of a conventional FED.
FIG. 12 is a configuration diagram schematically showing the structure of an electron emission portion in a conventional FED.
13 is an explanatory diagram showing drive waveforms used to drive the FED shown in FIG. 12. FIG.
FIG. 14 is a configuration diagram showing a main part of a configuration of an FED using a rectifying action of a MOS transistor.
FIG. 15 is an explanatory diagram showing drive waveforms used to drive the FED shown in FIG. 14;
16 is a characteristic diagram showing electrical characteristics, that is, Id-Vd characteristics, of a MOS transistor in the FED shown in FIG.
FIG. 17 is a characteristic diagram showing Id-Vd characteristics of a MOS transistor that has extremely steep rise characteristics and is not actually realizable.
FIG. 18 is a configuration diagram schematically showing the structure of a field emission electron emission device as a comparative example for the field emission electron emission device according to the first embodiment of the present invention;
FIG. 19 is an explanatory diagram showing drive voltage waveforms used for driving the field emission electron emission device of the comparative example shown in FIG. 18;
20 is a characteristic diagram showing Id-Vd characteristics of an NMOS transistor used in the field emission electron emission device of the comparative example shown in FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 101 ... Emitter, 103 ... Extraction electrode, 104 ... Anode electrode, 200 ... NMOS transistor, 201 ... Drain, 202 ... Gate, 204 ... Source, 300 ... Gate drive circuit, 701 ... Signal wiring, 707 ... Signal drive circuit, 708 ... Scanning drive circuit, 709 ... Scanning wiring.

Claims (16)

A fixed voltage application electrode to which a fixed voltage is applied; and
A plurality of electron-emitting devices that emit electrons according to the amount of current supplied in response to an electric field generated by a potential difference with the fixed voltage application electrode;
It is possible to control the amount of current supplied to the plurality of electron-emitting devices by electrically connecting each of one or more electron-emitting devices via the drain and changing the voltage applied to the gate. And a semiconductor device in which a sufficient current value required for emitting electrons from the plurality of electron-emitting devices is in a non-saturated region defined by a drain current-drain voltage characteristic. A field emission type electron-emitting device. 2. The field emission electron emission device according to claim 1, further comprising a gate driving circuit for controlling an electron emission amount of the electron emission element by controlling a voltage applied to a gate of the semiconductor element. A drain current value in a saturation region defined by a drain current-drain voltage characteristic of the semiconductor element is larger than a current value flowing through the electron emission element when the electron emission element is set to a ground potential. The field emission electron emission device according to claim 1. 2. The field emission electron emission apparatus according to claim 1, wherein the semiconductor element is operated at an operating voltage lower than a maximum operating voltage of the semiconductor element. 2. The field emission electron emission device according to claim 1, further comprising current control means for controlling a current supplied to a source of the semiconductor element. The current control means includes a saturation region in which a sufficient current value required for emitting electrons from the plurality of electron-emitting devices is connected to a source of the semiconductor device and defined by a drain current-drain voltage characteristic 6. The field emission electron emission device according to claim 5, further comprising a semiconductor element for current control as in the inside. A fixed voltage application electrode to which a fixed voltage is applied; and
A plurality of electron-emitting devices that emit electrons according to the amount of current supplied in response to an electric field generated by a potential difference with the fixed voltage application electrode;
Controlling the amount of current supplied to the plurality of electron-emitting devices by electrically connecting to the electron-emitting device every one or two or more electron-emitting devices via a drain and changing a voltage applied to the gate. A semiconductor capable of being performed and having a sufficient current value required for emitting electrons from the plurality of electron-emitting devices in a non-saturated region defined by a drain current-drain voltage characteristic Elements,
A field emission display device comprising: a light emitting unit that emits light in response to collision of electrons emitted from the electron emitting device. 8. The field emission display device according to claim 7, further comprising a scan driving circuit for controlling an electron emission amount of the electron-emitting device by controlling a voltage applied to a gate of the semiconductor device. 8. The field emission display device according to claim 7, wherein the scan driving circuit changes a voltage value applied to the gate of the semiconductor element in accordance with gradation display in image display. A drain current value in a saturation region defined by a drain current-drain voltage characteristic of the semiconductor element is larger than a current value flowing through the electron emission element when the electron emission element is set to a ground potential. The field emission display device according to claim 7. 8. The field emission display device according to claim 7, wherein the semiconductor element is operated at an operating voltage lower than a maximum operating voltage of the semiconductor element. 8. The field emission display device according to claim 7, further comprising current control means for controlling a current supplied to a source of the semiconductor element. 13. The field emission display device according to claim 12, wherein the current control means controls the current supplied to the source of the semiconductor element in accordance with gradation display in image display. The current control means is connected to a source of the semiconductor element, and a saturation region where a sufficient current value required for emitting electrons from the plurality of electron-emitting elements is defined by a drain current-drain voltage characteristic 13. The field emission display according to claim 12, further comprising a semiconductor element for current control as in the inside. 15. The field emission display device according to claim 14, wherein the current control means has a signal drive circuit for changing a signal voltage applied to the gate of the current control semiconductor element as required. 8. The field emission display device according to claim 7, wherein the semiconductor element is provided for each electron-emitting device or for each electron-emitting device corresponding to one pixel.

Images