JP4387364B2 - Liquid crystal display device and manufacturing method thereof - Google Patents

Description

  The present invention relates to an active matrix type liquid crystal display device, and more particularly to an active matrix type liquid crystal display device of an IPS (In-Plane Switching) type (= lateral electric field type).

  An active matrix type liquid crystal display device using an active element such as a thin film transistor (TFT) is known. Active matrix liquid crystal display devices can increase the pixel density, are small and light, and have low power consumption. Therefore, products such as personal computer monitors and liquid crystal televisions have been developed as alternatives to CRTs. Yes. In particular, the technology for forming the active layer of a TFT with a crystalline semiconductor film typified by polycrystalline silicon forms not only a switching TFT (hereinafter referred to as a pixel TFT) but also a driving circuit on the same substrate. Therefore, it is positioned as a technology that contributes to reducing the size and weight of liquid crystal display devices.

  In a liquid crystal display device, liquid crystal is sealed between a pair of substrates, and an electric field substantially perpendicular to the substrate surface is applied between a pixel electrode (individual electrode) on one substrate and a counter electrode (common electrode) on the other substrate. The liquid crystal molecules are aligned. However, such a liquid crystal driving method has a drawback in that the viewing angle is narrow when viewed in an oblique direction even if it is viewed in a direction perpendicular to the substrate surface, even if it is viewed from an oblique direction. there were.

There is an IPS method as a method for overcoming this drawback. This method is characterized in that both the pixel electrode and the common wiring are formed on one substrate and the electric field is switched in the horizontal direction, and the alignment is controlled in a direction substantially parallel to the substrate surface without rising up the liquid crystal molecules. .
This operating principle makes it possible to widen the viewing angle.

  FIG. 5 shows an example of a pixel structure in a conventional IPS active matrix liquid crystal display device. In FIG. 5, 301 is a gate wiring, 302 is a TFT semiconductor film, 303 is a common wiring, 304 and 308 are signal wirings (source wiring), 305 is a pixel electrode, 307 is a counter electrode, and 306 is a storage capacitor portion.

  However, in this pixel structure, there is a gap between the counter electrode 307 and the signal wirings 304 and 308, and the liquid crystal cannot be driven in accordance with the image signal in this gap part including the signal wirings 304 and 308. Problems occur. In order to prevent this, it is necessary to form a light-shielding film in this portion. As a result, the aperture ratio of the pixel portion is lowered. In the pixel structure as shown in FIG. 5, the maximum aperture ratio is about 30 to 40%, and the backlight brightness needs to be increased in order to ensure brightness. However, increasing the luminance of the backlight not only increases power consumption, but also has a concern of shortening the lifetime of the backlight itself.

  The IPS active matrix liquid crystal display device can widen the viewing angle, but has a drawback that the aperture ratio is lowered. The present invention provides means for solving such problems, improves the aperture ratio of an active matrix liquid crystal display device of the IPS system, and realizes a clear and bright image display with a wide viewing angle. With the goal.

  In an active matrix liquid crystal display device using an IPS mode in a pixel portion, an island-shaped semiconductor film, a gate wiring, a pixel electrode, and a common wiring are formed over an insulating surface in order to improve the aperture ratio. The signal wiring is formed on a first insulating layer that is a gate insulating film formed on the semiconductor film, and the pixel electrode and the common electrode are formed on the second insulating layer formed on the first insulating layer. The pixel electrode and the common wiring are arranged so as to generate an electric field parallel to the substrate surface, and the common electrode and the signal wiring overlap with each other via the second insulating layer. The signal wiring and the semiconductor film are arranged and connected through a connection electrode formed on the second insulating layer.

  Alternatively, a pixel portion and a driver circuit are provided over an insulating surface, and the pixel portion includes a semiconductor film, a TFT having a gate electrode and a gate wiring formed over the first insulating layer, and a second insulating layer. And a common wiring that intersects with the gate wiring, a pixel electrode that is formed on the second insulating layer and is connected to the TFT of the pixel portion, and is formed below the common wiring and overlaps with the second insulating layer. The pixel electrode and the common wiring are arranged so as to generate an electric field parallel to the substrate surface, and the signal wiring and the semiconductor film are connected on the second insulating layer. It has the structure provided with the structure connected through the electrode. Further, the other substrate on which the color filter is formed is provided so as to overlap with the red, blue, and green color filter layers corresponding to each pixel of the pixel portion and the TFT of the pixel portion. Or a light shielding film in which a red color filter layer and a blue color filter layer are laminated.

  In order to solve the above problems, a method for manufacturing a liquid crystal display device according to the present invention includes a first step of forming an island-shaped semiconductor film made of a crystalline semiconductor film over a substrate, and a first step over the island-shaped semiconductor film. A second step of forming a second insulating layer, a third step of forming a gate wiring and a signal wiring on the first insulating layer, and a fourth step of forming a second insulating layer on the gate wiring and the signal wiring. And a fifth step of forming the common wiring on the second insulating layer so as to overlap the signal wiring and the connection electrode connecting the common wiring and the semiconductor film. It is a feature.

  Alternatively, a first step of forming an island-shaped semiconductor film made of a crystalline semiconductor film on the substrate, a second step of forming a first insulating layer on the island-shaped semiconductor film, and the first insulating layer A third step of forming a gate electrode, a gate wiring, and a signal wiring, a fourth step of forming a second insulating layer on the gate wiring and the signal wiring, and forming the semiconductor film on the second insulating layer. A pixel electrode to be connected, a connection electrode for connecting the common wiring and the semiconductor film, a fifth step of forming the common wiring so as to overlap the signal wiring, and the other substrate of the pair of substrates corresponding to each pixel A sixth step of forming the red, blue and green color filter layers, and a step of forming a light shielding film by laminating the red color filter layer and the blue color filter layer so as to overlap at least the thin film semiconductor film. Process 7 and color fill on the other substrate It is characterized by having a eighth step of forming a translucent conductive film on the surface opposite to the over layer is formed.

  The active matrix substrate having the IPS pixel structure of the present invention improves the aperture ratio by forming the signal wiring and the common electrode in different layers and adopting the pixel structure as shown in FIGS. be able to. In addition, by forming the gate wiring with a low-resistance conductive material, the wiring resistance can be sufficiently reduced, and the pixel wiring (screen size) can be applied to a display device having a 4-inch class or more. Either the embodiment 1 or the embodiment 2 can be applied to the configuration of the electrode of the pixel portion.

  Further, according to the steps shown in this embodiment, the number of photomasks necessary for manufacturing an active matrix substrate is five (an island-like semiconductor film pattern, a gate electrode pattern, an n-channel region mask pattern, a contact hole pattern, a wiring Pattern). As a result, the process can be shortened, and the manufacturing cost can be reduced and the yield can be improved.

[Embodiment 1] A pixel portion of an active matrix type liquid crystal display device of an IPS system includes a pixel TFT composed of a p-channel or n-channel TFT, a pixel electrode and a storage capacitor, a signal wiring, a common wiring, and the like. The present invention is particularly characterized in the shapes of signal wiring and common wiring. Hereinafter, the configuration of the pixel portion of the present invention will be described with reference to FIGS.

  FIG. 1 shows almost one pixel in a pixel portion, and shows a state where island-like semiconductor films 101 and 102, a gate electrode 103, a gate wiring 104, and a signal line 106 are formed on an insulating surface. The substrate is preferably an alkali-free glass substrate or a quartz substrate, and a plastic substrate can also be used. The island-shaped semiconductor film 101 forms a TFT channel formation region, a source or drain region, an LDD region, and the like, and the island-shaped semiconductor film 102 is provided to form a storage capacitor. Although not illustrated, a first insulating film (a film corresponding to a gate insulating film) is formed over the island-shaped semiconductor films 101 and 102 and at least a substrate on which a pixel portion is formed, over which a gate electrode 103 is formed. It is formed. The gate electrode 103 is formed of an element selected from tungsten (W), tantalum (Ta), titanium (Ti), and molybdenum (Mo) or an alloy material containing the element as a component. Alternatively, a polycrystalline silicon film or a silicide film of the above element may be combined.

  The gate wiring 104 and the capacitor wiring 105 may be formed of the same material as the gate electrode, but the above material has a sheet resistance value of 10 Ω / □ or more, and a liquid crystal display device having a screen size of 4 inches class or more. Is not necessarily appropriate. As the screen size increases, the length of the wiring increases, and the signal delay time (wiring delay) due to the influence of the wiring resistance cannot be ignored. For example, the length of the diagonal line is 340 mm in the 13-inch class, and 460 mm in the 18-inch class. Therefore, the gate wiring 104 and the capacitor wiring 105 are preferably formed of a material mainly composed of aluminum (Al) or copper (Cu) that lowers the sheet resistance value.

  When the gate wiring 104 is formed of a material different from that of the gate electrode 103, the contact portion is provided outside the island-shaped semiconductor film 101 as shown in FIG. Since Al may ooze into the gate insulating film due to electromigration or the like, it is not appropriate to provide the gate wiring formed of Al on the island-shaped semiconductor film so as to be in direct contact with the gate insulating film. The contact between the gate electrode and the gate wiring does not require a contact hole, and is formed by overlapping the gate electrode and the gate wiring. The signal wiring 106 is formed simultaneously with the gate wiring 104.

  Thereafter, an interlayer insulating film (not shown) is formed, and the pixel electrode 112, the common wiring 113, and the connection electrode 111 are formed as shown in FIG. The pixel electrode 112 is connected to the island-shaped semiconductor film 101 through a contact portion 108 provided in the interlayer insulating film. This portion of the island-shaped semiconductor film 101 is a region where a source or drain to which an n-type or p-type impurity element is added is formed. One end of the pixel electrode 112 is connected to the island-shaped semiconductor film 102 through a contact portion 109.

  The connection electrode 111 connects the signal wiring 106 and the island-shaped semiconductor film 101 via the contact portions 110 and 107, and connects to the signal wiring of the adjacent pixel at the contact portion 114. That is, according to the embodiment of the present invention, the signal wiring is formed on the same layer as the gate wiring, and the intersection is performed using the connection electrode formed on the interlayer insulating film.

  As shown in FIG. 2, the common wiring 113 is formed on the interlayer insulating film and overlaps with the signal wiring 106. In this manner, by overlapping the common wiring and the signal wiring, it is possible to improve the aperture ratio of the pixel portion of the IPS active matrix liquid crystal display device formed in a transmission type.

  Thus, the pixel TFT 115 and the storage capacitor 116 are formed. In FIG. 2, the pixel TFT 115 has a multi-gate structure in which two gate electrodes are provided between a pair of sources or drains, but the number of gate electrodes is not limited and may be formed in a single gate structure. The storage capacitor 116 is formed of the semiconductor film 102, an insulating film (not shown) in the same layer as the gate insulating film, and the capacitor wiring 105. FIG. 3 is a circuit diagram of the pixel portion, and a portion surrounded by a dotted line 117 substantially corresponds to one pixel.

  The width of the pixel electrode is preferably 3 μm or more in consideration of the spread of the electric field in the direction parallel to the substrate surface. The interval between the pixel electrode and the common wiring is 10 to 20 μm, preferably 12 to 14 μm. 1 and 2 show the basic pixel configuration of the IPS system of the present invention, the pixel electrode and the common wiring may be formed in a comb shape in consideration of the size of one pixel and the visibility of the image.

  FIG. 17 shows an example, in which a pixel TFT 1015, a storage capacitor 1016, a pixel electrode 1012, and a common electrode 1013 are provided. The pixel TFT 1015 includes an island-shaped semiconductor film 1001, a gate electrode 1003, and the like, and is connected to the pixel electrode 1012 through a contact portion 1008. The signal wiring 1006 is connected to the connection wiring 1011 at the contact portion 1010, and the connection wiring 1011 is connected to the island-shaped semiconductor film 1001 at the contact portion 1007 and the signal wiring of the adjacent pixel at the contact portion 1014. The signal wiring 1006 is provided so as to overlap with the common wiring 1013 and the interlayer insulating film.

  The pixel structure shown in FIG. 2 or FIG. 17 does not necessarily require a light-shielding film covering these wiring portions by providing signal wirings and common wirings so as to overlap each other with an interlayer insulating film interposed therebetween. Therefore, the area where transmitted light is blocked in the transmissive liquid crystal display device can be reduced, and the aperture ratio can be improved to 50 to 60%. As a result, the power consumption of the backlight can be reduced as compared with the conventional IPS liquid crystal display device.

[Embodiment 2] In the IPS system, a dog-shaped electrode structure is known as a method for widening the viewing angle including white tone. FIG. 4 shows an example in which the pixel structure of the present invention described in Embodiment 1 adopts a dog-shaped electrode structure. The pixel is provided with a pixel TFT 215, a storage capacitor 216, a pixel electrode 212, and a common electrode 213. The pixel TFT 215 includes an island-shaped semiconductor film 201, a gate electrode 203, and the like, and is connected to the pixel electrode 212 through a contact portion 208. The signal wiring 206 is connected to the connection wiring 211 at the contact portion 210, and the connection wiring 211 is connected to the island-shaped semiconductor film 201 at the contact portion 207 and the signal wiring of the adjacent pixel at the contact portion 214. The signal wiring 206 is provided so as to overlap with the common wiring 213 and the interlayer insulating film, and the angle of the dogleg shape is 120 to 160 degrees, preferably 150 degrees. Adopting the U-shaped electrode structure further widens the viewing angle, and there is no change in color tone even when viewed at an angle of about 60 to 50 degrees, as well as the direction perpendicular to the substrate surface, and the decrease in contrast is reduced. be able to.

Embodiment 3 FIG. 18A illustrates another example of an IPS pixel structure. The pixel is provided with a pixel TFT 1115, a storage capacitor 1116, a pixel electrode 1112, and a common electrode 1113. The pixel TFT 1115 includes an island-shaped semiconductor film 1101, a gate electrode 1103, and the like, and is connected to the pixel electrode 1112 through a contact portion 1108. The signal wiring 1106 is connected to the connection wiring 1111 at the contact portion 1110, and the connection wiring 1111 is connected to the island-shaped semiconductor film 1101 at the contact portion 1107 and the signal wiring of the adjacent pixel at the contact portion 1114. The signal wiring 1106 is provided so as to overlap with the common wiring 1113 and the interlayer insulating film. A circuit diagram of such a pixel is shown in FIG.

  A semiconductor film 1102 that forms the storage capacitor 1116 is added with a p-type impurity element typified by boron to form one electrode, and an adjacent pixel is interposed through an insulating film formed of the same layer as the gate insulating film. The gate wiring 1105 is used as the other electrode. The reason why the semiconductor film 1102 is p-type conductivity is that the semiconductor film 1102 is turned on when the gate wiring 1105 is at a low level.

  With the pixel structure as shown in FIG. 18A, the capacitor wiring can be omitted, the circuit configuration including the pixel portion and the driver circuit can be simplified, and the aperture ratio can be further improved. .

  In this embodiment, a method for simultaneously manufacturing a pixel portion formed using an IPS pixel structure and a TFT of a driver circuit provided around the pixel portion will be described in detail.

  The gate electrode of the TFT shown in this embodiment has a two-layer structure. Each of the first layer and the second layer is formed of an element selected from Ta, W, Ti, and Mo, or an alloy material or a compound material containing the element as a main component. Alternatively, the first layer may be formed of a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus. As an example of a preferable combination, the first layer is formed of Ta or tantalum nitride (TaN), or a stacked structure of tantalum nitride (TaN) and Ta, and the second layer is formed of W.

  The same applies to the case where a semiconductor film is used for the first layer of the gate electrode. However, an element selected from Ta, W, Ti, and Mo, or an alloy material or a compound material containing the element as a main component has an area resistance of about The value is 10Ω or more, and is not necessarily suitable for manufacturing a display device having a screen size of 4 inch class or more. This is because, as the screen size increases, the length of wiring on the substrate inevitably increases, and the problem of signal delay time due to the influence of wiring resistance cannot be ignored. Further, if the width of the wiring is increased for the purpose of reducing the wiring resistance, the area of the peripheral region other than the pixel portion is increased, and the appearance of the display device is significantly impaired.

First, as shown in FIG. 6A, a silicon oxide film on a substrate 501 made of glass such as barium borosilicate glass represented by Corning # 7059 glass or # 1737 glass, or aluminoborosilicate glass, A base film 502 made of an insulating film such as a silicon nitride film or a silicon oxynitride film is formed. For example, a silicon oxynitride film 502a formed from SiH ₄ , NH ₃ , and N ₂ O by plasma CVD is formed to a thickness of 10 to 200 nm (preferably 50 to 100 nm), and similarly formed from SiH ₄ and N ₂ O. A silicon oxynitride film 502b is formed to a thickness of 50 to 200 nm (preferably 100 to 150 nm). Although the base film 502 is shown as a two-layer structure in this embodiment, it may be formed as a single-layer film of the insulating film or a structure in which two or more layers are stacked.

  The island-shaped semiconductor layers 503 to 506 and 563 formed over the insulating surface are formed using a crystalline semiconductor film in which a semiconductor film having an amorphous structure is formed using a laser crystallization method or a thermal crystallization method. The island-like semiconductor layers 503 to 506 and 563 are formed to have a thickness of 25 to 80 nm (preferably 30 to 60 nm). There is no limitation on the material of the crystalline semiconductor film, but it is preferably formed of silicon or a silicon germanium (SiGe) alloy.

In order to fabricate a crystalline semiconductor film by a laser crystallization method, a gas laser represented by a pulse oscillation type or a continuous emission type excimer laser, a solid laser represented by a YAG laser, or a YVO ₄ laser is used. In the case of using these lasers, it is preferable to use a method in which laser light emitted from a laser oscillator is condensed into a linear shape, a rectangular shape, or a rectangular shape by an optical system and irradiated onto a semiconductor film. The crystallization conditions are appropriately selected by the practitioner. When an excimer laser is used, the pulse oscillation frequency is 30 Hz, and the laser energy density is 100 to 400 mJ / cm ² (typically 200 to 300 mJ / cm ^2). ). In the case of using a YAG laser, the second harmonic is used, the pulse oscillation frequency is set to 1 to 10 kHz, and the laser energy density is set to 300 to 600 mJ / cm ² (typically 350 to 500 mJ / cm ² ). Then, laser light condensed linearly with a width of 100 to 1000 μm, for example, 400 μm, is irradiated over the entire surface of the substrate, and the superposition ratio (overlap ratio) of the linear laser light at this time is 80 to 98%.

The gate insulating film 507 is formed of an insulating film containing silicon with a thickness of 40 to 150 nm by a plasma CVD method or a sputtering method. In this embodiment, a silicon oxynitride film is formed with a thickness of 120 nm. Needless to say, the gate insulating film is not limited to such a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure. For example, when a silicon oxide film is used, TEOS (Tetraethyl Ortho Silicate) and O ₂ are mixed by a plasma CVD method, the reaction pressure is 40 Pa, the substrate temperature is 300 to 400 ° C., and the high frequency (13.56 MHz) power density is 0. It can be formed by discharging at 5 to 0.8 W / cm ² . The silicon oxide film thus manufactured can obtain good characteristics as a gate insulating film by subsequent thermal annealing at 400 to 500 ° C.

  Then, a first conductive film 508 and a second conductive film 509 for forming a gate electrode are formed over the gate insulating film 507. In this embodiment, the first conductive film 508 is formed with Ta to a thickness of 50 to 100 nm, and the second conductive film is formed with W to a thickness of 100 to 300 nm.

  The Ta film is formed by sputtering, and a Ta target is sputtered with Ar. In this case, when an appropriate amount of Xe or Kr is added to Ar, the internal stress of the Ta film can be relieved and peeling of the film can be prevented. The resistivity of the α-phase Ta film is about 20 μΩcm and can be used as a gate electrode, but the resistivity of the β-phase Ta film is about 180 μΩcm and is not suitable for a gate electrode. In order to form an α-phase Ta film, tantalum nitride having a crystal structure close to Ta's α-phase is formed on a Ta base with a thickness of about 10 to 50 nm, so that an α-phase Ta film can be easily obtained. be able to.

When forming a W film, it is formed by sputtering using W as a target. In addition, it can be formed by a thermal CVD method using tungsten hexafluoride (WF ₆ ). In any case, in order to use as a gate electrode, it is necessary to reduce the resistance, and the resistivity of the W film is desirably 20 μΩcm or less. The resistivity of the W film can be reduced by increasing the crystal grains. However, when there are many impurity elements such as oxygen in W, crystallization is hindered and the resistance is increased. Therefore, in the case of the sputtering method, by using a W target having a purity of 99.9999% and further forming a W film with sufficient consideration so as not to mix impurities from the gas phase during film formation, the resistivity 9-20 μΩcm can be realized.

Next, as shown in FIG. 6B, resist masks 510 to 513 are formed, and a first etching process for forming a gate electrode is performed. Although there is no limitation on the etching method, the ICP (Inductively Coupled Plasma) etching method is preferably used, and CF ₄ and Cl ₂ are mixed in the etching gas, and 0.5 to ₂ Pa, preferably 1 Pa is used. 500 W RF (13.56 MHz) power is applied to the coil-type electrode under pressure to generate plasma. 100 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. When CF ₄ and Cl ₂ are mixed, the W film and the Ta film are etched to the same extent.

Under the above etching conditions, by making the shape of the resist mask suitable, the end portions of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. The angle of the tapered portion is 15 to 45 °.
In order to perform etching without leaving a residue on the gate insulating film, it is preferable to increase the etching time at a rate of about 10 to 20%. Since the selection ratio of the silicon oxynitride film to the W film is 2 to 4 (typically 3), the surface where the silicon oxynitride film is exposed is etched by about 20 to 50 nm by the overetching process. Thus, the first shape conductive layers 515 to 518 (the first conductive layers 515a to 518a and the second conductive layers 515b to 518b) formed of the first conductive layer and the second conductive layer by the first etching treatment. Form. Reference numeral 514 denotes a gate insulating film. A region which is not covered with the first shape conductive layers 515 to 518 is etched and thinned by about 20 to 50 nm.

Then, an impurity element imparting n-type is added by performing a first doping process.
The doping method may be an ion doping method or an ion implantation method. The conditions of the ion doping method are a dose amount of 1 × 10 ^{13 to} 5 × 10 ¹⁴ atoms / cm ² and an acceleration voltage of 60 to 100 keV. As an impurity element imparting n-type, an element belonging to Group 15, typically phosphorus (P) or arsenic (As), is used here, but phosphorus (P) is used. In this case, the conductive layers 515 to 518 serve as a mask for the impurity element imparting n-type, and the first impurity regions 519 to 523 are formed in a self-aligning manner. An impurity element imparting n-type conductivity is added to the first impurity regions 519 to 523 in a concentration range of 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ .

Next, a second etching process is performed as shown in FIG. Similarly, using ICP etching, CF ₄ , Cl ₂ and O ₂ are mixed in the etching gas, and 500 W of RF power (13.56 MHz) is supplied to the coil-type electrode at a pressure of 1 Pa to generate plasma. Do. 50 W RF (13.56 MHz) power is applied to the substrate side (sample stage), and a lower self-bias voltage is applied than in the first etching process. Under such conditions, the W film is anisotropically etched, and Ta, which is the first conductive layer, is anisotropically etched at a slower etching rate to form second shape conductive layers 529 to 532 (first Conductive layers 529a to 532a and second conductive layers 529b to 532b)
Form. Reference numeral 528 denotes a gate insulating film. A region not covered with the second shape conductive layers 529 to 532 is further etched by about 20 to 50 nm to form a thinned region.

The etching reaction of the W film or Ta film with the mixed gas of CF ₄ and Cl ₂ can be estimated from the generated radical or ion species and the vapor pressure of the reaction product. When the vapor pressures of W and Ta fluorides and chlorides are compared, WF ₆ which is a fluoride of W is extremely high, and other WCl ₅ , TaF ₅ and TaCl ₅ are similar. Therefore, both the W film and the Ta film are etched with a mixed gas of CF ₄ and Cl ₂ . However, when an appropriate amount of O ₂ is added to this mixed gas, CF ₄ and O ₂ react to form CO and F, and a large amount of F radicals or F ions are generated. As a result, the etching rate of the W film having a high fluoride vapor pressure is increased. On the other hand, the increase in etching rate of Ta is relatively small even when F increases. Further, since Ta is more easily oxidized than W, the surface of Ta is oxidized by adding O ₂ . Since the Ta oxide does not react with fluorine or chlorine, the etching rate of the Ta film further decreases. Therefore, it is possible to make a difference in the etching rate between the W film and the Ta film, and the etching rate of the W film can be made larger than that of the Ta film.

Then, a second doping process is performed as shown in FIG. In this case, an impurity element which imparts n-type is doped under a condition of a lower acceleration amount and a higher acceleration voltage than in the first doping treatment. For example, the acceleration voltage is set to 70 to 120 keV and the dose is 1 × 10 ¹³ atoms / cm ^2. A new impurity region is formed inside the first impurity region formed in the island-shaped semiconductor layer in FIG. 6B. Form. Doping is performed using the second shape conductive layers 529 to 532 as a mask against the impurity element so that the impurity element is also added to the lower region of the first conductive layers 529 a to 532 a. Thus, third impurity regions 537 to 540 overlapping with the first conductive layers 529a to 532a and second impurity regions 533 to 536 between the first impurity region and the third impurity region are formed. The impurity element imparting n-type conductivity has a concentration of 1 × 10 ¹⁷ to 1 × 10 ¹⁹ atoms / cm ³ in the second impurity region, and 1 × 10 ¹⁶ to 1 × 10 ^{18 in} the third impurity region. The concentration is atoms / cm ³ .

Then, as shown in FIG. 7B, fourth impurity regions 544 to 546 having a conductivity type opposite to the one conductivity type are formed in the island-shaped semiconductor layer 504 forming the p-channel TFT. Using the second conductive layer 530 as a mask for the impurity element, an impurity region is formed in a self-aligning manner. At this time, the island-like semiconductor layers 503, 505, and 506 forming the n-channel TFT are entirely covered with resist masks 541 to 543. Phosphorus is added to the impurity regions 544 to 546 at different concentrations. The impurity regions 544 to 546 are formed by ion doping using diborane (B ₂ H ₆ ), and the impurity concentration in each region is 2 × 10 ²⁰ to It is set to 2 × 10 ²¹ atoms / cm ³ .

  Through the above steps, impurity regions are formed in each island-like semiconductor layer. The second shape conductive layers 529 to 532 function as gate electrodes.

  Thus, for the purpose of controlling the conductivity type, as shown in FIG. 7C, a step of activating the impurity element added to each island-like semiconductor layer is performed. This step is performed by a thermal annealing method using a furnace annealing furnace. In addition, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied. In the thermal annealing method, the oxygen concentration is 1 ppm or less, preferably 0.1 ppm or less in a nitrogen atmosphere at 400 to 700 ° C., typically 500 to 600 ° C. In this example, the temperature is 500 ° C. for 4 hours. Heat treatment is performed.

In the laser annealing method, excimer laser light having a wavelength of 400 nm or less, YAG laser, and second harmonic (532 nm) of YVO ₄ laser are used. The activation conditions are appropriately selected by the practitioner. When an excimer laser is used, the pulse oscillation frequency is set to 30 Hz, and the laser energy density is set to 100 to 300 mJ / cm ² . When a YAG laser is used, the second harmonic is used and the pulse oscillation frequency is 1 to 10 kHz, and the laser energy density is preferably 200 to 400 mJ / cm ² . Then, laser light condensed linearly with a width of 100 to 1000 μm, for example, 400 μm, is irradiated over the entire surface of the substrate, and the superposition ratio (overlap ratio) of the linear laser light at this time is 80 to 98%.

  Further, a heat treatment is performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen to perform a step of hydrogenating the island-shaped semiconductor layer. This step is a step of terminating dangling bonds in the semiconductor layer with thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.

  After the activation and hydrogenation treatment, a gate wiring, a signal wiring, and a capacitor wiring are formed using a low-resistance conductive material. The low-resistance conductive material is mainly composed of Al or Cu, and the gate wiring is formed using such a material. In this embodiment, an example using Al is shown, and an Al film containing 0.1 to 2% by weight of Ti is formed on the entire surface as a low resistance conductive layer (not shown). The thickness is 200 to 400 nm (preferably 250 to 350 nm). Then, a predetermined resist pattern is formed and etched to form gate wirings 547 and 549, a signal wiring 548, and a capacitor wiring 550. When the wiring is etched by wet etching using a phosphoric acid-based etching solution, it can be formed while maintaining selective processability with the base.

  When Cu is used for the gate wiring, a Ta nitride film is formed to a thickness of 50 to 200 nm as a base in order to improve adhesion. Cu is formed to a thickness of 200 to 500 nm by sputtering or plating, and wiring is formed by etching. Cu wiring has higher resistance to electromigration than Al wiring and can be miniaturized.

  In FIG. 8, the first interlayer insulating film 551 is formed with a thickness of 100 to 200 nm from a silicon oxynitride film. A second interlayer insulating film 552 made of an organic insulating material is formed thereon. The second interlayer insulating film 552 is formed with an average film thickness of 1.0 to 2.0 μm. As the organic insulating material, polyimide, acrylic, polyamide, polyimide amide, BCB (benzocyclobutene), or the like can be used. For example, when using a type of polyimide that is thermally polymerized after being applied to the substrate, it is formed by baking at 300 ° C. in a clean oven. When acrylic is used, a two-component type is used, and after mixing the main material and the curing agent, applying the entire surface of the substrate using a spinner, preheating at 80 ° C. for 60 seconds with a hot plate. It can be formed by baking at 250 ° C. for 60 minutes in a clean oven.

Then, source wirings 553 to 555 that form contacts with the source region of the island-shaped semiconductor layer and drain wirings 556 to 558 that form contacts with the drain region are formed in the driver circuit 406. In the pixel portion 407, a common wiring 559, a pixel electrode 561, a capacitor wiring 562, and a connection electrode 560 are formed. With this connection electrode 560, the signal wiring 548 is electrically connected to the pixel TFT 404. Wirings formed on the second interlayer insulating film 552 are, for example, as shown in FIG.
As shown in FIG. 5, the film is formed of a Ti film 768a of 50 to 200 nm, an Al film 768b of 100 to 300 nm, a tin (Sn) film or Ti film of 50 to 200 nm. The source wirings 553 to 555, the drain wirings 556 to 558, and the pixel electrode 561 formed as described above are connected to the source or drain region 765 of the TFT and the Ti via the contact holes formed in the second interlayer insulating film. A contact is formed with the film 768a to prevent the Al and the semiconductor from directly contacting and reacting with each other, thereby improving the reliability of the contact portion.

  As described above, the driver circuit 406 including the n-channel TFT 401, the p-channel TFT 402, and the n-channel TFT 403, and the pixel portion 407 including the pixel TFT 404 and the storage capacitor 405 can be formed over the same substrate. In this specification, such a substrate is referred to as an active matrix substrate for convenience.

  The n-channel TFT 401 of the driver circuit 406 is formed outside the channel formation region 563, a third impurity region 537 (Gate Overlapped Drain: GOLD region) overlapping the second shape conductive layer 529 forming the gate electrode, and the gate electrode. The second impurity region 533 (Lightly Doped Drain: LDD region) and the first impurity region 519 functioning as a source region or a drain region are provided. The p-channel TFT 402 includes a channel formation region 564, a fourth impurity region 546 that overlaps with the second shape conductive layer 530 that forms the gate electrode, a fourth impurity region 545 formed outside the gate electrode, and a source region Alternatively, a fourth impurity region 544 functioning as a drain region is provided. The n-channel TFT 403 includes a channel formation region 565, a third impurity region 539 (GOLD region) that overlaps with the second-shaped conductive layer 531 that forms the gate electrode, and a second impurity region formed outside the gate electrode. 535 (LDD region) and a first impurity region 521 functioning as a source region or a drain region.

The pixel TFT 404 in the pixel portion includes a channel formation region 566 and a third impurity region 540 (GOLD region) that overlaps with the second shape conductive layer 532 forming the gate electrode.
And a second impurity region 536 (LDD region) formed outside the gate electrode and a first impurity region 522 functioning as a source region or a drain region. Further, an impurity element imparting n-type conductivity is added to the semiconductor layer 523 functioning as one electrode of the storage capacitor 405 at the same concentration as that of the first impurity region, and the capacitor wiring 550 and an insulating layer (gate insulating layer) therebetween are added. A storage capacitor is formed by the same layer as the film). However, a storage capacitor 405 illustrated in FIG. 8 indicates a storage capacitor of an adjacent pixel.

  In the top view of the pixel portion of the active matrix substrate manufactured in this embodiment, AA ′ in FIG. 8 corresponds to the AA ′ line shown in FIG. That is, the common wiring 559, the signal wiring 548, the connection wiring 560, the pixel electrode 561, the gate wiring 549, and the capacitor wiring 550 shown in FIG. 8 are the common wiring 113, signal wiring 106, connection electrode 111, pixel electrode 112, It corresponds to the gate wiring 104 and the capacitor wiring 105 ′.

  As described above, the active matrix substrate having the IPS pixel structure according to the present invention can improve the aperture ratio by forming the signal wiring and the common electrode in different layers and forming the pixel structure as shown in FIG. it can. In addition, by forming the gate wiring with a low-resistance conductive material, the wiring resistance can be sufficiently reduced, and the pixel wiring (screen size) can be applied to a display device having a 4-inch class or more. Either the embodiment 1 or the embodiment 2 can be applied to the configuration of the electrode of the pixel portion.

  In this embodiment, a process of manufacturing an active matrix liquid crystal display device from the active matrix substrate manufactured in Embodiment 1 will be described. FIG. 9 shows a state where the active matrix substrate and the counter substrate 569 are bonded together. First, an alignment film 567 is formed on the active matrix substrate in the state shown in FIG. 8, and a rubbing process is performed. Color filter layers 570 and 571, an overcoat layer 573, and an alignment film 574 are formed on the counter substrate 569. The color filter layer is formed by overlapping a red color filter layer 570 and a blue color filter layer 571 above the TFT to serve as a light shielding film. In addition, a red color filter layer 570, a blue color filter layer 571, and a green color filter layer 572 are overlapped to form a spacer in accordance with the connection electrode. Each color filter is formed by mixing a pigment with an acrylic resin and having a thickness of 1 to 3 μm. This can be formed in a predetermined pattern using a photosensitive material and a mask. The height of the spacer can be set to 2 to 7 μm, preferably 4 to 6 μm in consideration of the thickness of the overcoat layer of 1 to 4 μm. When the active matrix substrate and the counter substrate are bonded to each other by this height, Forming a gap. The overcoat layer is formed of a photo-curing or thermosetting organic resin material, and for example, polyimide or acrylic resin is used. The arrangement of the spacers may be arbitrarily determined. For example, as shown in FIG. 9, the spacers may be formed so as to be aligned on the connection wiring. Thereafter, the active matrix substrate and the counter substrate are bonded together.

  FIG. 12 schematically shows how the active matrix substrate and the counter substrate are bonded together. The active matrix substrate 650 is provided with a pixel portion 653, a scanning line side driver circuit 652, a signal line side driver circuit 651, an external input terminal 654, a wiring 659 for connecting the external input terminal to the input portion of each circuit, and the like. . A color filter layer 656 is formed on the counter substrate 655 corresponding to the region where the pixel portion and the driving circuit of the active matrix substrate 650 are formed. Such an active matrix substrate 650 and the counter substrate 655 are attached to each other through a sealant 657, and liquid crystal is injected to provide a liquid crystal layer 658 inside the sealant 657. Further, an FPC (Flexible Printed Circuit) 660 is attached to the external input terminal 654 of the active matrix substrate 650. In order to increase the adhesive strength of the FPC 660, a reinforcing plate 659 may be provided.

  The section line AA ′ in the pixel portion of FIG. 9 corresponds to the AA ′ line in the top view of the pixel portion shown in FIG. On the upper surface of the pixel TFT, a red color filter and a blue color filter are laminated on the opposite substrate side, and this is used as a light shielding film.

  FIG. 11 is a front view of the active matrix substrate manufactured as described above. The top view shown in FIG. 11A connects a pixel portion, a driving circuit, an external input terminal 712 to which an FPC (Flexible Printed Circuit Board: Flexible Printed Circuit) is pasted, and the external input terminal 712 to the input portion of each circuit. An active matrix substrate 710 on which wirings 714 and the like are formed and a counter substrate 711 on which color filters and the like are formed are attached to each other with a sealant 713 interposed therebetween.

  On the upper surface of the scanning line side driving circuit 716 and the signal line side driving circuit 715, a light shielding film 718 in which a red color filter or red and blue color filters are stacked is formed on the counter substrate side. In addition, the color filter 719 formed on the counter substrate side over the pixel portion 717 is provided with a color filter layer of each color of red (R), green (G), and blue (B) corresponding to each pixel. FIG. 11B is a schematic diagram in which a part of the pixel is enlarged. In actual display, one pixel is formed with three colors of a red (R) color filter layer 701, a green (G) color filter layer 703, and a blue (B) color filter layer 702. The arrangement of the color filters of these colors Is optional. A red (R) color filter, or a red (R) color filter layer and a blue (B) color filter layer are used as a light shielding film 704 in a region 705 where a TFT of each pixel is formed and a region where a columnar spacer 706 is formed. And are laminated.

  FIG. 10 shows a cross-sectional structure of a pixel portion having an array of color filters along the line BB ′ shown in FIG. A red (R) pixel 626, a blue (B) pixel 627, and a green (G) pixel 628 are formed. On the active matrix substrate side, a base film 602, a gate insulating film 603, signal wirings 604 to 607, an interlayer insulating film 609, pixel electrodes 611, 613, 615, common wirings 610, 612, 614, 616, an alignment film 624 are formed on the substrate 601. Is formed. On the counter substrate 617 side, a red (R) color filter 618, a blue (B) color filter 619, and a green (G) color filter 620 are sequentially formed, and an overcoat layer 621 and an alignment film 622 are formed thereon. . In the meantime, a liquid crystal layer 623 is formed. Between adjacent pixels, a signal wiring and a common wiring are formed so as to overlap each other, and a light shielding portion 625 is formed.

  FIG. 13 is a diagram showing the configuration of the external input terminal section. The external input terminal is formed on the active matrix substrate side, and is formed in the same layer as the signal wiring 751 and the common wiring 752 through the interlayer insulating film 750 in order to reduce interlayer capacitance and wiring resistance and prevent defects due to disconnection. An FPC composed of a base resin 753 and a wiring 754 is bonded to the external input terminal with an anisotropic conductive resin 755. Further, the reinforcing plate 756 increases the mechanical strength.

  FIG. 14A shows a detailed view thereof, and shows a cross-sectional view of the external input terminal 712 shown in FIG. External input terminals provided on the active matrix substrate side are formed of a wiring 757 formed of the same layer as the signal wiring and a wiring 760 formed of the same layer as the common wiring. Of course, this is only an example of the configuration of the terminal portion, and it may be formed with only one of the wirings. For example, when the wiring 757 is formed in the same layer as the signal wiring, it is necessary to remove the interlayer insulating film formed thereon. The wiring 760 formed in the same layer as the common wiring has a three-layer structure of a Ti film 760a, an Al film 760b, and a Sn film 760c according to the configuration shown in the first embodiment. The FPC is formed of a base film 761 and a wiring 762, and the wiring 760 formed of the same layer as the wiring 762 and the common wiring is composed of a thermosetting adhesive 764 and conductive particles 763 dispersed therein. Are bonded together with an anisotropic conductive adhesive to form an electrical connection structure.

  On the other hand, FIG. 14B shows a cross-sectional view of the external input terminal 712 shown in FIG. Since the outer diameter of the conductive particles 763 is smaller than the pitch of the wirings 760, if the amount dispersed in the adhesive 764 is appropriate, the corresponding FPC side wiring is electrically connected without short-circuiting with the adjacent wiring. Can be formed.

  The active matrix liquid crystal display device using the IPS method manufactured as described above can be used as a display device for various electronic devices.

  In this embodiment, another example in which the TFT structure of the active matrix substrate is different will be described with reference to FIG.

  The active matrix substrate shown in FIG. 15 has a driving circuit 857 having a logic circuit portion 855 having a first p-channel TFT 850 and a first n-channel TFT 851 and a sampling circuit portion 856 having a second n-channel TFT 852. In addition, a pixel TFT 853 and a pixel portion 858 having a storage capacitor 854 are formed. The TFT of the logic circuit portion 855 of the driver circuit 857 forms a shift register circuit, a buffer circuit, and the like, and the TFT of the sampling circuit 856 is basically formed of an analog switch.

  These TFTs are formed by providing channel formation regions, source / drain regions, LDD regions, and the like on island-like semiconductor films 803 to 806 on a base film 802 formed on a substrate 801. The base film and the island-shaped semiconductor film are formed in the same manner as in Example 1. The gate electrodes 809 to 812 formed over the gate insulating film 808 are characterized in that end portions are tapered, and an LDD region is formed using this portion. Similar to the first embodiment, such a tapered shape can be formed by an anisotropic etching technique for a W film using an ICP etching apparatus.

  The LDD region formed by using the tapered portion is provided in order to improve the reliability of the n-channel TFT, thereby preventing on-current deterioration due to the hot carrier effect. In this LDD region, ions of the impurity element are accelerated by an electric field by an ion doping method, and added to the semiconductor film through the end portion of the gate electrode and the gate insulating film in the vicinity of the end portion.

  In the first n-channel TFT 851, a first LDD region 835, a second LDD region 834, and a source or drain region 833 are formed outside the channel formation region 832, and the first LDD region 835 is connected to the gate electrode 810. It is formed to overlap. In addition, the n-type impurity element contained in the first LDD region 835 and the second LDD region 834 is higher in the second LDD region 834 due to a difference in film thickness of the upper gate insulating film and the gate electrode. It has become. The second n-channel TFT 852 has a similar structure and includes a channel formation region 836, a first LDD region 839 overlapping with the gate electrode, a second LDD region 838, and a source or drain region 837. On the other hand, the p-channel TFT 850 has a single drain structure, and impurity regions 829 to 831 to which a p-type impurity is added are formed outside the channel formation region 828.

  In the pixel portion 858, a pixel TFT formed using an n-channel TFT is formed with a multi-gate structure for the purpose of reducing off-current, and the first LDD region 843 and the second LDD region 843 that overlap with the gate electrode are formed outside the channel formation region 840. The LDD region 842 and the source or drain region 841 are provided. In addition, the storage capacitor 854 includes an insulating layer formed using the same layer as the island-shaped semiconductor film 807 and the gate insulating film 808 and a capacitor wiring 815. An n-type impurity is added to the island-shaped semiconductor film 807, and the voltage applied to the capacitor wiring can be reduced because the resistivity is low.

  The interlayer insulating film is made of an inorganic material such as silicon oxide, silicon nitride, or silicon oxynitride, and has a first interlayer insulating film 816 having a thickness of 50 to 500 nm, polyimide, acrylic, polyimide amide, BCB (benzocyclobutene). And a second interlayer insulating film 817 made of an organic insulating material such as Thus, the surface can be satisfactorily flattened by forming the second interlayer insulating film with an organic insulating material. In addition, since the organic resin material generally has a low dielectric constant, parasitic capacitance can be reduced. However, it is hygroscopic and is not suitable as a protective film, and thus is preferably formed in combination with the first interlayer insulating film 816.

Thereafter, a resist mask having a predetermined pattern is formed, and contact holes reaching the source region or the drain region formed in each island-shaped semiconductor film are formed. Contact holes are formed by dry etching. In this case, an interlayer insulating film made of an organic resin material is first etched using a mixed gas of CF ₄ , O ₂ , and He as an etching gas, and then the protective insulating film 816 is etched using the etching gas as CF ₄ and O _2. To do. Furthermore, in order to increase the selection ratio with the island-shaped semiconductor film, the contact hole can be satisfactorily formed by switching the etching gas to CHF ₃ and etching the gate insulating film.

  Then, a conductive metal film is formed by sputtering or vacuum vapor deposition, a resist mask pattern is formed, and source and drain wirings 818 to 823, pixel electrodes 826, common wirings 824 and 827, and connection wirings 825 are formed by etching. Form. In this manner, an active matrix substrate having an IPS pixel portion configured as shown in FIG. 2 or FIG. 4 can be formed. Further, even when the active matrix substrate of this embodiment is used, the active matrix liquid crystal display device shown in Embodiment 2 can be manufactured.

  In this embodiment, another example in which the TFT structure of the active matrix substrate is different will be described with reference to FIG.

  The active matrix substrate shown in FIG. 16 includes a driving circuit 957 having a logic circuit portion 955 having a first p-channel TFT 950 and a first n-channel TFT 951 and a sampling circuit portion 956 made of a second n-channel TFT 952. In addition, a pixel TFT 953 and a pixel portion 958 having a storage capacitor 954 are formed. The TFT of the logic circuit portion 955 of the driver circuit 957 forms a shift register circuit, a buffer circuit, and the like, and the TFT of the sampling circuit 956 is basically formed of an analog switch.

In the active matrix substrate shown in this embodiment, a base film 902 is first formed on a substrate 901 with a thickness of 50 to 200 nm using a silicon oxide film, a silicon oxynitride film, or the like. Thereafter, island-shaped semiconductor films 903 to 907 are formed from a crystalline semiconductor film manufactured by a laser crystallization method or a thermal crystallization method. A gate insulating film 908 is formed thereon. The island-shaped semiconductor films 904 and 905 forming the n-channel TFT and the island-shaped semiconductor film 907 forming the storage capacitor are represented by phosphorus (P) at a concentration of 1 × 10 ¹⁶ to 1 × 10 ¹⁹ atoms / cm ^3. An impurity element imparting n-type is selectively added.

Then, gate electrodes 909 to 912, a gate wiring 914, a capacitor wiring 915, and a signal wiring 913 are formed using a material containing W or Ta as a component. The gate wiring, the capacitor wiring, and the signal wiring may be separately formed with a low efficiency material such as Al as in the first or third embodiment. Then, an n-type typified by phosphorus (P) at a concentration of 1 × 10 ¹⁹ to 1 × 10 ²¹ atoms / cm ³ is formed in a region outside the island-shaped semiconductor films 903 to 907 gate electrodes 909 to 912 and the capacitor wiring 915. An impurity element to be added is selectively added. Thus, channel formation regions 931 and 934, LDD regions 933 and 936, and source or drain regions 932 and 935 are formed in the first n-channel TFT 951 and the second n-channel TFT 952, respectively. The LDD region 939 of the pixel TFT 953 is formed in a self-aligned manner using the gate electrode 912 and is formed outside the channel formation region 937, and the source or drain region 938. It is formed in the same manner as the first and second n-channel TFTs.

  As in the third embodiment, the interlayer insulating film includes a first interlayer insulating film 916 made of an inorganic material such as silicon oxide, silicon nitride, or silicon oxynitride, polyimide, acrylic, polyimide amide, BCB (benzocyclobutene), or the like. And a second interlayer insulating film 917 made of the organic insulating material. Thereafter, a resist mask having a predetermined pattern is formed, and contact holes reaching the source region or the drain region formed in each island-shaped semiconductor film are formed. Then, a conductive metal film is formed by a sputtering method or a vacuum evaporation method, and source and drain wirings 918 to 923, a pixel electrode 926, common wirings 924 and 927, and a connection wiring 925 are formed. In this manner, an active matrix substrate having an IPS pixel portion configured as shown in FIG. 2 or FIG. 4 can be formed. Further, even when the active matrix substrate of this embodiment is used, the active matrix liquid crystal display device shown in Embodiment 2 can be manufactured.

  The first n-channel TFT 951 of the logic circuit 955 has a structure in which a GOLD region overlapping with the gate electrode is formed on the drain side. By this GOLD region, a high electric field region generated in the vicinity of the drain region can be relaxed to prevent the generation of hot carriers and to prevent the deterioration of the TFT. An n-channel TFT having such a structure is suitable for a buffer circuit or a shift register circuit. On the other hand, the second n-channel TFT 952 of the sampling circuit 956 has a structure in which a GOLD region and an LDD region are provided on the source side and the drain side, and prevents deterioration due to hot carriers in an analog switch that operates by inverting the polarity. The structure aims to reduce the current. The pixel TFT 953 has an LDD structure, is formed using a multi-gate, and has a structure for the purpose of reducing off-state current. On the other hand, the p-channel TFT is formed with a single drain structure, and impurity regions 929 and 930 to which a p-type impurity element is added are formed outside the channel formation region 928.

  As described above, the active matrix substrate shown in FIG. 16 specifically takes into account the optimization of the TFTs constituting each circuit according to the specifications required by the pixel portion and the drive circuit, and the operating characteristics and reliability of each circuit. It has a configuration.

  In Example 1, the gate electrode is formed of an element selected from Ta, W, Ti, and Mo, or an alloy material or a compound material containing the element, and the gate wiring is made of a material having a low resistivity such as Al or Cu. An example of forming this is shown. In this embodiment, an example in which Al is used for the gate electrode is shown. The steps for manufacturing the active matrix substrate are substantially the same as those in the first embodiment according to FIGS. 6 to 8, and the difference will be described here.

  In FIG. 6A, a first conductive film 508 is formed using a conductive film containing Ta, W, and Ti as components. For example, a Ta film, a W film, a Ta nitride film, or the like is formed by a sputtering method or a vacuum evaporation method. The second conductive film 509 is formed using a conductive film containing Al or Cu as a component. For example, an Al film containing 0.5 to 2 atomic% of scandium (Sc) is formed.

In the first etching process shown in FIG. 6B, taper etching of the Al film is performed using an ICP etching apparatus by a dry etching method using a mixed gas of boron trichloride (BCl ₃ ) and chlorine (Cl ₂ ). Do. In addition, the second etching process illustrated in FIG. 6C may be performed by a dry etching method similarly to the first etching process, but Al etching may be performed by a wet etching process using a phosphoric acid solution.

  Although not shown in detail in the drawing, the signal wiring 548, the gate wiring 549, and the capacitor wiring 550 are formed of the first conductive layer and the second conductive layer shown in this embodiment at the same time as the gate electrode.

After performing the doping treatment shown in FIGS. 6B to 7B, a first interlayer insulating film is formed on the gate electrodes 529 to 532, the signal wiring 548, the gate wiring 549, and the capacitor wiring 550 by a silicon nitride film or A silicon oxynitride film is formed to a thickness of 50 to 200 nm by a plasma CVD method. Thereafter, hydrogenation is performed at 300 to 500 ° C., preferably 350 to 450 ° C., in a nitrogen or inert gas atmosphere containing 1 to 3% hydrogen. Activation of the p-type or n-type impurity element added to the island-like semiconductor film is performed by a laser annealing method. As the laser beam, a solid laser such as a YAG laser, YVO ₄ laser, or YLF laser is used, and laser annealing is performed using the second harmonic (532 nm). Laser light emitted from the laser oscillator is condensed into a linear shape, a rectangular shape, or a rectangular shape by an optical system, and is irradiated to the island-shaped semiconductor film through the first interlayer insulating film. The second harmonic with a wavelength of 532 nm passes through the silicon nitride film or silicon oxynitride film formed as the first interlayer insulating film and is absorbed by the semiconductor film, so that the impurity element is activated by heating the semiconductor film. Suitable for doing. Further, since the second harmonic laser beam having a wavelength of 532 nm is almost reflected on the Al surface of the gate electrode, the island-like semiconductor film is heated preferentially, so that the impurity element is not changed without altering Al having low heat resistance. Can be activated.

  The subsequent steps may be performed in accordance with Embodiment 1, and the active matrix substrate shown in FIG. 8 can be manufactured. A liquid crystal display device as shown in Embodiment 2 can be manufactured using the active matrix substrate thus manufactured.

  In this embodiment, a method for manufacturing a semiconductor film which can be applied to the present invention will be described. In FIG. 21A, a base film 1602 made of a silicon oxynitride film is formed over the main surface of a substrate 1601, and an amorphous semiconductor film 1603 is formed thereover. The thickness of the amorphous semiconductor film may be 10 to 200 nm, preferably 30 to 100 nm. Further, an aqueous solution containing 10 ppm of the catalyst element in terms of weight is applied by a spin coating method to form the catalyst element-containing layer 1604 over the entire surface of the amorphous semiconductor film 1603. In addition, the catalyst element-containing layer 1604 may be formed to a thickness of 1 to 5 nm including a corresponding element by a sputtering method or a vacuum deposition method. Alternatively, the substrate may be exposed to glow discharge plasma generated by applying high-frequency power to an electrode made of the corresponding element. In addition to nickel (Ni), usable catalyst elements include germanium (Ge), iron (Fe), palladium (Pd), tin (Sn), lead (Pb), cobalt (Co), platinum ( Pt), copper (Cu), gold (Au), and other elements. The heat treatment for crystallization is performed by first releasing hydrogen remaining in the film at 350 to 500 ° C., and then performing the heat treatment at 500 to 600 ° C. for 4 to 12 hours, for example, 550 ° C. for 4 hours. A crystalline semiconductor film 1605 shown in FIG.

Next, a gettering step for removing the catalyst element used in the crystallization step from the crystalline semiconductor film is performed. By this gettering step, the concentration of the catalytic element in the crystalline semiconductor film is reduced to 1 × 10 ¹⁷ atoms / cm ³ or less, preferably 1 × 10 ¹⁶ atoms / cm ³ . First, a mask insulating film 1606 is formed to a thickness of 150 nm on the surface of the crystalline semiconductor layer 1605, an opening 1607 is provided by patterning, and a region where the crystalline semiconductor layer is exposed is provided. Phosphorus containing regions 1608 are provided in the crystalline semiconductor film by adding phosphorus to the portion by ion doping or the like (FIG. 21C).

In this state, when heat treatment is performed in a nitrogen atmosphere at 550 to 800 ° C. for 5 to 24 hours, for example, 600 ° C. for 12 hours, the phosphorus-containing region 1608 functions as a gettering site and remains in the crystalline semiconductor film 1605. The catalyst element obtained can be segregated in the phosphorus-containing region 1608 (FIG. 21D). Then, the mask insulating film 1606 and the phosphorus-containing region 1608 are removed by etching, whereby the concentration of the catalyst element used in the crystallization step is reduced to 1 × 10 ¹⁷ atoms / cm ³ or less. A quality semiconductor film can be obtained. After that, a gate insulating film 1610 is formed over the crystalline semiconductor film 1609 (FIG. 21E).

  In the example shown in FIG. 22, a base film 1702 and an amorphous semiconductor film 1703 are formed in this order over a substrate 1701, and a silicon oxide film 1704 is formed on the surface of the amorphous semiconductor film 1703. At this time, the thickness of the silicon oxide film 1704 was set to 150 nm. Further, the silicon oxide film 1704 is patterned to selectively form openings 1705, and then an aqueous solution containing 10 ppm catalyst element in terms of weight is applied. Thus, a catalyst element-containing layer 1706 is formed, and the catalyst-containing layer 1706 is in contact with the amorphous semiconductor film 1703 only through the opening 1705 (FIG. 22A).

  Next, heat treatment is performed at 500 to 650 ° C. for 4 to 24 hours, for example, 570 ° C. for 14 hours, so that a crystalline semiconductor film 1707 is formed. In this crystallization process, the region of the amorphous semiconductor film in contact with the catalytic element is first crystallized, and then the crystallization proceeds laterally from there. The crystalline semiconductor film 1707 formed in this way is composed of a collection of rod-like or needle-like crystals, and each crystal grows with a specific direction as viewed macroscopically, so that the crystallinity is uniform. (FIG. 22B)).

Next, similarly to FIG. 21, a step of removing the catalyst element used in the crystallization step from the crystalline semiconductor film is performed. A step of adding phosphorus is performed on the substrate in the same state as FIG. 22B to provide a phosphorus-containing region 1709 in the crystalline semiconductor film. The phosphorus content in this region is 1 × 10 ¹⁹ to 1 × 10 ²¹ atoms / cm ³ (FIG. 22C). In this state, when heat treatment is performed in a nitrogen atmosphere at 550 to 800 ° C. for 5 to 24 hours, for example, 600 ° C. for 12 hours, the phosphorus-containing region 1709 functions as a gettering site and remains in the crystalline semiconductor layer 1707. The catalyst element can be segregated in the phosphorus-containing region 1709 (FIG. 22D).

  Then, the mask oxide film and the phosphorus-containing region 1709 are removed by etching, so that an island-shaped crystalline semiconductor film 1710 is formed. Then, a gate insulating film 1711 is formed in close contact with the crystalline semiconductor film 1710. The gate insulating film 1711 is formed of one layer or a plurality of layers selected from a silicon oxide film and a silicon oxynitride film. The thickness may be 10 to 100 nm, preferably 50 to 80 nm (FIG. 22E).

Alternatively, halogen (typically chlorine) without performing this ring gettering step
A method of removing the catalyst element from the crystalline semiconductor film by performing heat treatment in an atmosphere containing oxygen and oxygen can also be applied. Further, after the gate insulating film 1711 is formed, a thermal oxide film is formed at the interface between the crystalline semiconductor film 1710 and the gate insulating film 1711 when heat treatment is performed, for example, at 950 ° C. for 30 minutes in an atmosphere containing halogen and oxygen. A good interface with a low interface state density can be formed. The treatment temperature may be selected in the range of 700 to 1100 ° C., and the treatment time may be selected between 10 minutes and 8 hours.

  Further, the gettering process using phosphorus described with reference to FIGS. 21 and 22 can be performed simultaneously in the thermal annealing step in the activation shown in FIG. In that case, the impurity region to which phosphorus is added becomes a gettering site, and the catalytic element can be segregated from the channel formation region to the impurity region.

  Using the island-shaped semiconductor film thus manufactured, the active matrix substrate shown in Examples 1, 3, 4, and 5 can be manufactured.

  In the active matrix substrate shown in Embodiments 1, 3, and 4, the number of photomasks used in the process can be set to five by simultaneously forming the gate electrode, the gate wiring, the signal wiring, and the capacitor wiring with the same material. it can. That is, a total of five photomasks are used for forming an island-shaped semiconductor film, forming a gate electrode and other wirings, forming a mask when a p-type impurity is added, forming contact holes, pixel electrodes, common wirings, and the like. The reduction in the number of masks not only reduces the photolithography process, but also eliminates the need for film formation, cleaning, and etching steps before and after that, which not only reduces the manufacturing cost but also improves the process yield. it can.

  In this embodiment, a semiconductor device incorporating an active matrix liquid crystal display device as shown in Embodiment 2 will be described with reference to FIGS.

  Examples of such a semiconductor device include a portable information terminal (electronic notebook, mobile computer, mobile phone, etc.), a video camera, a still camera, a personal computer, a television, and the like. Examples of these are shown in FIGS. 19 and 20.

  FIG. 19A illustrates a mobile phone, which includes a main body 9001, an audio output portion 9002, an audio input portion 9003, a display device 9004, operation switches 9005, and an antenna 9006. The present invention can be applied to a display device 9004 including an active matrix substrate.

  FIG. 19B illustrates a video camera which includes a main body 9101, a display device 9102, an audio input portion 9103, operation switches 9104, a battery 9105, and an image receiving portion 9106. The present invention can be applied to a display device 9102 including an active matrix substrate.

  FIG. 19C illustrates a mobile computer or a portable information terminal, which includes a main body 9201, a camera portion 9202, an image receiving portion 9203, operation switches 9204, and a display device 9205. The present invention can be applied to a display device 9205 including a TFT and an active matrix substrate which constitute a reading circuit of an image sensor provided as the image receiving portion 9203.

  FIG. 19D illustrates a head mounted display which includes a main body 9301, a display device 9302, and an arm portion 9303. The present invention can be applied to the display device 9302.

  FIG. 19E illustrates a television set including a main body 9401, speakers 9402, a display device 9403, a reception device 9404, an amplification device 9405, and the like. The active matrix liquid crystal display device of the present invention can be applied to the display device 9403.

  FIG. 19F illustrates a portable book which includes a main body 9501, display devices 9502 and 9503, a storage medium 9504, operation switches 9505, and an antenna 9506, and data stored in a minidisc (MD) or DVD, The data received by the antenna is displayed. The display devices 9502 and 9503 are direct-view display devices, and the present invention can be applied to them.

  FIG. 20A illustrates a personal computer which includes a main body 9601, an image input portion 9602, a display device 9603, and a keyboard 9604. The active matrix liquid crystal display device of the present invention can be applied to the display device 9603.

  FIG. 20B shows a player using a recording medium (hereinafter referred to as a recording medium) on which a program is recorded. The player includes a main body 9701, a display device 9702, a speaker portion 9703, a recording medium 9704, and operation switches 9705. This apparatus uses a DVD (Digital Versatile Disc), CD, or the like as a recording medium, and can perform music appreciation, movie appreciation, games, and the Internet. The active matrix liquid crystal display device of the present invention can be applied to the display device 9702.

  FIG. 20C illustrates a digital camera which includes a main body 9801, a display device 9802, an eyepiece unit 9803, an operation switch 9804, and an image receiving unit (not illustrated). The active matrix liquid crystal display device of the present invention can be applied to the display device 9802.

The top view which shows the process of the pixel part in one Embodiment of this invention. The top view which shows the process of the pixel part in one Embodiment of this invention. 1 is a circuit diagram of a pixel portion in one embodiment of the present invention. FIG. 4 is a top view of a pixel portion in one embodiment of the present invention. The top view explaining the structure of the pixel part of the conventional IPS system. 9 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit. 9 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit. 9 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit. 1 is a cross-sectional view of an active matrix liquid crystal display device of the present invention. 4 is a cross-sectional view illustrating a structure of a pixel portion of an active matrix liquid crystal display device of the present invention. FIG. The top view of an active-matrix liquid crystal display device and the schematic diagram which expanded a part of pixel. The assembly drawing of an active matrix type liquid crystal display device. Sectional drawing explaining the structure of a terminal part. Sectional drawing explaining the structure of a terminal part and wiring in detail. FIG. 6 is a cross-sectional view illustrating a structure of a pixel TFT and a driver circuit TFT. FIG. 6 is a cross-sectional view illustrating a structure of a pixel TFT and a driver circuit TFT. FIG. 4 is a top view of a pixel portion in one embodiment of the present invention. FIG. 4 is a top view of a pixel portion in one embodiment of the present invention. 4A and 4B each illustrate an example of an electronic device using an active matrix liquid crystal display device of the present invention. 4A and 4B each illustrate an example of an electronic device using an active matrix liquid crystal display device of the present invention. 10A and 10B illustrate a step of manufacturing a crystalline semiconductor film. 10A and 10B illustrate a step of manufacturing a crystalline semiconductor film.

Claims (8)

A semiconductor film formed on the first substrate;
A first insulating film formed on the semiconductor film;
A gate electrode, a gate wiring, and a signal wiring formed on the first insulating film in the same layer with the same material;
A second insulating film formed on the gate electrode, the gate wiring and the signal wiring;
A pixel electrode formed in the same layer with the same material on the second insulating film, electrically connected to the semiconductor film, a common wiring, and a connection electrode electrically connected to the signal wiring;
A red, blue and green color filter layer formed corresponding to each pixel on a second substrate facing the first substrate;
The pixel electrode and the common electrode are arranged so that an electric field is generated in a direction parallel to the substrate surface,
The red, blue, and green color filter layers each have a portion that overlaps the color filter layer of the adjacent pixel between adjacent pixels,
The signal wiring is disposed so as to overlap a portion where the color filter layer overlaps, the common wiring is disposed so as to completely overlap except for a connection portion between the signal wiring and the signal wiring, and the pixel electrode is A liquid crystal display device, wherein the liquid crystal display device is disposed so as not to overlap the signal wiring. A semiconductor film formed on the first substrate;
A first insulating film formed on the semiconductor film;
A gate electrode, a gate wiring, and a signal wiring formed on the first insulating film in the same layer with the same material;
A second insulating film formed on the gate electrode, the gate wiring and the signal wiring;
A pixel electrode electrically connected to the semiconductor film, a common wiring, and a connection electrode electrically connected to the signal wiring, which are formed on the second insulating film in the same layer with the same material,
A red, blue and green color filter layer formed corresponding to each pixel on a second substrate facing the first substrate;
The pixel electrode and the common electrode are arranged so that an electric field is generated in a direction parallel to the substrate surface,
The red, blue, and green color filter layers each have a portion that overlaps the color filter layer of the adjacent pixel between adjacent pixels,
The signal wiring is disposed so as to overlap a portion where the color filter layer overlaps, the common wiring is disposed so as to completely overlap except for a connection portion between the signal wiring and the signal wiring, and the pixel electrode is Arranged not to overlap the signal wiring,
A liquid crystal display device, wherein a distance between the pixel electrode and the common electrode is 10 to 20 μm. 3. The liquid crystal display device according to claim 1, further comprising a capacitor wiring formed in the same layer with the same material as the gate electrode, the gate wiring, and the signal wiring. 4. The liquid crystal display device according to claim 1, wherein each of the pixel electrode, the common electrode, and the signal wiring has a dogleg shape. Forming a semiconductor film on the first substrate;
Forming a first insulating film on the semiconductor film;
A gate electrode, a gate wiring, and a signal wiring are simultaneously formed on the first insulating film;
Forming a second insulating film on the gate electrode, the gate wiring, and the signal wiring;
A pixel electrode that is electrically connected to the semiconductor film, a common wiring, and a connection electrode that is electrically connected to the signal wiring are simultaneously formed on the second insulating film,
The pixel electrode and the common electrode are arranged so that an electric field is generated in a direction parallel to the substrate surface,
Forming red, blue and green color filter layers corresponding to each pixel on a second substrate facing the first substrate;
The red, blue, and green color filter layers each have a portion that overlaps the color filter layer of the adjacent pixel between adjacent pixels,
The signal wiring is arranged so as to overlap with a portion where the color filter layer overlaps,
The liquid crystal display device, wherein the common wiring is disposed so as to completely overlap except for a connection portion between the signal wiring and the signal wiring, and the pixel electrode is disposed so as not to overlap the signal wiring. Manufacturing method. Forming a semiconductor film on the first substrate;
Forming a first insulating film on the semiconductor film;
A gate electrode, a gate wiring, and a signal wiring are simultaneously formed on the first insulating film;
Forming a second insulating film on the gate electrode, the gate wiring, and the signal wiring;
A pixel electrode that is electrically connected to the semiconductor film, a common wiring, and a connection electrode that is electrically connected to the signal wiring are simultaneously formed on the second insulating film,
The pixel electrode and the common electrode are arranged so that an electric field is generated in a direction parallel to the substrate surface,
Forming red, blue and green color filter layers corresponding to each pixel on a second substrate facing the first substrate;
The red, blue, and green color filter layers each have a portion that overlaps the color filter layer of the adjacent pixel between adjacent pixels,
The signal wiring is arranged so as to overlap with a portion where the color filter layer overlaps,
The common wiring is disposed so as to completely overlap except for the signal wiring and the connection portion of the signal wiring, and the pixel electrode is disposed so as not to overlap the signal wiring.
A method for manufacturing a liquid crystal display device, wherein an interval between the pixel electrode and the common electrode is 10 to 20 μm. 7. The method for manufacturing a liquid crystal display device according to claim 5, further comprising a capacitor wiring formed simultaneously with the gate electrode, the gate wiring, and the signal wiring. 8. The method for manufacturing a liquid crystal display device according to claim 5, wherein each of the pixel electrode, the common electrode, and the signal wiring has a dogleg shape.

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