JP4384008B2 - Level shift circuit - Google Patents

Description

  According to the present invention, for a binary input signal having an amplitude between a predetermined first positive power supply voltage and a predetermined negative power supply voltage, a voltage of only a high level is larger than the first positive power supply voltage. The present invention relates to a level shift circuit using a high-breakdown-voltage switching element that outputs a level-shifted signal.

FIG. 14 is a circuit diagram showing an example of a conventional level shift circuit.
In FIG. 14, the PMOS transistor Pa and the NMOS transistor Ma are turned on or off according to the input signal Sin to control the gate voltage of the DMOS transistor DMa, and the DMOS transistor is controlled by the current mirror circuit and the resistor Ra of the NMOS transistors Mb and Mc. The current flowing through DMa is limited.

Although different from the present invention, a configuration in which a constant current source connected to the power supply voltage VCC is connected to the gate of the MOS transistor, and an NMOS transistor that controls connection between the gate and the ground voltage in accordance with a control signal is provided. (For example, refer to Patent Document 1). In addition, there is a circuit having a configuration in which a voltage source VG is connected to a gate of a MOS transistor via a constant current source (see, for example, Patent Document 2), but these are different from the present invention.
Japanese Patent Laid-Open No. 4-56511 Japanese Patent Laid-Open No. 10-4342

  However, in the circuit as shown in FIG. 14, in order to set the current value of the current flowing through the DMOS transistor DMa, the on-resistance of the PMOS transistor Pa, the resistance value of the resistor Rb, the threshold voltage of the DMOS transistor DMa, and the NMOS transistor There is a problem that the Mc gate-source voltage Vgs needs to be set, and the setting is complicated.

  The present invention has been made to solve the above-described problems, and flows to a high voltage switching element using a constant current circuit that supplies a constant current according to an input control signal on the low voltage side. An object of the present invention is to obtain a level shift circuit capable of easily setting the value of a current flowing through a high voltage switching element by performing current supply control and switching control of the high voltage switching element.

The level shift circuit according to the present invention shifts and outputs only a high level voltage with respect to a binary input signal having an amplitude of a predetermined first positive power supply voltage and a predetermined negative power supply voltage. In the level shift circuit,
A switching element that outputs a current having a predetermined second positive power supply voltage higher than the first positive power supply voltage when the control electrode is biased with a predetermined voltage and is turned on;
A constant current circuit section that controls supply of a predetermined first constant current to the switching element according to the input signal, and that operates using the first positive power supply voltage as a power source;
With
The switching element is turned on or off depending on whether or not a current is supplied from the constant current circuit unit, and the high-level voltage of the input signal is level-shifted and output.

  According to the level shift circuit of the present invention, the first constant current is supplied according to the signal level of the binary input signal having the amplitude of the first positive power supply voltage and the negative power supply voltage on the low voltage side. The current flowing through the switching element is controlled only by setting the constant current value supplied from the constant current circuit section while performing the switching control of the switching element by controlling the supply of the current flowing through the switching element using the current circuit section. The value can be easily set, and the design can be made more efficient.

Next, the present invention will be described in detail based on the embodiments shown in the drawings.
Embodiment 1 FIG.
FIG. 1 is a diagram illustrating a circuit example of a level shift circuit according to the first embodiment of the present invention.
The level shift circuit 1 of FIG. 1 responds to a binary input signal Sin having an amplitude of a predetermined first positive power supply voltage (hereinafter referred to as a first power supply voltage) VCC1 from a ground voltage that is a negative power supply voltage. The high level voltage is level-shifted to a voltage higher than the first power supply voltage VCC1 and output as the output signal Sout.

In FIG. 1, a level shift circuit 1 includes a constant current circuit 2 that supplies a predetermined constant current i1 according to the signal level of an input signal Sin, and a DMOS (double-diffused metal oxide semiconductor) that forms a high-breakdown-voltage switching element. The transistor DM1 and a resistor R1 constituting a load of the DMOS transistor DM1 are included. The constant current circuit 2 operates using the first power supply voltage VCC1 as a power supply, and the DMOS transistor DM1 has a predetermined second positive power supply voltage (hereinafter referred to as a second power supply voltage) higher than the first power supply voltage VCC1 through the resistor R1. (This is called a voltage.) Current output control using VCC2 as a power source is performed. For example, the first power supply voltage VCC1 is 15V, while the second power supply voltage VCC2 is 600 to 1200V.
The resistor R1 is connected between the second power supply voltage VCC2 and the drain of the DMOS transistor DM1, the constant current circuit 2 is connected between the source of the DMOS transistor DM1 and the ground voltage, and the gate of the DMOS transistor DM1 is connected to the first gate. One power supply voltage VCC1 is input. The constant current circuit 2 is a constant current circuit section, the DMOS transistor DM1 is a switching element, and the constant current i1 is a first constant current.

For example, the constant current circuit 2 stops the supply of the constant current i1 when the input signal Sin is at a high level, and supplies the constant current i1 when the input signal Sin is at a low level. When the current supply from the constant current circuit 2 is stopped, the DMOS transistor DM1 is turned off. When the current supply from the constant current circuit 2 is performed, the DMOS transistor DM1 is turned on. In this way, the input signal Sin having the amplitude of the first power supply voltage VCC1 is level-shifted only by the high level voltage and output as the output signal Sout.
The constant current circuit 2 includes a constant current source 5 that supplies a predetermined constant current i2 and NMOS transistors M1 to M3. The NMOS transistors M2 and M3 form a current mirror circuit. The constant current source 5 forms a first constant current source, and the NMOS transistor M1 forms a control circuit.

  A constant current source 5 and an NMOS transistor M1 are connected in series between the first power supply voltage VCC1 and the ground voltage, and an input signal Sin is input to the gate of the NMOS transistor M1. An NMOS transistor M2 is connected in parallel with the NMOS transistor M1, and an NMOS transistor M3 is connected between the source of the DMOS transistor DM1 and the ground voltage. The gates of the NMOS transistors M2 and M3 are connected, and the connection is connected to the drain of the NMOS transistor M2.

In such a configuration, when the high-level input signal Sin is input, the NMOS transistor M1 is turned on. Therefore, the constant current i2 from the constant current source 5 flows to the ground voltage via the NMOS transistor M1, so that the NMOS transistors M2 and M3 are turned off and the DMOS transistor DM1 is turned off. For this reason, the current from the second power supply voltage VCC2 is output via the resistor R1, and a high-level signal level-shifted to a voltage higher than the first power supply voltage VCC1 is output as the output signal Sout.
On the other hand, when the low level input signal Sin is input, the NMOS transistor M1 is turned off. Therefore, the NMOS transistors M2 and M3 are turned on, and a current corresponding to the transistor ratio of the NMOS transistors M2 and M3 is supplied from the NMOS transistor M3 with respect to the constant current i2 from the constant current source 5. Therefore, the DMOS transistor DM1 is turned on, and a low level signal is output as the output signal Sout.

The current flowing through the DMOS transistor DM1 is determined by the constant current i1 supplied from the constant current circuit 2, and the constant current value supplied from the constant current circuit 2 is the value of the constant current i2 supplied from the constant current source 5 and the NMOS. It is determined by setting the transistor size ratio of the transistors M2 and M3.
The constant current source 5 in FIG. 1 may be formed by a current mirror circuit formed by the constant current source 7 and the PMOS transistors P1 and P2 as shown in FIG.

  In this way, the constant current circuit 2 that supplies a constant current according to the signal level of the binary input signal Sin having the amplitude of the first power supply voltage VCC1 on the low voltage side is a high breakdown voltage switching element. The switching control of the DMOS transistor DM1 is performed by controlling the supply of the current flowing through the DMOS transistor DM1, and the current value flowing through the DMOS transistor DM1 can be easily set only by setting the constant current value of the constant current circuit 2. Can do.

Embodiment 2. FIG.
In FIG. 1 in the first embodiment, the first power supply voltage VCC1 is not constant. However, as shown in FIG. 3, the constant current circuit 2 uses the internal power supply in which the first power supply voltage VCC1 is constant. The voltage VREG may be operated as a power source. In this case, the internal power source voltage VREG is input to the gate of the DMOS transistor DM1. In this case, when the input signal Sin is a signal having an amplitude of the internal power supply voltage VREG, for example, an amplitude of 0 to 5V, in FIG. It was necessary to shift the level to a signal having the amplitude of the voltage VCC1. However, if it is made like FIG. 3, the circuit which makes such a level shift becomes unnecessary, and also the proof pressure of the MOS transistor which comprises the constant current circuit 2 can be made small, and size reduction can be achieved. The internal power supply voltage VREG forms a first constant voltage.

Embodiment 3 FIG.
In the first and second embodiments, the first power supply voltage VCC1 or the internal power supply voltage VREG is input to the gate of the DMOS transistor DM1, but the voltage input to the gate of the DMOS transistor DM1 is set. You may be able to do it.
FIG. 4 is a diagram showing a circuit example of the level shift circuit in such a case. In FIG. 4, the same or similar elements as those in FIG. 1 are denoted by the same reference numerals as those in FIG. 1, and description thereof is omitted here, and only differences from FIG. 1 are described.
4 is different from FIG. 1 in that a series circuit of resistors R2 and R3 for dividing the first power supply voltage VCC1 is added and the divided voltage is input to the gate of the DMOS transistor DM1. The resistors R2 and R3 form a voltage generation circuit unit.
In this way, the gate of the DMOS transistor DM1 can be biased with an arbitrary voltage, and the resistors R2 and R3 have the same temperature coefficient, and the ratio of the resistance values of the resistors R2 and R3 does not change with temperature change. The temperature characteristic of the divided voltage generated by the resistors R2 and R3 can be eliminated.

Embodiment 4 FIG.
Instead of the resistor R3 in FIG. 4 in the third embodiment, one or a plurality of diodes D1 to Dn (n is an integer of n> 0) may be connected in series. The circuit is shown in FIG. In FIG. 5, the same or similar elements as those in FIG. 4 are denoted by the same reference numerals as those in FIG. 4, and description thereof is omitted here, and only differences from FIG. 4 are described.
5 is different from FIG. 4 in that the resistor R3 in FIG. 4 is replaced with a series circuit in which diodes D1 to Dn are connected in series. The resistor R2 and the diodes D1 to Dn form a voltage generation circuit unit, and the diodes D1 to Dn form a diode circuit.

In FIG. 5, diodes D1 to Dn are connected in series in the forward direction between the connection portion of the resistor R2 and the gate of the DMOS transistor DM1 and the ground voltage, and the DMOS is changed by changing the number n of the diodes. The gate voltage of the transistor DM1 can be set. Assuming that the forward voltages of the diodes D1 to Dn are 0.7V, the gate voltage of the DMOS transistor DM1 is (0.7 × n) V.
Thus, the gate voltage of the DMOS transistor DM1 can be easily set by changing the number n of diodes connected in series between the gate of the DMOS transistor DM1 and the ground voltage. The resistor R2 has a negative temperature characteristic, whereas the diodes D1 to Dn have a positive temperature characteristic. For this reason, each temperature characteristic of resistance R2 and diode D1-Dn can be canceled, and temperature characteristic can be corrected.

Embodiment 5 FIG.
The diodes D1 to Dn in FIG. 5 in the fourth embodiment may be formed by MOS transistors, and in this case, FIG. 5 becomes as shown in FIG. 6 that are the same as or similar to those in FIG. 5 are denoted by the same reference numerals as those in FIG. 5, and description thereof will be omitted here, and only differences from FIG. 5 will be described.
6 is different from FIG. 5 in that the diodes D1 to Dn in FIG. 5 are replaced with NMOS transistors MD1 to MDn each having a gate and a drain connected to each other.
By doing so, the same effect as in the case of FIG. 5 can be obtained, and the bipolar process for forming the diodes D1 to Dn can be eliminated, and the manufacturing process can be simplified.

Embodiment 6 FIG.
In FIGS. 4 to 6 in the third to fifth embodiments, a predetermined constant voltage may be input to the gate of the DMOS transistor DM1, and in this case, FIGS. It becomes like 7. 7, the same or similar parts as those in FIG. 4 are denoted by the same reference numerals as those in FIG. 4, and the description thereof will be omitted here and only the differences from FIG. 4 will be described.
7 differs from FIG. 4 in that the resistor R3 in FIG. 4 is replaced with a Zener diode ZD1. The resistor R2 and the Zener diode ZD1 form a constant voltage generation circuit unit, and the Zener voltage of the Zener diode ZD1 forms a second constant voltage.
In FIG. 7, the cathode of the Zener diode ZD1 is connected to the connection between the resistor R2 and the gate of the DMOS transistor DM1, and the anode of the Zener diode ZD1 is connected to the ground voltage.
By doing so, the gate voltage of the DMOS transistor DM1 can be easily set in design, and variations in the gate voltage of the DMOS transistor DM1 can be reduced, and the operation of the DMOS transistor DM1 is stabilized. be able to.

Embodiment 7 FIG.
The resistor R2 of FIG. 4 in the third embodiment may be replaced with a constant current source 11 that supplies a predetermined constant current i3. In this case, FIG. 4 becomes as shown in FIG. In FIG. 8, the same or similar elements as those in FIG. 4 are denoted by the same reference numerals as those in FIG. 4, and description thereof will be omitted here and only differences will be described.
In FIG. 8, a constant current source 11 is connected between the first power supply voltage VCC1 and the gate of the DMOS transistor DM1. The constant current source 11 is a second constant current source, and the constant current source 11 and the resistor R3 form a voltage generation circuit unit.
Thus, the gate voltage of the DMOS transistor DM1 can be easily set by setting the resistance value of the resistor R3, and the gate voltage of the DMOS transistor DM1 can have a positive temperature characteristic. This is effective when the circuit to which the output signal Sout is input has negative temperature characteristics.

Embodiment 8 FIG.
The resistor R2 in FIG. 5 in the fourth embodiment may be replaced with a constant current source 11 that supplies a predetermined constant current i3. In this case, FIG. 5 becomes as shown in FIG. In FIG. 9, the same or similar parts as those in FIG. 5 are denoted by the same reference numerals as those in FIG. 5, and description thereof will be omitted here, and only differences will be described.
In FIG. 9, a constant current source 11 is connected between the first power supply voltage VCC1 and the gate of the DMOS transistor DM1. The constant current source 11 and the diodes D1 to Dn form a voltage generation circuit unit.
Thus, the gate voltage of the DMOS transistor DM1 can be easily set by changing the number n of diodes connected in series between the gate of the DMOS transistor DM1 and the ground voltage. Further, the gate voltage of the DMOS transistor DM1 can have a negative temperature characteristic, which is effective when the circuit to which the output signal Sout is input has a positive temperature characteristic.

Embodiment 9 FIG.
The resistor R2 of FIG. 6 in the fifth embodiment may be replaced with a constant current source 11 that supplies a predetermined constant current i3. In this case, FIG. 6 becomes as shown in FIG. In FIG. 10, the same or similar elements as those in FIG. 6 are denoted by the same reference numerals as those in FIG. 6, and the description thereof will be omitted here and only the differences will be described.
In FIG. 10, a constant current source 11 is connected between the first power supply voltage VCC1 and the gate of the DMOS transistor DM1. The constant current source 11 and the NMOS transistors MD1 to MDn constitute a voltage generation circuit unit.
Thus, the gate voltage of the DMOS transistor DM1 can be easily set by changing the number n of diode-connected NMOS transistors connected in series between the gate of the DMOS transistor DM1 and the ground voltage. . Further, the bipolar process for forming the diode can be eliminated, and the manufacturing process can be simplified.

Embodiment 10 FIG.
The resistor R2 in FIG. 7 in the sixth embodiment may be replaced with a constant current source 11 that supplies a predetermined constant current i3. In this case, FIG. 7 becomes as shown in FIG. In FIG. 11, the same or similar parts as those in FIG. 7 are denoted by the same reference numerals as those in FIG. 7.
In FIG. 11, a constant current source 11 is connected between the first power supply voltage VCC1 and the gate of the DMOS transistor DM1. The constant current source 11 and the Zener diode ZD1 form a constant voltage generation circuit unit.
By doing so, the gate voltage of the DMOS transistor DM1 can be easily set in design, and variations in the gate voltage of the DMOS transistor DM1 can be reduced, and the operation of the DMOS transistor DM1 is stabilized. be able to. Further, the gate voltage of the DMOS transistor DM1 can have a positive temperature characteristic, which is effective when the circuit to which the output signal Sout is input has a negative temperature characteristic.

Embodiment 11 FIG.
In the sixth and tenth embodiments, the Zener voltage is input to the gate of the DMOS transistor DM1 by the Zener diode ZD1, but the voltage input to the gate of the DMOS transistor DM1 can be set. Good.
FIG. 12 is a diagram showing a circuit example of the level shift circuit in such a case. In FIG. 12, the case of FIG. 11 is shown as an example, and the same or similar parts as in FIG. 11 are denoted by the same reference numerals as in FIG. Only the differences will be described.

12 is different from FIG. 11 in that a series circuit of resistors R4 and R5 for dividing the Zener voltage of the Zener diode ZD1 is added and the divided voltage is input to the gate of the DMOS transistor DM1. . The resistors R4 and R5 form a voltage dividing circuit, and the constant current source 11, the Zener diode ZD1, and the resistors R4 and R5 form a constant voltage generating circuit unit.
In this way, the gate of the DMOS transistor DM1 can be biased at an arbitrary voltage, the fine adjustment of the gate voltage of the DMOS transistor DM1 is easy, and the variation in the gate voltage can be reduced. Can be stabilized. Further, the gate voltage of the DMOS transistor DM1 can have a positive temperature characteristic, which is effective when the circuit to which the output signal Sout is input has a negative temperature characteristic. Further, the case of FIG. 7 is the same as that of FIG. 12 and the same effect can be obtained, but the description thereof is omitted.

8 to 12, when the constant current source 5 is formed of a current mirror circuit formed of the constant current source 7 and the PMOS transistors P1 and P2, as shown in FIG. The source 11 may be composed of a PMOS transistor P3 as shown in FIG.
In FIG. 13, the PMOS transistor P3 is connected between the first power supply voltage VCC1 and the gate of the DMOS transistor DM1, and the gate is connected to the connection portion of each gate of the PMOS transistors P1 and P2. FIG. 13 shows the case of FIG. 8 as an example, but the same applies to the cases of FIGS.
4 to 12, when the constant current source 5 is formed by the current mirror circuit formed by the constant current source 7 and the PMOS transistors P1 and P2, it is the same as the case of FIG. The description is omitted.

It is the figure which showed the circuit example of the level shift circuit in Embodiment 1 of this invention. It is the figure which showed the other circuit example of the level shift circuit in Embodiment 1 of this invention. It is the figure which showed the circuit example of the level shift circuit in Embodiment 2 of this invention. It is the figure which showed the circuit example of the level shift circuit in Embodiment 3 of this invention. It is the figure which showed the circuit example of the level shift circuit in Embodiment 4 of this invention. It is the figure which showed the circuit example of the level shift circuit in Embodiment 5 of this invention. It is the figure which showed the circuit example of the level shift circuit in Embodiment 6 of this invention. It is the figure which showed the circuit example of the level shift circuit in Embodiment 7 of this invention. It is the figure which showed the circuit example of the level shift circuit in Embodiment 8 of this invention. It is the figure which showed the circuit example of the level shift circuit in Embodiment 9 of this invention. It is the figure which showed the circuit example of the level shift circuit in Embodiment 10 of this invention. It is the figure which showed the circuit example of the level shift circuit in Embodiment 11 of this invention. It is the figure which showed the other circuit example of the level shift circuit in Embodiment 7 of this invention. It is the circuit diagram which showed the example of the conventional level shift circuit.

Explanation of symbols

1 level shift circuit, 2 constant current circuit, 5, 7, 11 constant current source, DM1 DMOS transistor, M1 to M3, MD1 to MDn NMOS transistor, P1 to P3 PMOS transistor, R1 to R5 resistor, D1 to Dn diode, ZD1 Zener diode

Claims (15)

In a level shift circuit that outputs a level-shifted voltage of only a high level with respect to a binary input signal having an amplitude between a predetermined first positive power supply voltage and a predetermined negative power supply voltage.
A switching element that outputs a current having a predetermined second positive power supply voltage higher than the first positive power supply voltage when the control electrode is biased with a predetermined voltage and is turned on;
A constant current circuit section that controls supply of a predetermined first constant current to the switching element according to the input signal, and that operates using the first positive power supply voltage as a power source;
With
The level shift circuit according to claim 1, wherein the switching element is turned on or off depending on whether or not a current is supplied from the constant current circuit unit, and only a high level voltage of the input signal is level shifted and output. The constant current circuit section is
A first constant current source that generates and outputs a predetermined second constant current using the first positive power supply voltage as a power source;
A current mirror circuit that generates the first constant current proportional to the second constant current and supplies the first constant current to the switching element;
A control circuit that performs input control of the second constant current to the current mirror circuit in accordance with the input signal and performs current output control on the current mirror circuit;
The level shift circuit according to claim 1, further comprising:   3. The level shift circuit according to claim 1, wherein the switching element has a control electrode biased with a first positive power supply voltage.   3. The level shift circuit according to claim 1, wherein the switching element has a control electrode biased with a predetermined first constant voltage.   A voltage generation circuit unit that generates and outputs a predetermined voltage from the first positive power supply voltage, and the switching element has a control electrode biased by a voltage from the voltage generation circuit unit. Item 3. The level shift circuit according to Item 1 or 2.   The level shift circuit according to claim 5, wherein the voltage generation circuit unit includes a plurality of resistors that divide and output the first positive power supply voltage.   The voltage generation circuit unit includes a diode circuit formed of one diode or a plurality of diodes connected in series, and a resistor that supplies a current that uses the first positive power supply voltage as a power source to the diode circuit. 6. The level shift circuit according to claim 5, wherein the switching element is biased with a control electrode having a forward voltage of a diode forming the diode circuit or a voltage obtained by adding a forward voltage of each diode. .   The voltage generation circuit unit includes a resistor and a second constant current source that uses a first positive power supply voltage that supplies a predetermined third constant current to the resistor as a power source. 6. The level shift circuit according to claim 5, wherein the level shift circuit is biased by a voltage generated in the resistor.   The voltage generation circuit unit includes a diode circuit composed of one diode or a plurality of diodes connected in series, and a first positive power supply voltage that supplies a predetermined third constant current to the diode circuit as a power source. The switching element is biased with a control electrode biased by a forward voltage of a diode forming the diode circuit or a voltage obtained by adding a forward voltage of each diode. The level shift circuit according to claim 5.   10. The level shift circuit according to claim 7, wherein the diode constituting the voltage generation circuit unit is formed of a MOS transistor.   The switching element includes a constant voltage generation circuit unit that generates and outputs a predetermined second constant voltage from the first positive power supply voltage, and the switching element is biased by a second constant voltage from the constant voltage generation circuit unit. The level shift circuit according to claim 1, wherein the level shift circuit is provided.   The constant voltage generation circuit unit includes a Zener diode and a resistor that supplies current to the Zener diode using a first positive power supply voltage as a power source. The switching element has a control electrode whose Zener voltage is the Zener diode. 12. The level shift circuit according to claim 11, wherein the level shift circuit is biased by using.   The constant voltage generation circuit unit includes a Zener diode, and a second constant current source that uses a first positive power supply voltage that supplies a predetermined third constant current to the Zener diode as a power source, and the switching element includes: 12. The level shift circuit according to claim 11, wherein the control electrode is biased by using a Zener voltage of the Zener diode.   14. The level shift circuit according to claim 12, wherein a control electrode of the switching element is biased by a Zener voltage of the Zener diode. The constant voltage generation circuit unit includes a voltage dividing circuit that divides and outputs the Zener voltage at a predetermined voltage dividing ratio, and the switching element has a control electrode biased by a divided voltage from the voltage dividing circuit. The level shift circuit according to claim 12 or 13,

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