JP4379285B2 - Display panel - Google Patents

Description

  The present invention relates to a display panel using light emitting elements as subpixels.

  Organic electroluminescence display panels can be broadly classified into passive drive type and active matrix drive type. Active matrix drive type organic electroluminescence display panels are passive in terms of high contrast and high definition. It is superior to the drive system. For example, in the conventional active matrix driving type organic electroluminescence display panel described in Patent Document 1, an organic electroluminescence element (hereinafter referred to as an organic EL element) and a voltage signal corresponding to image data are applied to the gate. In addition, a driving transistor that supplies current to the organic EL element and a switching transistor that performs switching for supplying a voltage signal corresponding to image data to the gate of the driving transistor are provided for each pixel. In this organic electroluminescence display panel, when a scanning line is selected, the switching transistor is turned on. At that time, a voltage representing a luminance is applied to the gate of the driving transistor via the signal line. As a result, the drive transistor is turned on, and a drive current having a magnitude corresponding to the level of the gate voltage flows from the power source to the organic EL element via the source-drain of the drive transistor, and the organic EL element corresponds to the magnitude of the current. Emits light with high brightness. From the end of the selection of the scanning line to the next selection of the scanning line, even if the switching transistor is turned off, the level of the gate voltage of the driving transistor is kept, and the organic EL element becomes the voltage. Light is emitted at a luminance according to the magnitude of the corresponding drive current.

  In order to drive an organic electroluminescence display panel, a drive circuit is provided around the organic electroluminescence display panel, and a voltage is applied to a scanning line, a signal line, a power supply line, etc. laid on the organic electroluminescence display panel. It has been broken.

In addition, in a conventional active matrix driving type organic electroluminescence display panel, wiring for passing a current through an organic EL element such as a power supply line is formed simultaneously with a thin film transistor patterning process using a thin film transistor material such as a switching transistor and a driving transistor. Patterned. That is, in manufacturing an organic electroluminescence display panel, a thin film transistor electrode is shaped from the conductive thin film by performing a photolithography method and an etching method on the conductive thin film that is the source of the thin film transistor electrode. At the same time, the wiring connected to the electrode is processed. Therefore, when the wiring is formed from a conductive thin film, the wiring has the same thickness as the electrode of the thin film transistor.
JP-A-8-330600

  However, since the electrode of the thin film transistor is designed on the assumption that it functions as a transistor, in other words, since it is not designed on the assumption that a current flows through the light emitting element, it is a thin film as the name implies. When an electric current is caused to flow from the wiring to the plurality of light emitting elements, a voltage drop occurs due to the electric resistance of the wiring, or a delay of the current flow through the wiring occurs. In order to suppress the voltage drop and current delay, it is desirable to reduce the resistance of the wiring. For this purpose, the metal layers that serve as the source and drain electrodes of the transistor and the metal layer that serves as the gate electrode are made thicker, or these metal layers are made to have current. If the pattern is made wide enough to allow sufficient flow, the area where the wiring overlaps with other wiring, conductors, etc. in plan view increases, and parasitic capacitance occurs between them. In other words, in the case of a so-called bottom emission structure in which EL light is emitted from the transistor array substrate side, the wiring blocks the light emitted from the EL element. This has led to a decrease in the aperture ratio. Further, when the gate electrode of the thin film transistor is made thicker in order to reduce the resistance, it is necessary to increase the thickness to a flattening film (equivalent to a gate insulating film when the thin film transistor has an inverted stagger structure) for flattening the step of the gate electrode. Therefore, the transistor characteristics may change greatly, and if the source and drain electrodes are made thicker, the etching accuracy of the source and drain electrodes decreases, which may adversely affect the transistor characteristics.

  Therefore, an object of the present invention is to suppress voltage drop and signal delay.

In order to solve the above problems, the display panel of the present invention is
A substrate,
A plurality of transistors provided on the substrate for each sub-pixel, each including a gate, a gate insulating film, and a source / drain;
A protective insulating film covering the plurality of transistors;
A planarization film laminated on the protective insulating film;
A plurality of wirings formed of a conductive layer different from gates, sources and drains of the plurality of transistors, and embedded in a groove dividing the protective insulating film and the planarization film on the substrate;
A water- and oil-repellent liquid-repellent insulating film formed so as to cover each of the wirings and protrude from the surface of the planarizing film;
A plurality of subpixel electrodes arranged on each of the substrates along the wirings between the wirings and provided for each subpixel;
A light emitting layer formed on each of the subpixel electrodes by a wet coating method;
A counter electrode coated with the light emitting layer and the liquid repellent insulating film.

  Preferably, the liquid repellent insulating film is made of a fluorine-based electrodeposition paint electrodeposited on each of the wirings by an electrodeposition coating method.

  According to the present invention, since the wiring is formed of a conductive layer different from the drain / source / gate of the transistor, the wiring can be thickened without widening the wiring, and the resistance of the wiring can be reduced. it can. Therefore, even when a signal is output to the transistor / subpixel electrode through the wiring, a voltage drop can be suppressed and a signal delay can also be suppressed.

  In addition, since the wiring is covered with the liquid repellent insulating film, the liquid for the light emitting layer can be prevented from being mixed between adjacent subpixels when the light emitting layer is patterned by the wet coating method. Further, the counter electrode and the wiring can be electrically insulated by the liquid repellent insulating film.

  According to the present invention, since the wiring can be thickened, the resistance of the wiring can be reduced. By reducing the resistance of the wiring, signal delay and voltage drop can be suppressed.

  Further, the liquid-repellent insulating film covering the wiring can prevent the liquid for the light emitting layer from being mixed between adjacent subpixels, and can electrically insulate the counter electrode and the wiring.

  The best mode for carrying out the present invention will be described below with reference to the drawings. However, although various technically preferable limitations for implementing the present invention are given to the embodiments described below, the scope of the invention is not limited to the following embodiments and illustrated examples. Further, in the following description, the term electroluminescence is abbreviated as EL.

[First Embodiment]
[Planar layout of display panel]
FIG. 1 shows a schematic plan view of a pixel 3 of 4 pixels provided on an insulating substrate 2 of a display panel 1 for color display that operates by an active matrix driving method. In this display panel 1, a plurality of red subpixels Pr are arranged in one row along the horizontal direction (row direction), a plurality of green subpixels Pg are arranged in one row along the horizontal direction, and a plurality of blue subpixels are arranged. Pb is arranged in one line along the horizontal direction. If attention is paid to the arrangement order in the vertical direction, the red subpixel Pr, the green subpixel Pg, and the blue subpixel Pb are repeatedly arranged in this order. A combination of 1-dot red subpixel Pr, 1-dot green subpixel Pg, and 1-dot blue subpixel Pb becomes one pixel 3, and such pixels 3 are arranged in a matrix. In the following description, the sub-pixel P represents an arbitrary sub-pixel among the red sub-pixel Pr, the green sub-pixel Pg, and the blue sub-pixel Pb, and the description of the sub-pixel P is a red sub-pixel Pr and a green sub-pixel. This applies to both the pixel Pg and the blue subpixel Pb.

  Further, three signal lines Yr, Yg, Yb extending along the vertical direction form one set, and a combination of the three signal lines Yr, Yg, Yb is referred to as a signal line group 4. When attention is paid to one signal line group 4, the three signal lines Yr, Yg, Yb are close to each other, but the interval between the adjacent signal line groups 4 is equal to the adjacent signal lines Yr, It is wider than the interval between Yg and Yb. A group of signal lines 4 is provided for each column of pixels 3 in the vertical direction (column direction). That is, the subpixels Pr, Pg, Pb in one column arranged in the vertical direction are connected to the signal lines Yr, Yg, Yb of the signal line group 4 in one group, respectively.

  Here, the signal line Yr supplies a signal to all red subpixels Pr in the column of the pixels 3 in the vertical direction, and the signal line Yg is all green subs in the column of the pixels 3 in the vertical direction. A signal is supplied to the pixel Pg, and the signal line Yb supplies a signal to all the blue subpixels Pb in the column of the pixels 3 in the vertical direction.

  Further, one common wiring 91 is provided for each column of the pixels 3 in the vertical direction. That is, one common wiring 91 is provided for each column of vertical subpixels Pr, Pg, and Pb. The common wiring 91 extends along the vertical direction, and is arranged between adjacent columns of the subpixels Pr, Pg, and Pb arranged along the vertical direction.

  Further, three supply lines Zr, Zg, Zb and one scanning line X are provided for each row of the pixels 3 in the horizontal direction. The scanning line X extends in the horizontal direction, and is arranged between the row of blue subpixels Pb arranged in the horizontal direction and the row of red subpixels Pr adjacent thereto. Here, the scanning line X supplies signals to all the sub-pixels Pr, Pg, and Pb of the pixels 3 arranged in one row along the horizontal direction.

  The supply line Zr extends in the horizontal direction, and is arranged between the row of blue subpixels Pb arranged in the horizontal direction and the row of red subpixels Pr adjacent thereto. The supply line Zg extends in the horizontal direction, and is arranged between the row of red subpixels Pr arranged in the horizontal direction and the row of green subpixels Pg adjacent thereto. The supply line Zb extends in the horizontal direction, and is disposed between the row of green subpixels Pg and the row of adjacent blue subpixels Pb arranged in the horizontal direction.

  Here, the supply line Zr supplies a signal to all red subpixels Pr arranged in one row along the horizontal direction, and the supply line Zg corresponds to all green subpixels arranged in one row along the horizontal direction. A signal is supplied to the pixel Pg, and the supply line Zb supplies a signal to all the blue subpixels Pb arranged in one line along the horizontal direction. The three supply lines Zr, Zg, Zb in the row of the pixels 3 in the horizontal direction form one set, and the three supply lines Zr, Zg, Zb are electrically connected to each other in the peripheral portion of the display panel 1. Yes.

  Also, in plan view, the supply line Zr is electrically connected to the supply line 90r by overlapping in the extending direction, and the supply line Zg is electrically connected to the supply line Zg by overlapping in the extending direction. The supply line Zb is electrically connected to the supply line Zb by overlapping the supply line 90b in the extending direction.

  The colors of the subpixels Pr, Pg, and Pb are determined by the emission color of the organic EL element 20 (shown in FIG. 2 and the like) described later. In FIG. 1, the positions of the subpixels Pr, Pg, and Pb shown in a rectangular shape elongated in the vertical direction represent the positions of the subpixel electrodes 20a (shown in FIG. 2 and the like) that are the anodes of the organic EL element 20. Is. That is, when viewed in plan with the display panel 1 as a whole, a plurality of subpixel electrodes 20a are arranged in a matrix, and one dot of subpixel P is determined by one subpixel electrode 20a. Accordingly, a plurality of subpixel electrodes 20a are arranged in a line along the horizontal direction between the power supply wiring 90r and the adjacent power supply wiring 90g, and a plurality of subpixel electrodes are disposed between the power supply wiring 90g and the adjacent power supply wiring 90b. 20a are arranged in one row along the horizontal direction, and a plurality of subpixel electrodes 20a are arranged in one row along the horizontal direction between the power supply wiring 90b and the adjacent power supply wiring 90r. On the other hand, if an insulating film having a sufficient thickness so as not to cause a parasitic capacitance between the signal line group 4 and an electrode or wiring positioned above the signal line group 4 is interposed, the signal line group 4 May overlap with the subpixel electrode 20a connected to the signal line group 4 in plan view, and the subpixel electrode 20a of one subpixel adjacent to the subpixel connected to the signal line group 4 And may overlap in plan view. If the display panel 1 has a bottom emission structure, it is preferable that the signal line group 4 does not overlap the subpixel electrode 20a in plan view.

  When each of m and n is an integer of 2 or more and the pixel 3 is arranged by m pixels along the vertical direction and n pixels along the horizontal direction, the subpixel electrode 20a has subpixel electrodes along the vertical direction. The same number (3 × m) as the number of one column is arranged in the horizontal direction by the same number n as the number of one row of subpixels. In this case, the signal line group 4 is an n group, and n or (n + 1) common wirings 91 are arranged, and the scanning line X, the supply line Zr, the supply line Zg, the supply line Zb, the power supply line 90r, and the power supply line. There are arranged m pieces of 90g and power supply wirings 90b, respectively. The total number of the liquid repellent insulating films 53 that dam up an organic compound-containing liquid to be an organic EL layer 20b of the organic EL element 20 to be described later in one row of subpixels is (3 × m + 1), of which (3 × m) The book is connected to the drive transistor 23 via the supply line Zr, the supply line Zg, and the supply line Zb, respectively, and the remaining one is not connected to the drive transistor 23.

[Sub-pixel circuit configuration]
Next, the circuit configuration of the subpixels Pr, Pg, and Pb will be described with reference to the equivalent circuit diagram of FIG. All of the subpixels Pr, Pg, and Pb are configured in the same manner. For each subpixel P of one dot, the organic EL element 20 and an N-channel amorphous silicon thin film transistor (hereinafter simply referred to as a transistor) 21,22. 23 and a capacitor 24 are provided. Hereinafter, the transistor 21 is referred to as a switch transistor 21, the transistor 22 is referred to as a holding transistor 22, and the transistor 23 is referred to as a drive transistor 23. In FIG. 2 and the following description, in the case of the red sub-pixel Pr, the signal line Y, the supply line Z, and the power supply wiring 90 represent the signal line Yr, the supply line Zr, and the power supply wiring 90r in FIG. In the case of Pg, the signal line Y, the supply line Z, and the power supply wiring 90 represent the signal line Yg, the supply line Zg, and the power supply wiring 90g in FIG. 1, respectively, and in the case of the blue subpixel Pb, the signal line Y, the supply line Z, and the power supply wiring 90g. The wirings 90 respectively represent the signal line Yb, the supply line Zb, and the power supply wiring 90b in FIG.

  In the switch transistor 21, the source 21s is conducted to the signal line Y, the drain 21d is conducted to the subpixel electrode 20a of the organic EL element 20, the source 23s of the driving transistor 23 and the upper layer electrode 24B of the capacitor 24, and the gate 21g is held. The transistor 22 is electrically connected to the gate 22g and the scanning line X.

  In the holding transistor 22, the source 22 s is connected to the gate 23 g of the drive transistor 23 and the lower layer electrode 24 A of the capacitor 24, the drain 22 d is connected to the drain 23 d of the drive transistor 23 and the supply line Z, and the gate 22 g is connected to the switch transistor 21. It is electrically connected to the gate 21g and the scanning line X.

  In the drive transistor 23, the source 23 s is electrically connected to the subpixel electrode 20 a of the organic EL element 20, the drain 21 d of the switch transistor 21 and the upper layer electrode 24 B of the capacitor 24, and the drain 23 d is connected to the drain 22 d of the holding transistor 22 and the supply line Z. The gate 23g is electrically connected to the source 22s of the holding transistor 22 and the lower layer electrode 24A of the capacitor 24.

  The counter electrode 20c serving as the cathode of the organic EL element 20 is electrically connected to a plurality of low resistance common wires 91, 91,.

  The sources 21s of the switch transistors 21 of any red subpixel Pr arranged in a line along the vertical direction are conducted to the common signal line Yr, and any of the green subpixels Pg arranged in a line along the vertical direction. The source 21s of the switch transistor 21 is also conducted to the common signal line Yg, and the source 21s of the switch transistor 21 of any blue subpixel Pb arranged in a line along the vertical direction is also conducted to the common signal line Yb. .

  On the other hand, the gates 21g of the switch transistors 21 of any of the sub-pixels Pr, Pg, Pb of the pixels 3 arranged in one row along the horizontal direction are conducted to the common scanning line X and arranged in one row along the horizontal direction. The gate 22g of the holding transistor 22 of any subpixel Pr, Pg, Pb of the pixel 3 is electrically connected to the common scanning line X. The drains 22d of the holding transistors 22 of any red subpixel Pr arranged in one row along the horizontal direction are connected to the common supply line Zr, and any of the green subpixels Pg arranged in one row along the horizontal direction. The drain 22d of the holding transistor 22 is also connected to the common supply line Zg, and the drain 22d of the holding transistor 22 of any blue subpixel Pb arranged in a row along the horizontal direction is also connected to the common supply line Zb. .

[Plane layout of pixels]
The planar layout of the pixel 3 will be described with reference to FIGS. 3 is a plan view mainly showing electrodes of the red subpixel Pr, FIG. 4 is a plan view mainly showing electrodes of the green subpixel Pg, and FIG. 5 is an electrode of the blue subpixel Pb. It is the top view which mainly showed. 3 to 5, illustration of the subpixel electrode 20a and the counter electrode 20c of the organic EL element 20 is omitted for easy viewing of the drawings.

  As shown in FIG. 3, in the red subpixel Pr, in plan view, the drive transistor 23 is disposed along the supply line Zr, the switch transistor 21 is disposed along the supply line Zg, and the holding transistor 22 is disposed. Are arranged at the corners of the red subpixel Pr near the supply line Zr.

  As shown in FIG. 4, in the green subpixel Pg, the driving transistor 23 is arranged along the supply line Zg, the switch transistor 21 is arranged along the supply line Zb, and the holding transistor 22 in the plan view. Is arranged at the corner of the green sub-pixel Pg near the supply line Zg.

  As shown in FIG. 5, in the blue subpixel Pb, the driving transistor 23 is arranged along the supply line Zb, the switch transistor 21 is arranged along the scanning line X, and the holding transistor 22 in the plan view. Are arranged at the corners of the blue subpixel Pb near the supply line Zb.

  As shown in FIGS. 3 to 5, in any of the subpixels Pr, Pg, and Pb, the capacitor 24 is disposed along the signal line group 4 in the adjacent column.

  When the entire display panel 1 is viewed in plan and attention is paid only to the switch transistors 21 of all the subpixels Pr, Pg, Pb, a plurality of switch transistors 21 are arranged in a matrix, and all of the subpixels Pr, Pg, Pb are arranged. Focusing only on the holding transistor 22, a plurality of holding transistors 22 are arranged in a matrix, and if focusing only on the driving transistors 23 of all the subpixels Pr, Pg, Pb, a plurality of driving transistors 23 are arranged in a matrix. Yes.

[Layer structure of display panel]
The layer structure of the display panel 1 will be described with reference to FIGS. 6 is a cross-sectional view taken in the direction of the thickness of the insulating substrate 2 along the broken line VI-VI shown in FIGS. 3 to 5, and FIG. 7 is shown in FIG. It is arrow sectional drawing cut | disconnected in the thickness direction of the insulated substrate 2 along the broken line VII-VII.

  The display panel 1 is obtained by laminating various layers on an insulating substrate 2 having optical transparency. The insulating substrate 2 is provided in the form of a flexible sheet or is provided in the form of a rigid plate.

  First, the layer structure of the transistors 21 to 23 will be described. As shown in FIG. 6, the switch transistor 21 includes a gate 21g formed on the insulating substrate 2, a gate insulating film 31 formed on the gate 21g, and a semiconductor facing the gate 21g across the gate insulating film 31. A film 21c, a channel protective film 21p formed on the central portion of the semiconductor film 21c, and impurity semiconductor films 21a formed on both ends of the semiconductor film 21c so as to be separated from each other and partially overlapping the channel protective film 21p, 21b, a drain 21d formed on the impurity semiconductor film 21a, and a source 21s formed on the impurity semiconductor film 21b. Note that the drain 21d and the source 21s may have a single-layer structure or a stacked structure of two or more layers.

  The driving transistor 23 includes a gate 23g formed on the insulating substrate 2, a gate insulating film 31 formed on the gate 23g, a semiconductor film 23c facing the gate 23g with the gate insulating film 31 interposed therebetween, and a semiconductor film 23c. Impurity protective film 23a, 23b formed on the both ends of the semiconductor film 23c and spaced apart from each other and partially overlapping the channel protective film 23p, and the impurity semiconductor film 23a The drain 23d formed above and the source 23s formed on the impurity semiconductor film 23b. When viewed in plan as shown in FIGS. 3 to 5, the channel width of the drive transistor 23 is widened because the drive transistor 23 is provided in a comb shape. The drain 23d and the source 23s may have a single layer structure or a stacked structure of two or more layers.

  Note that since the holding transistor 22 has the same layer structure as that of the driving transistor 23, a cross-sectional view of the holding transistor 22 is omitted. In any of the subpixels Pr, Pg, and Pb, the switch transistor 21, the holding transistor 22, and the driving transistor 23 have the same layer structure.

  Next, the layer structure of the capacitor 24 will be described. As shown in FIGS. 3 to 5, the capacitor 24 includes a lower layer electrode 24 </ b> A formed on the insulating substrate 2, a gate insulating film 31 formed on the lower layer electrode 24 </ b> A, and a lower layer electrode sandwiching the gate insulating film 31. And an upper layer electrode 24B opposed to 24A. The capacitor 24 has the same layer structure in any of the subpixels Pr, Pg, and Pb.

  Next, the relationship among the layers of the transistors 21 to 23 and the capacitor 24 and the signal lines Yr, Yg, Yb, the scanning line X, and the supply lines Zr, Zg, Zb will be described with reference to FIGS.

  The gate 21g of the switch transistor 21, the gate 22g of the holding transistor 22, the gate 23g of the driving transistor 23, the lower layer electrode 24A of the capacitor 24, and all the signal lines Yr, Yg, Yb of all the subpixels Pr, Pg, Pb are insulated. The conductive film formed on the entire surface of the substrate 2 is formed by patterning by a photolithography method and an etching method. Hereinafter, the gate 21g of the switch transistor 21, the gate 22g of the holding transistor 22, the gate 23g of the drive transistor 23, the lower layer electrode 24A of the capacitor 24, and the conductive film that is the source of the signal lines Yr, Yg, Yb are referred to as a gate layer.

  The gate insulating film 31 is an insulating film common to the switch transistor 21, the holding transistor 22, the driving transistor 23, and the capacitor 24 of all the subpixels Pr, Pg, and Pb, and is formed over the entire surface. Therefore, the gate insulating film 31 covers the gate 21g of the switch transistor 21, the gate 22g of the holding transistor 22, the gate 23g of the drive transistor 23, the lower layer electrode 24A of the capacitor 24, and the signal lines Yr, Yg, Yb.

  The drain 21d and source 21s of the switch transistor 21 of all the subpixels Pr, Pg, and Pb, the drain 22d and source 22s of the holding transistor 22, the drain 23d and source 23s of the driving transistor 23, the upper layer electrode 24B of the capacitor 24, and all the scans. The line X and the supply lines Zr, Zg, and Zb are formed by patterning a conductive film formed on the entire surface of the gate insulating film 31 by a photolithography method and an etching method. In the following, the drain 21d and source 21s of the switch transistor 21, the drain 22d and source 22s of the holding transistor 22, the drain 23d and source 23s of the driving transistor 23, the upper layer electrode 24B of the capacitor 24, the scanning line X and the supply lines Zr, Zg, The conductive film that is the source of Zb is called a drain layer.

  One contact hole 92 per pixel 3 is formed at a position overlapping the scanning line X of the gate insulating film 31, and the gate 21g of the switch transistor 21 and the gate 22g of the holding transistor 22 of the subpixels Pr, Pg, and Pb are contact holes. It is conducted to the scanning line X through 92. One contact hole 94 is formed at a position overlapping the signal line Y of the gate insulating film 31 for each subpixel P of one dot, and the source 21s of the switch transistor 21 is the contact hole 94 in any subpixel Pr, Pg, Pb. To the signal line Y. One contact hole 93 is formed at a position overlapping the lower layer electrode 24A of the gate insulating film 31 for each dot subpixel P, and the source 22s of the holding transistor 22 is connected to the drive transistor 23 in any of the subpixels Pr, Pg, Pb. It is electrically connected to the gate 23g and the lower layer electrode 24A of the capacitor 24.

  In any of the subpixels Pr, Pg, and Pb, the drain 22d of the holding transistor 22 and the drain 23d of the driving transistor 23 are provided integrally with the supply line Z.

  The switch transistors 21, the holding transistors 22 and the drive transistors 23 of all the subpixels Pr, Pg, and Pb, and all the scanning lines X and supply lines Z are protective insulating films such as silicon nitride or silicon oxide formed on the entire surface. 32. In addition, although mentioned later for details, the protective insulating film 32 is divided | segmented into the rectangular shape in the location which overlaps with the supply lines Zr, Zg, Zb.

  A planarizing film 33 is laminated on the protective insulating film 32, and unevenness caused by the switch transistor 21, the holding transistor 22, the driving transistor 23, the scanning line X and the supply lines Zr, Zg, Zb is eliminated by the planarizing film 33. Yes. That is, the surface of the planarizing film 33 is flat. The planarizing film 33 is obtained by curing a photosensitive insulating resin such as polyimide. In addition, although mentioned later for details, the planarization film | membrane 33 is divided | segmented into the rectangular shape in the location which overlaps with supply line Zr, Zg, Zb.

  When the display panel 1 is used as a bottom emission type, that is, when the insulating substrate 2 is used as a display surface, a transparent material is used for the gate insulating film 31, the protective insulating film 32, and the planarizing film 33. A stacked structure from the insulating substrate 2 to the planarizing film 33 is referred to as a transistor array substrate 50.

  In any of the supply lines Zr, Zg, and Zb, a long groove 34 is formed in the horizontal direction in the portion of the protective insulating film 32 and the planarizing film 33 that overlaps the supply line Z. The protective insulating film 32 and the planarizing film 33 are divided into rectangular shapes. Feeding lines 90r, 90g, and 90b are embedded in the groove 34, and the feeding lines 90r, 90g, and 90b are stacked on the supply lines Zr, Zg, and Zb in the groove 34, respectively. As described above, the power supply wirings 90r, 90g, and 90b are electrically connected to the supply lines Zr, Zg, and Zb, respectively. For this reason, the power supply wirings 90r, 90g, and 90b are located below the subpixel electrode 20c.

  Any of the power supply wirings 90r, 90g, and 90b is formed by electrolytic plating using the supply lines Zr, Zg, and Zb as a base, and is therefore sufficiently thicker than the supply lines Zr, Zg, and Zb. Further, the feed lines 90r, 90g, 90b are thinner than the total thickness of the protective insulating film 32 and the planarization film 33, and the feed lines 90r, 90g, 90b are lower than the surface of the planarization film 33. It is in. The power supply wirings 90r, 90g, and 90b preferably include at least one of copper, aluminum, gold, and nickel. A liquid repellent insulating film 53 having water repellency and oil repellency is formed on the surface of each of the power supply wirings 90r, 90g, 90b, and the liquid repellent insulating film 53 protrudes from the surface of the planarizing film 33 from the groove 34. ing. Thereby, the liquid repellent insulating film 53 is exposed on the surface of the planarizing film 33. The liquid repellent insulating film 53 is made of a fluororesin electrodeposition coating electrodeposited on the power supply wirings 90r, 90g, and 90b, and is formed by electrodeposition coating.

  A plurality of subpixel electrodes 20 a are arranged in a matrix on the surface of the planarizing film 33, that is, on the surface of the transistor array substrate 50. These subpixel electrodes 20a are obtained by patterning a transparent conductive film formed on the entire surface of the planarizing film 33 by a photolithography method or an etching method.

The subpixel electrode 20 a is an electrode that functions as an anode of the organic EL element 20. That is, it is preferable that the work function of the subpixel electrode 20a is relatively high and holes are efficiently injected into the organic EL layer 20b described later. In addition, the subpixel electrode 20a is transmissive to visible light in the case of bottom emission. As the subpixel electrode 20a, for example, tin-doped indium oxide (ITO), zinc-doped indium oxide, indium oxide (In ₂ O ₃ ), tin oxide (SnO ₂ ), zinc oxide (ZnO), or cadmium-tin oxide ( CTO) is the main component.

  When the display panel 1 is used as a top emission type, that is, when the opposite side of the insulating substrate 2 is used as a display surface, conductive and visible light is interposed between the subpixel electrode 20a and the planarizing film 33. A reflective film having high reflectivity may be formed, or the subpixel electrode 20a itself may be a reflective electrode.

  One contact hole 88 for each dot subpixel P is formed at a position overlapping the subpixel electrode 20a of the planarization film 33 and the protective insulating film 32, and a conductive pad is embedded in the contact hole 88. In any subpixel Pr, Pg, Pb, the subpixel electrode 20a is electrically connected to the upper layer electrode 24B of the capacitor 24, the drain 21d of the switch transistor 21 and the source 23s of the drive transistor 23.

  An organic EL layer 20b of the organic EL element 20 is formed on the subpixel electrode 20a. The organic EL layer 20b is a light-emitting layer in a broad sense, and the organic EL layer 20b contains a light-emitting material (phosphor) that is an organic compound. The organic EL layer 20b has a two-layer structure in which a hole transport layer and a narrowly-defined light emitting layer are sequentially stacked from the subpixel electrode 20a. The hole transport layer is made of PEDOT (polythiophene) that is a conductive polymer and PSS (polystyrene sulfonic acid) that is a dopant, and the light-emitting layer in the narrow sense is made of a polyfluorene-based light-emitting material.

  In the case of the red subpixel Pr, the organic EL layer 20b emits red light, in the case of the green subpixel Pg, the organic EL layer 20b emits green light, and in the case of the blue subpixel Pb, the organic EL layer 20b. 20b emits blue light.

  The organic EL layer 20b is provided independently for each subpixel electrode 20a, and when viewed in plan, a plurality of organic EL layers 20b are arranged in a matrix. The red subpixels Pr arranged in a line along the horizontal direction between the power supply line 90r and the power supply line 90g are all red, so that the line between the power supply line 90r and the power supply line 90g is aligned along the horizontal direction. The plurality of arranged subpixel electrodes 20a may be covered with a common red light emitting organic EL layer 20b which is elongated in a strip shape along the vertical direction. Similarly, a plurality of sub-pixel electrodes 20a arranged in a line along the horizontal direction between the power supply wiring 90g and the power supply wiring 90b have a common green light-emitting organic EL layer that is elongated in a strip shape along the vertical direction. The plurality of subpixel electrodes 20a arranged in a line along the horizontal direction between the power supply wiring 90b and the power supply wiring 90r may be covered with a long strip in the horizontal direction. The blue light emitting organic EL layer 20b may be covered.

  The organic EL layer 20b is formed by a wet coating method (for example, an ink jet method) after the liquid repellent insulating film 53 is formed. In this case, the organic compound-containing liquid is applied to the subpixel electrode 20a, but the liquid repellent insulating film 53 is provided on the surface of the transistor array substrate 50 between the subpixel electrodes 20a adjacent in the vertical direction. The organic compound-containing liquid applied to 20a does not leak to the adjacent subpixel electrode 20a. Therefore, the organic EL layer 20b can be applied for each color by a wet coating method.

  Furthermore, since the liquid containing the organic compound applied to the subpixel electrode 20a does not become thick around the subpixel electrode 20a due to the water and oil repellency of the liquid repellent insulating film 53, the organic EL layer 20b is formed with a uniform film thickness. Can be membrane.

  In addition to the two-layer structure, the organic EL layer 20b may have a three-layer structure that becomes a hole transport layer, a narrow light-emitting layer, and an electron transport layer in order from the subpixel electrode 20a, or a narrow light-emitting layer. It may be a single layer structure, or may be a laminated structure in which an electron or hole injection layer is interposed between appropriate layers in these layer structures, or another laminated structure.

  On the organic EL layer 20b, a counter electrode 20c that functions as a cathode of the organic EL element 20 is formed. The counter electrode 20c is a common electrode formed in common to all the subpixels Pr, Pg, and Pb, and is formed on the entire surface. Since the liquid repellent insulating film 53 is coated on the power supply wirings 90r, 90g, and 90b, the counter electrode 20c is insulated from any of the power supply wirings 90r, 90g, and 90b.

  The counter electrode 20c is formed of a material having a work function lower than that of the subpixel electrode 20a. For example, the counter electrode 20c is formed of a simple substance or an alloy containing at least one of magnesium, calcium, lithium, barium, indium, and a rare earth metal. It is preferable. Further, the counter electrode 20c may have a laminated structure in which layers of the above various materials are laminated, and in addition to the above layers of various materials, a metal layer that is not easily oxidized is deposited in order to reduce sheet resistance. Specifically, it may have a laminated structure. Specifically, a low-work function high-purity barium layer provided on the interface side in contact with the organic EL layer 20b, and an aluminum layer provided so as to cover the barium layer; And a laminated structure in which a lower layer is provided with a lithium layer and an upper layer is provided with an aluminum layer. In the case of a top emission structure, the counter electrode 20c may be a transparent electrode in which a thin film having a low work function as described above and a transparent conductive film such as ITO are laminated thereon.

  A common wiring 91 is stacked between the adjacent columns of the pixels 3 in the horizontal direction and on the counter electrode 20c. Therefore, as shown in the circuit diagram of FIG. 2, the counter electrode 20 c is electrically connected to the common wiring 91. Since the common wiring 91 is formed by a plating method, it is sufficiently thicker than the counter electrode 20c and the electrodes of the transistors 21 to 23.

  A sealing insulating film 56 is formed on the counter electrode 20c. The sealing insulating film 56 is an inorganic film or an organic film that covers the entire counter electrode 20c and covers all the common wiring 91, and prevents the counter electrode 20c and the common wiring 91 from being deteriorated.

  Conventionally, an EL display panel having a top emission type structure uses a transparent electrode having a high resistance value such as a metal oxide for at least a part of the counter electrode 20c. However, such a material is sufficiently thick. Otherwise, the sheet resistance will not be sufficiently low, so increasing the thickness will inevitably reduce the transmittance of the organic EL element, and the larger the screen, the less likely it will be a uniform potential in the plane, resulting in lower display characteristics. It was.

  However, in the present embodiment, since a plurality of low resistance common wires 91, 91,... Are provided for a sufficient thickness in the horizontal direction, the organic EL elements 20, 20,. The sheet resistance value of the entire cathode electrode can be lowered, and a large current can be sufficiently and uniformly supplied in the plane. Further, in such a structure, since the common wires 91, 91,... Reduce the sheet resistance as the cathode electrode, it is possible to improve the transmittance by using the counter electrode 20c as a thin film. In the top emission structure, the pixel electrode 20a may be a reflective material.

  Then, power supply wirings 90r, 90g, and 90b formed using a thick conductive layer other than the conductive layer in forming the thin film transistor are provided so as to be electrically connected to the supply lines Zr, Zg, and Zb, respectively. Therefore, a delay until a write current and a drive current, which will be described later, reach a predetermined current value in the plurality of organic EL elements 20 due to a voltage drop in the supply lines Zr, Zg, Zb formed only by the conductive layer of the thin film transistor is prevented. And it becomes possible to drive well.

[Driving method of display panel]
In the structure of the first display panel 1, as shown in FIG. 8, a selection driver 111 to which the scanning lines X _{1 to} X _m are connected is disposed on the first peripheral edge of the insulating substrate 2 and electrically connected to each other. A power supply driver 112 to which the insulated power supply wirings 90r, 90g, and 90b are connected is disposed on a second peripheral edge that is a peripheral edge facing the first peripheral edge of the insulating substrate 2. The first display panel 1 is driven by the active matrix method as follows. That is, as shown in FIG. 9, the scanning lines X ₁ to X by the connected selection driver 111 _m, the order from the scanning line X ₁ to scan line X _m (the next scan line X _m scanning lines X ₁₎ The scanning lines X _{1 to} X _m are sequentially selected by sequentially outputting high level shift pulses. In addition, a write power supply voltage VL for applying a write current is applied to the drive transistors 23 connected to the supply lines Z _{1 to} Z _m via the power supply lines 90 during the selection period, and the drive transistors 23 are used during the light emission period. A power supply driver 112 that applies a drive power supply voltage VH for causing a drive current to flow through the organic EL element 20 is connected to each power supply wiring 90. Here, one supply line Z _i corresponds to three power supply lines 90r, 90g, and 90b. The power supply driver 112 synchronizes with the selection driver 111 in order from the supply line Z ₁ to the supply line Z _m (next to the supply line Z _m is the supply line Z ₁ ). The supply lines Z _{1 to} Z _m are sequentially selected by sequentially outputting the write power supply voltage VL having a lower level than the voltage of the first voltage. Further, when the selection driver 111 selects each of the scanning lines X _{1 to} X _m , the data driver sends a write current (current signal) as a write current between the source and drain of the drive transistor 23 in a predetermined row. Through all the signal lines Y _{1 to} Y _n . At this time, low-level writing is performed on the power supply wiring 90 connected to the supply lines Z _{1 to} Z _m from both of the wiring terminals at both ends of the power supply wiring 90 positioned at the left and right peripheral edges of the insulating substrate 2 by the power supply driver 112. A power supply voltage VL is output. The counter electrode 20c and the common wiring 91 are connected to the outside by wiring terminals, and are kept at a constant common potential Vcom (for example, ground = 0 volts).

The direction in which the signal lines Y _{1 to} Y _n extend is called a vertical direction (column direction), and the direction in which the scanning lines X _{1 to} X _m extend is called a horizontal direction (row direction). Further, m and n are natural numbers of 2 or more, the numbers subscripted to the scanning line X represent the arrangement order from the top in FIG. 1, and the numbers subscripted to the supply line Z are the arrangement order from the top in FIG. 1, the number subscripted to the signal line Y represents the arrangement order from the left in FIG. 1, the front side of the number subscripted to the pixel circuit P represents the arrangement order from the top, and the rear side represents the arrangement order from the left. To express. That is, when an arbitrary natural number of 1 to m is i and an arbitrary natural number of 1 to n is j, the scanning line X _i is the i-th row from the top, and the supply line Z _i is the left To the i-th row, the signal line Y _j is the j-th column from the left, the pixel circuit P _{i, j} is the i-th row from the top, the j-th column from the left, and the pixel circuit P _{i, j} is the scanning line. It is connected to X _i , supply line Z _i and signal line Y _j .

The pixel circuit P _{i, j} includes an organic EL element 20 as a pixel and three N-channel amorphous silicon thin film transistors (hereinafter simply referred to as transistors) 21, 22, and 23 disposed around the organic EL element 20. And a capacitor 24.

In each selection period, the potential of the data driver side, feed interconnections 90, 90, ... and the supply lines Z ₁ to Z _m output to the and below the write feed voltage VL the write feed voltage VL below the common potential Vcom Is set to Therefore, at this time, since the organic EL element 20 does not flow to the signal lines Y _{1 to} Y _n , as shown in FIG. 2, a write current (write current) having a current value corresponding to the gradation is indicated by an arrow by the data driver. As shown in A, the signal flows to the signal lines Y _{1 to} Y _n , and in the pixel circuit P _{i, j} , the power supply wiring 90 and the supply line Z _i pass between the source and drain of the drive transistor 23 and between the source and drain of the switch transistor 21. Thus, a write current (write current) directed to the signal line Y _j flows. In this way, the current value of the current flowing between the source and drain of the drive transistor 23 is uniquely controlled by the data driver, and the data driver writes the write current (write current) according to the gradation input from the outside. Set the current value. While the write current (write current) is flowing, i-th row of P _i, 1 to P _i, the voltage between the gate 23g- source 23s of the driving transistor 23 of the _n each signal line Y ₁ to Y _The write current (write current) flowing between the drain 23d and the source 23s of the drive transistor 23 regardless of the current value of the write current (write current) flowing through _n , that is, the change in the Vg-Ids characteristic of the drive transistor 23 with time. The capacitor 24 is forcibly set so as to meet the current value of the current, and the capacitor 24 is charged with a charge having a magnitude according to the level of this voltage, so that the current value of the write current (write current) becomes the gate 23g of the drive transistor 23. -It is converted into the voltage level between the sources 23s. In the subsequent light emission period, the scanning line X _i becomes a low level, and the switch transistor 21 and the holding transistor 22 are turned off. However, the charge on the electrode 24A side of the capacitor 24 is confined by the holding transistor 22 in the off state and floats. Even if the voltage of the source 23s of the drive transistor 23 is modulated when the voltage shifts from the selection period to the light emission period, the potential difference between the gate 23g and the source 23s of the drive transistor 23 is maintained as it is. In this light emission period, the potential of the supply line Z _i and the power supply wiring 90 connected thereto becomes the drive power supply voltage VH, which is higher than the potential Vcom of the counter electrode 20c of the organic EL element 20, thereby connecting to the supply line Z _i and the supply line Z _i. A drive current flows from the power supply wiring 90 to the organic EL element 20 through the drive transistor 23 in the direction of arrow B, and the organic EL element 20 emits light. Since the current value of the drive current depends on the voltage between the gate 23g and the source 23s of the drive transistor 23, the current value of the drive current in the light emission period is equal to the current value of the write current (drawing current) in the selection period.

As shown in FIG. 10, the second display panel 1 has a structure in which a selection driver 111 to which the scanning lines X _{1 to} X _m are connected is arranged on the first peripheral edge of the insulating substrate 2, and the power supply wiring The routing wiring 90c in which 90r, 90g, and 90b are electrically connected to each other is disposed on the second peripheral edge that is the peripheral edge facing the first peripheral edge of the insulating substrate 2. The routing wiring 90c receives clock signals from both the terminal portion 90d and the terminal portion 90e located at the third peripheral portion and the fourth peripheral portion orthogonal to the first peripheral portion and the second peripheral portion, respectively. . The active matrix driving method of the second display panel 1 is as follows. That is, as shown in FIG. 11, a clock signal is output to the lead-out wiring 90c feed wirings 90, 90,... And the supply lines Z _{1 to} Z _m by the oscillation circuit. The scanning lines X ₁ to X _m by sequentially outputting the high-level shift pulse sequentially (the next scan line X _m scanning lines X ₁₎ from the scanning line X ₁ by the selection driver 111 to the scan line X _m Are sequentially selected, but when the selection driver 111 outputs a shift pulse to any _{one of the} scanning lines X _{1 to} X _m , the clock signal of the oscillation circuit becomes low level. Further, when the selection driver 111 selects each of the scanning lines X _{1 to} X _m , the data driver sends a drawing current (current signal) that is a write current to all the signal lines via the source and drain of the driving transistor 23. Flow from Y _{1 to} Y _n . The counter electrode 20c and the power supply wiring 90 are kept at a constant common potential Vcom (for example, ground = 0 volts).

In the selection period of the scan line X _i, from the shift pulse to the i-th scanning line X _i is output, the switch transistor 21 and holding transistor 22 are turned on. In each selection period, the potential of the data driver side, feed interconnections 90, 90, ... and the low level of the supply lines Z ₁ to Z _m and the clock signal following a low level of the clock signal output to the following common potential Vcom Is set to Therefore, at this time, since the organic EL element 20 does not flow to the signal lines Y _{1 to} Y _n , as shown in FIG. 2, the write current (drawing current) having a current value corresponding to the gradation is indicated by the arrow A by the data driver. As described above, the signal lines Y _{1 to} Y _n flow, and in the pixel circuit P _{i, j} , the power supply wiring 90 and the supply line Z _{i are connected} between the source and drain of the drive transistor 23 and between the source and drain of the switch transistor 21. A write current (drawing current) toward the signal line Y _j flows. In this way, the current value of the current flowing between the source and drain of the drive transistor 23 is uniquely controlled by the data driver, and the data driver has a write current (drawing current) according to the gradation input from the outside. Set the current value. While the write current (drawing current) is flowing, the voltage between the gate 23g and the source 23s of each driving transistor 23 of the _i- th row P _{i, 1 to} P _{i, n} is the signal line Y _{1 to} Y _n , respectively. Current value of the write current (extraction current) flowing through the transistor 23, that is, the current value of the write current (extraction current) flowing between the drain 23d and the source 23s of the drive transistor 23 regardless of the change with time in the Vg-Ids characteristic of the drive transistor 23. The capacitor 24 is forcibly set to meet the voltage level, the capacitor 24 is charged with a charge, and the current value of the write current (drawing current) is between the gate 23g and the source 23s of the drive transistor 23. Is converted to the voltage level. In the subsequent light emission period, the scanning line X _i becomes a low level, and the switch transistor 21 and the holding transistor 22 are turned off. However, the charge on the electrode 24A side of the capacitor 24 is confined by the holding transistor 22 in the off state and floats. Even if the voltage of the source 23s of the drive transistor 23 is modulated when the voltage shifts from the selection period to the light emission period, the potential difference between the gate 23g and the source 23s of the drive transistor 23 is maintained as it is. During this light emission period, during which the row is not a selection period, that is, the clock signal is high when the potential of the power supply wiring 90 and the supply line Z _i is higher than the potential Vcom of the counter electrode 20 c of the organic EL element 20 and the power supply wiring 90. During the level, the drive current flows in the direction of the arrow B from the higher potential power supply line 90 and the supply line Z _i to the organic EL element 20 through the source and drain of the drive transistor 23, and the organic EL element 20 emits light. . Since the current value of the drive current depends on the voltage between the gate 23g and the source 23s of the drive transistor 23, the current value of the drive current in the light emission period is equal to the current value of the write current (drawing current) in the selection period. Further, in the light emission period, during the selection period of any row, that is, when the clock signal is at a low level, the potential of the power supply wiring 90 and the supply line Z _i is equal to or lower than the potential Vcom of the counter electrode 20c and the power supply wiring 90. Therefore, no drive current flows through the organic EL element 20 and no light is emitted.

  In any driving method, the switch transistor 21 functions to turn on (selection period) and off (light emission period) the current between the source 23s of the driving transistor 23 and the signal line Y. The holding transistor 22 is in a state in which a current can flow between the source 23s and the drain 23d of the driving transistor 23 during the selection period, and holds the voltage applied between the gate 23g and the source 23s of the driving transistor 23 during the light emission period. It functions as a thing. Then, the drive transistor 23 causes a current having a magnitude corresponding to the gradation to flow to the organic EL element 20 when the supply lines Zr, Zg, Zb and the power supply lines 90r, 90g, 90b are at a high level during the light emission period. And functions as a device for driving the organic EL element 20.

As described above, the magnitude of the current flowing through each of the power supply wirings 90r, 90g, and 90b is determined by the n organic EL elements 20 connected to the supply line Z _i (any one of Zr, Zg, and Zb). Since the sum of the magnitudes of the drive currents flows, the parasitic capacitance of each of the power supply wirings 90r, 90g, and 90b increases when the selection period for moving image driving with the number of pixels equal to or greater than VGA increases. A wiring made of a thin film such as a gate electrode, a source, or a drain electrode has a resistance that is too high to cause a write current (that is, a drive current) to flow through the n organic EL elements 20, but in this embodiment, the pixel circuit P _{1 , 1} to P m, the gate electrode and the source of the _n thin film transistors, the power supply wiring by a conductive layer different from the drain electrode 90r, 90 g, the feed interconnections so constitute respectively 90b 9 r, 90 g, the voltage drop due 90b is reduced, even a short selection period can flow without delay sufficient write current (pull-out current). Since the power supply wirings 90r, 90g, and 90b are reduced in resistance by increasing the thickness of the power supply wirings 90r, 90g, and 90b, the widths of the power supply wirings 90r, 90g, and 90b can be reduced. Therefore, in the case of bottom emission, the decrease in pixel aperture ratio can be minimized.

Similarly, the magnitude of the drive current flowing through the common wiring 91 during the light emission period is the same as the magnitude of the write current (drawing current) flowing through the power supply wiring 90 during the selection period, but the common wiring 91 is connected to the pixel circuit P _{1. , 1 to} P _{m, n} using a conductive layer different from the gate electrode, the source, and the drain electrode of the thin film transistor, the thickness of the common wiring 91 can be reduced. Furthermore, even if the counter electrode 20c itself is thinned to have a higher resistance, the voltage of the counter electrode 20c can be made uniform in the plane. Therefore, even if the same potential is applied to all the pixel electrodes 20a, the light emission intensity of any organic EL layer 20b is substantially equal, and the in-plane light emission intensity can be made uniform. Further, when the EL display panel 1 is used as a top emission type, the counter electrode 20c can be made thinner, so that light emitted from the organic EL layer 20b is not easily attenuated while being transmitted through the counter electrode 20c. Furthermore, since the common wiring 91 is provided between the pixel electrodes 20a adjacent in the horizontal direction in plan view, a decrease in the pixel aperture ratio can be minimized.

[Width, cross-sectional area and resistivity of power supply wiring and common wiring]
Of the two driving methods described above, in the driving method of the second display panel 1, the power supply wirings 90r, 90g, 90b,... Are arranged on the second peripheral portion of the terminal portion 90d of the insulating substrate 2. Since the lead wires 90c are electrically connected to each other, they are equipotential by an external clock signal. Furthermore, the first routing wiring c is connected to the wiring terminal portions 90d and 90e at both ends of the insulating substrate 2, respectively. Since the voltages applied to the wiring terminals from the external drive circuit are both equipotential, current can be supplied to the entire power supply wirings 90, 90,.

  The common wires 91, 91,... Are connected to each other by a second routing wire arranged at the fourth peripheral edge of the insulating substrate 2, and a common voltage Vss is applied. The second routing wiring is insulated from the wiring that intersects in plan view.

  Hereinafter, the width, cross-sectional area, and resistivity of the power supply wiring and common wiring of the first and second display panels 1 are defined. Here, when the number of pixels of the display panel 1 is WXGA (768 × 1366), desirable widths and cross-sectional areas of the power supply wiring 90 and the common wiring 91 are defined. FIG. 18 is a graph showing current-voltage characteristics of the drive transistor 23 and the organic EL element 20 of each subpixel.

  In FIG. 18, the vertical axis represents the current value of the write current flowing between the source 23 s and the drain 23 d of one drive transistor 23 or the current value of the drive current flowing between the anode and the cathode of one organic EL element 20. The axis is the voltage between the source 23s and the drain 23d of one drive transistor 23 (at the same time, the voltage between the gate 23g and the drain 23d of one drive transistor 23). In the figure, solid line Ids max is a write current and drive current at the maximum luminance gradation (brightest display), and alternate long and short dash line Ids mid is an intermediate luminance between the highest luminance gradation and the lowest luminance gradation. The two-dot chain line Vpo is a threshold value, that is, a pinch-off voltage between the unsaturated region (linear region) and the saturated region of the driving transistor 23, and the three-dot chain line Vds is the driving transistor 23. The write current flowing between the source 23 s and the drain 23 d of the organic EL element 20, and the broken line Iel is the drive current flowing between the anode and the cathode of the organic EL element 20.

  Here, the voltage VP1 is a pinch-off voltage of the driving transistor 23 at the maximum luminance gradation, and the voltage VP2 is a source-drain voltage when a writing current of the maximum luminance gradation flows through the driving transistor 23. VELmax (voltage VP4−voltage VP3) is a voltage between the anode and the cathode when the organic EL element 20 emits light with the driving current of the maximum luminance gradation whose current value is equal to the writing current of the maximum luminance gradation. The voltage VP2 ′ is a source-drain voltage when the driving transistor 23 receives an intermediate luminance gradation write current, and the voltage (voltage VP4′−voltage VP3 ′) is an organic EL element 20 having an intermediate luminance gradation. This is the anode-cathode voltage when light is emitted with a drive current of an intermediate luminance gradation whose current value is equal to the write current.

  Since both the drive transistor 23 and the organic EL element 20 are driven in the saturation region, a value VX obtained by subtracting (the voltage Vcom during the light emission period of the common wiring 91) from (the voltage VH during the light emission period of the power supply wiring 90) is The following formula (1) is satisfied.

      VX = Vpo + Vth + Vm + VEL (1)

  Vth (equal to VP2−VP1 at the maximum luminance) is a threshold voltage of the drive transistor 23, VEL (equal to VELmax at the maximum luminance) is an anode-cathode voltage of the organic EL element 20, and Vm is The allowable voltage is displaced according to the gradation.

  As is apparent from the figure, the higher the luminance gradation of the voltage VX, the higher the voltage (Vpo + Vth) required between the source and drain of the transistor 23 and the voltage VEL required between the anode and cathode of the organic EL element 20. Becomes higher. Therefore, the allowable voltage Vm becomes lower as the luminance gradation becomes higher, and the minimum allowable voltage Vmmin becomes VP3−VP2.

  The organic EL element 20 generally deteriorates with time regardless of the low-molecular EL material and the high-molecular EL material, and increases in resistance. It has been confirmed that the anode-cathode voltage after 10,000 hours is about 1.4 times the initial voltage. That is, the voltage VEL increases with time even at the same luminance gradation. Therefore, the higher the allowable voltage Vm at the beginning of driving, the more stable the operation over a long period of time. Therefore, the voltage VX is set so that the voltage VEL is 8 V or higher, more preferably 13 V or higher.

  This allowable voltage Vm includes not only the increase in resistance of the organic EL element 20 but also the voltage drop due to the power supply wiring 90.

  When the voltage drop is large due to the wiring resistance of the power supply wiring 90, the power consumption of the display panel 1 is remarkably increased.

The pixel width Wp, which is the length of one pixel in the row direction, the number of pixels in the row direction (1366), the extension from the first lead-out wiring to one wiring terminal outside the pixel region, As a result of considering the extended portion from the first routing wiring to the other wiring terminal, when the panel size of the display panel 1 is 32 inches and 40 inches, the total length of the first routing wiring is 706.7 mm and 895, respectively. .2mm. Here, when the line width WL of the power supply wiring 90 and the line width WL of the common wiring 91 are widened, the area of the organic EL layer 20b is structurally reduced, and further, a parasitic capacitance with other wiring is generated, resulting in further voltage drop. Therefore, it is desirable to suppress the width WL of the power supply wiring 90 and the line width WL of the common wiring 91 to one fifth or less of the pixel width Wp. Considering this, when the panel size of the display panel 1 is 32 inches and 40 inches, the width WL is within 34 μm and 44 μm, respectively. Further, the maximum film thickness Hmax of the power supply wiring 90 and the common wiring 91 is 1.5 times the minimum processing dimension 4 μm of the transistors 21 to 23, that is, 6 μm, in consideration of the aspect ratio. Thus the maximum cross-sectional area Smax of the feed interconnection 90 and common interconnection 91 is 32-inch 40-inch respectively 204Myuemu ^2, a 264μm ^2.

  For such a 32-inch display panel 1, in order to reduce the maximum voltage drop of the power supply wiring 90 and the common wiring 91 when they are fully lit so that the maximum current flows, as shown in FIG. The wiring resistivity ρ / cross-sectional area S of each of the power supply wiring 90 and the common wiring 91 needs to be set to 4.7 Ω / cm or less. FIG. 20 shows the correlation between the cross-sectional area of each of the power supply wiring 90 and the common wiring 91 of the 32-inch display panel 1 and the current density. Note that the resistivity allowed at the time of the maximum cross-sectional area Smax of the power supply wiring 90 and the common wiring 91 is 9.6 μΩcm at 32 inches and 6.4 μΩcm at 40 inches.

  For the 40-inch display panel 1, in order to set the maximum voltage drop of the power supply wiring 90 and the common wiring 91 to 1 V or less when all lights up so that the maximum current flows, as shown in FIG. The wiring resistivity ρ / cross-sectional area S of each of the wiring 90 and the common wiring 91 needs to be set to 2.4 Ω / cm or less. FIG. 22 shows the correlation between the cross-sectional area of each of the power supply wiring 90 and the common wiring 91 of the 40-inch display panel 1 and the current density.

  The failure life MTF that does not operate due to the failure of the power supply wiring 90 and the common wiring 91 satisfies the following formula (2).

MTF = A exp (Ea / K _b T) / ρJ ² (2)

Ea is the activation energy, the resistivity of the ^{_{K b T = 8.617 × 10- 5}} eV, ρ is the feed interconnection 90 and common interconnection 91, J is the current density.

The failure life MTF of the power supply wiring 90 and the common wiring 91 is limited by an increase in resistivity or electromigration. When the power supply wiring 90 and the common wiring 91 are set to be Al-based (Al alone or an alloy such as AlTi or AlNd) and the MTF is estimated for 10,000 hours at an operating temperature of 85 ° C., the current density J is 2.1 × 10 ⁴ A. / Cm ² or less. Similarly, when the power supply wiring 90 and the common wiring 91 are set to Cu, the power supply wiring 90 and the common wiring 91 need to be 2.8 × 10 ⁶ A / cm ² or less. It is assumed that materials other than Al in the Al alloy have a lower resistivity than Al.
In consideration of these points, in the 32-inch display panel 1, the cross-sectional areas of the Al-based power supply wiring 90 and the common wiring 91 are such that the power supply wiring 90 and the common wiring 91 do not fail in 10,000 hours in the fully lit state. S needs to be 57 μm ² or more from FIG. 20, and similarly, the cross-sectional areas S of the Cu power supply wiring 90 and the common wiring 91 need to be 0.43 μm ² or more from FIG.

In the 40-inch display panel 1, the cross-sectional areas S of the Al-based power supply wiring 90 and the common wiring 91 so that the power supply wiring 90 and the common wiring 91 do not fail in 10,000 hours in the fully lit state are shown in FIG. 92 μm ² or more is required, and similarly, the cross-sectional areas S of the Cu power supply wiring 90 and the common wiring 91 are required to be 0.69 μm ² or more from FIG.

If the Al-based power supply wiring 90 and the common wiring 91 have an Al-based resistivity of 4.00 μΩcm, the 32-inch display panel 1 has a wiring resistivity ρ / cross-sectional area S of 4.7 Ω / cm or less as described above. Therefore, the minimum cross-sectional area Smin is 85.1 μm ² . At this time, since the wiring width WL of the power supply wiring 90 and the common wiring 91 is within 34 μm as described above, the minimum film thickness Hmin of the power supply wiring 90 and the common wiring 91 is 2.50 μm.

Further, in the 40-inch display panel 1 of the Al-based power supply wiring 90 and the common wiring 91, the wiring resistivity ρ / cross-sectional area S is 2.4Ω / cm or less as described above, so the minimum cross-sectional area Smin is 167 μm ² . At this time, since the wiring width WL of the power supply wiring 90 and the common wiring 91 is within 44 μm as described above, the minimum film thickness Hmin of the power supply wiring 90 and the common wiring 91 is 3.80 μm.

In the Cu power supply wiring 90 and the common wiring 91, if the Cu resistivity is 2.10 μΩcm, the 32-inch display panel 1 has the wiring resistivity ρ / cross-sectional area S of 4.7 Ω / cm or less as described above. The minimum cross-sectional area Smin is 44.7 μm ² . At this time, since the wiring width WL of the power supply wiring 90 and the common wiring 91 is within 34 μm as described above, the minimum film thickness Hmin of the power supply wiring 90 and the common wiring 91 is 1.31 μm.

Further, in the 40-inch display panel 1 of the Cu power supply wiring 90 and the common wiring 91, the wiring resistivity ρ / cross-sectional area S is 2.4Ω / cm or less as described above, so the minimum cross-sectional area Smin is 87.5 μm ^2. . At this time, since the wiring width WL of the power supply wiring 90 and the common wiring 91 is within 44 μm as described above, the minimum film thickness Hmin of the power supply wiring 90 and the common wiring 91 is 1.99 μm.

  From the above, in order to operate the display panel 1 normally and with low power consumption, it is preferable to set the voltage drop in the power supply wiring 90 and the common wiring 91 to 1 V or less. When the wiring 90 and the common wiring 91 are an Al-based 32-inch panel, the film thickness H is 2.50 μm to 6 μm, the width WL is 14.1 μm to 34.0 μm, and the resistivity is 4.0 μΩcm to 9.6 μΩcm. In a 40-inch panel in which the wiring 90 and the common wiring 91 are Al-based, when the power supply wiring 90 and the common wiring 91 are Al-based, the film thickness H is 3.80 μm to 6 μm, the width WL is 27.8 μm to 44.0 μm, The resistivity is 4.0 μΩcm to 9.6 μΩcm.

In general, in the case of the Al-based power supply wiring 90 and the common wiring 91, the film thickness H is 2.50 μm to 6 μm, the width WL is 14.1 μm to 44 μm, and the resistivity is 4.0 μΩcm to 9.6 μΩcm.
Similarly, in a 32-inch panel in which the power supply wiring 90 and the common wiring 91 are Cu, the film thickness H is 1.31 μm to 6 μm, the width WL is 7.45 μm to 34 μm, and the resistivity is 2.1 μΩcm to 9.6 μΩcm. When the power supply wiring 90 and the common wiring 91 are 40-inch panels made of Cu, when the power supply wiring 90 and the common wiring 91 are Cu-based, the film thickness H is 1.99 μm to 6 μm, the width WL is 14.6 μm to 44.0 μm, The resistivity is 2.1 μΩcm to 9.6 μΩcm.

In general, in the case of the Cu power supply wiring 90 and the common wiring 91, the film thickness H is 1.31 μm to 6 μm, the width WL is 7.45 μm to 44 μm, and the resistivity is 2.1 μΩcm to 9.6 μΩcm.
Therefore, when an Al-based material or Cu is applied as the power supply wiring 90 and the common wiring 91, the power supply wiring 90 and the common wiring 91 of the display panel 1 have a film thickness H of 1.31 μm to 6 μm and a width WL of 7.45 μm. 44 μm and resistivity becomes 2.1 μΩcm to 9.6 μΩcm.

  As described above, since the common wiring 91 provided on the surface of the counter electrode 20c is formed in a different layer from the electrodes of the transistors 21 to 23, the common wiring 91 can be made thicker. Can be reduced in resistance. Since the low-resistance common wiring 91 is electrically connected to the counter electrode 20c, the voltage of the counter electrode 20c can be made uniform in the plane even when the counter electrode 20c itself is thinned to have a higher resistance. . Therefore, even if the same potential is applied to all the subpixel electrodes 20a, the light emission intensity of any organic EL layer 20b becomes substantially equal, and the light emission intensity in the plane can be made uniform.

  Further, when the display panel 1 is used as a top emission type, the counter electrode 20c can be made thinner, so that light emitted from the organic EL layer 20b is not easily attenuated while being transmitted through the counter electrode 20c. Furthermore, since the common wiring 91 is provided between the subpixel electrodes 20a adjacent in the horizontal direction in plan view, a decrease in the pixel aperture ratio can be minimized.

  In addition, the power supply wirings 90r, 90g, and 90b embedded in the groove 34 of the planarizing film 33 and the protective insulating film 32 between the rows of the subpixels P in the horizontal direction are different from the electrodes of the transistors 21 to 23. Therefore, the feed lines 90r, 90g, and 90b can be made thick, and the feed lines 90r, 90g, and 90b can be reduced in resistance. Since the low-resistance power supply wirings 90r, 90g, and 90b are respectively stacked on the thin-film supply lines Zr, Zg, and Zb, the voltage drop of the supply lines Zr, Zg, and Zb can be suppressed. Signal delay of Zg, Zb and the power supply wirings 90r, 90g, 90b can be suppressed. For example, if the display panel 1 is enlarged when the power supply wirings 90r, 90g, and 90b are not provided, an in-plane emission intensity unevenness occurs due to a voltage drop of the supply lines Zr, Zg, and Zb, or an organic light that does not emit light. There is a possibility that the EL element 20 exists. However, in this embodiment, since the low-resistance power supply wirings 90r, 90g, and 90b are respectively connected to the supply lines Zr, Zg, and Zb, unevenness of the in-plane light emission intensity can be suppressed, and organic light is not emitted. The EL element 20 can be eliminated.

  Further, since the resistance of the power supply wirings 90r, 90g, 90b is reduced by increasing the thickness of the power supply wirings 90r, 90g, 90b, the width of the power supply wirings 90r, 90g, 90b can be reduced. Furthermore, since the narrow power supply wirings 90r, 90g, and 90b are provided between the subpixel electrodes 20a that are adjacent in the vertical direction in plan view, a decrease in the pixel aperture ratio can be minimized.

  Further, since the liquid repellent insulating film 53 is formed on the surfaces of the power supply wirings 90r, 90g, 90b and the liquid repellent insulating film 53 is exposed on the surface of the planarizing film 33, the organic EL layer 20b is applied by a wet coating method. Depending on the color, it can be applied separately for each color. Therefore, it is not necessary to separately provide banks for partitioning the subpixels P, and the display panel 1 can be easily manufactured.

  Further, since the liquid repellent insulating film 53 has electrical insulation, it is possible to avoid a short circuit between the power supply wirings 90r, 90g, 90b and the counter electrode 20c.

[Second Embodiment]
The display panel 101 according to the second embodiment will be described with reference to FIGS. In addition, as shown in FIGS. 12-16, about the display panel 101, the same code | symbol is attached | subjected with respect to the same part as any part of the display panel 1 in 1st Embodiment, and about the same part. Description is omitted.

  FIG. 12 is a schematic plan view of the 4-pixel pixel 3 of the display panel 101. As shown in FIG. 12, the arrangement of the pixel 3, subpixels Pr, Pg, Pb and signal lines Yr, Yg, Yb of the display panel 101 is the same as that of the pixel 3, subpixels Pr, Pg, Pb and signal lines of the display panel 1. It is the same as the arrangement of Yr, Yg, Yb.

  In the display panel 1 of the first embodiment, three supply lines Zr, Zg, Zb and one scanning line X are provided for each row of the pixels 3 in the horizontal direction, and the columns of the pixels 3 in the vertical direction are provided. One common wiring 91 is provided for each column. On the other hand, in the display panel 101 according to the second embodiment, two supply lines ZA and ZB, two power supply lines 90A and 90B, and one scan are performed for each row of pixels 3 in the horizontal direction. A line XA, one selection wiring 89A, and three common wirings 91A are provided.

  The supply lines ZA and ZB, the power supply wirings 90A and 90B, the scanning line XA, the selection wiring 89A, and the common wiring 91A all extend in the horizontal direction.

  The supply line ZA and the power supply wiring 90A are arranged between a row of blue subpixels Pb arranged in the horizontal direction and a row of red subpixels Pr adjacent thereto. The power supply wiring 90A and the common wiring 91A overlap the supply line ZA, and the power supply wiring 90A is electrically connected to the supply line ZA. However, the common wiring 91A is not electrically connected to either the supply line ZA or the power supply wiring 90A.

  The supply line ZB and the power supply wiring 90B are arranged between a row of red subpixels Pr arranged in the horizontal direction and a row of green subpixels Pg adjacent thereto. The power supply line 90B and the common line 91B overlap the supply line ZB, and the power supply line 90B is electrically connected to the supply line ZB, but the common line 91A is not electrically connected to either the supply line ZB or the power supply line 90B.

  The scanning line XA and the selection wiring 89A are arranged between a row of green subpixels Pg and a row of blue subpixels Pb adjacent thereto arranged in the horizontal direction. The selection wiring 89A and the common wiring 91A overlap the scanning line XA, and the selection wiring 89A is conductive to the scanning line XA, but the common wiring 91A is not conductive to either the scanning line XA or the selection wiring 89A.

  Two supply lines ZA and ZB are electrically connected to each other in the peripheral portion of the display panel 101.

  13 is a plan view mainly showing electrodes of the red subpixel Pr, FIG. 14 is a plan view mainly showing electrodes of the green subpixel Pg, and FIG. 15 is an electrode of the blue subpixel Pb. It is the top view which mainly showed. As shown in FIGS. 13 to 15, in the red subpixel Pr, the drain 22d of the holding transistor 22 and the drain 23d of the driving transistor 23 are provided integrally with the supply line ZA, and in the green subpixel Pg, the holding transistor 22 is provided. The drain 22d and the drain 23d of the driving transistor 23 are provided integrally with the supply line ZB. On the other hand, in the blue subpixel Pb, both the drain 22d of the holding transistor 22 and the drain 23d of the driving transistor 23 are provided separately from the supply lines ZA and ZB. Therefore, the drain 22d of the holding transistor 22 and the drain 23d of the driving transistor 23 of the blue subpixel Pb are electrically connected to the supply lines ZA and ZB as follows.

  That is, one connection line 96 per pixel 3 is provided so as to cut the pixel 3 vertically. The connection line 96 is formed by patterning the gate layer and is covered with the gate insulating film 31. A contact hole 97 is formed at a portion where the supply line ZB of the gate insulating film 31 and the connection line 96 overlap, and the connection line 96 is electrically connected to the supply line ZB through the contact hole 97. In the blue subpixel Pb, a contact hole 98 is formed at a position where the connection line 96 of the gate insulating film 31 and the drain 23d of the drive transistor 23 overlap, and the connection line 96 and the drive transistor 23 are connected via the contact hole 98. The drain 23d is conductive. As described above, the drain 22d of the holding transistor 22 and the drain 23d of the driving transistor 23 of the blue subpixel Pb are electrically connected to the supply line ZB through the connection line 96.

  16 is a cross-sectional view taken along the broken line XVI-XVI shown in FIGS. 13 to 15 in the thickness direction of the insulating substrate 2, and FIG. 17 is a broken line shown in FIG. It is arrow sectional drawing cut | disconnected in the thickness direction of the insulated substrate 2 along XVII-XVII. As shown in FIGS. 16 and 17, a long groove 34 </ b> A is recessed along the horizontal direction at a portion of the protective insulating film 32 and the planarizing film 33 that overlaps the supply line ZA. An elongated groove 34B is recessed along the horizontal direction at a location overlapping the supply line ZB of the conversion film 33, and at a location overlapping the scanning line XA of the protective insulating film 32 and the planarization film 33 in the horizontal direction. A long groove 34 </ b> C is recessed along. In the groove 34A, the groove 34B, and the groove 34C, a power supply wiring 90A, a power supply wiring 90B, and a selection wiring 89A are respectively embedded, and the power supply wirings 90A and 90B and the selection wiring 89A are supplied in the grooves 34A, 34B, and 34C. They are stacked on ZA, supply line ZB, and scanning line ZA, respectively. As described above, the power supply wiring 90A, the power supply wiring 90B, and the selection wiring 89A are electrically connected to the supply line ZA, the supply line ZB, and the scanning line XA, respectively. For this reason, the power supply wirings 90A and 90B and the selection wiring 89A are located below the subpixel electrode 20c.

  A liquid repellent insulating film 53A having water repellency and oil repellency is formed on the surfaces of the power supply wiring 90A, the power supply wiring 90B, and the selection wiring 89A, respectively, and the liquid repellent insulating film 53A protrudes from the surface of the planarization film 33. is doing. Thus, the liquid repellent insulating film 53A is exposed on the surface of the planarizing film 33. The liquid repellent insulating film 53A is made of a fluororesin electrodeposition paint, and a voltage is applied to the power supply wiring 90A, the power supply wiring 90B, and the selection wiring 89A exposed by immersing the insulating substrate 2 in the solution of the fluororesin electrodeposition paint. Films are formed on these surfaces by electrodeposition coating. Using the water / oil repellency of the liquid repellent insulating film 53A, the organic EL layer 20b of the organic EL element 20 is applied for each color by a wet coating method (for example, an ink jet method). Examples of the electrodeposition paint include Elecoat Nicelon, Elecoat Nicelon CTR, Elecoat AMF (manufactured by Shimizu Corporation), and the like.

  On the counter electrode 20c, a common wiring 91A is formed along the liquid-repellent insulating film 53A, and the common wiring 91A overlaps the power supply wiring 90A, the power supply wiring 90B, and the selection wiring 89A in plan view. For this reason, the common wiring 91A is electrically connected to the counter electrode 20c.

  Except for what has been described above, the display panel 101 is configured in the same manner as the display panel 1 of the first embodiment.

  The driving method of the display panel 101 is the same as the driving method of the display panel 1 of the first embodiment.

  Also in the present embodiment, the width, cross-sectional area, and resistivity of the power supply wiring and the common wiring are the same as those in the first embodiment, and the common wiring 91A is formed thick by a plating method. Even if the film thickness is reduced to a higher resistance, the voltage of the counter electrode 20c can be made uniform in the plane. Further, since the power supply wirings 90A and 90B are thickly formed by plating, voltage drop of the supply lines ZA and ZB can be suppressed, and unevenness of emission intensity in the surface can be suppressed.

  Further, since the selection wiring 89A stacked on the scanning line XA is formed thick by plating, signal delay of the scanning line XA and the selection wiring 89A can be further suppressed. That is, when attention is paid to the row of the sub-pixels P in the horizontal direction, the shift pulse becomes high level at the same time without delaying any sub-pixel P.

  Further, since the liquid repellent insulating film 53A has electrical insulation, it is possible to avoid a short circuit between the power supply wirings 90A and 90B, the selection wiring 89A, and the counter electrode 20c.

[Modification 1]
The present invention is not limited to the above-described embodiments, and various improvements and design changes may be made without departing from the spirit of the present invention.

  In each of the above embodiments, the transistors 21 to 23 are described as N-channel field effect transistors. The transistors 21 to 23 may be P-channel field effect transistors. In that case, in the circuit configuration of FIG. 2, the relationship between the sources 21s, 22s, and 23s of the transistors 21 to 23 and the drains 21d, 22d, and 23d of the transistors 21 to 23 is reversed. For example, when the drive transistor 23 is a P-channel field effect transistor, the drain 23d of the drive transistor 23 is conducted to the subpixel electrode 20a of the organic EL element 20, and the source 23s is conducted to the supply line Z.

[Modification 2]
In each of the above embodiments, three transistors 21 to 23 are provided for one dot sub-pixel P. However, one or more transistors are provided for one dot sub-pixel P, and active using these transistors. The present invention can be applied to any display panel that can be driven.

[Modification 3]
In each of the above embodiments, the signal line Y is patterned from the gate layer, but the signal line Y may be patterned from the drain layer. In this case, the scanning line X and the supply line Z are patterned from the gate layer, and the signal line Y is higher than the scanning line X and the supply line Z.

[Modification 4]
Further, in each of the above-described embodiments, the supply lines Z _{1 to} Z _m of the display panels 1 and 101 are relatively third peripheral portions (upper side in FIGS. 1 and 12 with respect to the scanning lines X _{1 to} X _m ). However, it may be located at the fourth peripheral edge (the lower peripheral edge in FIGS. 1 and 12).

[Modification 5]
In the above embodiment, the organic EL layer 20b of the red sub-pixel Pr, the organic EL layer 20b of the green sub-pixel Pg, and the organic EL layer 20b of the blue sub-pixel Pb are repeatedly arranged for each row in this order. It is not necessary to arrange.
A plurality of the above modifications may be combined.

3 is a plan view showing a pixel 3 of 4 pixels of the display panel 1. FIG. 3 is an equivalent circuit diagram of a sub-pixel P of the display panel 1. FIG. It is the top view which showed the electrode of red subpixel Pr. It is the top view which showed the electrode of the green sub pixel Pg. It is the top view which showed the electrode of the blue sub pixel Pb. It is arrow sectional drawing of the cross section along the fracture | rupture line VI-VI shown by FIGS. It is arrow sectional drawing of the cross section along the fracture | rupture line VII-VII shown by FIG. 3 is a plan view showing a main configuration of the first display panel 1. FIG. 3 is a timing chart for explaining a driving method of the first display panel 1. 4 is a plan view showing a main configuration of a second display panel 1. FIG. 6 is a timing chart for explaining a driving method of the second display panel 1. 4 is a plan view showing a pixel 3 of 4 pixels of the display panel 101. FIG. It is the top view which showed the electrode of red subpixel Pr. It is the top view which showed the electrode of the green sub pixel Pg. It is the top view which showed the electrode of the blue sub pixel Pb. It is arrow sectional drawing of the cross section along the fracture | rupture line XVI-XVI shown by FIGS. It is arrow sectional drawing of the cross section along the fracture | rupture line XVII-XVII shown by FIG. 4 is a graph showing current-voltage characteristics of a drive transistor 23 and an organic EL element 20 of each subpixel. It is a graph which shows the correlation of each maximum voltage drop of the electric power feeding wiring 90 of the 32 inch display panel 1, and the common wiring 91, and wiring resistivity (rho) / sectional area S. FIG. It is a graph which shows the correlation of each cross-sectional area and electric current density of the electric power feeding wiring 90 of the 32-inch display panel 1, and the common wiring 91. FIG. It is a graph which shows the correlation of each maximum voltage drop of the electric power feeding wiring 90 of the 40-inch display panel 1, and the common wiring 91, and wiring resistivity (rho) / sectional area S. FIG. It is a graph which shows the correlation of each cross-sectional area of the electric power feeding wiring 90 of the 40-inch display panel 1, and the common wiring 91, and a current density.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,101 Display panel 2 Insulating substrate 20a Subpixel electrode 20b Organic EL layer 20c Counter electrode 21 Switch transistor 22 Holding transistor 23 Drive transistor 21d, 22d, 23d Drain 21s, 22s, 23s Source 21g, 22g, 23g Gate 31 Gate insulating film 53, 53A Liquid repellent insulating film 89A Selection wiring 90r, 90g, 90b, 90A, 90B Power supply wiring P Subpixel

Claims (12)

A substrate,
A plurality of transistors provided on the substrate for each sub-pixel, each including a gate, a gate insulating film, and a source / drain;
A protective insulating film covering the plurality of transistors;
A planarization film laminated on the protective insulating film;
A plurality of wirings formed of a conductive layer different from the gate, source, and drain of the plurality of transistors, and embedded in a groove dividing the protective insulating film and the planarization film on the substrate;
A water- and oil-repellent liquid-repellent insulating film formed so as to cover each of the wirings and protrude from the surface of the planarizing film;
A plurality of subpixel electrodes arranged on each of the substrates along the wirings between the wirings and provided for each subpixel;
A light emitting layer formed on each of the subpixel electrodes by a wet coating method;
A display panel comprising: a counter electrode coated with the light emitting layer and the liquid repellent insulating film.   The display panel according to claim 1, wherein the liquid repellent insulating film is made of a fluorine-based electrodeposition paint electrodeposited on the wirings by an electrodeposition coating method.   The display panel according to claim 1, wherein a thickness of the wiring is 1.31 to 6 μm.   The display panel according to claim 1, wherein a width of the wiring is 7.45 to 44 μm.   The display panel according to claim 1, wherein a resistivity of the wiring is 2.1 to 9.6 μΩcm.   As the transistor, a drive transistor in which one of a source and a drain is connected to a subpixel electrode, a switch transistor for passing a write current between the source and drain of the drive transistor, and between the source and gate of the drive transistor during a light emission period The display panel according to claim 1, wherein a holding transistor that holds the voltage of 1 is provided for each subpixel.   The display panel according to claim 6, wherein the plurality of wirings are power supply wirings connected to the other of the source and the drain of the driving transistor.   The display panel according to claim 7, wherein the power supply wiring is located below the subpixel electrode.   The display panel according to claim 7, wherein the power supply wiring is embedded in a groove provided in a planarizing film located below the subpixel electrode.   The display panel according to claim 6, wherein the plurality of wirings are selection wirings for selecting the switch transistor.   The display panel according to claim 10, wherein the selection wiring is positioned below the sub-pixel electrode in the previous period.   The display panel according to claim 10, wherein the selection wiring is embedded in a groove provided in a planarization film located below the subpixel electrode.

Images