JP4378511B2 - Electronic component built-in wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which has high reliability of mechanical strength and moisture resistance as a semiconductor device and can be improved in integration degree by forming a wiring pattern over the entire surface of a multilayer substrate, and to provide a method for manufacturing the same. <P>SOLUTION: On both sides of a core substrate 10a having a through hole layer 18, an insulating substrate and the wiring pattern are laminated one another. A conductor bump is formed through respective insulating substrates 24, 25, 32, 34, 42, and 44 along the thickness, and respective wiring patterns are electrically connected to each other. In one of the insulating substrates, a mounted semiconductor element is buried. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
BACKGROUND OF THE INVENTION
  The present inventionElectronic component built-in wiring board with built-in electronic components such as semiconductor elements and passive elementsAnd its manufacturing method.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, a so-called embedded type semiconductor device in which a semiconductor element is embedded in a multilayer board in which a plurality of printed wiring boards are stacked in multiple stages is known. FIG. 15 is a vertical sectional view of a typical embedded semiconductor device 100. As shown in FIG. 15, in this semiconductor device 100, three layers of printed wiring boards 101, 102, and 103 are laminated, and a total of four layers of wiring patterns 104, 105, 106, and 107 are arranged. The patterns 104 to 107 are interlayer-connected by interlayer connection members such as through holes 108A to 108E. The semiconductor element 120 is mounted on a wiring pad 109 disposed between the printed wiring boards 101 and 102, and the semiconductor element 120 is placed in a space 110 in which a part of the printed wiring boards 102 and 103 is cut out. Buried.
[0003]
[Problems to be solved by the invention]
By the way, in order to manufacture such a buried type semiconductor device 100, a part 110 of the printed wiring boards 102 and 103 is cut out from one side to provide a space 110 for embedding the semiconductor element 120, and the semiconductor element 120 is mounted. In general, the semiconductor element 120 is embedded by filling the gap around the semiconductor element 120 with an insulating sealing material 130 such as an epoxy resin and then curing it.
[0004]
However, if a part of the printed wiring boards 102 and 103 is mechanically cut out in this way, the mechanical strength of the printed wiring boards 102 and 103 is reduced, or the cut surface when the printed wiring boards 102 and 103 are cut out, There is a problem that moisture easily enters from the boundary surface with the filled insulating sealing material 130 and the moisture resistance is lowered.
[0005]
Furthermore, since the wiring pattern cannot be formed in the portion where the insulating sealing material 130 is filled in the hollowed portion of the printed wiring board 103, there is a problem in that the wiring pattern cannot be formed using this portion and the degree of integration cannot be increased. is there.
[0006]
The present invention has been made to solve the above conventional problems. That is, the present invention provides a semiconductor device having high reliability as a semiconductor device such as mechanical strength and moisture resistance, and capable of improving the degree of integration by forming a wiring pattern on the entire surface of a multilayer board, and a method for manufacturing the same. For the purpose.
[0007]
[Means for Solving the Problems]
  The wiring board with a built-in electronic component of the present invention,(A) A multilayer board in which a wiring pattern including a plurality of electrode pads is formed on one surface, a wiring pattern is formed on the other surface, and the wiring patterns on each surface are interlayer-connected by conductive bumps between the opposing surfaces An intermediate body, (B) an electronic component mounted on the multilayer plate intermediate body by connecting a plurality of electrodes to the electrode pad, and (C) an opening through which the electronic component can be inserted, (D) a wiring pattern is formed on both surfaces, and an interlayer connection member through which the wiring pattern on each surface penetrates in the thickness direction; The electronic component is provided with an opening through which the electronic component can be inserted, and conductor bumps are provided on the wiring pattern on one side, and the electronic component is inserted into the opening, and First conductor bump A core substrate that penetrates through the insulating substrate and abuts the tip of the wiring substrate on the multilayer board intermediate body so that the wiring pattern on the one surface is connected to the opposing wiring pattern of the multilayer board intermediate body; and (E) the core (F) A wiring pattern is formed on both surfaces, and the wiring patterns on each surface are connected to each other by conductor bumps between the opposing surfaces, and the wiring pattern on one surface Conductive bumps are provided on the upper surface, the conductive bumps penetrate through the second insulating substrate, and the tip is brought into contact with the wiring pattern of the core substrate, so that the wiring pattern on the one surface faces the core substrate. A two-layer board with bumps connected to the wiring pattern to be
  These are electronic component built-in wiring boards integrated by heating and pressing,
The first and second insulating substrates are respectively disposed on the multilayer plate intermediate or the core substrate in the state of an insulating substrate precursor, and are crosslinked by heating and pressing, and the insulating substrate precursor is heated and pressurized. Each opening of the first insulating substrate and the core substrate is sealed with resin that has exuded from the body.It is characterized by that.
[0008]
  SaidElectronic component built-in wiring boardAs an example of the conductor bump, a paste bump formed by printing a conductive paste can be given.
[0009]
  SaidElectronic component built-in wiring boardAs an example of the conductor bump, a metal bump made of a metal obtained by etching a metal plate or a plated metal can be cited.
[0010]
  SaidElectronic component built-in wiring boardIn the aboveElectronic componentsAs an example, a face-down type semiconductor element can be given.
[0011]
  SaidElectronic component built-in wiring boardIn the aboveElectronic componentsAs an example, a face-up type semiconductor element can be given.
[0012]
  SaidElectronic component built-in wiring boardIn the aboveElectronic componentsAs an example, a passive element can be mentioned.
[0013]
  SaidElectronic component built-in wiring boardIn the aboveElectronic componentsAnd the electrode pad may be electrically connected via a paste bump made of a conductive paste.
[0014]
  SaidElectronic component built-in wiring boardIn the aboveElectronic componentsAnd the electrode pad may be electrically connected via a metal bump.
[0015]
  SaidElectronic component built-in wiring boardIn the aboveElectronic componentsAnd the electrode pad may be electrically connected via a bonding wire.
[0016]
  In the electronic component built-in wiring board,The first insulating substratePenetrate,coreSubstrateOn the bottom side (multilayer board intermediate side)The wiring pattern and the electronic parts were mountedOn the upper surface side (core substrate side) of the multilayer board intermediateConductive bumps that connect the wiring pattern to the interlayer are paste bumps formed by printing conductive paste.Or metal bumpAndBottom surface of core substrateThe side is large diameterMulti-layer board intermediateIt may be substantially frustoconical with the side having a small diameter.
[0017]
  The interlayer connection member for interlayer connection of the wiring patterns on both surfaces of the core substrate may be a through-hole plating metal layer or a paste bump formed by printing a conductive paste.
[0018]
  SaidElectronic component built-in wiring boardIn the aboveElectronic componentsHowever, it may be a semiconductor element or a passive element.
[0019]
  SaidElectronic component built-in wiring boardExamples of the interlayer connection member include paste bumps or metal bumps having a height of 10 to 30 μm, a bottom surface radius of 20 to 50 μm, and a head radius of 5 to 10 μm.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
Hereinafter, the manufacture of the semiconductor device according to the first embodiment of the present invention will be described. FIG. 1 is a flowchart of a method for manufacturing a semiconductor device according to the present embodiment, and FIGS. 2, 3 and 4 are vertical cross-sectional views of the semiconductor device according to the present embodiment being manufactured.
[0024]
In order to manufacture the semiconductor device according to this embodiment, first, a so-called two-layer board in which wiring patterns are formed on both surfaces of an insulating substrate is prepared. This two-layer plate is manufactured by stacking copper foil on both surfaces of a prepreg impregnated with a thermosetting resin such as an epoxy resin in a reinforcing material sheet such as glass fiber and pressurizing under heating.
[0025]
The conductive plates 14 and 16 on the surface of the two-layer wiring board 10 are patterned. As a patterning method, for example, a photosensitive resin is applied, and a mask pattern (not shown) is formed by a photolithographic method in which a mask pattern is overlaid, exposed, and developed (step 1). Next, an etching process is performed on the masking (step 2). Thus, as shown in FIG. 2B, the two-layer board 10 on which the wiring patterns 14a and 16a are formed is formed.
[0026]
  Next, as shown in FIG. 2C by an optical method such as drilling or laser beam irradiation at a position where a through hole is formed on the two-layer plate 10.Insulating substrate 12Through hole 17To obtain a two-layer plate 10a formed with(Step 3). The two-layer board is then subjected to electroless plating or electrolytic plating.10aA metal layer is deposited on the surface and the inner wall of the through-hole 17 (step 4). Thus, the core substrate 10b having the through-hole metal layer 18 as shown in FIG. 2D is formed.
[0027]
  Meanwhile, the two-layer plate10Separately, a bumped copper foil is formed. In order to form the copper foil with bumps, first, a mask screen (not shown) provided with holes is set on the surface of the copper foil 20 as shown in FIG. 3E (step 1a). Next, a conductive paste such as a silver paste in which silver fine particles are dispersed in a resin is printed on the mask screen (step 2a).22Form. Then paste bump22Is dried and semi-cured (step 3a). Thus, a bumped copper foil 20a as shown in FIG. 3 (f) is obtained.
[0028]
Next, as shown in FIG. 3G, the prepreg 24 and the bumped copper foil 20a are overlaid on the lower surface side of the core substrate 10b formed as described above (step 5). Similarly, another prepreg 25 is also stacked on the upper surface side of the core substrate 10b, and another bumped copper foil 21a formed thereon by the same method as the above bumped copper foil 20a is as shown in FIG. 3 (g). (Step 5). Next, pressure is applied under heating in the superposed state (step 6). Then, the paste bumps 22 and 23 penetrate the prepregs 24 and 25, and come into contact with the wiring patterns 14a and 16a on the surface of the core substrate 10b as shown in FIG. At the same time, the paste bumps 22 and 23 and the prepregs 24 and 25 are completely cured by heat. Thus, a multilayer board intermediate 30 in which the copper foils 20 and 21 and the wiring patterns 14a and 16a are electrically connected as shown in FIG.
[0029]
Next, the copper foils 20 and 21 on the surface of the multilayer board intermediate 30 are patterned (step 7). In this way, as shown in FIG. 3 (i), the multilayer board intermediate 30a having the wiring patterns 20a, 21a and 21b formed on the surface is obtained. Next, among the surface wiring patterns of the multilayer board intermediate 30a, as shown in FIG. 4 (j), silver paste bumps 26, 26,... Are formed on the electrode pads 21b, 21b,. Are formed (step 8). The method for forming the silver paste bumps 26, 26,... Is substantially the same as the method for forming the conductor bumps 20, 20,.
[0030]
That is, a mask pattern in which through holes are provided in a bump forming portion is set (step 1a), and a conductive paste, for example, metal paste such as silver dispersed in a liquid resin such as an epoxy resin in the through holes. This is a method comprising filling the composition, squeegeeing from the upper surface of the mask pattern (step 2a), peeling off the mask pattern, drying, heating and semi-curing (step 3a).
[0031]
However, the silver paste bumps 26, 26,... Formed here have a height of 10 to 30 μm and a bottom surface radius of 20 to 50 μm. This is to correspond to the size of the semiconductor element 28 described later.
[0032]
Next, after the bumps are formed, the silver paste bumps 26, 26,. Thereafter, Ni plating treatment such as electrolytic plating or electroless plating is performed to form a Ni layer 27a as a barrier metal layer on the surface of the silver paste bumps 26, 26,... Next, an Au layer 27b is formed by performing an Au plating process on the Ni layer 27a. In this way, the multilayer board intermediate 30b is obtained.
[0033]
Next, as shown in FIG. 4 (k), an ACF (anisotropic conductive adhesive layer) 29 is formed on the formation surface of the silver paste bumps 26, 26,. The semiconductor element 28 is aligned so that the electrode plates 28a, 28a, ... face the electrode pads 21b, 21b, .... Next, when the semiconductor element 28 and the multilayer board intermediate 30b are pressed in this state, the silver paste bumps 26, 26,... Penetrate through the ACF (anisotropic conductive adhesive layer) 29 as shown in FIG. The electrode plates 28a, 28a,. At this time, Au layers 27b, 27b, ... are formed on the surface of the silver paste bumps 26, 26, ..., and the electrode plates 28a, 28a, ... are made of Al. Therefore, an Al-Au bond is formed between the silver paste bumps 26, 26, ... and the electrode plates 28a, 28a, ..., and between the electrode pads 21b, 21b, ... and the electrode plates 28a, 28a, ... They are electrically joined and mounted via the Au layer 27b, Ni layer 27a, silver paste bump 26, and ACF (anisotropic conductive adhesive layer) 29 (step 9). Thus, a multilayer board intermediate 30c on which the semiconductor element 28 as shown in FIG. 4 (k) is mounted is obtained.
[0034]
Next, as shown in FIG. 4 (l), the multilayer board intermediate 30c thus obtained has a prepreg 32 with a hole and a double-layer board 40 with bumps on the upper surface side, and a prepreg 42 and a double-layer board 50 with bumps on the lower surface side. (Step 10). The perforated prepreg 32 used here is formed by impregnating a reinforcing material such as glass fiber with an insulating liquid thermosetting resin such as an epoxy resin, and punching out a portion corresponding to a semiconductor element (step 1b) to provide an opening 32a. It is a thing. The two-layer boards 40 and 50 with bumps are formed, for example, by forming a wiring pattern on both surfaces of an insulating material layer through which an interlayer connection member is inserted, and forming a conductor bump on the wiring pattern.
[0035]
Next, in this state, the multilayer board intermediate 30c, the perforated prepreg 32, the prepreg 42, and the two-layer boards 40 and 50 with bumps are heated and pressed under pressure (step 11). Thus, as shown in FIG. 4 (m), the conductor bump 39 of the bumped double-layer board 40 penetrates the perforated prepreg 32 to electrically connect the multilayer board intermediate 30c and the bumped double-layer board 40. Join. Similarly, the conductor bumps 49 of the two-layer board 50 with bumps penetrate the prepreg 42 to electrically connect the multilayer board intermediate 30c and the two-layer board 50 with bumps.
[0036]
At the same time, the epoxy resin impregnated in the perforated prepreg 32 oozes out and air is expelled from the gap between the opening 32a of the perforated prepreg 32 and the semiconductor element 28 accommodated therein to seal the gap. . Further, the epoxy resin is cured by the heat at the time of the heat pressing, and a so-called eight-layer wiring type semiconductor device 28 built-in type semiconductor device 52 as shown in FIG.
[0037]
As described above, in the semiconductor device 52 according to this embodiment, since the core substrate in which the interlayer connection is formed by the through-hole metal layer 18 is used as the core substrate 30, the thickness of the core substrate 30 can be freely adjusted. can do. In the semiconductor device 52 according to this embodiment, the semiconductor element 28 is embedded in the multilayer board, and the boundary between the resin that seals the periphery of the semiconductor element 28 and the multilayer board that surrounds the outer periphery of the resin. Since the surface is not exposed on the surface of the semiconductor device 1, it is possible to prevent moisture from entering through this boundary surface, and as a result, a highly moisture-resistant semiconductor device is obtained.
[0038]
Further, in the semiconductor device 52 according to the present embodiment, the mounted semiconductor element is embedded inside, and only the surface of the two-layer plates 40 and 50 is exposed on the surface of the semiconductor device 52. Further wiring patterns and semiconductor elements can be mounted using the surfaces of the two-layer plates 40 and 50, and the degree of integration of the semiconductor device can be further improved.
[0039]
(Second Embodiment)
The manufacture of the semiconductor device according to the second embodiment of the present invention will be described below. FIG. 5 is a flowchart of the manufacturing method of the semiconductor device according to the present embodiment, and FIGS. 6, 7 and 8 are vertical cross-sectional views of the semiconductor device according to the present embodiment during manufacturing.
[0040]
In order to manufacture the semiconductor device according to this embodiment, first, a so-called two-layer board in which wiring patterns are formed on both surfaces of an insulating substrate is prepared. To manufacture this two-layer plate, first, a conductor plate 60 such as a copper foil is prepared as shown in FIG. The conductor bumps 62, 62,... Are formed on the conductor plate 60 using a printing technique.
[0041]
As a method of forming the conductor bumps 62, 62,..., For example, a mask screen having through holes in the bump forming portion is set on the conductor plate 60 (step 1), and the conductive is placed in the through holes of the mask screen. A method comprising squeegeeing a paste-like composition in which fine metal particles such as silver are dispersed in a liquid resin such as an epoxy resin and peeling the mask screen (step 2). After forming the substantially conical conductor bumps 62, 62,... As shown in FIG. 6B in this way, the conductor bumps 62, 62,... Are dried and semi-cured (step 3).
[0042]
Next, as shown in FIG. 6C, a prepreg (insulating substrate precursor) 64 on the conductor bumps 62, 62,..., That is, an insulating resin such as an epoxy resin in a reinforcing material such as a glass fiber mat. Then, another conductor plate 66 such as a copper foil is placed on the prepreg 64 (step 4), and in this state, heat press, that is, pressurizing under heating (step 5). . By this heat pressing, the conductor bumps 62, 62,... Pass through the prepreg 64, and the conductor plate 60 and the conductor plate 66 are electrically connected, and at the same time, the prepreg 64 is cured, and FIG. A two-layer wiring board 70 as shown in FIG.
[0043]
Next, the conductive plates 60 and 66 on the surface of the two-layer wiring board 70 are patterned (step 6). As a patterning method, for example, a photosensitive resin is applied, and a mask pattern (not shown) is formed by a photolithographic method or the like in which a mask pattern is overlaid and exposed and developed. Next, an etching process is performed on the masking. Thus, as shown in FIG. 6E, the two-layer board 70a on which the wiring patterns 60a, 66a, 66b are formed is formed.
[0044]
Next, among the surface wiring patterns of the two-layer board 70a, as shown in FIG. 7 (f), silver paste bumps 68, 68,... Are formed on electrode pads 66b, 66b,. Is formed (step 7). The method for forming the silver paste bumps 68, 68,... Is substantially the same as the method for forming the conductor bumps 62, 62,.
[0045]
That is, a mask screen having through holes provided in bump forming portions is set (step 1), and a conductive paste, for example, metal fine particles such as silver dispersed in a liquid resin such as an epoxy resin in the through holes. This is a method comprising filling the composition, squeegeeing from the upper surface of the mask pattern (step 2), peeling off the mask pattern, drying, heating and semi-curing (step 3).
[0046]
However, the silver paste bumps 68, 68,... Formed here have a height of 10 to 80 μm and a bottom surface radius of 20 to 50 μm. This is to correspond to the size of the semiconductor element 74 described later.
[0047]
Next, after the bumps are formed, the silver paste bumps 68, 68,. Thereafter, Ni plating such as electrolytic plating or electroless plating is performed, so that the barrier metal as shown in FIG. 7G is formed on the surface of the silver paste bumps 68, 68,. A Ni layer 69a as a layer is formed. Next, an Au layer 69b is formed by performing an Au plating process on the Ni layer 69a. In this way, a multilayer board intermediate 70d as shown in FIG. 7 (h) is obtained.
[0048]
Next, as shown in FIG. 7 (i), an ACF (anisotropic conductive adhesive layer) 72 is formed on the formation surface of the silver paste bumps 68, 68,. The semiconductor element 74 is aligned so that the electrode plates 74a, 74a,... Face the electrode pads 66b, 66b,. Next, when the semiconductor element 74 and the multilayer plate intermediate 70d are pressed in this state, the silver paste bumps 68, 68,... Penetrate through the ACF (anisotropic conductive adhesive layer) 72 as shown in FIG. And pressed by the electrode plates 74a, 74a,. At this time, Au layers 69b, 69b,... Are formed on the surfaces of the silver paste bumps 68, 68,..., And the electrode plates 74a, 74a,. Are formed between the electrode pads 66a, 74a,... And the electrode plates 74a, 74a,... And the Au layers 69b, Ni layer 69a, and silver paste. The bumps 68 and ACF (anisotropic conductive adhesive layer) 72 are electrically connected. Thus, the semiconductor element 74 is mounted (step 10). In this way, a multilayer board intermediate body 70e on which the semiconductor element 74 as shown in FIG. 7J is mounted is obtained.
[0049]
On the other hand, a two-layer board with bumps is formed separately from the multilayer board intermediate 70e. For the two-layer board with bumps, the same operation as in steps 1 to 5 of the present embodiment is performed to form a two-layer board as shown in FIG. 6D (steps 1a to 5a). Next, patterning is performed in step 6a. Thereafter, a conductor bump 162 is formed on the wiring pattern of the two-layer board to form a two-layer board 82 with bumps as shown at 82 in FIG.
[0050]
Further, a core substrate 78 is formed separately from the multilayer board intermediate 70e and the two-layer board 82 with bumps. In order to form the core substrate 78 according to the present embodiment, the core substrate as shown in FIG. 2D is formed by performing the same operations as in Steps 1 to 4 of the first embodiment (Step 2). 1b-4b). Next, a conductor bump 163 is formed on the surface wiring pattern of the core substrate by the same method as described above (step 5b), and further, the vicinity of the center of the core substrate is punched (step 6b), as shown by 78 in FIG. A core substrate 78 with punching bumps as described above is formed.
[0051]
Next, on the upper surface side of the multilayer board intermediate body 70e thus obtained, a two-layer board 82 with bumps in which a perforated prepreg 76, a core board 78 with punched bumps, a prepreg 80, and a conductor bump 162 are inserted is shown in FIG. k) (step 11). The perforated prepreg 76 used here is obtained by, for example, impregnating a reinforcing material such as glass fiber with an insulating liquid thermosetting resin such as an epoxy resin, and punching out a portion corresponding to a semiconductor element to provide an opening 76a. .
[0052]
Next, in this state, the multilayer board intermediate body 70e, the perforated prepreg 76, the core board 78 with punching bumps having the opening 78a, the prepreg 80, and the two-layer board 82 with bumps are heated and pressed under pressure (step 12). ). Thus, a multilayer board intermediate 84 as shown in FIG. 8 (l) is formed. Next, the two-layer plates 90 and 94 with bumps through which the prepregs 88 and 92 and the conductor bumps 162 and 165 are inserted are superimposed on the upper and lower surfaces of the multilayer board intermediate body 84 (step 13). Thereafter, when heat pressing is performed (step 14), a so-called 10-layer type semiconductor device 86 as shown in FIG. 9 (m) is obtained.
[0053]
As described above, since the semiconductor device 86 according to the present embodiment uses the perforated core substrate as the core substrate, the semiconductor element 74 having a large thickness can be incorporated.
[0054]
  (Third embodiment)
  In the semiconductor device according to this embodiment, a semiconductor element is embedded in one of a plurality of stacked insulating substrates. Figure10FIG. 2 is a vertical sectional view of the semiconductor device according to the present embodiment. In the semiconductor device 150 according to the present embodiment, a semiconductor element 281 is embedded in an insulating substrate 123 that is one of the insulating substrates 121 to 127 stacked in seven layers. A wiring pattern 141 is disposed on the surface of each of the insulating substrates 121 to 127. Paste bumps 141 are inserted in the thickness direction of each of the insulating substrates 121 to 127 to electrically connect the wiring patterns 141 on the surface of the insulating substrate.
[0055]
In order to manufacture the semiconductor device 150 according to the present embodiment, for example, a prepreg and a copper foil with bumps are stacked on the both sides of the core substrate 121 formed with the wiring pattern 141 and pressed under heating to be laminated in multiple layers. A method of forming the wiring pattern 141 by etching the copper foil on the surface is mentioned. In order to embed the semiconductor element 281, a method is conceivable in which the semiconductor element 281 is mounted on the wiring pattern 141 on the surface of the insulating substrate 122, a perforated prepreg and a copper foil with bumps are stacked, and pressure is applied under heating. According to the present embodiment, the semiconductor device 150 with a built-in semiconductor element 281 can be formed without forming a through-hole plating layer.
[0056]
(Fourth embodiment)
In the semiconductor device according to the present embodiment, a thick semiconductor element is embedded in the core substrate at the center of the insulating substrates stacked in multiple layers. FIG. 11 is a vertical sectional view of the semiconductor device according to the present embodiment. In the semiconductor device 152 according to this embodiment, a thick semiconductor element 741 is embedded in the core substrate 121 located at the center of the insulating substrates 121 to 127 stacked in seven layers.
[0057]
In order to manufacture the semiconductor device 152 according to the present embodiment, for example, a prepreg and a bumped copper foil are stacked on a surface of the insulating substrate 126 on which the wiring pattern 141 is formed, and pressed under heating to be laminated in multiple layers. A method of forming the wiring pattern 141 by etching the copper foil on the surface is mentioned. In order to embed the semiconductor element 741, the semiconductor element 741 is mounted on the wiring pattern 141 on the surface of the insulating substrate 126, a perforated prepreg, an opening near the middle of the core substrate 121, and a paste bump 221 are further formed. A method may be considered in which printed and cured materials are stacked and pressed under heating. According to this embodiment, the semiconductor device 152 in which the thick semiconductor element 741 is embedded near the center of the multilayer board can be formed.
[0058]
(Fifth embodiment)
In the semiconductor device according to this embodiment, a plurality of semiconductor elements are embedded in different layers of an insulating substrate stacked in multiple layers. FIG. 12 is a vertical sectional view of the semiconductor device according to the present embodiment. In the semiconductor device 154 according to the present embodiment, a thick semiconductor element 741 is embedded in the insulating substrates 121 and 125 among the insulating substrates 121 to 127 stacked in seven layers. A thin semiconductor element 281 is embedded in the insulating substrate 123. On the other hand, a thin semiconductor element 283 is also mounted on the upper surface of the uppermost insulating substrate 124. In the core substrate 121 at the center in the thickness direction, an interlayer connection is formed through a through-hole layer 181. On the other hand, in the other insulating substrates 122 to 127, interlayer connections are formed by paste bumps 221 that are inserted in the thickness direction.
[0059]
In order to manufacture the semiconductor device 154 according to the present embodiment, for example, the wiring pattern 141 is formed on both surfaces of the insulating substrate 126, and the prepreg and the bumped copper foil are overlapped on the layers connected by the paste bumps 221, and heated. And a method of forming a wiring pattern 141 by etching the copper foil on the surface. In order to embed the semiconductor element 741, the semiconductor element 741 is mounted on the wiring pattern 141 on the surface of the insulating substrate 126, and an opening is formed near the center of the core substrate 121 including the perforated prepreg and the through-hole layer 181. A method is also possible in which the paste bumps 221 printed and cured are stacked and pressed under heating. The semiconductor element 281 is embedded in the same manner as in the third embodiment. In order to mount the semiconductor element 283, seven layers of insulating substrates 121 to 127 are stacked, and then a paste bump is formed on the wiring pattern 141 on the upper surface of the uppermost insulating substrate 124. After the Ni plating and the Au plating are performed thereon, the semiconductor element 283 is pressurized and mounted under heating.
[0060]
According to the present embodiment, it is possible to form a semiconductor device 154 in which a plurality of semiconductor elements 741 and 281 including a thick semiconductor element 741 are embedded in an insulating substrate.
[0061]
Further, since the interlayer connection of the core substrate 121 is formed through the through-hole layer 181, a thick core substrate 121 can be used. Accordingly, a thick semiconductor element 741 can be embedded in the core substrate 121.
[0062]
(Sixth embodiment)
In the semiconductor device according to the present embodiment, paste bumps 221 are used for interlayer connection of the core substrate 121 in the semiconductor device 154 according to the fifth embodiment. FIG. 13 is a vertical sectional view of the semiconductor device according to this embodiment. In the semiconductor device 156 according to the present embodiment, paste bumps 221 are inserted in the thickness direction instead of the through-hole layer 181 in the interlayer connection of the core substrate 121 located in the center in the thickness direction of the insulating substrates 121 to 127. . To manufacture the semiconductor device 156 according to the present embodiment, the manufacturing procedure of the fifth embodiment is followed except that the paste bump 221 is inserted instead of forming the through-hole layer 181 as the core substrate 121. According to the present embodiment, the semiconductor device 156 in which the plurality of semiconductor elements 741 and 281 are embedded in the insulating substrate can be formed without forming the through-hole layer 181.
[0063]
(Seventh embodiment)
In the semiconductor device according to this embodiment, in addition to the plurality of semiconductor elements of the fifth embodiment, a plurality of passive elements are embedded in an insulating substrate stacked in multiple layers. FIG. 14 is a vertical sectional view of the semiconductor device according to the present embodiment. In the semiconductor device 158 according to the present embodiment, a capacitor, a resistor, or the like is formed on the insulating substrate 125, 122, and the wiring pattern 141 on the upper surface of the semiconductor element 154 of the semiconductor device 154 according to the fifth embodiment. Passive elements are mounted and embedded in the insulating substrates 125, 121, and 123.
[0064]
In order to manufacture the semiconductor device 158 according to the present embodiment, when the semiconductor elements 281, 741, and 283 are mounted in the manufacturing process of the fifth embodiment, the passive elements 231, 232, and 233 are mounted. To do. Other manufacturing processes are the same as those of the fifth embodiment. According to the semiconductor device 158 according to the present embodiment, a semiconductor device in which a plurality of semiconductor elements and passive elements are embedded in multiple stages can be formed.
[0065]
【The invention's effect】
  According to the present invention,An electronic component mounted on a multilayer board intermediate is converted into an insulating substrate precursor,Housed in the opening of the core substrate, and further on itThe insulating substrate is overlapped with another insulating substrate precursor and cross-linked by heat and pressure, and the openings of the insulating substrate and the core substrate are sealed by the resin exuded from the insulating substrate precursor during the heat and pressure. With being stoppedCompletely lidHas beenTherefore, the reliability as a semiconductor device such as mechanical strength and moisture resistance is high, and the degree of integration can be improved by forming a wiring pattern on the entire surface of the multilayer board.Electronic component built-in wiring boardIs obtained.
[Brief description of the drawings]
FIG. 1 is a flowchart of a method for manufacturing a semiconductor device according to a first embodiment.
FIG. 2 is a vertical sectional view of the semiconductor device according to the first embodiment during manufacture.
FIG. 3 is a vertical sectional view of the semiconductor device according to the first embodiment during manufacture.
FIG. 4 is a vertical cross-sectional view of the semiconductor device according to the first embodiment during manufacture.
FIG. 5 is a flowchart of a method for manufacturing a semiconductor device according to a second embodiment.
FIG. 6 is a vertical sectional view in the middle of manufacturing the semiconductor device according to the second embodiment.
FIG. 7 is a vertical sectional view in the middle of manufacturing the semiconductor device according to the second embodiment.
FIG. 8 is a vertical sectional view of the semiconductor device according to the second embodiment in the middle of manufacture.
FIG. 9 is a vertical sectional view in the middle of manufacturing the semiconductor device according to the second embodiment;
FIG. 10 is a vertical sectional view of a semiconductor device according to a third embodiment.
FIG. 11 is a vertical sectional view of a semiconductor device according to a fourth embodiment.
FIG. 12 is a vertical sectional view of a semiconductor device according to a fifth embodiment.
FIG. 13 is a vertical sectional view of a semiconductor device according to a sixth embodiment.
FIG. 14 is a vertical sectional view of a semiconductor device according to a seventh embodiment.
FIG. 15 is a vertical sectional view of a conventional semiconductor device.
[Explanation of symbols]
18 ... through-hole plating layer, 14a ... first wiring pattern, 16a ... second wiring pattern, 21a ... third wiring pattern, 38 ... fourth wiring pattern, 12 ... first substrate, 25 ... second 32 ... third substrate, 34 ... fourth substrate, 22 ... conductor bump, 23 ... conductor bump, 37 ... conductor bump, 47 ... conductor bump, 39 ... conductor bump, 49 ... conductor bump, 27a ... Ni Layer (barrier metal layer), 27b ... Au layer, 29 ... ACF, 28 ... semiconductor element.

Claims (4)

(A) A multilayer board in which a wiring pattern including a plurality of electrode pads is formed on one surface, a wiring pattern is formed on the other surface, and the wiring patterns on each surface are interlayer-connected by conductive bumps between the opposing surfaces Intermediates,
(B) an electronic component mounted on a multilayer board intermediate body by connecting a plurality of electrodes to the electrode pad;
(C) a first insulating substrate that includes an opening through which the electronic component can be inserted, and is disposed on a multilayer board intermediate body through which the electronic component is inserted;
(D) A wiring pattern is formed on both surfaces, the wiring pattern on each surface is interlayer-connected by an interlayer connection member penetrating in the thickness direction, and has an opening through which the electronic component can be inserted. Conductive bumps are provided on the wiring pattern so that the electronic parts are inserted into the openings, the conductive bumps are passed through the first insulating substrate, and the tip is formed on the wiring pattern of the multilayer board intermediate. A core substrate in which the wiring pattern on the one surface is connected to the opposing wiring pattern of the multilayer board intermediate body,
(E) a second insulating substrate disposed on the core substrate;
(F) A wiring pattern is formed on both surfaces, the wiring patterns on each surface are connected to each other by a conductive bump between the opposing surfaces, and a conductive bump is projected on the wiring pattern on one surface, A two-layer board with bumps, in which a conductor bump is passed through a second insulating substrate and a tip is brought into contact with the wiring pattern of the core substrate, and the wiring pattern of the one surface is connected to the opposing wiring pattern of the core substrate; With
These are electronic component built-in wiring boards integrated by heating and pressing,
The first and second insulating substrates are respectively disposed on the multilayer plate intermediate or the core substrate in the state of an insulating substrate precursor, and are crosslinked by heating and pressing, and the insulating substrate precursor is heated and pressurized. A wiring board with a built-in electronic component, wherein each opening of the first insulating substrate and the core substrate is sealed with a resin that has exuded from the body.   2. The wiring board with a built-in electronic component according to claim 1, wherein the conductor bump is a paste bump formed by printing a conductive paste. 3. The wiring board with a built- in electronic component according to claim 1, wherein the interlayer connection member is a through-hole plated metal layer. The wiring board with a built-in electronic component according to claim 1 or 2 , wherein the interlayer connection member is a paste bump formed by printing a conductive paste.

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