JP4369109B2 - Method for manufacturing semiconductor device - Google Patents

Description

[0001]
[Technical field to which the invention belongs]
The present invention relates to a semiconductor device in which an active layer is formed of a crystalline semiconductor film having a crystal structure and a manufacturing method thereof. In particular, the present invention relates to a thin film transistor in which an active region is formed using a crystalline semiconductor film, a semiconductor device such as an integrated circuit using the thin film transistor, and a method for manufacturing the semiconductor device. Note that a semiconductor device in this specification refers to all devices that function by utilizing semiconductor characteristics, and includes, for example, a semiconductor integrated circuit, an active matrix display device, a semiconductor integrated circuit, an active matrix display device, and the like. Other electronic devices such as electronic devices are included.
[0002]
[Prior art]
In the development of an active matrix type display which is a kind of flat panel display, a thin film transistor (a thin film transistor) in which a crystalline semiconductor film having a crystalline structure is used as an active layer as an element of a pixel portion or an integrated circuit transistor for driving the pixel portion (Hereinafter referred to as TFT)), a monolithic display in which a pixel portion and an integrated circuit such as a drive circuit necessary for driving the pixel portion are integrated on the same glass substrate or quartz substrate, It has been realized. At present, various products such as notebook computers and mobile phones equipped with active matrix liquid crystal display devices made of TFTs using a polycrystalline silicon film obtained by crystallizing an amorphous silicon film are on the market.
[0003]
In order to realize higher pixel and higher definition of a monolithic active matrix display, a TFT having a high operation speed, that is, a high field effect mobility is required. In order to achieve high field effect mobility, it is necessary to fabricate a TFT using a crystalline silicon film obtained by crystallizing an amorphous silicon film. For this reason, diligent research has been conducted on crystallization techniques such as a silicon film. Yes. As a crystallization technique, a method of solid-phase growth by heating an amorphous semiconductor film with a heating furnace or an RTA apparatus, a method of crystallization by heating with irradiation of laser light, and the like are known.
[0004]
In order to increase the field effect mobility of the TFT, it is only necessary to smoothly move the carrier through the channel without being scattered. However, in the TFT using a crystalline silicon film which is currently in practical use, there are many in the channel. Therefore, the field effect mobility of a TFT cannot be increased as much as a transistor using a silicon wafer.
[0005]
Therefore, in order to make the field effect mobility of the TFT close to that of a transistor of a single crystal silicon wafer, attempts have been made to increase the crystal grains of the channel semiconductor. This is because by increasing the crystal grains, the number of crystal grain boundaries of the semiconductor in the TFT channel is reduced, so that the probability that carriers are scattered at the crystal grain boundaries can be reduced.
[0006]
In addition, it is known that the ease of carrier flow in semiconductors varies depending on the crystal orientation, but it is very difficult to align the crystal orientation of the carriers flowing in the channel with conventional crystallization techniques. is there. In the conventional crystallization technique as described above, the crystal growth is performed using the crystal nuclei accidentally generated in the amorphous silicon film as a seed, so the crystal grain boundary cannot be eliminated at all, and the position of the crystal grain boundary and It is also very difficult to control the crystal orientation.
[0007]
The fact that the positions and crystal orientations of the crystal grain boundaries cannot be aligned in this way means that the crystallized silicon film has a different crystal structure at each location, and therefore TFTs are fabricated using the same silicon film. However, it may be one of the causes that the TFT characteristics vary from place to place.
[0008]
In addition to field effect mobility, TFTs are also required to have characteristics such as a small threshold voltage value and a small subthreshold value (S value) as a switching element. In order to improve these characteristics, it is known that the thickness of the semiconductor film in the channel portion should be reduced. This is because if the semiconductor film in the channel portion is thinned, the depletion layer (channel) spreads in the film thickness direction (vertical direction) is suppressed, so that the characteristics of the subthreshold region of the IV characteristics are improved. .
[0009]
In the case of a TFT using a polycrystalline silicon film, it is generally desirable to reduce the film thickness of the channel formation region to about 60 nm or less. However, in the case of crystallization by solid phase growth using a heating furnace or the like, the crystal grain size is difficult to increase as the film thickness decreases.
[0010]
Also, in the case of crystallization using a continuous wave laser beam such as a YAG laser or a pulsed laser beam such as an excimer laser, it is difficult to reduce the thickness of the amorphous silicon film as in the case of growth. This is because it becomes easy to ablate and a new problem arises that the optimum energy margin is reduced. In the case of continuous wave laser light, the thickness must be 60 nm or more, and in the case of excimer laser, the thickness must be 50 nm or more. It becomes difficult to set an optimum energy and it is difficult to crystallize with good reproducibility.
[0011]
Conventionally, a method using thermal oxidation is known to thin the semiconductor film in the channel portion of the TFT. However, in this method, only a heat-resistant limited substrate such as a quartz substrate or a silicon wafer is used. Cannot be used.
[0012]
For example, the following Patent Document 1 describes a method for crystallizing an amorphous silicon film for solving the problem that the process margin of crystallization by conventional excimer laser light is narrow.
[0013]
In Patent Document 1, two strip-shaped amorphous silicon films are formed and melted and recrystallized by an excimer laser to form two polycrystalline silicon films. An amorphous silicon film is formed thereon. In addition, it is described that a polycrystalline silicon film is formed by crystallizing an upper amorphous silicon film using a two-band polycrystalline silicon film as a seed crystal by a solid phase growth method. In addition, it is described that the upper polycrystalline silicon film can be made to have a uniform grain size and a large grain size by crystal growth using the two lower belt-like polycrystalline silicon films as seeds. ing.
[0014]
[Patent Document 1]
Japanese Patent Laid-Open No. 2001-127301 (see pages 5 to 7 of the first embodiment)
[0015]
[Problems to be solved by the invention]
As described above, conventional crystallization by laser annealing and crystallization of amorphous silicon by solid phase growth using an electric furnace are due to crystal growth from accidental crystal nuclei. The generation position and the generation density cannot be controlled, and the plane orientation of the crystalline semiconductor film is not controlled.
[0016]
For example, in the above-mentioned Patent Document 1, it is described that the crystal grains are made large in size and uniform in size, but it is not described that the plane orientation of the crystal is controlled.
[0017]
An object of the present invention is to solve the above problems, to provide a thin film transistor having high field-effect mobility and good threshold characteristics, and to produce a large number of thin film transistors so that variation in characteristics is reduced. is there.
[0018]
In addition, the present invention controls the position of the crystal grain boundary of the crystalline semiconductor film to be a channel and the crystal orientation of the crystal grain so that the direction of the crystal grain boundary is parallel to the channel length direction. The present invention provides a method that enables crystal growth so that the orientation of the axis of growth is uniform. In addition, the present invention is characterized in that a substrate having a strain point of about 600 ° C. such as a glass substrate can be used.
[0019]
[Means for Solving the Problems]
As described above, crystallization of an amorphous silicon film using a conventional electric furnace or laser light is due to crystal growth from an accidentally generated crystal nucleus, and the generation position and density of the crystal nucleus are determined. In addition, the crystal plane orientation of the crystalline semiconductor film cannot be aligned, and the position of the crystal grain boundary cannot be controlled.
In order to solve the above problems, a novel method for manufacturing a crystalline semiconductor layer used for a channel formation region of a semiconductor element such as a thin film transistor is provided.
[0020]
A semiconductor device according to the present invention includes a semiconductor in which two first crystalline semiconductor layers and a second crystalline semiconductor layer provided in contact with the two first crystalline semiconductor layers are stacked. The thin film transistor includes a thin film transistor, wherein a source region and a drain region of the thin film transistor are provided in a portion where the first crystalline semiconductor layer and the second crystalline semiconductor layer are stacked, respectively, The formation region is the second crystalline semiconductor layer, and the channel formation region of the second crystalline semiconductor layer is a ratio of {111} among {001}, {101}, and {111} crystal planes. Is the highest.
[0021]
In another semiconductor device according to the present invention, two first crystalline semiconductor layers and a second crystalline semiconductor layer provided in contact with the two first crystalline semiconductor layers are stacked. A semiconductor device having a thin film transistor provided with a formed semiconductor layer, wherein a source region and a drain region of the thin film transistor are portions in which the first crystalline semiconductor layer and the second crystalline semiconductor layer are stacked, respectively. The channel formation region is formed of the second crystalline semiconductor layer, and the channel formation region of the second crystalline semiconductor layer includes {001} {101} and {111} crystal planes among { 101} is the highest.
[0022]
The distribution of the crystal orientation of the semiconductor is determined by a backscattered electron diffraction pattern (EBSP). EBSP is a technique in which a scanning electron microscope (SEM: Scanning Electron Microscope) is provided with a dedicated detector to detect crystal orientation from backscattering of primary electrons (hereinafter, this technique is referred to as EBSP method for convenience).
[0023]
When an electron beam is incident on a sample having a crystal structure, inelastic scattering occurs also in the back, and a linear pattern (generally called Kikuchi image) peculiar to the crystal orientation by Bragg diffraction is also included in the sample. Observed. In the EBSP method, a crystal orientation of a sample is obtained by analyzing a Kikuchi image reflected on a detector screen.
[0024]
In the sample having a polycrystalline structure, each crystal grain has a different crystal orientation. By repeating the orientation analysis while moving the position where the electron beam of the sample strikes (mapping measurement), it is possible to obtain crystal orientation or orientation information about the planar sample. Although the thickness of the incident electron beam varies depending on the type of the electron gun of the scanning electron microscope, in the case of the Schottky field emission type, a very thin electron beam having a spot diameter of 10 to 20 nm is irradiated. In the mapping measurement, as the number of measurement points is larger and the measurement region is wider, more average information of crystal orientation can be obtained. Actually, 100 × 100 μm ² In this region, measurements of about 10,000 points (1 μm interval) to 40000 points (0.5 μm interval) are performed.
[0025]
When all the crystal orientations of each crystal grain are obtained by mapping measurement, the state of crystal orientation relative to the film can be statistically known. FIG. 35 shows an example of a standard triangle obtained by the EBSP method of a polycrystalline silicon film. Standard triangles are often used to display the preferred orientation of a sample with a polycrystalline structure, and collectively indicate which lattice plane a specific surface of the sample (here, the film surface) matches. Is.
[0026]
The fan-shaped frame shown in FIG. 35A is generally called a standard triangle, and includes all indexes in the cubic system. The length in FIG. 35 corresponds to the angle in the crystal orientation. For example, 45 degrees between {001} and {101}, 35.26 degrees between {101} and {111}, and 54.74 degrees between {111} and {001}. In addition, white dotted lines indicate ranges of deviation angles of 5 degrees and 10 degrees from {101}.
[0027]
FIG. 35A is a plot of all measurement points in mapping (11,655 points in this example) within a standard triangle. It can be seen that the density of points is high in the vicinity of {101}. FIG. 35 (B) shows the concentration of such points in a contour line. The numerical values in the figure indicate the magnification when assuming that each crystal grain has a completely disordered orientation, that is, when the points are uniformly distributed in the standard triangle.
[0028]
If it is found that the preferential orientation is at a specific index (here {101}), the degree of preferential orientation can be determined by quantifying the ratio of how many crystal grains are gathered in the vicinity of the index. It becomes easier to image.
[0029]
For example, in the standard triangle illustrated in FIG. 35A, the deviation angle from the {101} (allowable angle) is appropriately determined within 5 degrees and within 10 degrees (indicated by a white dotted line in the figure). The ratio of the number of points existing in the whole can be obtained by the following formula as the orientation ratio.
[0030]
{101} orientation ratio = {101} The number of measurement points where the angle formed by the lattice plane and the film surface is within an allowable value / total number of measurement points
[0031]
This ratio can also be explained as follows. In an actual crystalline silicon film in which the distribution is concentrated in the vicinity of {101} as shown in FIG. 35A, the <101> orientation of each crystal grain is a direction perpendicular to the substrate. It is considered that the crystal axes of each crystal grain are arranged with a slight fluctuation around the normal, not the normal direction. The fluctuation angle (deviation angle from the normal line) is set as an allowable value, for example, 5 degrees or 10 degrees, and the fluctuation from the normal direction of the crystal axis is smaller than the allowable value. The calculation of the orientation rate as a molecule on the right side in the above formula is what the above formula means.
[0032]
For example, the <101> orientation of a certain crystal grain is not included in the range where the allowable angle is 5 degrees, but is included in the range where the allowable angle is 10 degrees. In the data described later, the allowable value of the deviation angle is set to 5 degrees, and the crystal orientation ratio may be calculated as the ratio of crystal grains that satisfy the allowable value.
[0033]
In this specification, the S-4300SE scanning electron microscope manufactured by Hitachi Science Systems is used as the scanning electron microscope, and the “0rientation Imaging Microscope” manufactured by TSL is used as the dedicated detector. Yes.
[0034]
In the present invention, in order to crystallize a semiconductor layer that becomes a channel formation region, a first crystalline semiconductor film that serves as a seed for crystal growth is formed in a lower layer, and is adhered to the crystalline semiconductor film. Then, an amorphous semiconductor film is formed on the upper layer. Furthermore, by irradiating the upper amorphous semiconductor film with continuous wave laser light or pulsed laser light while moving relatively to the substrate, the lower amorphous semiconductor is used as a seed. Crystallize the semiconductor film. Using the obtained upper crystalline semiconductor layer as a channel of a semiconductor element such as a thin film transistor or a diode, and a region where the lower first crystalline semiconductor layer and the upper second crystalline semiconductor layer overlap, It is characterized by being used for impurity regions such as a source region and a drain region.
[0035]
In the present invention, the crystal orientation of the lower crystalline semiconductor film that becomes the seed of the crystal is aligned, and the crystal plane with the aligned crystal orientation is parallel to the carrier flow direction (channel length direction) in the upper amorphous semiconductor layer. The crystal growth (lateral growth) is performed so that the crystal orientation of the crystalline semiconductor layer is uniform in the channel length direction, and the position of the crystal grain boundary is controlled.
[0036]
For this reason, one of the methods for forming the lower first crystalline semiconductor layer according to the present invention is to form a first semiconductor film made of an amorphous semiconductor on a substrate, thereby reducing the crystallization energy of the semiconductor. A metal element is selectively added to the first semiconductor film, the first semiconductor film is crystallized by heat treatment, and the crystallized first semiconductor film is patterned into a predetermined shape, Forming a crystalline semiconductor layer. The obtained first crystalline semiconductor layer has the highest {111} orientation ratio among {001} {101} and {111} crystal planes.
[0037]
As the first amorphous semiconductor film, silicon, a compound of silicon and germanium (Si _x Ge _1-x (0 <x <1)), amorphous germanium made of germanium alone is used.
[0038]
The metal element is a metal element that reacts with silicon (Si) or germanium (Ge) to form a metal compound, and is any of Pd, Pt, Ni, Cr, Fe, Co, Ti, Au, Cu, and Rh. These elements can be used.
[0039]
Ni can be most preferably used as the metal element. Taking the case where the semiconductor is silicon as an example, nickel silicide (NiSi) formed by reaction of nickel and silicon. ₂ ) Is a fluorite-type crystal structure, NiSi ₂ This is because the lattice constant of is closest to the lattice constant of single crystal silicon with respect to other silicides.
[0040]
The metal element is added by a solution in which a metal element or a compound of a metal element is dissolved, a method of applying a paste containing a metal element or a compound of a metal element, a metal element or a metal element by a sputtering method or a CVD method. A method of forming a compound of the above on an amorphous semiconductor film, a method of accelerating the addition of metal element ions to the semiconductor film, such as plasma doping or ion implantation, or an amorphous semiconductor film by plasma containing a metal element. The method of processing is given.
[0041]
The energy required for a metal element such as nickel to react with a semiconductor to form a metal compound (silicide in the case of silicon) is lower than the energy for crystallizing a semiconductor such as amorphous silicon. Therefore, by performing crystallization by reacting an amorphous silicon film or the like with a metal element to form a compound, crystallization can be performed at a lower temperature (energy) than when natural nuclei are generated in the semiconductor film. .
[0042]
In the first crystalline semiconductor crystallization method, a crystalline semiconductor film having a high orientation ratio with respect to a predetermined crystal plane is obtained by adding a metal element partially to the first amorphous semiconductor film. In this method, an amorphous semiconductor containing silicon as a main component and containing germanium is formed as the first semiconductor film, so that the position of adding the metal element is not particularly controlled, and {001} {101} Of the {111} crystal planes, a crystalline semiconductor film having the highest {101} orientation rate can be formed.
[0043]
That is, another method for forming the first crystalline semiconductor layer as the lower layer according to the present invention is the first amorphous semiconductor film made of an amorphous semiconductor film mainly containing silicon containing germanium on a substrate. A metal element that lowers the crystallization energy of the semiconductor is added to the first amorphous semiconductor film, and the first amorphous semiconductor film is heated to be crystallized and crystallized. This includes patterning the first crystalline semiconductor film into a predetermined shape to form a first crystalline semiconductor layer made of a crystalline semiconductor.
[0044]
In the method for forming the first crystalline semiconductor layer, the metal element used, the method for adding the metal element, and the method for crystallizing the first semiconductor made of an amorphous semiconductor are the above-described {111}. The metal element is a metal element that reacts with silicon (Si) or germanium (Ge) to form a metal compound. Thus, any element of Pd, Pt, Ni, Cr, Fe, Co, Ti, Au, Cu, and Rh can be used.
[0045]
The metal element is added by a solution in which a metal element or a compound of a metal element is dissolved, a method of applying a paste containing a metal element or a compound of a metal element, a metal element or a metal element by a sputtering method or a CVD method. A method of forming a compound of the above on an amorphous semiconductor film, a method of accelerating the addition of metal element ions to the semiconductor film, such as plasma doping or ion implantation, or an amorphous semiconductor film by plasma containing a metal element. The method of processing is given.
[0046]
Heating for crystallizing the amorphous semiconductor film using the above metal element is performed by solidifying the amorphous semiconductor film, such as heat treatment in an electric furnace or heat radiation using an infrared lamp. A means capable of phase growth is selected.
[0047]
In the present invention, when the first amorphous semiconductor film is crystallized using a metal element, the metal element intentionally added from the crystallized first semiconductor film is added after crystallization. In order to remove, a gettering process may be performed.
[0048]
Examples of the gettering method include a method in which a film serving as a gettering sink is formed over a crystallized semiconductor film and heat treatment is performed so that the metal element is absorbed by the gettering sink. As a film serving as a gettering sink, an amorphous silicon film containing argon, an amorphous silicon film containing phosphorus, or the like can be used.
[0049]
So far, the method of crystallizing by adding a metal element has been described as the method of crystallizing the first semiconductor film as a seed, but a crystallizing method without adding a metal element can be used. One of the crystallization methods is to crystallize a lower layer amorphous semiconductor with continuous wave laser light, and one of them is to form a first semiconductor film made of an amorphous semiconductor on a substrate. Then, the first semiconductor film is crystallized by irradiating the first semiconductor film with the continuous wave laser light while moving the irradiation region by the continuous wave laser light relatively to the substrate. The semiconductor film is patterned into a predetermined shape to form a first crystalline semiconductor layer made of a crystalline semiconductor.
[0050]
The other is to form a first semiconductor film made of an amorphous semiconductor on a substrate, pattern the first semiconductor film made of an amorphous semiconductor into a predetermined shape, Crystallization is performed by forming a crystalline semiconductor layer and irradiating the first amorphous semiconductor layer with the continuous-wave laser light while moving an irradiation region with the continuous-wave laser light relative to the substrate. And forming a first crystalline semiconductor layer.
[0051]
In the present invention, the first crystalline semiconductor layer is patterned into a predetermined shape, but the shape is characteristically a seed crystal for crystallizing the upper second amorphous semiconductor film. At the same time, patterning is performed so as to function as a connection portion with an electrode or a wiring, such as a source region or a drain region of a thin film transistor.
[0052]
In the present invention, the second semiconductor made of an amorphous semiconductor is in contact with the first crystalline semiconductor layer formed by any of the above-described methods and in contact with the first crystalline semiconductor layer. Forming a film, patterning the second semiconductor film into a predetermined shape so as to include a region overlapping with the first crystalline semiconductor layer and a region not overlapping with the first crystalline semiconductor layer; Forming and irradiating the second amorphous semiconductor layer while moving the continuous wave laser beam relative to the substrate to crystallize the second amorphous semiconductor layer; A method for manufacturing a semiconductor device for forming a crystalline semiconductor layer, wherein the second amorphous semiconductor layer overlaps the first crystalline semiconductor layer in crystallization of the second amorphous semiconductor layer. A region that does not overlap the first crystalline semiconductor layer , And wherein the moving the irradiation area of the continuous wave laser beam.
[0053]
In the present invention, in order to crystallize the second amorphous semiconductor layer, a pulsed laser beam may be irradiated instead of the continuous wave laser beam. In this case, the laser beam moving method is different, and in the crystallization of the second amorphous semiconductor layer, a region where the second amorphous semiconductor layer overlaps the first crystalline semiconductor layer; The pulsed laser beam is moved so that both the region not overlapping with the first crystalline semiconductor layer are included in the irradiation region of the pulsed laser beam.
[0054]
As described above, the surface to be formed (substrate) is formed in the second amorphous semiconductor layer using the first crystalline semiconductor layer as a seed by irradiating continuous wave laser light or pulsed laser light while moving the irradiation region. The crystal growth proceeds in the horizontal direction with respect to the plane of the first crystal semiconductor layer, and proceeds to copy the crystal plane of the first crystalline semiconductor layer.
Therefore, by growing the crystal from the plane in which the crystal orientation of the first crystalline semiconductor layer is aligned, the region of the second crystalline semiconductor layer that does not overlap the first crystalline semiconductor layer is oriented in a fixed direction and the crystal orientation. Crystal growth can be achieved.
[0055]
Therefore, when a region of the second crystalline semiconductor layer having the above crystal structure that does not overlap with the first crystalline semiconductor layer is used as a channel formation region of the semiconductor element, the crystal growth direction of this region is the channel length direction (carrier In parallel with the direction of movement).
[0056]
In the present invention, the crystal structure of a semiconductor is not only an amorphous structure in a narrow sense but also includes an amorphous semiconductor partially containing microcrystals.
[0057]
In the present invention, the continuous wave laser beam can be selected from a laser beam emitted from a gas laser oscillator or a solid laser oscillator. For example, solid-state laser oscillation devices include YAG and YVO _Four , YLF, YAlO _Three There is a laser oscillation device using a crystal doped with Cr, Nd, Er, Ho, Ce, Co, Ti, or Tm. The wavelength of the fundamental wave emitted from this laser oscillation device varies depending on the element doped in the crystal, but is in the range of 1 μm to 2 μm.
[0058]
As the gas laser oscillation device, a gas laser oscillation device such as an argon laser or a krypton laser can be selected.
[0059]
In the present invention, the pulsed laser is an excimer laser oscillation device using a gas of a halide such as ArF, KrF, or XeCl, or YAG doped with Cr, Nd, Er, Ho, Ce, Co, Ti, or Tm. , YVO _Four , YLF, YAlO _Three A solid-state laser oscillation device using a crystal such as can be used. The laser light emitted from the excimer laser oscillation apparatus is ultraviolet light having a wavelength range of 400 nm to 200 nm. In the case of solid laser light, the wavelength of the fundamental wave excited from the crystal is about 1 to 2 μm.
[0060]
Since the energy of laser light is efficiently used for crystallization of an amorphous semiconductor film, the wavelength of continuous wave laser light that is actually irradiated to the amorphous semiconductor film to be crystallized is effective in the amorphous semiconductor film. It is preferable that the wavelength is absorbed in a visible manner, and the wavelength is in the visible to ultraviolet range. Therefore, if the fundamental wave excited by the laser oscillation apparatus is a laser having a wavelength of 1 μm to 2 μm, it is preferable to apply the second to fourth harmonics of the fundamental wave.
Typically, when crystallizing an amorphous silicon film, Nd: YVO _Four In the case of a laser oscillation device (continuous oscillation or pulse oscillation), the wavelength of the fundamental wave excited from the crystal is 1064 nm. Therefore, the second harmonic (532 nm) is preferably used as the laser beam to be irradiated.
[0061]
Note that in this specification, in the case of irradiating continuous wave laser light or pulsed laser light other than crystallization of a semiconductor, the above laser device can be used.
[0062]
Further, in the present invention, to move the irradiation area by the continuous wave laser light or pulsed laser light with respect to the substrate means that the substrate is fixed and the laser light is moved by the scanning optical system and scanned by the laser light, or It also includes scanning the laser beam by moving the substrate with a stage provided with a moving mechanism while fixing the irradiation region by the laser beam, and further moving both the irradiation region of the laser beam and the substrate.
[0063]
In the present invention, in the case where the first crystalline semiconductor layer is formed using a metal element having a function of reducing crystallization energy, the film thickness may be about 50 nm to 100 nm. This is because when the film thickness is thinner than 50 nm, the crystal growth as described above hardly proceeds. Further, if the film thickness exceeds 100 nm, it is difficult to make one crystal grain in the film thickness direction, and more metal elements are necessary for crystallization.
[0064]
In the case where the first crystalline semiconductor layer is formed using continuous wave laser light, the thickness may be 30 nm to 400 nm, more preferably 100 nm to 150 nm.
[0065]
Conventionally, when an amorphous semiconductor film is crystallized using continuous wave laser light, it is necessary to make the film thickness thicker than 60 nm because of problems such as a margin of irradiation energy. In the present invention, continuous wave laser light is used to crystallize the second amorphous semiconductor film, but the second crystalline semiconductor layer is grown using the first crystalline semiconductor layer as a seed. The nucleation position for crystal growth can be controlled. Therefore, the thickness of the second crystalline semiconductor layer can be reduced to a range of 60 nm or less and 10 to 60 nm, and a range of 10 to 40 nm is more preferable.
[0066]
Also, in the case of crystallization using pulsed laser light, it has been difficult to crystallize an amorphous semiconductor film thinner than 50 nm in the past, but in the case of the present invention, for the same reason as described above. The thickness of the second crystalline semiconductor layer can be reduced to a range of 50 nm or less and 10 to 50 nm, and 40 nm or less is more preferable.
[0067]
Note that the lower limit of the thickness of the second amorphous semiconductor layer largely depends on the film forming means, and is preferably 10 nm or more and 20 nm or more from the viewpoint of no pinholes and reproducibility.
[0068]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described with reference to FIGS.
[0069]
[Embodiment 1]
In this embodiment, an example of a method for forming a first crystalline semiconductor layer by selectively adding a metal element that promotes crystallization to the first amorphous semiconductor film will be described. In this embodiment, a method using nickel (Ni) and using a solution as a method for adding a metal element will be described.
[0070]
(See Figure 1)
A substrate 10 for forming a crystalline semiconductor layer is prepared. The substrate 10 can be appropriately selected depending on the use of a semiconductor device such as glass made of barium borosilicate glass or aluminium borosilicate glass, quartz, silicon wafer, or the like, or process conditions such as temperature. A substrate made of a plastic material having high heat resistance, such as polycarbonate, polyimide, or an acrylic material, can be used as long as it can withstand the process temperature. The shape of the substrate 10 has a flat surface, a curved surface, or both, and is appropriately selected depending on the process and the manufacturing apparatus such as a flat plate shape, a strip shape, and a long shape.
[0071]
In the case where a glass substrate containing impurities such as glass is used for the substrate 10, in order to prevent the semiconductor film from being contaminated before forming the first semiconductor film 12 made of an amorphous semiconductor, An insulating film to be the base film 11 is formed. As this insulating film, a single layer such as a silicon oxide film, a silicon nitride film, a silicon nitride oxide film, an aluminum nitride film, a diamond-like carbon film, or a multilayer film in which these are appropriately combined is formed. As a film forming method, a known method such as a sputtering method or a plasma CVD method can be employed.
[0072]
Next, the first amorphous semiconductor film 12 is formed in close contact with the base film 11. Here, an amorphous silicon film is formed. As a forming method, a known film forming method such as a sputtering method, a plasma CVD method, or a low pressure CVD method can be adopted.
[0073]
The thickness of the first amorphous semiconductor film 12 made of an amorphous semiconductor can be 50 nm to 100 nm. This is because the first amorphous semiconductor film 12 is crystallized and finally constitutes the source region and drain region of the TFT, and if it is too thin, the sheet resistance of the source and drain regions becomes high. Further, as will be described later, in order to increase the orientation ratio of {111}, if the film is thin, the margin for crystallization becomes very narrow.
[0074]
Next, a mask film 13 is formed. The mask film 13 is for selectively adding a metal element that lowers the crystallization energy of the semiconductor to the first amorphous semiconductor film 12. As the mask film 13, a film having etching selectivity with the first amorphous semiconductor film 12 is preferable for removal later, and an insulating film such as a resist, silicon oxide, or silicon nitride can be used.
[0075]
Further, the mask film 13 is provided with a groove-shaped (slit-shaped) opening 13a, and a metal element is added to the amorphous semiconductor film 12 through the opening 13a. The size of the groove of the opening 13a is not particularly limited, but the width may be 10 to 40 μm, and the length in the longitudinal direction may be arbitrarily set according to the circuit arrangement. The shape of the opening 13a is not limited to the groove shape, and can be arbitrarily determined such as a dot shape.
[0076]
(See Figure 2)
Next, in order to add the metal element, a solution containing nickel is applied to the entire surface of the substrate using a spinner to form the nickel layer 14. As the solution, a solution in which a metal salt such as nickel acetate or nickel nitrate is dissolved in water or ethanol can be used. The method of applying the solution is useful in that the concentration of the metal element to be added can be easily adjusted by adjusting the concentration of the solution.
[0077]
When the solution is applied using the spinner, the solvent is dried by the rotation of the spinner, and the nickel dissolved in the solution remains on the entire surface of the substrate to form the nickel layer 14. Therefore, the thickness of the nickel layer 14 is about a monoatomic layer and is not considered to be a complete film. However, if the nickel atoms can be brought into contact with the surface of the first amorphous semiconductor film 12, It is known that the effect can be obtained.
[0078]
However, since the amorphous silicon repels water, it cannot be applied uniformly when applying an aqueous solution. Therefore, the first amorphous film made of amorphous silicon exposed in the opening 13a of the mask film 13 is used. A silicon oxide film having a thickness of several nanometers may be formed on the surface of the semiconductor film 12 to improve the surface paintability.
If the oxide film is extremely thin, a metal element such as nickel can be selectively brought into contact with the first amorphous semiconductor film 12 in the region 12a through the oxide film.
[0079]
In consideration of throughput and process temperature, the oxide film forming method includes a method of irradiating UV light in an oxidizing atmosphere such as ozone or oxygen, and the surface of the region 12a of the first amorphous semiconductor film 12 contains ozone. A method with a low process temperature in a short time such as a method of applying an aqueous solution with a spinner is suitable.
[0080]
(See Figure 3)
In the state where the mask film 13 exists, heat treatment is performed to crystallize the first amorphous semiconductor film 12 to form the first crystalline semiconductor film 16.
A heating furnace using resistance or the like is used for the heat treatment. In the case of crystallizing an amorphous silicon film with Ni, heat treatment is performed at a temperature of 400 to 700 ° C., preferably 500 to 600 ° C. for 4 to 24 hours.
[0081]
Further, when an amorphous semiconductor containing silicon as a main component and containing germanium is crystallized, an amorphous silicon film containing about 1 to 10 atomic% of germanium is crystallized more than the case of an amorphous silicon film. It is necessary to raise the heating temperature slightly, and the temperature is 500 to 700 ° C, preferably 550 to 600 ° C.
[0082]
Alternatively, the heat treatment may be performed in an RTA heating apparatus using a high output lamp such as an arc lamp or a halogen lamp. Further, in the RTA heating apparatus, the heating area by the arc lamp or the halogen lamp is made linear, and the heating area is formed in the same direction as the laser beam from the area 12a to which nickel is added in the direction in which the crystal is to be grown. It is also possible to adopt a method in which the crystal is grown by moving it relatively.
[0083]
First, crystallization is performed by heat treatment at 400 to 500 ° C., whereby a metal element reacts with silicon to form silicide, which becomes a crystal nucleus and contributes to subsequent crystal growth. Nickel silicide (hereinafter referred to as NiSi) ₂ Will be formed). NiSi ₂ This structure is a fluorite structure, in which nickel atoms are arranged between silicon lattices of a diamond structure. NiSi ₂ When there are no nickel atoms, silicon crystals remain. From the results of numerous experiments, it has been found that nickel atoms move to the amorphous silicon side because the solid solubility in amorphous silicon is higher than that in crystalline silicon. This is probably because of this.
[0084]
Therefore, a model is created in which the crystalline silicon 16 ′ is formed as if nickel moves in the first crystalline semiconductor film (amorphous silicon film) 12 while forming the nickel silicide 14. Can do.
[0085]
(See Figure 4)
As described above, by selectively adding a metal element, the first amorphous semiconductor film 12 made of amorphous silicon is crystallized by so-called lateral growth, and the first crystalline material made of crystalline silicon is crystallized. A semiconductor film 16 is formed. After the heat treatment, the mask film 13 is removed.
[0086]
Since the first crystalline semiconductor film 16 made of crystalline silicon is crystallized by selectively adding a metal element as described above, the orientation of crystal grains can be aligned, and {001} {101} It has been experimentally found that the film has the highest {111} ratio among the {111} crystal planes. In other words, it can be said that the film has the largest proportion of crystal grains in which the crystal axis in the normal direction of the substrate surface (the surface of the first crystalline semiconductor film 16) indicates <111>. . The crystal orientation will be described later together with Embodiment 2 using measurement data.
[0087]
Further, after crystallizing the first amorphous semiconductor film 12, irradiation with continuous wave laser light, pulsed laser light, infrared light, or the like is performed in the crystal grains of the first crystalline semiconductor film 16. The remaining crystal defects can be reduced.
[0088]
(See Figure 5)
The first crystalline semiconductor film 16 is patterned into a predetermined shape by etching to form a pair of first crystalline semiconductor layers 17 that become the source region and the drain region of the TFT. However, nickel is contained in a high concentration in the region 12a serving as the base point of crystal growth and the region at the end of crystal growth. Therefore, since it is not preferable to use such a region for a semiconductor element, the first crystalline semiconductor layer 17 is patterned so as not to include these regions.
[0089]
(See Fig. 6 (a))
Next, a second amorphous semiconductor film 18 made of an amorphous semiconductor is formed in close contact with the first crystalline semiconductor layer 17. Here, an amorphous silicon film is formed. As a film forming method, a known method such as a sputtering method or a plasma CVD method can be employed.
[0090]
The thickness of the second amorphous semiconductor film 18 is 10 nm to 60 nm, preferably 20 nm to 40 nm. Since the second amorphous semiconductor film is crystallized and finally becomes a channel formation region of the thin film transistor, the thickness of the channel formation region is reduced by forming the second amorphous semiconductor film 18 thinly to 60 nm or less. Therefore, the effect of suppressing the leakage current value in the off state and the effect of increasing the on-current / off-current ratio can be expected.
[0091]
(See FIG. 6 (b) and FIG. 6 (c))
Next, the second amorphous semiconductor film (amorphous silicon) 18 is patterned by etching, leaving a region to be a TFT, and a second amorphous semiconductor layer 19 is formed. Since the two first crystalline semiconductor layers 17 are formed larger than the pattern of the second amorphous semiconductor layer 19, the first crystalline semiconductor film is used by the mask used for this etching. 17 is also patterned.
[0092]
As shown in the figure, the second amorphous semiconductor layer 19 is patterned so as to include a region overlapping the first crystalline semiconductor layer 17. A region 19a that does not overlap with the first crystalline semiconductor layer 17 is a region that becomes a channel formation region of the TFT. FIG. 6B is a top view, and FIG. 6C is a cross-sectional view taken along the line xx ′ of FIG.
[0093]
(See FIGS. 7A to 7C)
As shown in FIG. 7A, continuous wave laser light is irradiated from a region where the irradiation region 21 overlaps the first crystalline semiconductor layer 17 in a direction parallel to the channel length direction with respect to the substrate 10. Irradiation is performed while moving toward the non-overlapping region 19a.
By irradiating the entire second amorphous semiconductor layer 19 with continuous laser light while moving the irradiation region 21 relative to the substrate as described above, the entire second amorphous semiconductor layer 19 is irradiated. Crystallization forms the second crystalline semiconductor layer 22.
[0094]
Since the laser is constantly irradiated on the irradiation region 21 by the continuous wave laser beam, the second amorphous semiconductor layer 19 is melted in the irradiation region, and a molten part (liquid phase) -non-melted part (solid phase). The interface is formed. Therefore, when the irradiation region 21 is moved, it is considered that the liquid phase-solid phase interface is moved along with the movement, and the previously melted portion is cooled and solidified. Through this process, the second amorphous semiconductor layer 19 is crystallized. For this reason, the second amorphous semiconductor layer 19 grows in the moving direction of the molten portion (corresponding to the irradiation region 21), and the surface of the substrate 10 (the surface of the second amorphous semiconductor layer 19). ) In the horizontal direction can be grown (so-called lateral growth).
[0095]
By moving the irradiation region 21 once along the channel length direction, continuous oscillation laser light is continuously irradiated as shown in the figure so that the entire at least one second crystalline semiconductor layer 19 is irradiated. The beam (light beam) of the oscillation laser light is expanded in one direction so as to become a long-axis beam. In FIG. 7A, the cross-sectional shape of the beam is illustrated as a rectangular shape with four rounded corners, but it may be oblong, linear, or rectangular.
[0096]
Further, the irradiation of continuous wave laser light is not limited to the irradiation while moving only once in the moving direction indicated by the white arrow, but it can be reciprocated along the channel length direction, It includes moving a plurality of times in one direction indicated by an arrow.
[0097]
As described above, crystallization by continuous wave laser light melts the semiconductor to grow crystals, and thus the crystallinity of the obtained crystalline semiconductor depends on the crystallinity of the crystalline semiconductor as a seed.
[0098]
Therefore, since the region of the second crystalline semiconductor layer 22 (the region not overlapping with the first crystalline semiconductor layer 17) 22a grows using the first crystalline semiconductor layer 17 as a seed, the crystal structure is the first. The crystal structure of one crystalline semiconductor layer 17 is grown so as to be copied.
[0099]
Since the crystal of the first crystalline semiconductor layer 17 has the largest proportion of {111} orientation, the crystal structure in the region 22a of the second crystalline semiconductor layer 22 is also {001}, {101 }, {111} has the highest {111} orientation rate and the crystal planes are aligned to {111}.
[0100]
(See Fig. 7 (d))
FIG. 7D is a schematic perspective view of the region 22 a in the second crystalline semiconductor layer 22.
In this embodiment, even if the second amorphous semiconductor film to be crystallized is thinned to 60 nm or less, and further to 40 nm or less, the crystal grains are larger than the length in the channel length direction of the region 22a to be a channel formation region. Since the growth distance can be made sufficiently long, there is a grain boundary GB parallel to the channel length direction, which is the crystal growth direction, in the region 22a, but not in the channel width direction. .
[0101]
Crystallization with continuous wave laser light allows one crystal to grow to a distance of about 100 μm to 150 μm in the moving direction of the laser light. However, when the thickness of the semiconductor film to be crystallized decreases, the crystal It has been found that it is very difficult to increase the growth distance.
[0102]
In the case of this embodiment, even if the thickness is as thin as 60 nm or less, the region 22a is crystal-grown using the first crystalline semiconductor layer 17 as a seed, so that the nucleation position can be controlled, and an element such as a TFT can be used. In general, the size of the region 22a is about the length of the channel length × the channel width, and is at most about a dozen μm square. Therefore, in the region 22a as described above, the channel length direction is parallel to the crystal growth direction. Although the grain boundary GB exists, it is easy not to exist in the channel width direction.
[0103]
Further, since the region 22a of the second crystalline semiconductor layer 22 is composed of one crystal grain in the film thickness direction, the region 22a can reduce the crystal grain boundary, and the grain boundary GB can be reduced as described above. It can be formed only in the channel length direction parallel to the crystal growth direction.
[0104]
In order to perform such crystal growth, the energy density given to the semiconductor by continuous wave laser light is adjusted by adjusting the output of continuous wave laser light, the moving speed of the irradiated region, the area of the irradiated region and the width in the moving direction, etc. It can be realized by optimizing.
In addition, when irradiating continuous wave laser light, the substrate is heated or irradiated with microwaves, etc., to give thermal energy, electromagnetic energy, etc. to the semiconductor layer, thereby reducing the crystallization energy. You may make it make it.
[0105]
Through the above-described steps, the first and second crystalline semiconductor layers serving as the active layer of the thin film transistor are formed. Thereafter, the thin film transistor can be formed according to a known top gate thin film transistor manufacturing method.
[0106]
(See Fig. 8 (a))
For example, the gate insulating film 30 is formed on the second crystalline semiconductor layer 22, and the gate electrode 31 is formed on the gate insulating film 30.
[0107]
(See FIG. 8 (b))
Using the gate electrode 32 as a mask, the first and second crystalline semiconductor layers 17 and 22 are doped with impurities. If the thin film transistor is N-channel type, P (phosphorus) is doped, and if it is P-channel type, B (boron) is doped. As a result, the channel formation region 32, the source region 33, and the drain region 34 are formed in a self-aligned manner in the active layer formed by laminating the first and second crystalline semiconductor layers 17 and 22.
[0108]
(See Fig. 8 (c))
An interlayer insulating film 35 is formed on the gate electrode 32. In order to connect the source region 33 and the drain region 34 to electrodes or wirings, contact holes are formed in the interlayer insulating film 35, source electrodes 36 and drain electrodes 37 are formed, and the thin film transistor is completed.
[0109]
The source and drain regions 33 and 34 are provided in a portion where the first crystalline semiconductor layer 17 and the second crystalline semiconductor layer 22 are stacked. The channel formation region 32 is provided in a region 22 a where the second crystalline semiconductor layer 22 does not overlap the first crystalline semiconductor layer 17. The above-described configuration is also common when a top gate type TFT and a bottom gate type TFT such as an inverted stagger are manufactured.
[0110]
In the thin film transistor of this embodiment, the second crystalline semiconductor layer 22 constituting the channel formation region 32 is formed so that the crystal grain boundary is parallel to the channel length direction and the grain boundary that hinders carrier movement is eliminated. Therefore, the field effect mobility of the thin film transistor can be increased.
[0111]
Further, even when a large number of thin film transistors are formed over the same substrate, the second crystalline semiconductor layer serving as a channel formation region is aligned with {111}, so that variation in characteristics among elements can be suppressed.
[0112]
Even in a thin channel formation region of about 10 to 40 nm, since the crystal orientation can be aligned as described above, not only the field effect mobility is increased, but also the threshold voltage value and the subthreshold characteristics are good. It can be.
[0113]
[Embodiment 2]
In Embodiment 1, the crystal orientation of the first crystalline semiconductor film is preferentially oriented to {111} by selectively adding a metal element. In contrast, in this embodiment, a method of forming a first crystalline semiconductor film preferentially oriented in {101} by using a silicon film added with germanium as the first amorphous semiconductor film. explain.
[0114]
(See Figure 9)
First, as in Embodiment 1, the base film 11 is formed on the substrate 10, and a silicon film to which amorphous germanium is added is formed as the first amorphous semiconductor film 43 on the base film 11. As a forming method, a known film forming method such as a sputtering method, a plasma CVD method, or a low pressure CVD method can be adopted.
[0115]
When applying plasma CVD, SiH _Four And GeH _Four Or a reaction gas consisting of _Four And H ₂ Diluted with GeH _Four The reaction gas is added to the reaction chamber and decomposed by high-frequency discharge of 1 to 200 MHz to deposit an amorphous semiconductor film on the substrate. The reaction gas is SiH _Four Instead of Si ₂ H ₆ Or SiF _Four The GeH _Four Instead of GeF _Four May be adopted.
The same reaction gas can also be used when using the low pressure CVD method, and it is preferable to use a reaction gas diluted with He. Moreover, it is good to form at the temperature of 400-500 degreeC.
[0116]
In this embodiment, the first amorphous semiconductor film 42 containing germanium-containing silicon as a main component has a germanium content of 1 atomic% to 1% in order to increase the {101} orientation rate. The range is 10 atomic%, preferably 1 to 5 atomic%. In the case of the CVD method, the germanium content is, for example, SiH used as a reaction gas. _Four And GeH _Four The flow rate ratio (partial pressure) can be adjusted. In the case of using the sputtering method, the concentration of germanium contained in the target and the GeH containing germanium used in the reaction gas _Four The flow rate can be adjusted.
[0117]
(See Figure 10)
A metal element that lowers the crystallization energy of silicon is added to the entire surface of the first amorphous semiconductor film 42 to form a layer containing the metal element on the surface of the first amorphous semiconductor film 42. Here, a nickel acetate aqueous solution is applied using a spinner to form the nickel layer 43. Alternatively, before forming the first crystalline semiconductor film 42, the nickel solution 43 is applied to the surface of the base film 11 to form the nickel layer 43 as described above, and then the first amorphous semiconductor film is formed. 42 may be formed.
[0118]
(See Figure 11)
After introducing the metal element, the amorphous semiconductor film is crystallized using the metal element, whereby the first crystalline semiconductor film 45 in which {101} is preferentially oriented can be formed. Crystallization can be performed by heat treatment using a heating furnace, irradiation with intense light such as laser light, ultraviolet light, or infrared light.
[0119]
The heat treatment can be performed in the range of 500 to 700 ° C. The upper limit of the temperature is considered as one upper limit of the heat resistant temperature of the substrate to be used. In the case of a glass substrate, the temperature below the strain point is one ground for the upper limit temperature. Furthermore, as an upper limit of the temperature, it is considered that the temperature is such that no accidental natural nucleus is generated in the first amorphous semiconductor film 42, and only the reaction between the metal element and silicon described in the first embodiment is performed. Thus, the temperature is set such that crystal growth proceeds.
[0120]
The mechanism for obtaining a crystalline silicon film having a high orientation ratio of the {101} plane by adding a metal element for crystallization as described above and including germanium in the amorphous silicon film is the current stage. Although it is not clear, the following guess can be made.
[0121]
As described in Embodiment 1, when an amorphous silicon film is crystallized using nickel, nickel silicide reacts with nickel silicide (NiSi) by heat treatment at about 400 to 600 ° C. ₂ ) Is formed. This nickel silicide becomes a crystal nucleus and contributes to the subsequent crystal growth. ₂ Since the interface energy between the crystal silicon and the [111] plane is the smallest, the plane parallel to the surface of the crystalline silicon film is the [101] plane, and this lattice plane is preferentially oriented. I think that.
[0122]
However, when the crystal growth direction is parallel to the substrate surface and grows in a columnar shape, the {101} plane is not necessarily oriented because there is a degree of freedom in the rotation direction around the columnar crystal. In the experiment, as shown in the first embodiment, {111} tends to be preferentially oriented.
[0123]
In the present embodiment, in order to increase the orientation of the {101} lattice plane of the first crystalline semiconductor film, the rotation direction of the columnar crystal is restricted, and germanium is added to amorphous silicon in order to reduce the degree of freedom. By adding about 1 atomic% to 10 atomic%, the orientation ratio to {101} is set to 20% or more.
[0124]
It has been found that when amorphous silicon contains about 1 atomic% to 10 atomic% of germanium, the generation density of crystal nuclei decreases. This is because the crystal nucleus NiSi ₂ As a result of the difference in the interatomic distance between silicon and nickel and the interatomic distance between germanium and nickel, germanium becomes NiSi. ₂ It is presumed that the above-mentioned crystal growth occurs while being excluded from the above.
[0125]
Therefore, according to this assumption, germanium contained in the silicon film exists in a state of segregating outside the silicon crystal, and the germanium in such a state is in the normal direction of the substrate with respect to the silicon crystal. In order to reduce the degree of freedom in the rotation direction of the crystal axis, the plane parallel to the surface of the crystalline silicon film is the {101} plane, and this lattice plane is preferentially oriented.
[0126]
(See Figure 12)
A first crystalline semiconductor film 45 with {101} preferentially oriented is formed. The subsequent steps may be performed in the same manner as in the first embodiment. The first crystalline semiconductor film 45 is patterned into a predetermined shape to form a pair of first crystalline semiconductor layers 46. The pair of first crystalline semiconductor layers 46 constitute a source region and a drain region, respectively.
[0127]
(See Figure 13)
An amorphous silicon amorphous semiconductor film is formed in contact with the first crystalline semiconductor layer 46 and patterned into a predetermined shape in the same manner as in the first embodiment to form a second amorphous semiconductor layer 47. To do. FIG. 13A is a top view, and FIG. 13B is an xx ′ cross-sectional view of FIG.
[0128]
(See FIGS. 14A and 14B)
Similar to the first embodiment, the continuous-wave laser beam irradiation region 21 is parallel to the substrate 10 in the channel length direction, and overlaps the first crystalline semiconductor layer 46 to the non-overlapping region 47a. , The entire second amorphous semiconductor layer 47 is crystallized so as to be irradiated with laser light, and a second crystalline semiconductor layer 48 is formed.
[0129]
Irradiation of continuous wave laser light is not limited to once, but includes the case of multiple irradiation. In this case, the continuous wave laser beam may be moved so as to reciprocate along the channel length direction, or may be moved a plurality of times in one direction.
[0130]
(See FIGS. 14B and 14C)
Therefore, since the second crystalline semiconductor layer 48 is crystallized using the first crystalline semiconductor layer 46 as a seed, including the region 48a that does not overlap with the first crystalline semiconductor layer 46, the first crystal semiconductor layer 48 is crystallized. Crystal growth is performed so as to copy the crystal structure of the crystalline semiconductor layer 46, and a crystalline semiconductor having the highest ratio of {101} among crystal planes of {001} {101} and {111} can be obtained.
[0131]
(See FIG. 14 (d))
FIG. 14D is a schematic perspective enlarged view of a region 48a of the second crystalline semiconductor layer 48 (a region not overlapping with the first crystalline semiconductor layer 46) 48a. As described in the first embodiment, even when the second amorphous semiconductor layer 47 is 60 nm or less, for example, as thin as 10 to 40 nm, in the second crystalline semiconductor layer 48 crystallized by continuous wave laser light, At least in the region 48a serving as a channel formation region, there is a grain boundary GB parallel to the channel length direction, which is the crystal growth direction, but it is possible not to exist in the channel width direction.
[0132]
Through the above steps, the first and second crystalline semiconductor layers to be the active layer of the thin film transistor are formed. Thereafter, as shown in Embodiment Mode 1, a thin film transistor can be formed in accordance with a known top gate thin film transistor manufacturing method. Of course, before forming the first and second crystalline semiconductor layers, a gate electrode can be formed to manufacture a bottom-gate thin film transistor.
[0133]
In the thin film transistor using the first and second crystalline semiconductor layers of this embodiment as an active layer, the crystal grain boundary of the second crystalline semiconductor layer constituting the channel formation region has a channel length as in the first embodiment. The field effect mobility of the thin film transistor can be increased because it is formed to be parallel to the direction and eliminate the grain boundary that hinders carrier movement.
[0134]
Further, in this embodiment, since the crystal of the second crystalline semiconductor layer 48 serving as a channel formation region is aligned with {101}, even if a large number of thin film transistors are formed on the same substrate, channel formation is performed for each element. Since the crystal orientations of the regions can be aligned, variations in characteristics from element to element can be suppressed.
[0135]
In particular, by forming a thin channel formation region of about 10 to 40 nm, the threshold voltage value and the subthreshold characteristics are improved, and the field effect transfer is achieved by aligning the orientation to {101} as described above. The degree can be increased.
[0136]
In addition, the present embodiment is characterized in that the channel formation region is preferentially oriented in {101} as shown at the beginning. In general, in a P-channel TFT, holes are carriers, so it is more difficult to increase the field-effect mobility than an N-channel TFT, but the {101} crystal plane has the highest hole mobility. It is known that the effect of increasing the field effect mobility of the P-channel TFT can be expected according to this embodiment.
[0137]
[Orientation of first crystalline semiconductor film]
Here, the crystal orientation of the first crystalline semiconductor film formed by the method of Embodiments 1 and 2 will be described using the standard triangle obtained by the EBSP method described above (see FIGS. 36 and 37). Although the standard triangle has already been described with reference to FIG. 35, FIG. 35 (B) shows the distribution of orientation in contour lines, but FIG. 36 and FIG. 37 also display contour lines in the same manner as FIG. 35 (B). However, the contour lines are shown by color (shading).
[0138]
The numerical value indicating the density of the standard triangle is called “times random” and literally indicates a multiple of the case where random orientation is assumed. That is, it shows how many times the density of the inverse pole points of the actual data is based on the point density when all measurement points are evenly distributed in the standard triangle. Therefore, if it is a numerical value larger than 1, it has a preferential orientation. Moreover, the ratio of the orientation rate indicates the ratio to the total number of points.
[0139]
(Fig. 36)
The standard triangle of FIG. 36A is that of the crystalline semiconductor film of the first embodiment, and the standard triangle of FIG. 36B is that of the crystalline semiconductor film of the second embodiment.
[0140]
In the sample manufacturing method in FIG. 36A, a base film made of silicon oxide is formed on a glass substrate, and the first amorphous semiconductor film does not contain germanium (Ge) on the base film. A silicon film was formed. The amorphous silicon film is formed by a plasma CVD apparatus, and SiH is used as a reaction gas. _Four Was used. SiH _Four The flow rate of was 100 sccm. In order to selectively add the metal element, a mask film made of silicon oxide was formed, and an aqueous solution of nickel acetate having a nickel concentration of 10 ppm was selectively applied. The heating conditions for crystallization are a temperature of 570 ° C. and a heating time of 14 hours.
[0141]
From the standard triangle in FIG. 36 (a), it can be easily understood that {111} is most strongly preferentially oriented in the sample of Embodiment 1.
[0142]
In the sample manufacturing method in FIG. 36B, an amorphous silicon film containing germanium was formed as a first crystalline semiconductor film on a quartz substrate by a CVD apparatus. As reaction gas, SiH _Four And H ₂ Diluted with GeH _Four And were used. The flow rate of the reaction gas is SiH _Four Is 100 sccm, H ₂ Diluted with GeH _Four Is 10 sccm. In order to add the metal element, an aqueous solution of nickel acetate having a nickel concentration of 10 ppm was applied to the entire surface of the film. For crystallization, the mixture was heated at a temperature of 500 ° C. for 1 hour, and further heated at 580 ° C. for 4 hours.
[0143]
From the standard triangle in FIG. 36 (b), it can be easily understood that the sample of Embodiment 2 has a tendency to orient preferentially {101} most strongly. In addition, by comparing the data in FIGS. 36A and 36B, it can be understood that {101} orientation occurs preferentially in the crystalline silicon film by adding germanium. In the illustrated example, an orientation ratio as high as 60% is shown.
[0144]
Note that the sample in FIG. 36B uses quartz as the substrate, but in the case of a sample in which a glass substrate is used and a silicon oxide film is formed on the base, the nickel concentration of the aqueous solution of nickel acetate is 0.1 ppm. By doing so, the {101} orientation rate can be 60% or more.
[0145]
From experiments, it has been found that the orientation ratio of {101} varies depending on the concentration of nickel added to the amorphous silicon film. An amorphous silicon film containing germanium is formed on a glass substrate through a base film, the nickel concentration of the aqueous nickel acetate solution is changed, and the other conditions are the same, and the {101} orientation ratio (allowable angle = (10 degrees) change was examined. When the nickel concentration was 0.1 ppm, it was about 60%, when it was 1 ppm, about 50%, when it was 10 ppm, it was about 30%, and when it was 30 ppm, it was about 20%. That is, it can be seen that the smaller the amount of nickel added, the higher the {101} orientation rate.
[0146]
Furthermore, it has been found from experiments that the {101} orientation rate of the crystalline silicon film containing germanium in the example of Embodiment 2 depends on the germanium concentration.
[0147]
An amorphous silicon film containing germanium is formed on a glass substrate through a base film, and the nickel concentration of the nickel acetate aqueous solution is 10 ppm. ₂ Diluted with GeH _Four The change in the {101} orientation rate was examined by changing the flow rate of the liquid and changing the other conditions to be the same. As a result, H ₂ Diluted with GeH _Four When the flow rate is 5 sccm, 10 sccm, and 15 sccm, the respective {101} orientation ratios (allowable angle = 10 degrees) are about 20%, about 30%, and about 20%.
[0148]
The concentration of germanium in the silicon film formed under the above conditions is 1.5 atomic%, 3.5 atomic%, and 11.0 atoms when the flow rate is 5 sccm, 10 sccm, and 15 sccm, as measured by SIMS. %Met.
[0149]
Therefore, depending on the amount of nickel added and the type of substrate used, in order to make the {101} orientation 20% or more when the angle of tolerance is within 10 degrees, the concentration of germanium in the silicon film Is preferably 1 atom% or more and 10 atom% or less.
[0150]
FIG. 36C shows a standard triangle for the crystalline silicon film of Reference Example 1. The sample of Embodiment 1 shown in FIG. 36 (a) was crystallized by selectively applying a nickel acetate solution, whereas in Reference Example 1, the nickel acetate solution was converted to amorphous silicon. It is applied to the entire surface of the film and crystallized.
[0151]
Since the sample of Reference Example 1 is also a crystalline silicon film crystallized by adding nickel, it can be seen that it tends to be oriented in {111}. However, as can be seen by comparing the standard triangles in FIGS. 36A and 36C, in Reference Example 1, the orientation ratio of {111} is 14%, compared with the sample of Embodiment 1 being about 49%. Then, it is a low value. Therefore, it can be seen that the addition of the metal element and the lateral growth by selectively selecting the added portion has the effect of increasing the {111} orientation rate.
[0152]
(See Figure 37)
FIG. 37 shows a standard triangle for the crystalline silicon film of Reference Example 2, which is a polycrystalline silicon film called so-called polysilicon. This is a sample obtained by heating an amorphous silicon film on a quartz substrate at 600 ° C. for 20 hours.
[0153]
The polycrystalline silicon film of Reference Example 2 is not preferentially oriented in any of {111}, {101}, and {001}, and has no crystallinity and random orientation. You can see that
[0154]
Therefore, by comparing FIGS. 36A and 36B with FIG. 37, the crystal plane of the silicon film crystallized by adding a metal element and containing germanium in the amorphous silicon film. It can be seen that there is an effect of preferentially aligning to a specific plane orientation.
[0155]
[Embodiment 3]
In the present embodiment, the lower first crystalline semiconductor layer is formed by irradiating the continuous wave laser, and the upper second layer is formed using the first crystalline semiconductor layer as a seed by irradiating the continuous wave laser light. An example of crystallizing an amorphous semiconductor layer will be described.
[0156]
(See Figure 15)
First, as in the first embodiment, a base film 11 is formed on a substrate 10, and an amorphous silicon film 52 is formed on the base film 11 as a first amorphous semiconductor film. As a forming method, a known film forming method such as a sputtering method, a plasma CVD method, or a low pressure CVD method can be adopted.
[0157]
(See Figure 16)
Next, continuous wave laser light is irradiated to crystallize the first amorphous semiconductor film 52. Laser light is irradiated while moving the irradiation region 21 by the continuous wave laser light in the direction of the arrow relative to the substrate 10. In FIG. 16, a region 52a indicated by a one-dot chain line of the first amorphous semiconductor film 52 is an element region in which a thin film transistor is formed, and shows an outer shape of a second crystalline semiconductor layer described later.
[0158]
As described above, since the crystal grows with the movement of the irradiation region 21 of the continuous wave laser beam, crystal grains having a long grain size can be grown in the horizontal direction (lateral direction) on the plane of the substrate. When continuous wave laser light is used, the orientation is not oriented in a specific plane direction as in the first and second embodiments, but the <100> axis tends to grow in the moving direction of the irradiation region 21. I know that.
[0159]
Similarly, in the case of the present embodiment, the laser light is radiated by a continuous wave laser as shown in the drawing so that at least the entire region 52a is irradiated by moving the irradiation region 21 once in one direction. The beam (light beam) of the light 14 is expanded in one direction so as to become a long-axis beam. In FIG. 16, the shape of the beam is oblong, but it may be linear, rectangular, or rectangular with rounded corners.
[0160]
In the present invention, the irradiation of the continuous wave laser beam is not limited to the irradiation while moving only once in the direction of the arrow. It includes reciprocating along one direction indicated by an arrow, or moving a plurality of times in one direction indicated by an arrow.
[0161]
(See Figure 17)
Further, it is not necessary to crystallize the entire surface of the first amorphous semiconductor film 52, and it is sufficient that at least the region 52 a to be the first crystalline semiconductor layer can be crystallized to form the crystalline semiconductor 53.
[0162]
(See Figure 18)
After crystallization using continuous wave laser light, the region 53 crystallized by etching is patterned into a predetermined shape to form two first crystalline semiconductor layers 54 made of crystalline silicon. These first crystalline semiconductor layers 54 are seed crystals for crystallizing the channel formation region of the thin film transistor and also serve as a source region and a drain region of the thin film transistor.
[0163]
Since the crystal growth in the horizontal direction, so-called lateral growth, is performed on the surface of the substrate as described above, the crystal structure of the first crystalline semiconductor layer 54 has one crystal grain in the film thickness direction. The crystal grains are long in the moving direction of the continuous wave laser beam.
[0164]
The thickness of the first amorphous semiconductor film 52 to be crystallized is 30 nm or more. This is because the first crystalline semiconductor layer that finally becomes an element is a portion that constitutes a source region and a drain region, and in order to prevent the contact resistance with the electrode and wiring here from increasing, a certain thickness is required. Because it is necessary. More preferably, the thickness of the amorphous semiconductor film 52 is 100 nm or more. This is to widen the margin of the irradiation condition of the continuous wave laser beam when crystallizing, and also because the <100> axis is easily aligned in the scanning direction of the laser beam by increasing the thickness to some extent.
[0165]
In addition, the upper limit of the thickness of the first amorphous semiconductor film 52 is set to 400 nm or less, preferably 150 nm or less so that the entire film is melted in the irradiation region of the continuous wave laser beam.
[0166]
(See FIGS. 19A and 19B)
Next, a second amorphous semiconductor film made of an amorphous semiconductor is formed in close contact with the first crystalline semiconductor layer 54. Here, an amorphous silicon film is formed. Then, the second amorphous semiconductor film 55 is patterned into a predetermined shape to form the second amorphous semiconductor layer 55 as in the first embodiment. The region 55a of the second amorphous semiconductor layer 55 that does not overlap with the first crystalline semiconductor layer 54 is a region that becomes a channel formation region.
[0167]
Similar to the first and second embodiments, the thickness of the second amorphous semiconductor film 55 is set to a range of 10 nm to 60 nm, preferably 20 nm to 40 nm, of 60 nm or less. The second amorphous semiconductor film is a film that is crystallized and finally forms a channel formation region of the thin film transistor. By forming the second amorphous semiconductor film 55 as thin as about 10 nm to 60 nm, the thickness of the channel formation region is reduced, and the effect of suppressing the leakage current value in the off state, and the on current / off The effect of increasing the current ratio can be obtained.
[0168]
(See Figure 20)
Then, similarly to the case where the first amorphous semiconductor film 52 is crystallized, the irradiation region 21 by the continuous wave laser light is irradiated while moving relative to the substrate 10 along the channel length direction. Thus, the entire second amorphous semiconductor layer 55 is crystallized to form the second crystalline semiconductor layer 56.
[0169]
In the second crystalline semiconductor layer 56, a channel formation region of the thin film transistor is provided in a region 56 a that does not overlap with the first crystalline semiconductor layer 54. Also in this embodiment, since the second crystalline semiconductor layer 56 is formed using continuous wave laser light, the grain boundary of the region 56a exists only in the channel length direction parallel to the crystal growth direction, and the channel There can be no grain boundaries in the width direction.
[0170]
(See Figure 21)
The crystallization of the second amorphous semiconductor layer 54 will be described with reference to FIG.
As in the first and second embodiments, the continuous wave laser beam is overlapped from the region where the irradiation region 21 overlaps the first crystalline semiconductor layer 54 in the direction parallel to the channel length direction with respect to the substrate 10. Irradiation is performed while moving toward the non-existing region 55a.
[0171]
Unlike the first and second embodiments, the first crystalline semiconductor layer 54 of the present embodiment has a random plane orientation, but it is known that the <100> axis tends to appear in the crystal growth direction. Focusing on this point, in this embodiment, when the second amorphous semiconductor layer is laterally grown using continuous wave laser light, the crystallinity of the first crystalline semiconductor layer has anisotropy. By disposing the side surface 54a so as to contribute to the crystal growth of the region 56a serving as the channel formation region, the crystal axis in this region 56a is <100>, that is, the crystal plane is aligned to {100}. It is a thing. Therefore, when the first and second amorphous semiconductor films are crystallized, the moving direction of the irradiation region of the continuous wave laser light is adjusted to the channel length direction.
[0172]
As described above, in this embodiment, the orientation of the crystal plane of the region 56a of the second crystalline semiconductor layer is determined by the plane orientation of the side surface 54a of the first crystalline semiconductor layer. When the thickness of the crystalline semiconductor layer 54 is set to 100 nm or more and the second amorphous semiconductor layer is crystallized, preferential crystal growth is likely to occur from the side surface 54a of the first crystalline semiconductor layer. .
[0173]
Through the above steps, the first and second crystalline semiconductor layers 54 and 56 to be the active layer of the thin film transistor are formed. In the following, a thin film transistor may be formed as described in Embodiment 1, for example, in accordance with a known method for manufacturing a top gate thin film transistor. Of course, it goes without saying that a bottom-gate thin film transistor can be formed by forming the gate electrode first and forming the first and second crystalline semiconductor layers.
[0174]
[Embodiment 4]
In the third embodiment, the first crystalline semiconductor layer is formed by crystallizing a predetermined region of the first amorphous semiconductor film 52 made of an amorphous semiconductor and then patterning by etching.
[0175]
In contrast to this forming method, the first amorphous semiconductor film 52 is patterned in advance into a predetermined shape by etching, and then continuously oscillated laser light is irradiated while moving in a certain direction as in the third embodiment. The first crystalline semiconductor layer can be formed by crystallization.
[0176]
[Embodiment 5]
In the above embodiment, the shape of the first crystalline semiconductor layer is a cube. However, in the present invention, if the second amorphous semiconductor layer can be crystallized using the first crystalline semiconductor layer as a seed. The shape of the first crystalline semiconductor layer is not limited to a cube. In the present embodiment, a modification of the shape of the first crystalline semiconductor layer is shown.
[0177]
(See FIG. 22 (a))
First, as described in the first and second embodiments, the first crystalline semiconductor layer 61 is formed on the substrate 10 via the base film 11. Note that a region 11a indicated by a one-dot chain line of the base film 11 indicates an outline of a second crystalline semiconductor layer to be formed later. In the present embodiment as well, the first crystalline semiconductor layer 61 is widened so as to protrude from the second crystalline semiconductor layer, as in the above embodiment.
[0178]
(See FIGS. 22 (b), (c), (d))
Next, an amorphous silicon film is formed as a second amorphous semiconductor film over the entire surface of the substrate 10 in close contact with the first crystalline semiconductor layer 61. A resist mask is formed by a known method, and the second amorphous semiconductor film is etched into a predetermined shape using the mask to form the second amorphous semiconductor layer 62. One crystalline semiconductor layer 61 is also etched.
[0179]
FIG. 22C is a cross-sectional view taken along line xx ′ in FIG. 22B, and FIG. 22D is a top view of the first crystalline semiconductor layer 61 ′. Hereinafter, as described in Embodiments 1 to 3, the second amorphous semiconductor layer 62 is crystallized using continuous wave laser light to form a second crystalline semiconductor layer. A thin film transistor can be manufactured by forming a channel formation region, a source region, a drain region, and the like in the obtained semiconductor layer in which the first and second crystalline semiconductor layers are stacked.
[0180]
In general, in a semiconductor layer of a thin film transistor, a channel formation region is narrower than a source region and a drain region. Therefore, as in the present embodiment, the feature is that the width of the seed crystal face is narrowed in accordance with the channel width. By forming the first crystalline semiconductor layer 61 ′ in this way, an effect of suppressing crystal growth that does not follow the channel length direction in the channel formation region is expected, and the crystal orientation in the channel formation region is changed. Alignment can be more reproducible.
[0181]
(See Figure 23)
Next, FIG. 23 illustrates an example in which unevenness is provided on a side surface in contact with the second amorphous semiconductor layer in the first crystalline semiconductor layer. 23, the same reference numerals as those in FIG. 22 denote the same components. FIG. 23A corresponds to FIG. 22B and shows a state in which the first crystalline semiconductor layer 63 and the second crystalline semiconductor layer 64 are formed.
[0182]
FIG. 23B is a top view of the first crystalline semiconductor layer 63. As shown in the figure, sawtooth irregularities are formed on the side surface 63 a of the first crystalline semiconductor layer 63. By forming the unevenness, it can be expected that crystal growth from the side surface of the first crystalline semiconductor layer 63 will be dominant, and this is particularly effective in the case of the third and fourth embodiments.
[0183]
Note that the shape of the side surface is not limited to the shape shown in FIG. 23, and irregularities such as a triangular wave, a rectangular wave, a sine wave, and an arc can be added.
[0184]
[Embodiment 6]
In Embodiments 1 to 3 described above, an example in which continuous wave laser light is used to form the second crystalline semiconductor layer is described. However, in the present invention, pulse oscillation is used instead of continuous wave laser. Laser light can also be used. In this embodiment, a method using pulsed laser light will be described.
[0185]
(See FIG. 24 (a))
Here, the present embodiment will be described using the process described in the first embodiment as an example. Similar to the first embodiment, the steps up to FIG. 6 are performed. That is, a pair of first crystalline semiconductor layers 71 are formed on the substrate 10 through the base film 11, and are in contact with the first crystalline semiconductor layers 71 to be in contact with the second amorphous semiconductor layers 72. Form. The region 72a of the second crystalline semiconductor layer is a region that becomes a channel formation region of the thin film transistor.
[0186]
Then, by moving the irradiation region 73 of the pulsed laser beam relative to the substrate 10 in a fixed direction, the entire second amorphous semiconductor layer 72 is irradiated with the pulsed laser beam, A second crystalline semiconductor layer 74 is formed. The region 74 a of the second crystalline semiconductor layer 74 corresponds to the region 72 a of the second amorphous semiconductor layer 72.
[0187]
(Refer to FIGS. 24B and 24C)
The pulsed laser beam is irradiated while moving the irradiation region 73 of the pulsed laser beam in a direction parallel to the surface of the substrate 10 and perpendicular to the channel length direction. The irradiation region 73 includes a region that overlaps the first crystalline semiconductor layer 71 of the second amorphous semiconductor layer 72 and a region 72a that does not overlap.
[0188]
In pulsed laser light, the irradiation time is several nanoseconds to several tens of nanoseconds, which is very short compared to continuous-wave laser light. Therefore, the solid-liquid interface moves like continuous-wave laser light. This is because the irradiation cannot be performed. Therefore, in the present embodiment, the first crystalline semiconductor layer 71 that is always a seed for crystal growth is included in the irradiation region 73 that is a region melted by the pulsed laser beam.
[0189]
By irradiating the pulsed laser beam while moving as described above, it is possible to always grow a crystal only from the first crystalline semiconductor layer 71 in the irradiation region 73, and the crystal growth direction is parallel to the channel length direction. can do. That is, by controlling the nucleation position and the crystal growth direction, the second amorphous semiconductor layer 72 can be laterally grown so as to copy the crystal structure of the first crystalline semiconductor layer 71.
[0190]
(See FIGS. 24 (c) and (d))
Further, since the region 74a of the second crystalline semiconductor layer 74 grows from each of the pair of first crystalline semiconductor layers 71, a plurality of grains formed in the channel length direction parallel to the crystal growth direction. One grain boundary GB2 is formed in which the grain boundary grown by using the first crystalline semiconductor layer 71 different from the boundary GB1 and the channel width direction collide with each other. The region 74a is formed of one crystal grain in the film thickness direction.
[0191]
Crystal growth can be achieved by optimizing the energy density to be applied by adjusting the output of pulsed laser light, the moving speed of the irradiated region, the area of the irradiated region, the width in the moving direction, and the like. . In addition, when irradiating pulsed laser light, the substrate is heated or irradiated with microwaves, etc., to give thermal energy, electromagnetic energy, etc. to the semiconductor layer, thereby reducing the crystallization energy. You may make it make it.
[0192]
Through the above steps, the first and second crystalline semiconductor layers to be the active layer of the thin film transistor are formed. Thereafter, a thin film transistor can be formed in accordance with a known manufacturing method.
[0193]
A grain boundary such as a grain boundary GB2 parallel to the channel width direction can be excluded from the channel formation region by devising the circuit configuration as in the seventh embodiment described later.
[0194]
[Embodiment 7]
In the case of the sixth embodiment, because of crystallization using pulsed laser light, a grain boundary GB2 in the channel width direction is formed in the second crystalline semiconductor layer. However, by designing the element so that the grain boundary is not included in the channel formation region, the influence of the grain boundary can be eliminated.
[0195]
(See FIG. 25 (a))
For example, the first crystalline semiconductor layer constituting the source region 85 and the drain region 86 is provided asymmetrically so that the channel formation region 84 does not include the grain boundary GB2 of the second crystalline semiconductor layer. can do. In FIG. 25A, 10 is a substrate, 11 is a base film, 82 is a gate insulating film, 83 is a gate electrode, 87 is an interlayer insulating film, 88 is a source electrode, and 89 is a drain electrode.
[0196]
(See FIG. 25 (b))
In addition, a multi-channel structure in which one channel formation region of the thin film transistor is divided into two or more can be formed so as to increase the channel length and avoid the grain boundary GB2.
[0197]
In FIG. 25B, 10 is a substrate, 11 is a base film, 92 is a gate insulating film, 93a and 93b are gate electrodes, 94a and 94b are channel formation regions, and 95 is a first and second crystalline semiconductor layer. Similarly, the source region 96 is a drain region. The region 91 is an impurity region that connects the two channel formation regions 94a and 94b, and element design may be performed so that the grain boundary GB2 is included therein. Reference numeral 97 denotes an interlayer insulating film, 98 denotes a source electrode, and 99 denotes a drain electrode.
[0198]
Embodiments 1 to 7 described above can be appropriately combined. For example, the formation method of the first crystalline semiconductor layer and the second amorphous semiconductor layer shown in Embodiment 3 is to be applied to other embodiments. The thin film transistor is not limited to a top gate type, and the present invention can be applied to a bottom gate type, typically an inverted stagger type thin film transistor.
[0199]
[Embodiment 8]
The semiconductor device of the present invention is not limited to a semiconductor element such as a thin film transistor. It includes all semiconductor devices using an integrated circuit made up of elements using the first and second crystalline semiconductor layers of the present invention, such as thin film transistors. For example, an active matrix liquid crystal panel or an active matrix electroluminescence panel is a typical example of a semiconductor device using a thin film transistor.
[0200]
Further, the semiconductor device of the present invention includes an electronic device in which these active matrix display devices are mounted, and includes a mobile phone, a personal digital assistant (PDA), a notebook computer, a display for a personal computer, a television, and the like. I can give you.
[0201]
【Example】
Embodiments of the present invention will be described with reference to FIGS.
[0202]
[Example 1] (FIGS. 26 to 31)
In this embodiment, an example in which the present invention is applied to an active matrix liquid crystal panel having a pixel portion and a driving circuit on the same substrate will be described.
[0203]
(See Figure 26)
FIG. 26 is a schematic view of an active matrix liquid crystal panel. In the liquid crystal panel, the periphery of the two substrates 100 and 101 is sealed with a sealing material with the liquid crystal interposed therebetween. The substrate 100 is a substrate generally called a TFT (Thin Film Transistor) array substrate. A substrate 100 is provided with a pixel portion provided with a TFT as a switching element, a gate line driving circuit 104 and a source line driving circuit 105 which are integrated circuits composed of TFTs and the like. Further, an external input terminal 107 for attaching an FPC (Flexible Printed Circuit Board: Flexible Printed Circuit) 106, a wiring 108 for connecting the input portions of the drive circuits 104 and 105 and the external connection terminal 107, and the like are provided.
[0204]
The other substrate 101 is a substrate generally called a counter substrate. A counter electrode (not shown) is provided on the substrate 101 so as to face the pixel portion 103, and an alignment film for aligning liquid crystal is provided on the counter electrode as necessary. In the case of a color panel, a color filter is provided in a portion facing the pixel portion 103.
[0205]
(See FIGS. 27 and 28)
FIG. 27 is an equivalent circuit of a pixel. FIG. 28 is a top view of the pixel portion of the substrate 100. In each pixel, a gate line 110 to which a signal is transmitted from the gate line driver circuit 104 and a source line 111 to which a signal is transmitted from the source line driver circuit 105 are crossed. A thin film transistor 112, a liquid crystal element 113, and a capacitor 114 are provided at the intersection. The liquid crystal element 113 is a capacitor using a pixel electrode 115 connected to the pixel TFT 112, a counter electrode (not shown) provided on the counter substrate 101 as an electrode, and liquid crystal as a dielectric. The capacitor 114 is an element for supplementing the capacity of the liquid crystal element 113.
[0206]
Hereinafter, a method for manufacturing the substrate 100 will be described with reference to FIGS. Note that the drive circuits 104 and 105 are represented by a manufacturing process of a CMOS thin film transistor which is a basic circuit for convenience of explanation. 29 to 31, the upper side is a cross-sectional view of the driving circuit (CMOS TFT), the lower side is a cross-sectional view of the pixel portion, and is a cross-sectional view along the line XX ′ in FIG. 28. .
[0207]
(See FIG. 29 (a))
Corning # 1737 glass is prepared as the substrate 120. As the substrate 120, a substrate made of glass such as barium borosilicate glass or alumino borosilicate glass, or a quartz substrate may be used.
[0208]
As the base film 121, silane (SiH) is used in a plasma CVD apparatus. _Four ), Dinitrogen monoxide (N ₂ Silicon nitride oxide film (SiOx N) using O as a source gas _y ) To a thickness of 100 nm. The thickness of the base film 121 is about 20 to 200 nm.
[0209]
A film mainly containing silicon containing amorphous germanium (hereinafter referred to as SiGe) in close contact with the base film 121. _x Marked as membrane. ) In a plasma CVD apparatus. The source gas includes silane (SiH _Four ) And hydrogen gas (H ₂ ) Germane (GeH) diluted to 10% _Four ). Flow rate is SiH _Four Is 90 sccm, H ₂ Diluted with GeH _Four Is 10 sccm. High frequency power is 0.35W / cm ² Although it is (27 MHz), it is modulated to a pulse discharge with a repetition frequency of 5 kHz (duty ratio 20%) and is fed to the cathode of a parallel plate type plasma CVD apparatus. In addition, amorphous SiGe _x The thickness of the film is 55 nm.
[0210]
Amorphous SiGe _x A nickel acetate solution having a concentration of 10 ppm is applied to the entire surface of the film using a spinner, and is crystallized by heat treatment in a heating furnace. First, heat treatment is performed at 500 ° C. for 1 hour, followed by crystallization at 580 ° C. for 4 hours to crystallize, and crystalline SiGe having an orientation ratio of {101} of 20% or more _x A film is formed.
[0211]
(See FIG. 29 (b))
A resist mask is formed by photolithography, and crystalline SiGe is used with this mask. _x The film is etched to form first crystalline semiconductor layers 123 to 129 having a desired shape.
[0212]
The first crystalline semiconductor layers 123 and 124 of the CMOS TFT are layers serving as a source region and a drain region of a P-channel TFT (hereinafter referred to as a Pch TFT). The first crystalline semiconductor layers 125 and 126 are layers serving as a source region and a drain region of an N-channel TFT (hereinafter referred to as an Nch TFT).
[0213]
(See Figure 28)
In the pixel portion, the first crystalline semiconductor layers 127 and 128 are layers serving as a source region and a drain region of a pixel TFT (NchTFT). The first crystalline semiconductor layer 129 is a layer that forms the capacitor 114 and serves as a connection portion with the pixel electrode 115.
[0214]
(See FIG. 29 (c))
Next, it is in close contact with the first crystalline semiconductor layers 123 to 129, and silane (SiH) in a plasma CVD apparatus. _Four ) As a source gas to form an amorphous silicon film with a thickness of 250 nm. A resist mask is formed by photolithography, and the amorphous silicon film is etched using the mask to form second amorphous semiconductor layers 131 to 134 having desired shapes.
[0215]
(See FIG. 30 (a))
While scanning along the channel length direction, the second amorphous semiconductor layers 131 to 134 are irradiated with continuous wave laser light and crystallized to form second crystalline semiconductor layers 135 to 138.
[0216]
Crystallization with continuous wave laser light is a continuous wave laser device that uses Yd doped with Nd. _Four A solid-state laser using crystals is used. The laser beam to be irradiated is light of the second harmonic (532 nm) of the fundamental wave. The shape (cross-sectional shape) of the beam is expanded into an elliptical shape having a major axis of 200 μm and a minor axis of 20 μm by an optical system. The output of the laser light is 3 to 6 W (here 5 W), the moving speed of the substrate is 5 to 100 cm / sec (here 50 cm / sec), and the irradiation atmosphere of the laser light is the air atmosphere. In addition, the continuous wave laser beam is irradiated while fixing the laser beam and moving the substrate so that the irradiation region moves in the short axis direction of the beam. Further, the moving direction is set to the channel length direction of the CMOS TFT and the pixel TFT 112.
[0217]
By crystallization under the above conditions, in the second crystalline semiconductor layer, the crystal grain boundary in the portion where the channel formation region is provided is made parallel to the channel length direction so that the crystal grain boundary in the channel width direction cannot be formed.
[0218]
Note that before the second amorphous semiconductor layer is crystallized, boron or gallium may be doped into the silicon film in advance for the purpose of controlling the threshold voltage of the TFT. Doping can be performed while the amorphous silicon film is formed, or after the film formation, doping can be performed by an ion doping apparatus. Doped boron and gallium are activated by continuous wave laser light irradiated for crystallization of the second amorphous semiconductor layer.
[0219]
(See FIG. 30 (b))
Next, an insulating film 139 is formed in close contact with the second crystalline semiconductor layers 135 to 138. The insulating film 139 functions as a gate insulating film of the TFT and a dielectric of the capacitor. Here, as the insulating film 139, in a plasma CVD apparatus, silane (SiH _Four ), Dinitrogen monoxide (N ₂ A silicon nitride oxide film (SiOxNy) is formed to a thickness of 110 nm using O) as a source gas.
[0220]
Next, a conductive film is formed in close contact with the insulating film 139, and a resist mask is formed by photolithography. Using this mask, the gate electrode 140 of the CMOS TFT, the gate line 111 and the electrode 141 of the pixel portion are connected. Form. As shown in FIG. 28, this electrode 141 is a gate electrode of the pixel TFT and also an electrode of a capacitor provided in the next row of the pixel. Here, as the conductive film, a tungsten film (W film) is formed to a thickness of 300 nm in a sputtering apparatus. In an ICP (Inductively Coupled Plasma) etching apparatus, CF is used as an etching gas. _Four And Cl ₂ The tungsten film is etched with the mixed gas to form the gate line 111 and the electrode 141.
[0221]
(See FIG. 30 (c))
Next, doping is performed in a plasma doping apparatus to form N-type and P-type impurity regions. The first crystalline semiconductor layers 123 and 124 and the second crystalline semiconductor layer 135 of the PchTFT of the driving circuit are doped with boron as a P-type impurity, thereby exhibiting P-type conductivity. ⁺ Regions 142 and 143 are formed. In addition, the N-channel TFT of the driving circuit, the pixel TFT, and the first crystalline semiconductor layers 125 to 129 and the second crystalline semiconductor layers 136 to 138 of the capacitor are doped with phosphorus as an N-type impurity to increase the N-type conductivity. N ⁺ Regions 144-150 and N ^- Regions 151 to 156 are formed. N ^- Area is N ⁺ This is a region in which the concentration of phosphorus is lower than that in the region to increase the resistance.
[0222]
P ⁺ The regions 142 and 143 are formed in a self-aligned manner using the gate electrode 140 as a mask. N ⁺ The regions 144 to 148 are formed in a non-self-aligned manner using a resist mask, and N ⁺ The regions 149 and 150 are formed in a self-aligned manner using the electrode 141, and N ^- The regions 151 to 156 are formed in a self-aligned manner using the electrodes 140 and 141. In addition, channel formation regions 158 to 161 are defined by forming these impurity regions.
[0223]
In this step, the capacitor 114 is completed. The capacitor 114 has a configuration in which the electrode 141 and a channel induced in the channel formation region 161 by the electric field of the electrode 141 are an electrode pair and the insulating film 139 is a dielectric.
[0224]
(See Fig. 31 (a))
Next, an insulating film 163 is formed over the entire surface of the substrate. This insulating film is a first interlayer insulating film, and is a protective film for preventing the gate line 110 and the like from being oxidized during heat treatment for activating the impurity region. Here, as the insulating film 163, a silicon oxynitride film was formed to a thickness of 50 nm in a plasma CVD apparatus. In this silicon oxynitride film, the composition (concentration) of O is larger than the composition (concentration) of N.
[0225]
Next, the previously doped phosphorus and boron are activated by heat treatment at 550 ° C. in a nitrogen atmosphere in a heat treatment apparatus. Then, an insulating film 164 is formed on the entire surface of the substrate. This insulating film is a second interlayer insulating film. Here, a silicon oxynitride film is formed to a thickness of 100 nm in a plasma CVD apparatus.
[0226]
(See FIG. 31 (b))
In order to planarize the substrate surface, a planarization film 165 is formed. As the planarizing film 165, as an inorganic material, a silicon oxide film formed using TEOS (Tetraethyl Orthosilicate) as a source gas by a plasma CVD method, or SOG, PSG, or BSG formed by a coating method is used. be able to. As the organic resin material, polyimide, acrylic, BCB (benzocyclobutene) formed by a coating method can be applied. A film that can be formed by a coating method rather than a CVD method can have higher flatness. Alternatively, after the insulating film is formed, the surface of the film can be polished by CMP to further improve the flatness. Here, as the planarizing film 165, an acrylic resin is formed on the gate electrode 141 so as to have a thickness of 1 μm by a coating method. Next, contact holes are opened at predetermined positions of the insulating films 163 and 164 and the planarization film 165 (see FIG. 28).
[0227]
In order to use the pixel electrode 115 as a reflective electrode, a conductive film made of a material having excellent reflectivity such as a film containing aluminum (Al) or Ag as a main component, titanium (Ti), or a stacked film thereof is formed. . Here, an aluminum film is formed by a sputtering method. A resist mask is formed by photolithography, and this aluminum film is etched using this mask. An electrode 167 for connecting the Nch TFT and the Pch TFT, wirings 168 and 169 serving as input / output parts of the CMOS TFT, a pixel part The gate signal line 110, the pixel electrode 115, and the electrode 170 for connecting the pixel TFT 112 and the source signal line 111 are formed (see FIG. 28). Although not shown in the cross-sectional view, the electrode 141 is connected to the gate signal line 110 through a contact hole as shown in FIG. It is preferable to increase the whiteness by adding a step such as a known sandblasting method or an etching method to make the surface uneven, thereby preventing specular reflection and scattering the reflected light.
[0228]
Through the above steps, a TFT array substrate in which the pixel portion including the pixel TFT and the capacitor 114 and the drive circuits 104 and 105 including the CMOS TFT are manufactured on the same substrate is completed.
[0229]
Next, a counter substrate is prepared, and then a liquid crystal panel is completed through a known cell assembly process. In this example, TFTs and the like were manufactured based on the method described in Embodiment 2, but of course, the methods of other embodiments may be adopted.
[0230]
[Example 2] (FIGS. 32 and 33)
In this embodiment, an example will be described in which the present invention is applied to an active matrix electroluminescence (EL) panel having a pixel portion and a driver circuit on the same substrate.
[0231]
The TFT array substrate of the active matrix EL panel includes a pixel portion, a gate line driving circuit for transmitting a signal to the gate line of the pixel portion, and a source line driving circuit for transmitting a signal to the source line, as in the liquid crystal panel. An integrated circuit using TFTs is used.
[0232]
(See Figure 32)
FIG. 32 is an example of a basic equivalent circuit diagram of a pixel. At the intersection of the gate line 201 and the source line 202, a switching TFT 204, a current control TFT 205, an EL element 206, and a capacitor 207 are provided. Further, a power supply line 203 for supplying current to the EL element 206 is provided. The crystalline semiconductor layer of the present invention is applied to a driver circuit and a TFT in a pixel portion.
[0233]
The EL element 206 is a diode element that is a light emitting element, and emits light when current is supplied from the power supply line via the current control TFT 205. The switching TFT 204 is for controlling the timing when the current control TFT 205 is turned on.
[0234]
FIG. 33 is a cross-sectional view of the pixel portion. FIG. 33A is a downward emission type pixel in which light emitted from the EL element radiates from the lower side through the TFT substrate, and FIG. 33B is a diagram illustrating light from the EL element in the TFT substrate. This is an upward emitting pixel that radiates from above without passing through.
[0235]
(See Fig. 33 (a))
A switching TFT 204 made of an Nch TFT and a current control TFT 205 made of a Pch TFT are provided on a substrate 210 via a base film 211. The drain of the current control TFT 205 is connected to the anode layer 216 of the EL element 206.
[0236]
The structure of the switching TFT 204 and the current control TFT 205 and the connection structure of the gate electrodes 220 and 221 and the source wiring 202 provided on the insulating film 212 and the electrodes 222 to 224 provided on the interlayer insulators 213 and 214 are as follows. The same as in the first embodiment. Although not shown, a capacitor 207 is provided as in the first embodiment.
[0237]
The EL element 206 includes an anode layer 216, an organic compound layer 217 containing a light emitter, and a cathode layer 218, and a passivation layer 219 is formed thereon. A partition layer 215 is formed so as to cover an end portion of the anode layer 216.
[0238]
The material for forming the anode layer 216 is a material having a high work function such as indium oxide, tin oxide, or zinc oxide, and the cathode is an alkali metal or alkaline earth such as MgAg, AlMg, Ca, Mg, Li, AlLi, or AlLiAg. A material having a low work function formed of a metal, typically a magnesium compound, is used.
[0239]
The organic compound layer 217 includes a light emitting layer, a hole injection layer, an electron injection layer, a hole transport layer, an electron transport layer, and the like. Luminescence in organic compounds includes light emission (fluorescence) when returning from the singlet excited state to the ground state and light emission (phosphorescence) when returning from the triplet excited state to the ground state. Includes luminescence.
[0240]
As the passivation layer 219, a film of a material having a high barrier property against oxygen and water vapor such as silicon nitride, silicon oxynitride, and diamond-like carbon (DLC) is formed. With such a configuration, light emitted from the EL element 206 is emitted from the anode layer 216 side.
[0241]
(See FIG. 33 (b))
On the other hand, the pixel portion in FIG. 33B is the same as that in FIG. 33A, except that the current control TFT 205 is an Nch TFT and the cathode and anode of the EL element 206 are interchanged. An electrode 230 connected to the electrode 224 of the current control TFT 205 is a cathode, and 231 is an anode layer.
[0242]
As described above, an active matrix EL panel can be manufactured. Note that the circuit of the pixel portion is not limited to the circuit shown in FIG. 32, and various circuits can be designed by a driving method. In any case, the TFT of the pixel portion is formed of the crystalline semiconductor layer of the present invention. As a result, a panel with a small variation in luminance can be manufactured for each pixel.
[0243]
[Example 3] (see FIG. 34)
The liquid crystal panel which is a non-self-luminous display device described in Embodiment 1 and the EL panel which is a self-luminous display device can be mounted on various electronic devices as a display portion.
[0244]
For example, a video camera, a digital camera, a goggle type display (head mounted display), a navigation system, an audio playback device (car audio, audio component, etc.), a notebook type personal computer, a game machine, a portable information terminal (mobile computer, mobile phone, Portable game machine or electronic book), image reproducing apparatus provided with a recording medium (specifically, an apparatus equipped with a display device capable of reproducing a recording medium such as a digital versatile disc (DVD) and displaying the image) Etc. Specific examples of these electronic devices are shown in FIGS.
[0245]
(See FIG. 34 (A))
FIG. 34A shows a display device, which includes all information display devices for personal computers, for receiving TV broadcasts, for displaying advertisements, and the like.
A housing 1001, a support base 1002, a display portion 1003, a speaker portion 1004, a video input terminal 1005, and the like are provided. As the display unit 1003, the direct-view type liquid crystal panel or EL panel of the embodiment is mounted. Further, a projection display device that projects an image displayed on a liquid crystal panel or an EL panel by an optical system using the display portion 1003 as a screen can be used.
[0246]
Currently, since the luminance of the electroluminescent material is small, a liquid crystal panel can be applied to the projection type. However, if an electroluminescent material with high luminance is developed in the future, the TFT array substrate of the present invention will be used. The conventional projection type electroluminescence display device can be put into practical use.
[0247]
(Refer to FIG. 34 (B))
FIG. 34B shows a digital still camera, which includes a main body 1101, a display portion 1102, an image receiving portion 1103, operation keys 1104, an external connection port 1105, a shutter 1106, and the like. The liquid crystal panel or EL panel of the embodiment is mounted as the display unit 1102. The digital still camera includes not only a still recording / reproducing function but also a moving image recording / reproducing function.
[0248]
(Refer to FIG. 34 (C))
FIG. 34C illustrates a laptop personal computer, which includes a main body 1201, a housing 1202, a display portion 1203, a keyboard 1204, an external connection port 1205, a pointing mouse 1206, and the like. The liquid crystal panel or EL panel of the embodiment is mounted as the display unit 1203.
[0249]
(Refer to FIG. 34 (D))
FIG. 34D shows a PDA, which includes a main body 1301, a display portion 1302, a switch 1303, operation keys 1304, an infrared port 1305, and the like. The liquid crystal panel or EL panel of the embodiment is mounted as the display unit 1302.
[0250]
(Refer to FIG. 34 (E))
FIG. 34E shows a portable image reproducing device (specifically assuming a DVD reproducing device) provided with a recording medium, which includes a main body 1401, a housing 1402, a display portion 1403, a display portion 1404, a recording medium. A medium (DVD or the like) playback unit 1405, operation keys 1406, a speaker unit 1407, and the like are included. A display unit 1403 mainly displays image information recorded on a recording medium. The display unit 1404 displays mainly character / symbol information such as a title of image information recorded on a recording medium and an operation method. The liquid crystal panel and EL panel of the embodiment are mounted as the display units 1403 and 1404.
[0251]
(See FIG. 34 (F))
FIG. 34F illustrates a goggle type display including a main body 1501, a display portion 1502, and an arm portion 1503. The liquid crystal panel or EL panel of the embodiment is used for the display unit 1502. Although the illustrated display device is a glasses-type face-mount display device, it is obvious that the display device can also be applied to a head-mount display.
[0252]
In addition, the display unit 1502 has a type in which a liquid crystal panel or an EL panel having a panel size diagonal of less than 1 inch is directly viewed, or an optical system built in the main body 1501 so that an image displayed on such a fine panel can be displayed. There are two types of projection, which are projected by an optical system.
[0253]
(Refer to FIG. 34 (G))
FIG. 34G illustrates a video camera, which includes a main body 1601, a display portion 1602, a housing 1603, an external connection port 1604, a remote control receiving portion 1605, an image receiving portion 1606, a battery 1607, an audio input portion 1608, operation keys 1609, an eyepiece. Part 1610 and the like. The liquid crystal panel or EL panel of the embodiment is mounted as the display unit 1602.
[0254]
(Refer to FIG. 34 (H))
FIG. 34H illustrates a mobile phone, which includes a main body 1701, a housing 1702, a display portion 1703, an audio input portion 1704, an audio output portion 1705, operation keys 1706, an external connection port 1707, an antenna 1708, and the like. The liquid crystal panel or EL panel of the embodiment is mounted as the display unit 1703.
[0255]
As described above, the active matrix display panel including the TFT of the present invention has a very wide application range, and can be used for electronic devices in various fields. FIG. 34 is just an example. Note that the application is not limited.
[0256]
【The invention's effect】
In the present invention, a crystalline semiconductor layer serving as a channel of a semiconductor element such as a thin film transistor or a diode is grown in the horizontal direction of the substrate using the underlying crystalline semiconductor layer as a seed. The crystal grain boundaries can be controlled in parallel to the channel length direction.
Furthermore, since the crystal orientation of the lower crystalline semiconductor layer as this seed is aligned, the crystal orientation of the semiconductor crystal grains can be aligned in the channel length direction in the channel formation region.
[0257]
Accordingly, since the position of the grain boundary of the crystal grain in the channel formation region and the crystal orientation of the crystal grain can be controlled as described above, the thin film transistor with high field effect mobility can be used to vary the characteristics of each element. It is possible to manufacture an integrated circuit with a reduced amount.
[0258]
Even if the thickness of the upper amorphous semiconductor layer is reduced to 60 nm or less, and further to 40 nm or less, there is a crystalline semiconductor layer serving as a seed, so that the upper amorphous semiconductor layer is formed as described above. In addition, the crystal growth can be achieved by aligning the crystal grain boundary position and crystal orientation. Therefore, for example, when such a crystallization technique is applied to a thin film transistor manufacturing technique, a semiconductor layer serving as a channel formation region can be thin and have excellent crystallinity as described above. Current leakage in the state can be reduced, and the on-current / off-current ratio can be increased.
[0259]
The crystallization method of the present invention is a process temperature at which a glass substrate can be used. Therefore, the thickness of the channel formation region can be as thin as 60 nm or less, and further 40 nm or less, without using a thin film using thermal oxidation as in the prior art.
[0260]
Further, as described above, even if the semiconductor layer serving as the channel formation region is thinned to 60 nm or less, and further to 40 nm or less, the lower first crystalline semiconductor layer and the upper second crystalline are formed in the wiring or electrode and contact portions. By providing two semiconductor layers called semiconductor layers and adjusting the thickness of the lower crystalline semiconductor layer, an increase in contact resistance can be avoided.
[Brief description of the drawings]
FIG. 1 is a perspective view showing a method for forming a first crystalline semiconductor layer (Embodiment 1).
FIG. 2 is a view showing a continuation of FIG. 1, and is a view showing a method for forming a first crystalline semiconductor film (Embodiment 1);
3 is a continuation of FIG. 2, illustrating a method for forming a first crystalline semiconductor film (Embodiment 1). FIG.
FIG. 4 is a diagram showing a continuation of FIG. 3, and is a diagram showing a method of forming a first crystalline semiconductor film (Embodiment 1).
FIG. 5 is a continuation of FIG. 4, illustrating a method for forming a first crystalline semiconductor layer (Embodiment 1).
6 is a continuation of FIG. 5, illustrating a method of forming a second amorphous semiconductor layer (Embodiment 1). FIG.
FIG. 7 is a diagram showing a continuation of FIG. 6 and shows a method for forming a second crystalline semiconductor layer by crystallization with continuous wave laser light (Embodiment 1).
FIG. 8 is a continuation of FIG. 7 and shows a manufacturing process of a thin film transistor. (Embodiment 1)
FIG. 9 is a perspective view showing a method for forming a first crystalline semiconductor film (Embodiment 2).
FIG. 10 is a diagram showing a continuation of FIG. 9, and is a diagram showing a method of forming a first crystalline semiconductor film (Embodiment 2).
FIG. 11 is a diagram showing a continuation of FIG. 10, and is a diagram showing a method of forming a first crystalline semiconductor film (second embodiment).
FIG. 12 is a diagram showing a continuation of FIG. 11 and a method for forming a first crystalline semiconductor layer. (Embodiment 2)
FIG. 13 is a diagram showing a continuation of FIG. 12, and is a diagram showing a method of forming a second amorphous semiconductor layer (second embodiment).
FIG. 14 is a diagram showing a continuation of FIG. 13 and shows a method for forming a second crystalline semiconductor layer by crystallization with continuous wave laser light (Embodiment 2).
FIG. 15 is a perspective view showing a method for forming a first crystalline semiconductor film (Embodiment 2).
FIG. 16 is a diagram showing a continuation of FIG. 9, and is a diagram showing a method of forming a first crystalline semiconductor layer (embodiment 3).
FIG. 17 is a diagram showing a continuation of FIG. 10, and is a diagram showing a method of forming a first crystalline semiconductor layer (third embodiment).
FIG. 18 is a diagram showing a continuation of FIG. 11 and a method for forming a first crystalline semiconductor layer. (Embodiment 3)
FIG. 19 is a diagram showing a continuation of FIG. 18, and is a diagram showing a method of forming a second crystalline semiconductor layer (third embodiment).
FIG. 20 is a diagram showing a continuation of FIG. 19 and a method for forming a second crystalline semiconductor layer (third embodiment).
FIG. 21 is a view corresponding to the perspective view of FIG. 20 and showing a method of forming a second crystalline semiconductor layer by continuous wave laser light (Embodiment 3).
FIG. 22 is a diagram showing a method for forming a first crystalline semiconductor layer (Embodiment 5).
FIG. 23 is a diagram showing a method for forming a first crystalline semiconductor layer (Embodiment 5).
FIG. 24 is a diagram showing a method for forming a second crystalline semiconductor layer by crystallization with pulsed laser light. (Embodiment 6)
FIG. 25 is a cross-sectional view of a thin film transistor. (Embodiment 7)
FIG. 26 is a schematic diagram illustrating a configuration of an active matrix liquid crystal panel. (Example 1)
FIG. 27 is an equivalent circuit diagram of a pixel portion of an active matrix liquid crystal panel. (Example 1)
FIG. 28 is a top view of a pixel portion of an active matrix liquid crystal panel. (Example 1)
FIG. 29 is a cross-sectional view illustrating a method for manufacturing a TFT array substrate of an active matrix liquid crystal panel. (Example 1)
FIG. 30 is a diagram showing a continuation of FIG. 29 and a cross-sectional view showing a method for manufacturing the TFT array substrate of the active matrix liquid crystal panel. (Example 1)
FIG. 31 is a diagram illustrating the continuation of FIG. 30 and a cross-sectional view illustrating a method for manufacturing a TFT array substrate of an active matrix liquid crystal panel. (Example 1)
FIG. 32 is an equivalent circuit diagram of a pixel portion of a display device using electroluminescence. (Example 2)
FIG. 33 is a cross-sectional view of the pixel portion. (Example 2)
FIG. 34 is a diagram showing an example of an electronic apparatus to which the present invention is applied. (Example 3)
FIG. 35 illustrates a standard triangle obtained from EBSP data.
36 is a standard triangle for the first crystalline semiconductor layer of Embodiment 1, Embodiment 2, and Reference Example 1. FIG.
37 is a standard triangle for the first crystalline semiconductor layer of Reference Example 2. FIG.
[Explanation of symbols]
10 Substrate
11 Underlayer
12 First amorphous semiconductor film (amorphous silicon film)
17 First crystalline semiconductor layer (crystalline silicon layer)
22 Second crystalline semiconductor layer (crystalline silicon layer)

Claims (14)

Forming a first amorphous silicon film;
Forming a mask film having an opening on the first amorphous silicon film;
Adding a metal element that lowers the crystallization energy of the semiconductor to the surface of the first amorphous silicon film exposed in the opening;
Crystallizing the first amorphous silicon film to form a first crystalline silicon film;
Removing the mask film,
Etching the first crystalline silicon film to form a pair of first island-like crystalline silicon layers;
A pair of first regions stacked in close contact with the pair of first island-shaped crystalline silicon layers; and the pair of first island-shaped crystalline silicon layers not stacked with the pair of first island-shaped crystalline silicon layers. Forming an island-shaped amorphous silicon layer including a second region provided between the regions;
The island-shaped amorphous silicon layer is crystallized by moving an irradiation region of the continuously oscillated laser beam from one of the pair of first regions toward the other of the pair of first regions. Forming two island-like crystalline silicon layers;
A method for manufacturing a semiconductor device, wherein at least part of the second region is used as a channel formation region, and the pair of first regions is used as a source region and a drain region. A crystalline silicon germanium film is obtained by crystallizing an amorphous silicon germanium film having a germanium concentration of 1 atomic% or more and 10 atomic% or less using a metal element that lowers the crystallization energy of a semiconductor. Forming,
Etching the crystalline silicon germanium film to form a pair of island-like crystalline silicon germanium layers;
A pair of first regions stacked in close contact with the pair of island-shaped crystalline silicon germanium layers and a pair of first regions not stacked with the pair of island- shaped crystalline silicon germanium layers Forming an island-shaped amorphous silicon layer including a second region provided;
The island-shaped amorphous silicon layer is crystallized by moving the irradiation region of the continuously oscillated laser beam from one of the pair of first regions toward the other of the pair of first regions. Forming a crystalline silicon layer,
A method for manufacturing a semiconductor device, wherein at least part of the second region is used as a channel formation region, and the pair of first regions is used as a source region and a drain region. Forming an amorphous silicon germanium film having a germanium concentration in the silicon film of 1 atomic% to 10 atomic%;
Adding a metal element that lowers the crystallization energy of the semiconductor to the amorphous silicon germanium film surface,
Crystallizing the amorphous silicon germanium film to form a crystalline silicon germanium film,
Etching the crystalline silicon germanium film to form a pair of island-like crystalline silicon germanium layers;
A pair of first regions stacked in close contact with the pair of island-shaped crystalline silicon germanium layers and a pair of first regions not stacked with the pair of island- shaped crystalline silicon germanium layers Forming an island-shaped amorphous silicon layer including a second region provided;
The island-shaped amorphous silicon layer is crystallized by moving the irradiation region of the continuously oscillated laser beam from one of the pair of first regions toward the other of the pair of first regions. Forming a crystalline silicon layer,
A method for manufacturing a semiconductor device, wherein at least part of the second region is used as a channel formation region, and the pair of first regions is used as a source region and a drain region. Apply a metal element that lowers the crystallization energy of the semiconductor to the surface of the underlying film,
Forming an amorphous silicon germanium film having a germanium concentration in the silicon film of 1 atomic% or more and 10 atomic% or less on the base film;
Crystallizing the amorphous silicon germanium film to form a crystalline silicon germanium film,
Etching the crystalline silicon germanium film to form a pair of island-like crystalline silicon germanium layers;
A pair of first regions stacked in close contact with the pair of island-shaped crystalline silicon germanium layers and a pair of first regions not stacked with the pair of island- shaped crystalline silicon germanium layers Forming an island-shaped amorphous silicon layer including a second region provided;
The island-shaped amorphous silicon layer is crystallized by moving the irradiation region of the continuously oscillated laser beam from one of the pair of first regions toward the other of the pair of first regions. Forming a crystalline silicon layer,
A method for manufacturing a semiconductor device, wherein at least part of the second region is used as a channel formation region, and the pair of first regions is used as a source region and a drain region. Oite to claim 1,
Concave and convex shapes are formed on the side surfaces of the pair of first island-like crystalline silicon layers ,
The method for manufacturing a semiconductor device, wherein the uneven shape is provided so as to be in contact with the second region. Forming a first amorphous silicon film;
Forming a mask film having an opening on the first amorphous silicon film;
Adding a metal element that lowers the crystallization energy of the semiconductor to the surface of the first amorphous silicon film exposed in the opening;
Crystallizing the first amorphous silicon film to form a first crystalline silicon film;
Removing the mask film,
Etching the first crystalline silicon film to form a pair of first island-like crystalline silicon layers;
A pair of first regions stacked in close contact with the pair of first island-shaped crystalline silicon layers; and the pair of first island-shaped crystalline silicon layers not stacked with the pair of first island-shaped crystalline silicon layers. Forming an island-shaped amorphous silicon layer including a second region provided between the regions;
The island-shaped amorphous silicon layer is crystallized by moving the irradiation region of the pulsed laser light while irradiating the pair of the first region and the second region, and the second island-shaped crystalline material is crystallized. Forming a silicon layer,
A method for manufacturing a semiconductor device, wherein at least part of the second region is used as a channel formation region, and the pair of first regions is used as a source region and a drain region. A crystalline silicon germanium film is obtained by crystallizing an amorphous silicon germanium film having a germanium concentration of 1 atomic% or more and 10 atomic% or less using a metal element that lowers the crystallization energy of a semiconductor. Forming,
Etching the crystalline silicon germanium film to form a pair of island-like crystalline silicon germanium layers;
A pair of first regions stacked in close contact with the pair of island-shaped crystalline silicon germanium layers and a pair of first regions not stacked with the pair of island- shaped crystalline silicon germanium layers Forming an island-shaped amorphous silicon layer including a second region provided;
The island-shaped amorphous silicon layer is crystallized by moving the irradiation region of the pulsed laser light while irradiating the pair of the first region and the second region. Forming,
A method for manufacturing a semiconductor device, wherein at least part of the second region is used as a channel formation region, and the pair of first regions is used as a source region and a drain region. Forming an amorphous silicon germanium film having a germanium concentration in the silicon film of 1 atomic% to 10 atomic%;
Adding a metal element that lowers the crystallization energy of the semiconductor to the amorphous silicon germanium film surface,
Crystallizing the amorphous silicon germanium film to form a crystalline silicon germanium film,
Etching the crystalline silicon germanium film to form a pair of island-like crystalline silicon germanium layers;
A pair of first regions stacked in close contact with the pair of island-shaped crystalline silicon germanium layers and a pair of first regions not stacked with the pair of island- shaped crystalline silicon germanium layers Forming an island-shaped amorphous silicon layer including a second region provided;
The island-shaped amorphous silicon layer is crystallized by moving the irradiation region of the pulsed laser light while irradiating the pair of the first region and the second region. Forming,
A method for manufacturing a semiconductor device, wherein at least part of the second region is used as a channel formation region, and the pair of first regions is used as a source region and a drain region. Apply a metal element that lowers the crystallization energy of the semiconductor to the surface of the underlying film,
Forming an amorphous silicon germanium film having a germanium concentration in the silicon film of 1 atomic% or more and 10 atomic% or less on the base film;
Crystallizing the amorphous silicon germanium film to form a crystalline silicon germanium film,
Etching the crystalline silicon germanium film to form a pair of island-like crystalline silicon germanium layers;
A pair of first regions stacked in close contact with the pair of island-shaped crystalline silicon germanium layers and a pair of first regions not stacked with the pair of island- shaped crystalline silicon germanium layers Forming an island-shaped amorphous silicon layer including a second region provided;
The island-shaped amorphous silicon layer is crystallized by moving the irradiation region of the pulsed laser light while irradiating the pair of the first region and the second region. Forming,
A method for manufacturing a semiconductor device, wherein at least part of the second region is used as a channel formation region, and the pair of first regions is used as a source region and a drain region. Oite to claim 6,
Crystals grown using one of the pair of first island-like crystalline silicon layers as seeds and the other of the pair of first island-like crystalline silicon layers as seeds by irradiation with the pulsed laser light And a crystal grain boundary formed by colliding with each other is generated in the second region,
The method for manufacturing a semiconductor device, wherein the channel formation region does not include the crystal grain boundary. Oite to claim 6,
A plurality of the channel formation regions are provided,
Crystals grown using one of the pair of first island-like crystalline silicon layers as seeds and the other of the pair of first island-like crystalline silicon layers as seeds by irradiation with the pulsed laser light And a crystal grain boundary formed by colliding with each other is generated in the second region,
The method for manufacturing a semiconductor device, wherein the crystal grain boundary is disposed between adjacent channel formation regions among the plurality of channel formation regions. In any one of Claims 2 thru | or 4,
Concave and convex shapes are formed on the side surfaces of the pair of island-like crystalline silicon germanium layers,
The method for manufacturing a semiconductor device, wherein the uneven shape is provided so as to be in contact with the second region. In any one of Claims 7 to 9,
A crystal grown using one of the pair of island-like crystalline silicon germanium layers as a seed by irradiation with the pulsed laser light; and a crystal grown using the other of the pair of island-like crystalline silicon germanium layers as a seed; A grain boundary formed by bumps is generated in the second region,
The method for manufacturing a semiconductor device, wherein the channel formation region does not include the crystal grain boundary. In any one of Claims 7 to 9,
A plurality of the channel formation regions are provided,
A crystal grown using one of the pair of island-like crystalline silicon germanium layers as a seed by irradiation with the pulsed laser light; and a crystal grown using the other of the pair of island-like crystalline silicon germanium layers as a seed; A grain boundary formed by bumps is generated in the second region,
The method for manufacturing a semiconductor device, wherein the crystal grain boundary is disposed between adjacent channel formation regions among the plurality of channel formation regions.

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