JP4367207B2 - Information processing apparatus, wireless communication system, and wireless communication method - Google Patents

Description

  The present invention relates to a system for reading electronic price tags attached to tableware in restaurants, merchandise, etc. in stores, a system for reading electronic tag tags attached to articles distributed on goods distribution bases, etc. The present invention relates to an information processing apparatus, a wireless communication system, and a wireless communication method that are suitable for application to a guidance sign reading system for guiding.

  Specifically, when receiving and processing a response signal obtained by modulating a carrier signal of a predetermined frequency with predetermined data from a signal responder of a backscatter communication method, the signal processing unit includes a demodulator and receives the signal from the signal responder. The response signal is delayed by one code of data, the response signal at the current time is subtracted from the response signal at the previous time delayed here, and the response signal after this subtraction is ternary-determined. The determined response signal is converted into binary data so that the DC component based on the unmodulated carrier wave signal reflected from the surrounding object at the previous time by one code of data and the surrounding object at the current time The DC component based on the unmodulated carrier wave signal reflected from the signal can be canceled, and the same delay detection function as that of a normal multiplying type delay detector can be realized.

  In recent years, with the development of semiconductor integrated circuit technology, wireless communication technology has been increasingly applied in the information processing field such as a wireless mouse and an access point, in addition to the communication processing field such as a mobile phone. A tag reader system has been devised as an application of this type of wireless communication technology. This tag reader system wirelessly communicates predetermined data by a backscattering communication (back scattering) method, and is applied to, for example, a system that reads an electronic price tag attached to tableware in a restaurant. As the electronic price tag, a tag as an example of a reflected wave modulation device equipped with a reflector is used.

  FIG. 10 is a perspective view showing a configuration example of a tag reader system 1 according to a conventional example. In the tag reader system 1 shown in FIG. 10, a tag reader (reflected wave reader) 101 is provided with a monitor 16, a read operation button 171 and the like. When the read operation button 171 of the tag reader 101 is pressed in the tag reader system 1, a carrier wave signal (carrier) is radiated from the antenna body 13 shown in FIG. 10 is transmitted.

  When the object 90 is present in the surroundings, the carrier wave signal transmitted to the tag 10 reflects the object 90 on the path II, and the reflected carrier wave signal is a tag reader along with the response signal from the tag 10 on the path III. 101. Hereinafter, the reflected carrier signal and the response signal from the tag 10 are referred to as a response composite signal. Note that the tag 10 performs amplitude modulation, phase modulation, or the like on the carrier wave signal through the path I based on data. The tag reader 101 receives the response composite signal returned from the tag 10 by the antenna body 13 and processes the signal.

  FIG. 11 is a block diagram illustrating a configuration example of the receiving unit of the tag reader 101. FIG. 12 is a diagram illustrating an input eye pattern example and a distribution example of the multiplication result signal S11 at the time of binary determination. The receiving unit of the tag reader 101 shown in FIG. 11 includes a synchronous detector 30, a multiplying delay detector 80 and a data reading unit 50 in addition to the antenna 13. The multiplication type delay detector 80 has a 1-symbol delay device 81, a multiplier 82, and a binary decision circuit 83.

  When the reception unit of the tag reader 101 receives the response composite signal Sin from the antenna 13, the synchronous detector 30 performs synchronous detection processing on the response composite signal Sin. When the response composite signal Sin is subjected to the synchronous detection process, the baseband signal S (D) and the direct current (signal) component Sd of the data are output from the synchronous detector 30 to the multiplier 82.

  In this system 1, when an object 90 exists in the surrounding area, a carrier wave synthesis signal returned from the surrounding object 90 causes noise. When the carrier wave signal from the surrounding object 90 is synchronously detected, a large DC signal Sd (t) is generated. Further, the response signal (reflected signal) Sf (D) from the tag 10 is an AC signal having a small amplitude. When this is Sf (D) = Sa (t), 1 symbol delay time of the data in the 1 symbol delay unit 81 is τ, and the current time is t, the multiplying delay detector is based on the following multiplication formula. The detection process is performed.

Multiplication formula = {Sd (t) + Sa (t)} × {Sd (t−τ) + Sa (t−τ)}
Expanding the above multiplication formula,
Sd (t) × Sd (t−τ) + Sd (t) × Sa (t−τ) + Sa (t) × Sd (t−τ) + Sa (t) × Sa (t−τ)
It becomes. In the expanded multiplication formula, the first to third terms are unnecessary components based on the reflection of the surrounding object 90, and the fourth term is a data demodulation component of the response signal based on the modulation processing of the tag 10.

  Such a multiplier 82 is connected to a binary determination circuit 83, and receives a multiplication result signal S11 based on the above-described multiplication formula to perform binary determination. In order to determine the binary value of the data in the binary determination circuit 83, the determination level Lth is set in the multiplication result signal S11 shown in FIG. 12A. The determination level Lth is set to the point where the amplitude level crosses zero in the multiplication result signal S11.

  In the distribution plotting the amplitude of the multiplication result signal S11 at the determination time t = “7” shown in FIG. 12B, all the dots exceed the determination level Lth = “0”. As described above, the binary determination circuit 83 outputs binary data specific to the tag from the multiplication result signal S11 based on the determination level Lth. A data reading unit 50 is connected to the binary determination circuit 83 to read tag-specific data and output it to a control device (not shown). The control device displays tag-specific data on the monitor 16 shown in FIG.

  In connection with the tag reader system, Patent Document 1 describes a modulation back-scattering wireless communication system. According to this wireless communication system, an interrogator and a remote tag are provided, and an interrogation signal having a predetermined frequency is transmitted from the interrogator to the remote tag. At this time, a narrowband downlink signal is used as the interrogation signal.

  Further, the interrogator receives the response signal that has been amplitude-modulated by the remote tag and is converted into a broadband uplink signal after amplitude modulation, and the signal is processed. By using such a narrowband downlink signal and a wideband uplink signal, an MBS wireless communication system having a processing gain related to MBS (Modulation Back Scattering) background noise can be provided.

  Further, in relation to a background noise reduction method in this type of system, Patent Document 2 discloses a background noise reduction device. This background noise reduction apparatus includes a demodulator, a frame power measurement circuit, a linear prediction analysis circuit, an inverse filtering circuit, and a subtracter. The frame power measurement circuit inputs a demodulated audio signal (hereinafter referred to as a demodulated signal) from the demodulator, obtains its power level for each frame, and compares it with a predetermined threshold value.

  As a result of the comparison, if the power level is equal to or lower than the threshold value, the linear prediction analysis circuit receives the demodulated signal and performs linear prediction analysis to obtain a linear prediction coefficient. The inverse filtering circuit obtains a prediction value by performing an inverse filtering process on the demodulated signal based on the linear prediction coefficient. The subtracter is configured to subtract the predicted value from the input demodulated signal. In this way, only the background noise level can be reduced to a predetermined value or less, and the receiver can comfortably talk while using the background noise as part of the information.

Japanese Patent Laid-Open No. 11-239078 (FIG. 3 [0005] to [0016]) JP 07-193519 A (FIG. 1 [0007] to [0029])

  Incidentally, the tag reader system 1 to which the MBS wireless communication system according to the conventional example is applied has the following problems.

  i. As shown in FIG. 10, when the object 90 exists around the tag reader 101, the carrier wave signal reflected and returned from the object 90 causes noise. This is because the unnecessary components from the first term to the third term become a large level of noise in the multiplication formula described above. As a result, the component of the fourth term becomes relatively small, which causes the S / N of the response signal from the tag 10 to decrease.

  ii. Incidentally, in order to suppress a decrease in the S / N ratio of the response signal transmitted from the tag 10, a method of combining the wireless communication system described in Patent Document 1 and the background noise reduction device described in Patent Document 2 is conceivable. Since it is difficult to derive a configuration for removing the carrier wave signal reflected and returned from the object 90 only by combining the two technical ideas, the data modulation component of the original response signal transmitted from the tag 10 is obtained. There are difficulties associated with reliable demodulation.

  Therefore, the present invention solves such a conventional problem, and when predetermined data is wirelessly communicated by the backscatter communication method, the configuration of the demodulator is devised and reflected from surrounding objects. Another object of the present invention is to provide an information processing apparatus, a wireless communication system, and a wireless communication method that can demodulate highly reliable data from which the influence of interference noise caused by an unmodulated carrier signal is removed.

Problems described above, the signal response of the backscatter communication method that is attached to a predetermined identification target object, when receiving and processing a response signal a carrier signal is modulated by predetermined data of a predetermined frequency, signal response member And a signal processing unit that receives and processes the response signal scattered from the signal responder, and the signal processing unit is provided with a demodulator. The baseband signal based on 1 is delayed by one data code, the baseband signal at the previous time delayed by one data code is subtracted from the baseband signal at the current time of data, and the reference based on the signal after subtraction Two determination levels are set by generating a voltage, and the two determination levels set here are compared with the signal after subtraction to make a ternary determination, and the ternary determined signal is converted into binary data Turn into It is solved by to that information processing device.

According to the information processing apparatus of the present invention, when a response signal obtained by modulating a carrier signal having a predetermined frequency with predetermined data is received from a signal responder of the backscatter communication method and processed, Send a carrier signal to the body. The signal processing unit receives and processes the response signal scattered from the signal responder. On the premise of this, in the demodulator provided in the signal processing unit, for example, the signal delay unit delays the baseband signal based on the response signal by one data code. The subtracter subtracts the baseband signal at the previous time delayed by one data code by the signal delay device from the baseband signal at the current time. The threshold setting circuit generates a reference voltage based on the signal after being subtracted by the subtracter and sets two determination levels. The determiner compares the two determination levels set by the threshold setting circuit with the signal after subtraction, and makes a ternary determination. The code converter converts the signal that has been ternary-determined by the determiner into binary data.

  Therefore, a direct current component based on an unmodulated carrier signal reflected from a peripheral object at a time before one data code, and a direct current component based on an unmodulated carrier signal reflected from a peripheral object at the current time, Can be canceled out, so that the interference wave can be removed. Moreover, the signal after the subtraction is ternary-determined, and the ternary-determined signal is converted into binary data, so that the same delay detection function as that of a normal multiplication type delay detector can be realized. .

The wireless communication system according to the present invention, when wirelessly communicating predetermined data using a backscatter communication method, receives a carrier signal of a predetermined frequency attached to a predetermined identified object, and modulates the carrier signal with the data. A signal responding body that transmits a response signal, and an information processing device that transmits a carrier wave signal to the signal response body and receives a response signal scattered from the signal response body to perform information processing, The information processing apparatus is provided with a demodulator, and the demodulator delays the baseband signal based on the response signal by one data code, and the previous time delayed by one data code from the baseband signal at the current time. of subtracting the base-band signal, and generates a reference voltage based on a signal after the subtraction is set to two decision levels, wherein the set of two decision levels and the signal after subtraction Determining three values to compare, here is a ternary decision signals to be that converts the binary data.

According to the wireless communication system according to the present invention, when predetermined data is wirelessly communicated by the backscatter communication method, the information processing apparatus according to the present invention is applied, and the demodulator provided in the information processing apparatus has a response The baseband signal based on the signal is delayed by one data code, the baseband signal at the previous time delayed by one data code is subtracted from the baseband signal at the current time, and the reference based on the signal after the subtraction Two determination levels are set by generating a voltage, and the two determination levels set here are compared with the signal after subtraction to make a ternary determination, and the ternary determined signal is converted into binary data To be converted to.

  Therefore, a direct current component based on an unmodulated carrier signal reflected from a peripheral object at a time before one data code, and a direct current component based on an unmodulated carrier signal reflected from a peripheral object at the current time, Can be offset. Thereby, the interference wave based on the unmodulated carrier wave signal reflected from the surrounding object can be removed.

In the wireless communication method according to the present invention, a signal response body that receives a carrier wave signal of a predetermined frequency, modulates the carrier wave signal with predetermined data and transmits a response signal is attached to the identified object, and is attached to the identified object. A backscatter communication type wireless communication system that transmits a carrier wave signal to the signal responder and receives the response signal returned from the signal responder to perform signal processing is performed by receiving a baseband signal based on the response signal at the time of reception. Delayed by one data code, subtract the baseband signal at the previous time delayed by one data code from the baseband signal at the current time , generate a reference voltage based on the signal after the subtraction, and make two decisions set the level, here set to be the two determination level to determine three values by comparing the signal after the subtraction, even to the converting where ternary decision signals into binary data It is.

  According to the wireless communication method of the present invention, when predetermined data is wirelessly communicated by the backscatter communication method, direct current based on an unmodulated carrier wave signal reflected from a peripheral object at a time before one data code. It is possible to cancel the component and the DC component based on the unmodulated carrier wave signal reflected from the surrounding object at the current time. Therefore, the interference wave based on the unmodulated carrier wave signal reflected from the surrounding object can be removed.

According to the information processing apparatus of the present invention, a response signal obtained by modulating a carrier wave signal of a predetermined frequency with predetermined data from a signal responder of a backscatter communication method attached to a predetermined identified object is processed. In this case, the signal processing unit includes a demodulator, and the demodulator delays the baseband signal based on the response signal by one data code and is delayed by one data code from the baseband signal at the current time. Subtract the baseband signal of the previous time, generate a reference voltage based on the signal after the subtraction , set two determination levels, and compare the two determination levels set here with the signal after the subtraction determination 3 value each to be done here ternary decision signals to convert into binary data.

  With this configuration, a direct current component based on an unmodulated carrier signal reflected from a peripheral object at a time before one data code and a direct current based on an unmodulated carrier signal reflected from the peripheral object at the current time. Since the components can be canceled out, interference waves can be removed. Moreover, the signal after the subtraction is ternary-determined, and the ternary-determined signal is converted into binary data, so that the same delay detection function as that of a normal multiplication type delay detector can be realized. . Therefore, it is possible to demodulate highly reliable data that is not affected by the interference noise caused by the carrier wave signal reflected from the peripheral object.

According to the wireless communication system and the wireless communication method according to the present invention, the information processing apparatus according to the present invention is applied when predetermined data is wirelessly communicated by the backscatter communication method. By the demodulator, the DC component based on the unmodulated carrier signal reflected from the peripheral object at the previous time by one data code based on the response signal, and the unmodulated signal reflected from the peripheral object at the current time. The DC component based on the carrier wave signal can be canceled out.

  Therefore, the interference wave based on the unmodulated carrier wave signal reflected from the surrounding object can be removed. In addition, it is possible to process highly reliable demodulated data from which the influence of interference noise due to the unmodulated carrier wave signal reflected from the surrounding object is removed.

  Subsequently, an embodiment of an information processing apparatus, a wireless communication system, and a wireless communication method according to the present invention will be described with reference to the drawings. FIG. 1 is a conceptual diagram showing a configuration example of a tag reader system 100 as an embodiment according to the present invention.

  In this embodiment, when a response signal obtained by modulating a carrier signal having a predetermined frequency with predetermined data is received from a signal responder of a backscatter communication system and processed, a demodulator is provided in the signal processing unit. This demodulator delays the baseband signal based on the response signal received from the signal responder by one data code, and the baseband signal at the previous time delayed by one data code from the baseband signal at the current time. Is subtracted, and the signal after the subtraction is subjected to ternary determination, and the signal subjected to the ternary determination is converted into binary data.

  In this system 100, based on a DC component based on an unmodulated carrier signal reflected from a peripheral object at a time one code earlier, and an unmodulated carrier signal reflected from a peripheral object at the current time. The DC component can be canceled out, and the same delay detection function as that of a normal multiplication type delay detector can be realized.

  A tag reader system 100 shown in FIG. 1 is an example of a wireless communication system, and is a system that wirelessly communicates predetermined data using a backscattering communication method. This system 100 is a system that reads electronic price tags attached to tableware in restaurants, merchandise, etc. in stores, a system that reads electronic tag tags attached to articles distributed on an article distribution base, etc., walking of visually impaired people The present invention is suitable for application to a guidance sign reading system for guiding

  In FIG. 1, a tag reader system 100 includes a tag 10 as an example of a signal responder and a tag reader (reflective reader) 20 as an example of an information processing apparatus. The tag reader 20 includes an antenna body 13, a monitor 16, a read operation button 17, and the like in the reader body. In this example, when the read operation button 17 is pressed, a carrier wave signal (question signal) Sf having a predetermined frequency, for example, 2.45 GHz, is radiated from the antenna body 13 to the tag (reflected wave modulation device) 10. In FIG. 1, the carrier wave signal Sf is indicated by a one-dot chain line.

  The tag 10 receives the carrier signal Sf, performs a predetermined modulation process on the carrier signal Sf with specific data, and spreads the tag modulation signal (hereinafter also simply referred to as a response signal Sf (D)) after the modulation process ( Send). In FIG. 1, the response signal Sf (D) is indicated by a wavy line. What is actually received by the antenna 13 is combined with the carrier signal Sf ′ reflected from the surrounding object in addition to the response signal Sf (D). The tag 10 is used by being attached to a predetermined identified object 9. The tag 10 is used as an electronic price tag or an electronic tag, and is attached to an identified object 9 such as tableware in a restaurant or a product in a store. The tag 10 includes an IC chip 10 ′ and a loop antenna body 1. The IC chip 10 ′ and the antenna body 1 are integrally formed (modulated) into a flat plate shape using a resin or the like, and attached to each tableware or product.

  FIG. 2 is a block diagram illustrating an example of an internal configuration at the time of transmission / reception in the tag reader system 100. It should be noted that the antenna body 1 of the tag 10 and the antenna body 13 of the tag reader 20 shown in FIG. 1 are used for the transmission and reception antennas 1A, 1B and 13A, in order to clearly explain the principle of the tag reader. 13B is expanded and described in two. In the tag reader system 100 shown in FIG. 2, the tag 10 receives a carrier signal Sf having a predetermined frequency, modulates the carrier signal Sf with specific data (DATA), for example, and responds after amplitude modulation. A signal Sf (D) is transmitted. In this example, a BPSK (Binary Phase Shift Keying) modulation unit may be provided instead of the amplitude modulation unit 2.

  In this example, the tag 10 includes a reception antenna body 1A, a transmission antenna body 1B, an amplitude modulation section 2, a memory section 3, a clock oscillator 4, and a power supply section 5. The amplitude modulation unit 2, the memory unit 3, the clock oscillator 4, and the power supply unit 5 are integrated into a semiconductor integrated circuit to form an IC chip 10 '. The antenna body 1A receives a carrier wave signal Sf that is an interrogation signal in the tag reader system 100. As the antenna bodies 1A and 1B, loop antennas in which a conductor is wound in a coil shape are used. A power supply unit 5 (also simply referred to as a power supply unit) is connected to the antenna bodies 1A and 1B, and induced power based on the carrier wave signal Sf received by the antenna body 1A is transmitted to the amplitude modulation unit 2, the memory unit 3, and the clock oscillator 4. Operates to supply.

  In the memory unit 3, for example, the price of the dish placed on the tableware and the data (code data etc .; DATA) specific to the identified object added to the clothing, home appliances, etc. are recorded, and this data is stored as a clock signal ( CLK), and the data is output to the amplitude modulation section 2. As the memory unit 3, a read only memory (ROM) or an electrically programmable read only memory (EEPROM) is used. A clock oscillator 4 is connected to the memory unit 3 and operates to oscillate a clock signal having a predetermined frequency and output it to the memory unit 3. The amplitude modulation unit 2 amplitude-modulates the carrier signal Sf based on the data read from the memory unit 3. The carrier signal Sf amplitude-modulated with the data becomes the response signal Sf (D). An antenna body 1B is connected to the amplitude modulator 2, and the response signal Sf (D) after amplitude modulation is scattered (transmitted).

  In addition to the tag 10 described above, the tag reader system 100 includes a tag reader 20 with a wireless transmission / reception function, which is an example of an information processing apparatus. The tag reader 20 transmits the carrier signal Sf to the tag 10 of the backscatter communication system, and receives the response signal Sf (D) scattered from the tag 10 to perform signal processing. The tag reader 20 includes an oscillator 11, a transmission unit 12, a transmission antenna body 13A, a reception antenna body 13B, a reception unit 14, a control device 15, an operation unit 16, a monitor 17, and a power supply unit 18. Yes.

  The oscillator 11 generates a carrier signal Sf (= cosωt) of 2.45 GHz that is an example of a predetermined frequency. The transmitter 11 is connected to the oscillator 11, amplifies the carrier signal Sf based on the output permission signal S1 from the control device 15, and outputs the amplified carrier signal Sf to the transmitting antenna body 13A. For example, the output permission signal S1 is permitted to be transmitted at a high level and is not permitted to be transmitted at a low level. The transmitting antenna body 13A radiates the amplified carrier wave signal Sf. Thereby, the carrier wave signal Sf can be transmitted from the transmission unit 12 to the tag 10.

  The receiving unit 14 constitutes a signal processing unit, which receives the response composite signal Sin at the time of reception and performs data demodulation processing. The response composite signal Sin at the time of reception includes an unmodulated carrier wave signal (2.45 GHz carrier) Sf ′ reflected from surrounding objects and a response signal Sf (D) from the tag 10. .

  The receiving unit 14 includes a synchronous detector 30, a subtractive delay detector 40, and a data reading unit 50. The synchronous detector 30 receives the carrier signal Sf ′ and the response signal Sf (D) and executes synchronous detection processing. The carrier signal Sf ′ is converted into the DC signal Sd, and the response signal Sf (D) is converted into data ( DATA) baseband signal S (D). The synchronous detector 30 is connected to a subtractive delay detector 40 as an example of a demodulator, and delays the baseband signal S (D) based on the response signal Sf (D) by one data code, The baseband signal S (D) at the current time is subtracted from the baseband signal S (D) at the previous time delayed by the time, and the baseband signal S (D) subtracted here is ternary determined, The baseband signal S (D) that has been ternary-determined in (2) is converted into binary data.

  A data reading unit 50 is connected to the subtraction type delay detector 40. The data reading unit 50 receives binary data output from the subtractive delay detector 40 and reads data specific to the tag. In this example, the control unit 15 is connected to the data reading unit 50, and the monitor 16 and the operation unit 17 are connected to the control unit 15. A CPU is used for the control device 15. The monitor 16 displays the price, name, etc. based on the unique data of the identified object 9 read from the tag 10. The price, name, and the like are displayed based on the display data D2 after the control device 15 that has input the unique data of the identified object 9 performs data conversion.

  The operation unit 17 is operated to instruct the control device 15 to read data when reading unique data such as price and name from the identified object 9. Operation data D3 indicating a reading instruction is output from the operation unit 17 to the control device 15. The control device 15 controls the transmission unit 12 based on the operation data D3. For example, the control device 15 outputs the output permission signal S1 to the transmission unit 12, and controls the output of the transmission unit 12 so as to transmit the carrier signal Sf based on the output permission signal S1.

  The power supply unit 5 supplies power to the oscillator 11, the transmission unit 12, the control device 15, the monitor 16, the operation unit 17, the synchronous detector 30, the subtractive delay detector 40, and the data reading unit 50 described above. The In FIG. 2, description of power supply wiring is omitted.

  FIG. 3 is a block diagram illustrating a configuration example of the subtractive delay detector 40. The subtractive delay detector 40 shown in FIG. 3 includes a one-symbol delay device 41, a subtractor 42, a ternary decision circuit 43, a threshold setting circuit 44, a code converter 45, an input terminal 46, and an output terminal 47.

  In this example, the subtractive delay detector 40 constitutes a differential detector, and the previous baseband signal S (D) delayed by the data 1 symbol time τ from the baseband signal S (D) at the current time. It is made to subtract. The subtractive delay detector 40 can eliminate the DC signal Sd, which is the surrounding reflected wave component, and can also eliminate the interference wave simultaneously with the detection.

  The input terminal 46 of the subtractive delay detector 40 shown in FIG. 3 is connected to the synchronous detector 30 described above. The input terminal 46 is connected to a 1-symbol delay device 41 as an example of a signal delay device so as to delay the baseband signal S (D) after synchronous detection of the response signal Sf (D) by one data code. To be made. As the 1-symbol delay unit 41, a register or the like in which D-type flip-flop circuits are connected in cascade is used.

  A subtracter 42 is connected to the 1-symbol delay unit 41 and the input terminal 46. The subtractor 42 supplies the baseband signal S (D) at the current time from the input terminal 46, and the baseband signal S (D) at the previous time delayed from the 1-symbol delay device 41 by one data code. Then, the baseband signal S (D) at the previous time is subtracted from the baseband signal S (D) at the current time. By this subtraction processing, the DC signal (DC component) Sd is removed (high-pass filter processing), and only the change component (AC component; Sa) of the data signal remains. For example, taking the case where the data is a BPSK modulated signal as an example, Table 1, that is,

It becomes.

  That is, when the current time data is “1” and the data one symbol before is “1”, the output of the subtractor 42 is “0”. When the current time data is “1” and the data one symbol before is “−1”, the output of the subtractor 42 is “2”. When the current time data is “−1” and the data one symbol before is “1”, the output of the subtracter 42 is “−2”. When the current time data is “−1” and the data one symbol before is also “−1”, the output of the subtractor 42 is “0”. Thus, the data baseband signal S (D) becomes the differential demodulated signal SD from which the DC component Sd is removed.

  In addition, a ternary determination circuit 43 as an example of a determiner is connected to the subtractor 42, and the subtracted differential demodulated signal SD output from the subtractor 42 is “based on two determination levels Lth 1 and Lth 2. -2 "," 0 ", and" 2 "are determined. The determination levels Lth1 and Lth2 are supplied from the threshold setting circuit 44 in the form of a reference voltage.

  In addition to the ternary determination circuit 43, a threshold setting circuit 44 is connected to the subtractor 42. The threshold setting circuit 44 sets two determination levels Lth1 and Lth2 based on the subtracter output, that is, the differential demodulated signal SD. In this example, since the differential demodulated signal SD has three values “0”, “−2”, and “2” as shown in Table 1, the determination level Lth1 is the differential demodulated signal SD. It is set to “1” which is the middle point between “2” and “0”. Further, the determination level Lth2 is set to “−1”, which is the midpoint between “−2” and “0” of the differential demodulated signal SD.

  The ternary data “−2”, “0”, and “2” subjected to the ternary determination by the ternary determination circuit 43 are output to the code converter 45. A code converter 45 is connected to the ternary determination circuit 43, and the differential demodulated signal SD determined by the ternary determination circuit 43 is converted into binary data “1” and “0”. The

FIG. 4 is a circuit diagram illustrating an internal configuration example of the ternary determination circuit 43, the threshold setting circuit 44, and the code conversion circuit 45 in the subtraction type delay detector 40.
In the subtractive delay detector 40 shown in FIG. 4, the ternary determination circuit 43 has two comparators 31 and 32. Each comparator 31, 32 has a + terminal and a-terminal. The + terminals of each of the comparators 31 and 32 are connected to the output terminal of the subtractor 42 and supplied with a subtraction output signal S1. The − terminals of each of the comparators 31 and 32 are connected to the output terminal of the threshold setting circuit 44. The reference voltage Vref1 is supplied to the negative terminal of the comparator 31, and the reference voltage Vref2 is supplied to the negative terminal of the comparator 32.

  The reference voltage Vref1 is set to the first determination level Lth1. In this example, the determination level Lth1 is set to “1” which is the midpoint between “2” and “0” of the differential demodulated signal SD. The reference voltage Vref2 is set to a second determination level Lth2. The determination level Lth2 is set to “−1” which is the midpoint between “−2” and “0” of the differential demodulated signal SD. When the ternary determination circuit 43 is configured in this way, the differential demodulated signal SD output from the subtracter 42 is converted into three values “−2”, “0”, and “2” based on the two determination levels Lth1 and Lth2. Can be determined. The ternary data “−1”, “0”, “1” that has been ternary determined by the ternary determination circuit 43 is output to the code converter 45.

  The above threshold setting circuit 44 has two diodes 48 and 49, two resistors R1 and R2, and two capacitances C1 and C2. The anode of the diode 48 and the cathode of the diode 49 are connected to the output of the subtractor 42 and supplied with the differential demodulated signal SD. An anard of the diode 48 is connected to one end of the resistor R1. The other end of the resistor R1 is connected to one end of the capacitance C1, and the other end of the capacitance C1 is grounded. The reference voltage Vref1 is an accumulated voltage of the capacitance C1, and when the diode 48 is turned on, a charging current limited by the resistor R1 flows through the capacitance C1. The reference voltage Vref1 is used for setting the determination level Lth1.

  The cathode of the diode 49 is connected to one end of the resistor R2. The other end of the resistor R2 is connected to one end of the capacitance C2, and the other end of the capacitance C2 is grounded. The reference voltage Vref2 is an accumulated voltage of the capacitance C2, and when the diode 49 is turned on, a charging current limited by the resistor R2 flows through the capacitance C2. The reference voltage Vref2 is used for setting the determination level Lth2. If the threshold setting circuit 44 is configured in this manner, two reference voltages Vref1 and Vref2 can be generated based on the differential demodulated signal SD, and two determination levels Lth1 and Lth2 can be set.

  The sign conversion circuit 45 includes two inverters 51 and 52, two-input logical product (AND) circuits 53 and 54, one two-input logical sum circuit (OR) circuit 55, and a two-input exclusive logical sum circuit (EXOR) circuit. 56 and a memory 57. The inverter 51 has its input terminal connected to the comparator 31 and its output terminal connected to one input terminal of the two-input AND circuits 53 and 54, and an inverted comparison obtained by inverting the comparison result signal S2 output from the comparator 31. The result signal S2 bar (the upper line is omitted) is supplied.

  The inverter 52 has an input terminal connected to the comparator 32 and an output terminal connected to the other input terminal of the two-input AND circuits 53 and 54, and is an inverted version of the comparison result signal S3 output from the comparator 32. The comparison result signal S3 bar (the upper line is omitted) is supplied. The two-input AND circuit 53 calculates a logical product of the two inverted comparison result signals S2 and S3 bars output from the two inverters 51 and 52, and outputs a two-input AND signal S4. The two-input AND circuit 54 is connected to the two comparators 31 and 32, calculates the logical product of the two non-inverted comparison result signals S2 and S3 output from the comparators 31 and 32, and outputs the two-input AND signal S5. To do.

  The outputs of the two-input AND circuits 53 and 54 are connected to the two-input OR circuit 55, and the two-input AND signals S4 and S5 output from the two-input AND circuits 53 and 54 are calculated to obtain a two-input. An OR signal S6 is output. A two-input exclusive OR circuit (EXOR) circuit 56 is connected to the two-input OR circuit 55. The two-input OR signal S6 is input to one input terminal of the two-input EXOR circuit 56. A memory 57 is connected to the output of the two-input EXOR circuit 56 so as to hold one symbol of data (DATA) output from the EXOR circuit 56. The output of the memory 57 is input to the other input terminal of the two-input EXOR circuit 56. When the code converter 45 is configured in this way, a differential demodulated signal (hereinafter also referred to as comparison result signals S2 and S3) SD that has been subjected to ternary determination by the ternary determination circuit 43 is converted into binary data (DATA = "1"). , “0”).

  FIGS. 5A and 5B are diagrams showing an input eye pattern example and a distribution example (determination level Lth1) of the differential demodulated signal SD at the time of ternary determination. In FIG. 5A, the vertical axis represents the amplitude (level) of the differential demodulated signal SD after synchronous detection. The horizontal axis represents time (time) t for level determination. In the figure, the horizontal thick line indicates the first determination level Lth1, and the vertical thin line is a scroll bar for viewing the amplitude distribution of the differential demodulated signal SD, and the determination time, for example, The case of determination time t = “7” is shown. The determination level Lth1 is set to “1” which is the midpoint between the amplitude levels “2” and “0”.

  In FIG. 5B, both the vertical axis and the horizontal axis represent the amplitude (level) of the differential demodulated signal SD. The dots in the figure indicate the distribution in which the amplitude of the differential demodulated signal SD at the determination time t = “7” is plotted. Any dot exceeds the determination level Lth1 = “+ 1”. The dots plotted in FIG. 5B in this example form three groups I to III, and the wider the interval between these groups, the better the S / N ratio (detection accuracy). It can be seen that the S / N ratio is improved as compared with the case where the determination threshold is set at the zero crossing point shown in FIG.

  6A and 6B are diagrams showing an input eye pattern example and a distribution example (determination level Lth2) of the differential demodulated signal SD at the time of ternary determination. In FIG. 6A, the vertical axis represents the amplitude (level) of the differential demodulated signal SD after synchronous detection. The horizontal axis represents time (time) t for level determination. In the figure, the horizontal thick line indicates the second determination level Lth2, and the vertical thin line is a scroll bar for viewing the amplitude distribution of the differential demodulated signal SD, and the determination time, for example, The case of determination time t = “7” is shown. The determination level Lth2 is set to “−1” which is the midpoint between the amplitude levels “−2” and “0”.

  In FIG. 6B, both the vertical axis and the horizontal axis represent the amplitude (level) of the differential demodulated signal SD. The dots in the figure indicate the amplitude distribution of the differential demodulated signal SD at the determination time t = “7”. Any dot is below the determination level Lth2 = “− 1”. In this way, the three values “−2”, “0”, and “2” can be determined based on the two determination levels Lth1 and Lth2. The ternary data “−2”, “0”, and “2” subjected to the ternary determination are output to the code converter 45.

  The code converter 45 converts the ternary data “−2”, “0”, and “2” into “1” when “−2” and “2”, and “0” when “0”. It is converted into binary data of “0”. Thereby, it is possible to obtain the same demodulated data (DATA) as the normal delay detection shown by the multiplication type delay detection circuit shown in the conventional example.

  Next, the wireless communication method according to the present invention will be described. 7A and 7B are diagrams showing an operation example in the 1-symbol delay unit 41 and the subtracter 42. FIG. FIGS. 8A and 8B are diagrams illustrating an operation example in the ternary determination circuit 43 and the code conversion circuit 45. 9A and 9B are diagrams showing an operation example of the output stage.

  In this embodiment, a tag that receives a carrier signal Sf of 2.45 GHz, modulates the carrier signal Sf with predetermined data, for example, DATA = “1011001...”, And transmits a response signal Sf (D). 10 is attached to the identified object 9. It is assumed that the carrier wave signal Sf is transmitted to the tag 10 attached to the identified object 9 and the response signal Sf (D) returned from the tag 10 is received for signal processing (backscatter communication method). Wireless communication method).

  The tag reader 20 is provided with a subtractive delay detector 40, which delays the baseband signal S (D) based on the response signal Sf (D) by one data code at the time of reception, and the baseband signal at the current time. The baseband signal S (D) at the previous time delayed by one data code is subtracted from S (D), and the differential demodulated signal SD after the subtraction is ternary-determined. An example in which the result signals S2 and S3 are converted to binary data will be described.

  Under this operating condition, a carrier signal Sf of 2.45 GHz is generated by the oscillator 11 shown in FIG. The carrier signal Sf generated by the oscillator 11 is output to the transmitter 12. The transmission unit 12 amplifies the carrier signal Sf based on the output permission signal S1 from the control device 15, and outputs the amplified carrier signal Sf to the transmitting antenna body 13A. For example, the output permission signal S1 is permitted to be transmitted at a high level and is not permitted to be transmitted at a low level. The amplified carrier wave signal (question signal) Sf is radiated from the transmitting antenna body 13A toward the tag 10.

  On the other hand, the tag 10 receives a carrier signal (interrogation signal) Sf of 2.45 GHz. At this time, the interrogation signal transmitted from the tag reader 20 is reflected from the surrounding objects and the tag 10 and returned. The signal reflected from other than the tag is a carrier signal whose phase is shifted compared to the carrier signal Sf transmitted from the tag reader 20. That is, when the carrier wave signal (question signal) Sf radiated toward the tag 10 is reflected by an object other than the tag, the phase of the carrier wave signal at the time of reception is shifted compared to the carrier wave signal Sf at the time of transmission. Moreover, the waveform has a reduced amplitude.

  In the tag 10, in the power supply unit 5 connected to the antenna body 1A, the induced power based on the carrier signal Sf received by the antenna body 1A is supplied to the amplitude modulation unit 2, the memory unit 3, and the clock oscillator 4. The In the memory unit 3, data (code data or the like; for example, DATA = “1011001...”) Specific to the identified object shown in FIG. 6A is read based on a clock signal (CLK) having a predetermined frequency. 101101 ... "is output to the amplitude modulation section 2. The clock signal is oscillated by the clock oscillator 4 and output to the memory unit 3. Thus, the system 100 is configured such that the tag 10 does not need to be provided with a battery or the like.

  In the amplitude modulation unit 2, for example, the carrier wave signal Sf is amplitude-modulated by the unique data “1011001...” Read from the memory unit 3, and tag amplitude modulation after amplitude modulation as shown in FIG. 6B is performed. A signal (response signal) Sf (D) is transmitted. The response signal Sf (D) is scattered (transmitted) through the antenna body 1B. In this example, a BPSK (Binary Phase Shift Keying) modulation unit may be provided instead of the amplitude modulation unit 2. The response signal Sf (D) scattered (transmitted) from the antenna body 1B is received by the antenna 13B of the tag reader 20. At this time, the carrier wave signal reflected from the object is also received through the antenna body 13B as the response composite signal Sin together with the response signal Sf (D).

  The synchronous detector 30 connected to the antenna 13B receives the carrier signal Sf ′ and the response signal Sf (D) and executes synchronous detection processing. The carrier signal Sf ′ is converted into a DC signal Sd and data (DATA = “1011001...”) Is a response signal Sf (D) whose amplitude is modulated, for example, the baseband signal S (D) = “1, −1,1,1, −1, − , 1,... The DC signal Sd and the baseband signal S (D) are output from the synchronous detector 30 to the subtractive delay detector 40.

  In the subtractive delay detector 40, the 1-symbol delay device 41 delays the baseband signal S (D) by one data code. In this example, the baseband signal S (D) = “1, −1,1,1, −1, −1,1,...” Shown in FIG. 7A is delayed by one data code. The baseband signal Sτ (D) after the data delay is “1, −1,1,1, −1, −1,1...” Obtained by delaying S (D) by one symbol. In the figure, the baseband signal Sτ (D) is described by being lowered by one stage.

  Then, the subtractor 42 shown in FIG. 7B subtracts the baseband signal S (D) at the previous time delayed by one data code from the baseband signal S (D) at the current time. In the figure, S (D) −Sτ (D) is calculated for the baseband signal. In this example, the data “1” of the previous time is subtracted from the data “−1” of the current time shown in FIG. 7A, and the differential demodulated signal SD = “− 2” is output.

  Similarly, data “−1” is subtracted from data “1”, differential demodulated signal SD = “2” is output, data “1” is subtracted from data “1”, and differential demodulated signal SD = “0” is output, data “−1” is subtracted from data “−1”, differential demodulated signal SD = “− 2” is output, data “−1” is subtracted from data “−1”, The differential demodulated signal SD = “0” is output, the data “−1” is subtracted from the data “1”, and the differential demodulated signal SD = “2”.

  The differential demodulated signal SD is output from the subtractor 42 to the comparators 31 and 32 shown in FIG. The comparators 31 and 32 are configured to determine the differential demodulated signal SD in three values. For example, when the differential demodulated signal SD is “−2”, the comparator 31 compares the determination level Lth1 = “+ 1” and outputs the comparison result signal S2 = “0”. The comparator 32 compares the determination level Lth2 = “− 1” and outputs a comparison result signal S3 = “0”.

  Similarly, when the differential demodulated signal SD = “2”, the comparator 31 compares the determination level Lth1 = “+ 1” and outputs the comparison result signal S2 = “1”. The comparator 32 compares the determination level Lth2 = “− 1” and outputs a comparison result signal S3 = “1”. Further, when the differential demodulated signal SD = “0”, the comparator 31 compares the determination level Lth1 = “+ 1” and outputs the comparison result signal S2 = “0”. The comparator 32 compares the determination level Lth2 = “− 1” and outputs a comparison result signal S3 = “1”.

  The comparison result signal S2 is inverted by the inverter 51 to become an inverted signal S2 bar (the upper line is omitted). Similarly, the comparison result signal S3 is inverted by the inverter 52 to become an inverted signal S3 bar (the upper line is omitted). When the differential demodulated signal SD is “−2”, the inverter 51 outputs the inverted signal S2 bar = “1”, and when the differential demodulated signal SD is “2”, the inverter 51 outputs the inverted signal S2 bar = “0”. When the differential demodulated signal SD is “0”, the inverter 51 outputs the inverted signal S2 bar = “1”.

  When the differential demodulated signal SD is “−2”, the inverter 52 outputs the inverted signal S3 bar = “1”, and when the differential demodulated signal SD is “2”, the inverter 51 outputs the inverted signal S2 bar = When “0” is output and the differential demodulated signal SD is “0”, the inverter 51 outputs the inverted signal S2 bar = “0”.

  Further, the two-input AND circuit 53 calculates a logical product of the two inverted comparison result signals S2 and S3 output from the two inverters 51 and 52, and outputs a two-input AND signal S4. In this example, when the differential demodulated signal SD is “−2”, the two-input AND circuit 53 outputs a two-input AND signal S4 = “1”, and when the differential demodulated signal SD is “2”, S4 = When “0” is output and the differential demodulated signal SD is “0”, the two-input AND signal S4 = “0” is output.

  The two-input AND circuit 54 calculates a logical product of the two non-inverted comparison result signals S2 and S3 output from the comparators 31 and 32 and outputs a two-input AND signal S5. In this example, when the differential demodulated signal SD is “−2”, the two-input AND circuit 53 outputs a two-input AND signal S5 = “0”, and when the differential demodulated signal SD is “2”, S5 = When “1” is output and the differential demodulated signal SD is “0”, S5 = “0” is output.

  The two-input AND signals S4 and S5 are input to the two-input OR circuit 55. The two-input OR circuit 55 calculates a logical sum of the two two-input AND signals S4 and S5 output from the two-input AND circuits 53 and 54, and outputs a two-input OR signal S6. In this example, when the differential demodulated signal SD is “−2”, the two-input OR circuit 55 outputs a two-input OR signal S6 = “1”, and when the differential demodulated signal SD is “2”, S6 = When “1” is output and the differential demodulated signal SD is “0”, S6 = “0” is output.

  The two-input OR signal S6 is input to one input terminal of the two-input EXOR circuit 56 shown in FIG. 9B. To the other side of the two-input EXOR circuit 56, DATA that holds one symbol in the memory 57 is input. In this example, the initial value M of the memory 57 is set to “1”.

  The two-input EXOR circuit 56 calculates the exclusive OR of the data DATA = “1” at the previous time delayed by one data code and the two-input OR signal S6 = “1” at the current time. “0” is output. At this time, the initial value M = “1” of the memory 57 is inverted to “0”. Similarly, the exclusive OR of the stored value = “0” in the memory 57 at the previous time and the two-input OR signal S6 = “1” at the current time is calculated, and DATA = “1” is output. At this time, the stored value = “0” in the memory 57 is inverted to “1”. Then, the exclusive OR of the stored value = “1” of the memory 57 at the previous time and the two-input OR signal S6 = “0” at the current time is calculated, and DATA = “1” is output. At this time, the stored value = “1” in the memory 57 remains the same.

  Further, the exclusive OR of the stored value = “1” of the memory 57 at the previous time and the two-input OR signal S6 = “1” at the current time is calculated, and DATA = “0” is output. At this time, the stored value = “1” in the memory 57 is inverted to “0”. Then, the exclusive OR of the stored value = “0” of the memory 57 at the previous time and the two-input OR signal S6 = “0” at the current time is calculated, and DATA = “0” is output. At this time, the stored value of the memory 57 remains “0”. Then, the exclusive OR of the stored value = “0” of the memory 57 at the previous time and the two-input OR signal S6 = “1” at the current time is calculated, and DATA = “1” is output. At this time, the stored value = “0” in the memory 57 is inverted to “1”.

  In this way, binary data DATA = “1011001...” Can be output from the code converter 45. The binary data DATA = “1011001...” Is nothing but the tag-specific data DATA = “1011001. The data DATA is read by the data reading unit 50 and displayed on the monitor 16 through the control device 15. The monitor 16 displays the price, name, etc. based on the unique data of the identified object 9 read from the tag 10.

  As described above, according to the tag reader system 100 as the embodiment of the present invention, the response signal Sf () in which the carrier signal Sf having the frequency of 2.45 GHz is modulated by the predetermined data DATA = “1011001... In the case where D) is received from the backscattering communication type tag 10 and processed, in the subtractive delay detector 40 provided in the receiving unit 14, the 1-symbol delay device 41 is based on the response signal Sf (D). The signal S (D) is delayed by one data code. The subtracter 42 subtracts the baseband signal S (D) at the previous time delayed by one data code by the one symbol delay unit 41 from the baseband signal S (D) at the current time. .

  Therefore, the DC component Sd based on the unmodulated carrier signal Sf ′ reflected from the surrounding object at the time before one data code and the unmodulated carrier signal Sf ′ reflected from the surrounding object at the current time. Since the DC component Sd based on can be canceled out, the interference wave can be removed. In addition, the differential demodulated signal SD after the subtraction is ternary-determined, and the comparison result signals S2 and S3 subjected to the ternary determination are converted into binary data. Thus, the delay detection function can be realized. As a result, it is possible to demodulate highly reliable data that is not affected by interference noise caused by the carrier wave signal Sf ′ reflected from the surrounding object.

  The present invention relates to a system for reading electronic price tags attached to tableware in restaurants, merchandise, etc. in stores, a system for reading electronic tag tags attached to articles distributed on goods distribution bases, etc. The present invention is extremely suitable when applied to a guidance sign reading system for guiding.

It is a conceptual diagram which shows the structural example of the tag reader system 100 as an Example which concerns on this invention. 2 is a block diagram showing an example of an internal configuration at the time of transmission / reception in the tag reader system 100. FIG. 3 is a block diagram illustrating a configuration example of a subtraction type delay detector 40. FIG. 3 is a diagram illustrating a circuit configuration example of a subtraction type delay detector 40. FIG. (A) And (B) is a figure which shows the example of an input eye pattern of the differential demodulation signal SD at the time of ternary determination, and the example of distribution (determination level Lth1). (A) And (B) is a figure which shows the example of an input eye pattern of the differential demodulation signal SD at the time of ternary determination, and the example of distribution (determination level Lth2). (A) and (B) are diagrams showing an operation example in the 1-symbol delay unit 41 and the subtracter 42. (A) and (B) are diagrams illustrating exemplary operations in the ternary determination circuit 43 and the code conversion circuit 45. (A) And (B) is a figure which shows the operation example of the output stage of the code conversion circuit 45. FIG. It is a perspective view which shows the structural example of the tag reader system 1 which concerns on a prior art example. 3 is a block diagram illustrating a configuration example of a receiving unit of the tag reader 101. FIG. A and B are diagrams showing an example of input eye patterns and an example of distribution of the multiplication result signal S11 at the time of binary determination.

Explanation of symbols

1A, 1B, 13A, 13B ... antenna body, 2 ... amplitude modulation unit, 3 ... memory unit, 4 ... clock oscillator, 5,18 ... power supply unit, 10 ... tag , 11 ... Oscillator, 12 ... Transmission unit, 14 ... Reception unit, 15 ... Control device, 16 ... Operation unit, 17 ... Monitor, 20 ... Tag reader, 30 ... Synchronous detector, 40 ... Subtractive delay detector, 50 ... Data reader, 100 ... Tag reader system (wireless communication system)

Claims (6)

From the signal response of the backscatter communication method that is attached to a predetermined identification target object, when receiving and processing a response signal a carrier signal is modulated by predetermined data of a predetermined frequency,
A transmitter for transmitting a carrier wave signal to the signal responder;
A signal processing unit that receives and processes a response signal scattered from the signal responder,
The signal processing unit is provided with a demodulator,
The demodulator
A baseband signal based on the response signal is delayed by one data code;
Subtract the baseband signal of the previous time delayed by one data code from the baseband signal of the current time of the data , generate a reference voltage based on the signal after the subtraction, and set two determination levels ,
Three values are determined by comparing the set two determination levels with the signal after subtraction ,
Ternary the determined information processing apparatus that converts the signal into binary data. The demodulator
A signal delay unit for delaying a baseband signal based on the response signal by one data code;
A subtractor for subtracting the baseband signal at the previous time delayed by one data code by the signal delay device from the baseband signal at the current time;
A threshold setting circuit that generates a reference voltage based on the signal after subtraction by the subtractor and sets two determination levels;
A determinator for comparing the two determination levels set by the threshold setting circuit with the signal after subtraction to determine a ternary value;
The determining unit by 3 values determined to be the information processing apparatus according to 請 Motomeko 1 that have a a code converter that converts the signal into binary data. A signal that is attached to a predetermined identification object, receives a carrier signal of a predetermined frequency, modulates the carrier signal with the data, and transmits a response signal when wirelessly communicating the predetermined data using the backscatter communication method. A responder;
An information processing device that transmits the carrier wave signal to the signal responder and receives a response signal scattered from the signal responder to perform information processing;
The information processing apparatus is provided with a demodulator,
The demodulator
A baseband signal based on the response signal is delayed by one data code;
Subtracting the baseband signal of the previous time delayed by one data code from the baseband signal of the current time, generating a reference voltage based on the signal after the subtraction, and setting two determination levels;
Three values are determined by comparing the set two determination levels with the signal after subtraction ,
Ternary the determined radio communications system that converts the signal into binary data. The demodulator
A signal delay unit for delaying a baseband signal based on the response signal by one data code;
A subtractor for subtracting the baseband signal at the previous time delayed by one data code by the signal delay device from the baseband signal at the current time;
A threshold setting circuit that generates a reference voltage based on the signal after subtraction by the subtractor and sets two determination levels;
A determinator for comparing the two determination levels set by the threshold setting circuit with the signal after subtraction to determine a ternary value;
The wireless communication system according to 請 Motomeko 3 that have a a code converter for converting the signals is determined ternary by the determiner to the binary data. The signal responder is
An antenna body for receiving the carrier signal;
A memory unit storing the data;
An amplitude modulation unit that modulates the amplitude of the carrier signal based on data read from the memory unit;
The wireless communication system according to induced electromotive force based on the carrier signal received by the antenna body 請 Motomeko 3 that have a power supply section for supplying to said memory unit and the amplitude modulation section. A signal responder that receives a carrier signal of a predetermined frequency, modulates the carrier signal with predetermined data and transmits a response signal is attached to the identified object, and the carrier signal is attached to the signal responder attached to the identified object And a radio communication system of the backscattering communication system that receives the response signal returned from the signal responder and performs signal processing ,
When receiving, the baseband signal based on the response signal is delayed by one data code,
Subtracting the baseband signal of the previous time delayed by one code of the data from the baseband signal of the current time,
Generate a reference voltage based on the signal after subtraction and set two judgment levels,
Three values are determined by comparing the set two determination levels with the signal after subtraction ,
Ternary the determined radio communications method that converts the signal into binary data.

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