JP4365226B2 - Plasma etching apparatus and method - Google Patents

Description

  The present invention relates to a plasma etching apparatus and method, and more particularly to a plasma processing apparatus and method used for processing a semiconductor integrated circuit, and more particularly to a plasma etching apparatus and method.

  Semiconductor devices that support an advanced information society are rapidly miniaturized and highly integrated. Recently, not only miniaturization of dimensions but also the use of structures with increased density by using space in the depth direction has come to be used. . For this reason, in the etching process, deep holes and grooves are required to be processed. In the processing of these deep grooves and holes, the etching is performed by increasing the bias voltage applied to the wafer through the electrodes more than usual.

  When etching is performed using a high bias voltage, the sheath formed between the plasma and the periphery of the electrode, that is, the space above the edge of the wafer, is distorted, and the processed shape is also distorted. Tend to occur. This is because the bias voltage applied to the electrode is basically high, and the electrode is not biased on the non-wafer mounting portion of the electrode. The sheath structure formed between the plasma and the electrode is not relative to the wafer mounting portion. This is caused by the fact that the difference in size increases and becomes discontinuous.

  Holes and grooves in the edge portion of the wafer having a distorted processing shape generate voids in a subsequent embedding process or the like by subsequent deposition, resulting in malfunction of the device and reducing the yield.

  In particular, when a semiconductor integrated circuit is produced using a wafer having a diameter of 300 mm as in recent years, the area of the wafer edge portion is relatively large, the number of defective chips is large, and this is a major factor in increasing the production cost. Yes.

  As one of countermeasures, there is a method in which a voltage is applied to the wafer non-mounting portion of the electrode similarly to the wafer mounting portion in order to reduce the distortion of the sheath at the peripheral portion of the wafer. In this case, since the material of the wafer non-mounting portion is also etched like the wafer, the material has little influence on the etching process and must not contain impurities that affect the device characteristics. As this material, a method is known in which silicon having the same high purity as the wafer is processed into a ring shape.

  However, in this method, the silicon ring wears out due to etching, and the height position of the surface changes relative to that of the wafer. As a result, the sheath is distorted by the same mechanism as above, and the distortion of the processed shape gradually occurs. Therefore, it was necessary to frequently perform a vacuum break of the etching apparatus and replace the silicon ring.

  For this reason, the operating time of the apparatus is reduced, and also in this case, the price of the silicon ring is increased as the wafer diameter is increased, which has been a factor in increasing the production cost.

  An object of the present invention is to provide a plasma etching apparatus and method capable of producing a semiconductor integrated circuit with a large diameter wafer at a low cost.

In the present invention, the supply of the peripheral bias voltage to the ring installed in the peripheral portion of the electrode of the non-wafer mounting portion is performed independently of the bias voltage supply of the wafer mounting portion, and the voltage ratio is relatively changed. The relative change amount is determined by directly or indirectly monitoring the processing shape distortion at the wafer edge portion. One method of indirectly monitoring is a method of monitoring the thickness of a ring installed around the electrode from the outside using a laser.

That is, the present invention relates to a plasma etching apparatus comprising a vacuum processing chamber, means for supplying a gas to the vacuum processing chamber, plasma generation means, and an electrode on which a wafer is placed and a voltage is applied. A peripheral member to which a peripheral bias voltage independent of the bias voltage of the wafer mounting portion is applied is placed on the non-wafer mounting portion around the electrode, and applied to the peripheral member with respect to the bias voltage applied to the electrode. In the plasma etching apparatus, the ratio of the peripheral bias voltage to be set is set with reference to the thickness of the peripheral member .

  Moreover, this invention is a plasma etching apparatus which has a laser displacement meter which measures the thickness of the said peripheral member.

Further, the present invention is a plasma etching apparatus having a circuit for calculating an output signal of the laser displacement meter and controlling a ratio of a peripheral bias voltage applied to the peripheral member to a bias voltage applied to the electrode. is there.

Furthermore, the present invention is a plasma etching apparatus having suitable characteristic function data of a displacement amount of the laser displacement meter and a ratio of a peripheral bias voltage applied to the peripheral member to a bias voltage applied to the electrode. .

Further, the present invention is a method for plasma-generating and plasma-etching a wafer by applying a voltage to an electrode on which a wafer is placed, wherein the electrode is a peripheral portion independent of a bias voltage of the wafer placement portion. and placing the peripheral member a bias voltage is applied to the non-wafer placing portion near the electrode, the ratio of the perimeter bias voltage applied to the peripheral member with respect to the bias voltage applied to the pre-Symbol electrodes, wherein This is a plasma etching method set by referring to the thickness of the peripheral member .

The present invention provides a ratio of a peripheral bias voltage applied to the peripheral member to a bias voltage applied to the electrode when processing a hole or groove shape having an aspect ratio of 5 or more on a wafer. This is a plasma etching method set by referring to the thickness of the peripheral member.

  Furthermore, the present invention is a plasma etching method in which the method of referring to the thickness of the peripheral member is measurement of the thickness with a laser displacement meter.

  By these means, etching can be performed up to the peripheral part of the wafer without causing distortion in the processed shape, further reducing the cost of consumables and increasing the operating time of the apparatus, thereby reducing the production cost.

  According to the present invention, a semiconductor integrated circuit can be produced at a low cost with a large-diameter wafer.

The best mode for carrying out the present invention will be described.
An embodiment of the plasma etching apparatus and method of the present invention will be described with reference to FIG. FIG. 1 is a schematic cross-sectional view of a plasma etching apparatus using UHF-ECR. Here, 101 is a vacuum processing chamber, a quartz window 102 is provided for passing the UHF electromagnetic field into the vacuum processing chamber 101, and an electrode 103 is disposed in the vacuum processing chamber 101 so as to face the quartz window 102, and a semiconductor A wafer 104 on which an integrated circuit is formed is placed, and a high frequency power source 105 for generating a bias voltage is connected. The antenna 107 is connected to the quartz window 102 and introduces an electromagnetic field from the UHF power source 110 into the vacuum processing chamber 101. The solenoid coil 108 forms a magnetic field in the vacuum processing chamber 101. The gas dispersion plate 109 disperses the gas supplied from the mass flow controller 111 according to the etching recipe into the vacuum processing chamber 101 and introduces it uniformly.

  A silicon ring 121 is installed on the non-wafer mounting portion of the electrode 103 via an insulating ring 123 and a conductor ring 122. A high frequency power source 105 is connected to the conductor ring 122 from outside the vacuum processing chamber 101 via an impedance adjustment circuit 124.

  A laser displacement meter 125 is provided at a position facing the silicon ring 121 outside the vacuum of the quartz window 102. An output signal of the laser displacement meter 125 is input to the arithmetic processing unit 126. A signal for controlling the impedance adjustment circuit 124 is output from the arithmetic processing unit 126.

In order to explain the effect of the present embodiment, first, let us look at the shape after drilling when the thickness of the silicon ring 121 is 4 mm and the voltage ratio between the wafer 104 and the silicon ring 121 is 1: 1. The target processing shape is a hole (aspect ratio: 7.2) having a diameter of 0.25 μm and a depth of 1.8 μm. 2 (a) and 2 (b) show the hole processing shapes at the center and the periphery of the wafer, and normal processing has been performed vertically at the center, but the holes at the wafer edge have been processed obliquely. The

  Here, FIGS. 3A and 3B show the results of performing etching in the same manner by using the impedance adjustment circuit 124 to attenuate the supply voltage to the silicon ring 121 to 65% of the voltage to the wafer 104. It can be seen that both the wafer center portion and the wafer edge portion are vertical and have a normal hole.

  Next, several hundreds of wafers are sequentially processed from the above state, and the later drilled shapes are shown in FIGS. 4 (a) and 4 (b). It can be seen that the processing shape is skewed and distorted at the wafer edge portion, and at this time, it is inclined in the opposite direction from the case of FIG.

  When the signal of the laser displacement meter 125 at this time was monitored, it was found that the distance to the silicon ring 121 was displaced by +1 mm, the silicon ring 121 was worn out by 1 mm, and the thickness was 3 mm. It is considered that the inclination of the processed shape at the wafer edge portion is caused by a change in the relative relationship between the surface position of the silicon ring 121 and the surface position of the wafer 104.

  Therefore, when this embodiment is applied and etching is performed with the impedance adjustment circuit 124 setting the supply voltage to the silicon ring 121 to 80% of the supply voltage to the wafer 104, normal hole machining is performed at both the wafer center portion and the edge portion. I was able to get the shape.

  Further, when the processing was continued and the hole processing shape at the time when the indicated value of the laser displacement meter reached +2 mm was confirmed, it was observed that the hole processing shape at the wafer edge portion was inclined in the same direction as in FIG. Therefore, by setting the supply voltage to the silicon ring 121 to 92% of the supply voltage to the wafer 104 using the impedance adjustment circuit 124, a normal processing shape can be obtained at all positions in the plane as shown in FIG. I was able to.

  From the above results, it was possible to obtain the relationship between the output of the impedance adjustment circuit 124 and the laser displacement meter 125 in order to obtain a normal processing shape without inclination in the wafer surface as shown in FIG. This characteristic curve is a function that indicates a preferable relationship between the displacement amount of the laser displacement meter and the non-mounting portion / mounting portion voltage ratio. In response to this, the output of the impedance adjustment circuit 124 is automatically adjusted sequentially.

  In order to confirm this effect, the silicon ring 121 was replaced with a new one, the displacement of the laser displacement meter 125 was reset to the zero point, and processing was performed continuously. When the processed shape of the processed wafer up to the point when the indicated value of the displacement amount of the laser displacement meter reached +2.5 mm was extracted and the processed shape was confirmed, it was confirmed that all were processed normally.

  As described above with reference to the embodiments, according to the present invention, even when the silicon ring is worn down over time, it is possible to automatically maintain a state where it can be processed normally up to the wafer edge, and the silicon ring can be used without replacement for a long period Therefore, the operating time of the apparatus can be kept high and the exchange amount of the silicon ring can be reduced, so that the production cost can be greatly reduced.

Sectional drawing of the plasma processing apparatus explaining an Example. The figure which shows an example of the process shape at the time of etching, without adjusting. The figure which shows an example of the process shape at the time of adjusting and etching. The figure which shows another example of the process shape at the time of etching, without adjusting. The figure which shows the calculation function used for control of the bias voltage ratio in an Example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 ... Vacuum processing chamber 103 ... Electrode 104 ... Wafer 121 ... Silicon ring 122 ... Conductor ring 124 ... Impedance adjustment circuit 125 ... Laser displacement meter 126 ... Processing unit

Claims (7)

In a plasma etching apparatus comprising a vacuum processing chamber, means for supplying a gas to the vacuum processing chamber, plasma generation means, and an electrode on which a wafer is placed and a voltage is applied,
The electrode is mounted on a non-wafer mounting portion around the electrode with a peripheral member to which a peripheral bias voltage independent of the bias voltage of the wafer mounting portion is applied,
A plasma etching apparatus , wherein a ratio of a peripheral bias voltage applied to the peripheral member to a bias voltage applied to the electrode is set with reference to a thickness of the peripheral member . The plasma etching apparatus according to claim 1, wherein
A plasma etching apparatus comprising a laser displacement meter for measuring the thickness of the peripheral member. The plasma etching apparatus according to claim 2, wherein
A plasma etching apparatus, comprising: a circuit for calculating an output signal of the laser displacement meter and controlling a ratio of a peripheral bias voltage applied to the peripheral member to a bias voltage applied to the electrode. The plasma etching apparatus according to claim 3, wherein
A plasma etching apparatus comprising suitable characteristic function data of a displacement amount of the laser displacement meter and a ratio of a peripheral bias voltage applied to the peripheral member to a bias voltage applied to the electrode. A method for plasma-etching a wafer by generating a plasma and applying a voltage to an electrode on which the wafer is placed,
The electrode has a peripheral member to which a peripheral bias voltage independent of the bias voltage of the wafer mounting part is applied mounted on a non-wafer mounting part around the electrode ,
Plasma etching method characterized in that the ratio of the perimeter bias voltage applied to the peripheral member with respect to the bias voltage applied to the pre-Symbol electrodes, set with reference to the thickness of the peripheral member. The plasma etching method according to claim 5, wherein
When the aspect ratio on the wafer to process the hole or groove shape is 5 or more, the ratio of the perimeter bias voltage applied to the peripheral member with respect to the bias voltage applied to the electrode, the thickness of the peripheral member A plasma etching method characterized by being set with reference. The plasma etching method according to claim 6, wherein
A plasma etching method characterized in that the method of referring to the thickness of the peripheral member is measurement of the thickness by a laser displacement meter.

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