JP4341371B2 - Matrix device, driving method thereof, and electronic apparatus - Google Patents

Description

  The present invention relates to a matrix device that sequentially selects functional elements arranged in a matrix. More specifically, the present invention relates to a capacitance detection technique for reading a surface shape of a test object having minute irregularities such as a fingerprint by a capacitance detection element arranged in a matrix.

  JP 11-118415 A, JP 2000-346608 A, JP 2001-56204 A, and JP 2001-133213 A public information include a sensor electrode and a dielectric film formed on a single crystal silicon substrate. A technique for detecting the uneven shape of a fingerprint as a capacitance formed between a fingertip and a sensor electrode has been disclosed.

  However, the element formed on the single crystal silicon substrate is broken when the finger is pressed strongly. In addition, the fingerprint sensor needs to be about the size of the fingertip area (about 20 mm × 20 mm) depending on its use, and is heavy and expensive. Further, the element formation region is the very surface of the single crystal silicon substrate, and most of the single crystal silicon substrate plays a role as a mere support, so it is formed on a great deal of waste and waste. There was a problem such as.

  Therefore, as disclosed in R.Hashido et. Al., IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.38, NO.2, p274 (2003) Technology has been developed. A capacitance detection device formed of a thin film semiconductor is lighter and lower in cost than that formed on a single crystal silicon substrate. Furthermore, if this is transferred to a plastic substrate by applying the peeling transfer technique disclosed in S. Utsunomiya et. Al., Society for Information Display, p.916 (2000), it is cheaper, less likely to break, and lighter. Since it can realize a simple fingerprint sensor, it is expected to be mounted on smart cards.

  These electrostatic capacitance devices using thin film semiconductors use an active matrix driving circuit which is a circuit for sequentially selecting functional elements arranged in a matrix. This circuit technology has already been put into practical use in an active matrix type liquid crystal driving circuit.

  The conventional active matrix driving circuit shown in FIG. 10 includes a plurality of scanning lines 32 for sequentially selecting functional elements 51 arranged in a matrix, a scanning driver 20 for selecting the scanning lines, and data. A line 33 and a data driver 10 for selecting the data line are provided. Functional elements 51 are arranged at the intersections of the scanning lines 32 and the data lines 33, respectively. The scan driver 20 includes a scan shift register 21 for determining timing. The scan shift register 21 has a terminal CLKY for inputting a scan line selection reference signal corresponding to a row reference signal for determining operation timing. I have. The data driver 10 includes a data shift register 11 for determining timing, and the data shift register 11 has a terminal CLKX for inputting a data line selection reference signal corresponding to a column reference signal for determining operation timing. I have. The operation timing of each reference signal is controlled by an external control circuit, and the scanning shift register 21 and the data shift register 11 are arranged in the first stage of each shift register based on the scanning line selection reference signal and the data line selection reference signal which are reference signals. Are sequentially transferred to the signals SPX and SPY. The scanning driver 20 and the data driver 10 sequentially select the scanning line 32 and the data line 33, so that one functional element 51 on the matrix is sequentially selected, and the functional element is connected via the data line 33. Operate.

JP 11-118415 A JP 2000-346608 PR JP 2001-56204 PR JP 2001-133213 PR S. Utunomiya et.al., Society for Information Display p.916 (2000) R.Hashido et.al., IEEE JOURNAL OF SOLID-STATES CIRCUITS, VOL.38, NO.2, p274 (2003)

  However, in the conventional configuration, as a control signal for controlling the operation timing of the data driver 10 and the scan driver 20, a row reference signal and a column reference signal, which are two dedicated reference signals, are generated by an external control circuit, respectively. It was controlled by supplying to the shift register. Also, the start pulse signals SPX and SPY are supplied to the first stage of each shift register. As a result, an external connection terminal for inputting a reference signal and an external connection terminal for inputting a start pulse signal are required for each selection circuit as external connection terminals for inputting a control signal. As described above, the increase in the number of connection terminals increases the restrictions on mounting, and there are problems with ease of mounting, connection reliability, design freedom, inspection efficiency, and the like.

  Further, in order to control the operation timing of the data driver 10 and the scan driver 20, it is necessary to synchronize these control signals by an external control circuit, and the external control circuit is complicated. For this reason, there was a problem that the development efficiency was poor.

  In view of the above-described circumstances, an object of the present invention is to propose a matrix device and a driving method thereof in which the number of control signals and the number of external connection terminals are reduced and the control system is simplified.

In order to solve the above problems, the matrix device of the present invention includes M row lines and N column lines, and functional elements provided at intersections of the row lines and the column lines. column in a matrix shape arranged matrix device, the matrix device, which selects the row selection means for selecting a particular row line from the row lines of the M, the particular column line from the column lines of the N comprising selecting means, and a non-selection means for switching between said row selection means and said column selecting means to a non-selected state, said column selection means, have a column selection end signal output means for outputting the column selection end signal and, said row selection means, said column selection end signal is inputted and a column selection end signal input means for providing a row reference signal for selecting a particular row line, said row reference signal is input a plurality of output A scan shift register having a stage, and the scan shift register Selecting a specific row line by selecting a specific stage from the plurality of output stages, and a specific output stage selected by the input row reference signal is advanced by one stage, The deselecting means supplies a reset signal to each stage of the scan shift register, and at least two stages on the input side of the scan shift register are selected by the reset signal, and the other stages are not selected. It is characterized by being configured as follows.

  In the matrix device, the row selection means includes a scanning shift register having a plurality of output stages, and the scanning shift register selects the specific row line by selecting a specific stage from the plurality of output stages. It is desirable that a specific output stage selected every one cycle of the row reference signal advances by one stage.

  The matrix device preferably includes a non-selection unit that switches a plurality of the column selection unit and the row selection unit to a non-selected state at the same time.

  In the matrix device, the deselecting means supplies a reset signal to each stage of the scan shift register, and at least two stages on the input side of the scan shift register are selected by the reset signal. It is desirable that each stage is configured to be in a non-selected state.

  In the matrix device, it is preferable that at least two outputs on the input side of the scan shift register that are selected by the reset signal are not connected to a functional element.

  With this configuration, a row reference signal that has been conventionally supplied from an external control circuit is generated by the column selection means and supplied to the row selection means. Further, the reset signal sets two stages on the input side of the scan shift register of the row selection means to the selected state, and the other stages are set to the non-selected state, so that means for inputting the start signal is not necessary. For this reason, the number of terminals is reduced by two as compared with the conventional configuration, and the ease of mounting and the reliability of wiring can be improved. Further, since the column selection circuit operates in conjunction with the row selection circuit, it is not necessary to synchronize the control signals, and the control system can be simplified.

  In the matrix device, it is preferable that the functional element is composed of a MIS thin film semiconductor. The MIS thin film semiconductor can be formed on an insulating substrate. By employing a glass substrate, a plastic substrate, or the like as the insulating substrate, the manufacturing cost can be reduced.

  An electronic apparatus according to the present invention includes the matrix device according to the present invention. Since the electronic device has a simple control system and less wiring restrictions compared to an electronic device having a conventional matrix device, the degree of freedom in mounting is high. For example, when a capacitance detection device is made by applying the matrix device of the present invention, in addition to various card media such as an IC card, a cash card, a credit card, and an identification card, an identity verification device for electronic commerce, an entrance / exit It is suitable for a management device, an authentication device for a computer terminal device, and the like.

  According to the matrix device of the present invention, the reset signal, the column reference signal for controlling the operation timing of the matrix device and its inverted signal, and the input of only the low potential power line and the high potential power line which are the voltage sources of the drive circuit are Matrix operation is possible. As a result, the number of input signals can be reduced and the number of external connection terminals can be reduced as compared with the conventional matrix driving device. In addition, the control system can be simplified.

  Assuming that matrix devices are applied to smart cards, etc., external connections can be made because the area allowed for wiring and mounting is limited in addition to the ease of mounting, connection reliability, and development efficiency. It is preferable that the number of terminals is small and the control signal is simple. If the number of external connection terminals is reduced, the yield during wiring and the inspection efficiency can be improved. If the control system is simple, the development efficiency can be improved. In addition, a free design with few restrictions on wiring and mounting becomes possible.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. As an embodiment, the matrix device of the present invention is applied to a capacitance detection device that reads unevenness information on the surface of the test object by outputting a detection signal corresponding to the capacitance formed between the surface of the test object. did.

  FIG. 1 is a block diagram of a capacitance type fingerprint sensor 1 which is a capacitance detection device in which capacitance detection circuits 31 are arranged in a matrix. The capacitance detection circuit 31 corresponds to a functional element of the present invention. As shown in the figure, the fingerprint sensor 1 includes a data line 33 corresponding to the column line of the present invention, a data driver 10 for selecting a data line corresponding to the column selection means of the present invention, A scanning line 32 corresponding to a row line, a scanning driver 20 for selecting a scanning line corresponding to a row selection means of the present invention, an active matrix unit 30 functioning as a fingerprint detection unit, and a signal for amplifying a detection signal An amplifier circuit 40 is provided.

  The data driver 10 includes a data shift register 11 that determines the timing for sequentially selecting the data lines 33 and an analog switch 13. The data driver 10 is one aspect of the column selection means of the present invention. The scan driver 20 includes a scan shift register 21 that determines the timing for sequentially selecting the scan lines 32. The scan driver 20 is one aspect of the row selection means of the present invention. The data shift register 11 and the scan shift register 21 are connected to a reset signal RST generation circuit (not shown) corresponding to the non-selection means of the present invention. The final stage of the data shift register 11 includes an EP / EPB generation circuit corresponding to the column selection end signal output means of the present invention, and XEP which is the output of the final stage of the data shift register 11 is input. The EP / EPB generation circuit generates EP and EPB having opposite phases from XEP. EP and EPB are connected to the column reference signal input terminal of the scanning shift register 21 corresponding to the column selection signal input means of the present invention.

  Capacitance detection circuits 31 are arranged in a matrix (M rows × N columns) in the active matrix unit 30, and M scanning lines 32 and M low potential power supply lines VSS are wired in the row direction. The N data lines 33 are wired along the column direction.

  In the above configuration, when the M scanning lines 32 are activated for each line, the N data lines 33 arranged on the scanning lines 32 that are active at a certain time are sequentially selected and amplified by the analog switch 13. Point-sequential driving is performed so as to connect to the circuit 40.

  The data driver 10 and the scan driver 20 of the present embodiment include a data shift register 11 and a scan shift register 21, respectively, and can sequentially select the data line 33 and the scan line 32 at high speed by the operation. However, in the conventional active matrix driving device, when the variation in potential at the time of turning on the power is erased, it is necessary to perform a full scan with a normal shift register, and it takes an extra time to start up after turning on the power. In order to avoid this, in the present embodiment, the data in the shift register can be collectively reset only by applying the reset signal RST to the data shift register 11 and the scan shift register 21. In response to the reset signal RST, only two stages on the input side of the scan shift register 21 of the scan driver 20 are selected, and all other stages are unselected.

  FIG. 2 is a circuit diagram of the data driver 10 used in the capacitance fingerprint sensor, and FIG. 3 is a circuit diagram of the scanning driver 20.

  The data shift register 11 provided in the data driver of FIG. 2 includes a clocked inverter 14 that controls reception of data from the previous stage, an inverter 15 that inverts the output of the clocked inverter, and an output or shift of the inverter 15. A combination with the clocked NAND 16 for inversion control of the output to the subsequent stage of the register is made into one stage, and this is connected over a plurality of stages. The data shift register 11 receives a clock signal CLK and a clock inverted signal CLKB that are opposite in phase to each other and correspond to the column reference signal of the present invention. In the odd stages of the data shift register 11, CLK is input to the clocked inverter 14 and CLKB is input to the clocked NAND 16. At even stages, CLKB is input to the clocked inverter 14 and CLK is input to the clocked NAND 16. Therefore, the operation timings of the even and odd stages of the data shift register 11 are opposite to each other.

  As shown in the circuit configuration of the clocked NAND 16, the clocked NAND 16 includes a clocked inverter 16a and reset signal input transistors Tr1 and Tr2. As an input signal to the clocked NAND 16, a reset signal RST from a reset signal generation circuit (not shown) and an output signal from the inverter 15 are input as an IN signal. When the reset signal RST is at the level L, the transistor Tr2 is inactive, and the transistor Tr1 to which the inverted signal is inverted is activated, so that the output voltage is close to the high potential VDD. Therefore, the clocked NAND 16 outputs the level H regardless of the input signal IN. At this time, since the output H of the clocked NAND 16 is inverted by the inverter 15, the outputs (N3, N5) of each stage of the shift register are all at the level L.

  When the input signal RST for the clocked NAND 16 is at level H, the transistor Tr2 is active and the transistor Tr1 is inactive. In this case, the clocked NAND 16 is equivalent to a circuit including only the clocked inverter 16a. Accordingly, at this time, the data shift register 11 performs the following normal shift register operation.

  At odd stages (2n-1 stages; n is a natural number) of the data shift register 11, the clocked inverter 14 becomes active in synchronization with the rising edge of the clock signal CLK, and the clocked NAND 16 becomes active in synchronization with the rising edge of the clock inverted signal CLKB. It has become. On the other hand, in an even number stage (2n stage; n is a natural number), the clocked inverter 14 becomes active in synchronization with the rising edge of the clock inverted signal CLKB, and the clocked NAND 16 becomes active in synchronization with the rising edge of the clock signal CLK. Since the clock signal CLK and the clock inversion signal CLKB are complementary signals, the operation timing is shifted by a half period of CLK between the odd-numbered stage and the even-numbered stage of the data shift register 11.

  First, the operation of the data shift register 11 when the clock signal CLK rises will be described.

  In the odd stage (2n-1 stage; n is a natural number) of the data shift register 11, the clocked inverter 14 becomes active in synchronization with the rising edge of the clock signal CLK. At this time, the signal of the input section (N1) of the clocked inverter 14 is inverted and output to the output section (N2) of the clocked inverter 14. The output signal of the clocked inverter 14 is inverted again by the inverter 15. Therefore, a signal having the same level as that of N1 is output to the output section (N3) of the inverter 15. The output signal of the inverter 15 becomes the input signal of the subsequent stage, that is, the even stage. At this time, the clocked NAND 16 for inverting the output of the inverter 15 is inactive.

  On the other hand, in the even-numbered stage (2n stage; n is a natural number) of the data shift register 11, the clocked inverter 14 becomes inactive in synchronization with the rising edge of the clock signal CLK, and the same output part as the input part (N3) of the clocked inverter 14 The signal transmission path (N4) is blocked. As a result, the input from the odd-numbered stage of the previous stage is cut off. At this time, the clocked NAND 16 becomes active, but since the reset signal RST is at the level H, the clocked NAND 16 is equivalent to the inverter circuit 16a. Therefore, the output signal (N5) of the inverter 15 is inverted and output to the output section (N4) of the clocked NAND 16. The output signal of the clocked NAND 16 is inverted again by the inverter 15. Thus, a latch circuit is configured by the inverter 15 and the clocked NAND 16, and two stable states are maintained in the input unit (N4) and the output unit (N5) of the inverter 15. At this time, the levels immediately before the clocked inverter 14 becomes inactive, that is, immediately before the clock signal CLK rises, are held in the input section (N4) and the output section (N5) of the latch circuit.

  Next, the operation of the data shift register 11 when the clock signal CLK falls will be described.

  In the odd-numbered stages (2n-1 stages; n is a natural number) of the shift register, the clocked inverter 14 becomes inactive in synchronization with the rising edge of the clock inverted signal CLKB, that is, the falling edge of the clock signal CLK. The signal transmission path between the part (N1) and the output part (N2) is cut off. As a result, the input from the even-numbered stage in the previous stage is cut off. At this time, the clocked NAND 16 becomes active, but since the reset signal RST is at the level H, the clocked NAND 16b is equivalent to the inverter circuit 16a. Therefore, the output signal (N3) of the inverter 15 is inverted and output to the output section (N2) of the clocked NAND 16. The output signal of the clocked NAND 16 is inverted again by the inverter 15. As a result, the inverter 15 and the clocked NAND 16 constitute a latch circuit, and two stable states are maintained in the input section (N2) and the output section (N3) of the inverter 15. At this time, the levels immediately before the clocked inverter 14 becomes inactive, that is, immediately before the clock signal CLK falls, are held in the input section (N2) and the output section (N3) of the latch circuit.

  On the other hand, in the even number stage (2n stage; n is a natural number) of the data shift register 11, the clocked inverter 14 becomes active in synchronization with the rising edge of the clock inverted signal CLKB, that is, the falling edge of the clock signal CLK. At this time, the signal of the input section (N3) of the clocked inverter 14 is inverted and output to the output section (N4) of the clocked inverter 14. The output signal of the clocked inverter 14 is inverted again by the inverter 15. Therefore, a signal having the same level as that of N3 is output to the output section (N5) of the inverter 15. At this time, the signal of the input part (N3) of the clocked inverter 14 is latched at a previous odd-numbered stage (2n-1 stage; n is a natural number) and becomes a stable potential, so that the rising edge of the clock inverted signal CLKB At this timing, the information of the odd-numbered output section (N3) of the data shift register 11 is transferred to the even-numbered output section (N5). At this time, since the clocked NAND 16 for inverting the output of the inverter 15 is inactive, the latch operation is not performed. The signal of the output section (N5 = N1) of the inverter 15 becomes an input signal of the latter stage, that is, the odd stage (2n + 1 stage; n is a natural number), and is shifted to the subsequent stage at the rising timing of the next clock signal CLK. Become.

  As described above, since the timing at which signals are fetched and latched at the even and odd stages of the data shift register 11 are shifted by a half cycle of the clock signal CLK, the data shift register 11 is provided every half cycle of the clock signal CLK. The start pulse signal SP input to the first stage is sequentially shifted to the next shift register. That is, at the first half clock (timing of the rising edge of the clock signal CLK), the odd-numbered stage (2n-1 stage) latches the signal, and at the same timing, the clocked inverter 14 of the even-numbered stage (2n stage) is the odd-numbered stage of the preceding stage. A signal which is latched and stabilized at the stage (2n-1 stage) is transmitted. At the next half clock (falling clock signal CLK), the even stage (2n stage) latches the signal captured during the previous half clock, and the odd stage (2n + 1 stage) at the back stage transmits this signal at the same timing. To do. By repeating such an operation, signals are sequentially transferred at each stage of the data shift register 11.

  The two stages on the input side of the scan shift register 21 provided in the scan driver of FIG. 3, that is, the first and second stages, are a clocked inverter 24 ′ and an inverter 25 ′ that inverts the output of the clocked inverter, The inverter 25 ′, that is, the output to the subsequent stage of the shift register is combined with a clocked inverter 27 for inversion control. The output side of the inverter 25 ', that is, the input side of the clocked inverter 27 is connected to the high potential line VDD via the switching transistor Tr3 controlled by the input signal RST. The input side of the clocked inverter 24 ′ at the first stage of the shift register is connected to the low potential line VSS. The switching transistor Tr3 includes a PMOS TFT, and becomes active when the input signal RST is at the level L, and becomes inactive when the input signal RST is at the level H.

The third and subsequent stages of the scan shift register 21 have the same configuration as each stage of the data shift register 11, and a clocked inverter 24 that controls the reception of data from the previous stage and the output of this clocked inverter are inverted. The inverter 25 and the clocked NAND 16 for inversion control of the output of the inverter 25, that is, the output to the subsequent stage of the shift register, are combined in a single stage and connected in a plurality of stages. As shown in its circuit configuration, the clocked NAND 16 includes a clocked inverter 26a and reset signal input transistors Tr1 and Tr2. As an input signal to the clocked NAND 16 , an RST signal from a reset signal generation circuit (not shown) and an IN signal from the inverter 25 are input.

The scan shift register 21 includes terminals EP and EPB corresponding to the column selection end signal input means of the present invention, and column selection end signals EP and EPB having opposite phases corresponding to the row reference signal are input thereto. In the odd stages of the scan shift register 21, CLK is input to the clocked inverter 24, and CLKB is input to the clocked NAND 16 and the clocked inverter 27. At even stages, CLKB is input to the clocked inverter 24, and CLK is input to the clocked NAND 16 and the clocked NAND 27. Therefore, the operation timings of the even and odd stages of the scan shift register 21 are opposite to each other.

When the input signal RST for Tr3 and the clocked NAND 16 is at level L, the switching transistor Tr3 becomes active in the first two stages located on the input side of the scan shift register 21. When Tr3 becomes active, the input part of the clocked inverter 27 and the output part of the inverter 25 ′ in the two stages on the input side of the scan shift register 21 are close to VDD. Therefore, the two stages on the input side of the scan shift register 21 output level H regardless of EP and EPB. On the other hand, after the third stage of the scan shift register 21, the transistor Tr2 of the clocked NAND 16 is inactive and the transistor Tr1 is active. As a result, the output voltage of the clocked NAND 16 becomes close to the high potential VDD, and the clocked NAND 16 outputs the level H regardless of the input signal IN. At this time, since the output H of the clocked NAND 16 is inverted by the inverter 15, the outputs (N3, N5) of the third and subsequent stages of the scan shift register 21 are all at the level L.

When the input signal RST for Tr3 and the clocked NAND 16 is at level H, the transistor Tr3 is inactive, the transistor Tr2 is active, and the transistor Tr1 is inactive. In this case, the clocked NAND 16 is equivalent to a circuit including only the clocked inverter 26a. Accordingly, the scan shift register 21 performs the normal shift register operation similar to the data shift register 11 described above.

  Next, a description will be given of a series of driving operations from the non-operating state immediately after power-on to the resetting operation and the fingerprint detection in the electrostatic capacitance fingerprint sensor 1. FIG. 7 is a timing chart of the data driver 10 and the scan driver 20.

In the data driver 10, the reset signal RST is set to the level L immediately after the power is turned on. As a result, the outputs of all the clocked NANDs 16 included in the data shift register 11 constituting the data driver 10 become level H. As a result, all outputs of each stage of the shift register become level L. Thereby, all the analog switches 13 that control the connection between the global data line 70 and each data line 33 become non-conductive. When this reset operation is completed, unnecessary initial current is suppressed, and subsequent stable operation becomes possible.

  When the reset signal RST is set to the level H, the data shift register 11 constituting the data driver 10 performs a normal shift register operation. When the level H start pulse signal SP is input to the data shift register 11, both the input part of the clocked inverter 14 and the output part of the inverter 15 become the level H in the first stage of the data shift register 11. This state shifts to the next stage every half cycle of the clock signal CLK and the clock inverted signal CLKB. The data shift register 11 is provided with a NAND circuit 18 whose input terminals are connected to the input section of the clocked inverter 14 and the output section of the inverter 15, respectively. Therefore, the NAND circuit 18 latches the start pulse signal SP transferred from the previous stage, and outputs the level L when both the input part of the clocked inverter 14 and the output part of the inverter 15 become the level H. The output of the NAND circuit 18 is inverted to the level H by the inverter 19, and after the drive capacity is increased by the buffer 12, the output XSEL {n; n is a natural number} controls the conduction between the data line 33 and the amplifier circuit 40. Connected to the analog switch 13. When the start pulse signal SP is sequentially transferred to the data shift register 11, the analog switch 13 is sequentially activated every half cycle of the clock signal CLK. As a result, the data lines 33 are sequentially selected, data of each capacitance detection circuit 31 is acquired, and a fingerprint detection operation is performed.

  The output of the last stage of the data shift register 11, that is, the data driver end signal EP corresponding to the column selection end signal of the present invention and its inverted signal EPB are not connected to the active matrix portion but are sent to the shift register of the scan driver 20. Output as a reference signal.

Also in the scan driver 20, the reset signal RST is set to the level L immediately after the power is turned on. As a result, both DMA and DMB, which are the two outputs on the input side of the scan shift register 21 constituting the scan driver 20, become H, and the outputs of all clocked NANDs 26 included in the third and subsequent stages of the scan shift register 21. Certain {m} A and {m} B (m is a natural number) are at level L. The scanning shift register 21 is provided with a NAND circuit 28 whose input terminals are connected to the odd-numbered stage (2m-1 stage) output and the even-numbered stage (2m stage) output of the scanning shift register 21, respectively. . The output of the NAND circuit 28 is increased in drive capability by the inverter 29 and output as YSEL {DM}, YSEL {m}. Here, YSELDM is at the level H because it is the logical product of DMA and DMB, which is the output from the previous two stages of the scan shift register 21, but is not connected to the active matrix section. On the other hand, YSEL {n: n is a natural number}, which is the logical product negation of the outputs {nA} and {nB} after the third stage in the scan shift register 21, is all at the level L. Since these are connected to the scanning lines 32 of the active matrix portion, all the potentials of the scanning lines 32 are at level L, and all the selection transistors 35 that control the connection between the data lines 33 and the capacitance detection circuits 31 are all. Become inactive. When this reset operation is completed, unnecessary initial current is suppressed, and subsequent stable operation becomes possible.

  When the reset signal RST is set to the level H, the scan shift register 21 constituting the scan driver 20 performs a normal shift register operation. At this time, the data driver end signal EP and its inverted signal EPB serve as a signal transfer reference signal. That is, after the reset operation, the level H is held in the two stages on the input side of the scan shift register 21 until the first EP is input, and this state is successively performed at the timing of the rise and fall of the EP. To the next stage. Since the input side of the shift register is connected to the low-potential power supply line VSS, the two stages on the input side always keep transferring the level L when EP and EPB are operating. As a result, the scanning line YSEL {n: n is a natural number} sequentially becomes the level H, and the scanning lines 32 are selected one by one to perform the fingerprint detection operation.

  FIG. 4 is a circuit configuration diagram of a capacitance detection circuit 31 that converts unevenness information of a subject's fingerprint into an electrical signal. The detection circuit 31 is based on a selection transistor 35 for selecting the detection circuit 31, a capacitance 36 formed between the fingertip of the subject and the sensor electrode, and a minute capacitance change of the capacitance 36. A signal output element 37 for outputting a detection signal carrying the unevenness information of the fingerprint, a scanning line 32 for transmitting a signal for controlling opening and closing of the selection transistor 35, a data line 33 for transmitting a detection signal, and detection A low-potential power supply line VSS that forms a signal output path, a reference capacitor Cs having a constant capacitance value, and a reset transistor 38 are included. When the capacitance value of the capacitance 36 is Cd, the detection capacitance Cd is determined according to the distance between the unevenness of the fingerprint of the subject and the sensor electrode (see FIG. 6). The signal output element 37 is not particularly limited as long as it is an element that outputs a detection signal corresponding to the detection capacitor Cd. However, the signal output element 37 is a signal amplification element (current amplification) that performs a current amplification operation according to the size of the detection capacitor Cd. Element). As such a signal amplifying element, in the present embodiment, a three-terminal transistor including a gate terminal (current control terminal), a source terminal (current output terminal), and a drain terminal (current input terminal) is exemplified. It is not limited.

で表される。即ち、信号出力素子３７自体の寄生容量Ｃｔと、基準容量Ｃｓと、検出容量Ｃｄとのそれぞれの容量比によって定まる。例えば、被験者の指先をセンサ電極に近づけた場合に、指紋の凸部がセンサ電極に近接すると、検出容量Ｃｄは寄生容量Ｃｔ、基準容量Ｃｓに対して十分に大きくなり、信号出力素子３７のゲート電位はグランド電位に近づく。この結果、信号出力素子３７は略オフ状態となり、信号出力素子３７のソース／ドレイン間には極めて微弱な電流が流れる。一方、指紋の凹部がセンサ電極に近接すると、検出容量Ｃｄは寄生容量Ｃｔ、基準容量Ｃｓに対して十分に小さくなり、信号出力素子３７のゲート電位は走査線３２の電位に近づく。走査線３２がアクティブとなっている状態では、走査線３２の電位は高電位ＶＤＤである。この結果、信号出力素子３７は略オン状態となり、信号出力素子３７のソース／ドレイン間には上述の微弱電流よりも大きな電流が流れる。ここで、信号出力素子３７のソース端子は低電位電源線ＶＳＳに接続しているため、信号出力素子３７を流れる検出電流の向きはデータ線３３から低電位電源線ＶＳＳへ流れ込む向きとなる。つまり、被験者の指紋の凹凸情報を担う検出信号は外部回路から静電容量検出回路３１へ流れ込むように出力される。 In the above configuration, when a logic level H signal is output on the scanning line 32 and the selection transistor 35 is opened, a detection current determined by the gate potential of the signal output element 37 flows through the data line 33. This detection current is processed as a detection signal corresponding to the detection capacitor Cd. The detection signal includes fingerprint unevenness information. The gate potential of the signal output element 37 is

It is represented by That is, it is determined by the respective capacitance ratios of the parasitic capacitance Ct of the signal output element 37 itself, the reference capacitance Cs, and the detection capacitance Cd. For example, when the fingertip of the subject is brought close to the sensor electrode and the convex portion of the fingerprint is close to the sensor electrode, the detection capacitance Cd becomes sufficiently larger than the parasitic capacitance Ct and the reference capacitance Cs, and the gate of the signal output element 37 The potential approaches the ground potential. As a result, the signal output element 37 is substantially turned off, and a very weak current flows between the source / drain of the signal output element 37. On the other hand, when the concave portion of the fingerprint is close to the sensor electrode, the detection capacitance Cd becomes sufficiently smaller than the parasitic capacitance Ct and the reference capacitance Cs, and the gate potential of the signal output element 37 approaches the potential of the scanning line 32. When the scanning line 32 is active, the potential of the scanning line 32 is the high potential VDD. As a result, the signal output element 37 is substantially turned on, and a current larger than the above-described weak current flows between the source / drain of the signal output element 37. Here, since the source terminal of the signal output element 37 is connected to the low-potential power line VSS, the direction of the detection current flowing through the signal output element 37 is the direction from the data line 33 to the low-potential power line VSS. That is, the detection signal carrying the unevenness information of the subject's fingerprint is output so as to flow into the capacitance detection circuit 31 from the external circuit.

  Note that, by connecting the source terminal of the signal output element 37 to the high-potential power supply line VDD, a current may flow in a direction that flows from the capacitance detection circuit 31 to the data line 33.

  The reset transistor 38 is controlled to be opened and closed at a stage (pre-sensing period) when the previous-stage capacitance detection circuit 31 is selected. By opening the reset transistor 38, the gate terminal of the signal input terminal 37 becomes conductive with VSS, and the charge injected into the gate terminal can be discharged. In the manufacturing process of the capacitive fingerprint sensor, there is a possibility that unintended charges are injected into the gate terminal of the signal output element 37 to adversely affect the detection of fingerprint information. Since the gate potential of the signal output element 37 can be reset before the detection of fingerprint information, a more stable operation can be performed.

  In the stage where the signal detection element 34 is opened and the detection signal is output to the data line 37 (sensing period), the reset transistor 38 is closed in order to accurately read the detection capacitor Cd. Controlled.

FIG. 5 is a circuit configuration diagram of the amplifier circuit 40 that amplifies the detection signal of the capacitance detection circuit 31. The amplifier circuit 40 includes a front-stage current mirror circuit 41 and a rear-stage current mirror circuit 42. In the previous stage current mirror circuit 41, the constant reference current Iref output from the MOS transistor 41a whose gate potential is held at the reference voltage VR is compared with the detection current Idat output from the capacitance detection circuit 31, and the subsequent stage current mirror circuit 41 compares the detected current Idat. The current mirror circuit 42 outputs a signal OUT obtained by amplifying the difference between the reference current Iref and the detection current Idat. The reference current Iref is set in advance so as to be approximately halfway between the maximum value and the minimum value of the detection current Idat. By comparing a predetermined threshold value determined in advance with the signal level of the signal OUT, fingerprint information composed of binary data can be obtained.

  In the figure, the CLK signal is the same as the pulse signal input to the data shift register 11 and is synchronized with the switching timing of the analog switch 12.

  FIG. 6 is a cross-sectional structure diagram of the capacitance detection circuit 31 centering on the sensor electrode. As shown in the figure, the capacitance detection circuit 31 is provided with a capacitance 36 between the signal output element 37 that outputs a detection signal carrying the unevenness information of the fingerprint and the fingertip F of the subject. A sensor electrode (detection electrode) 71 is formed. The signal output element 37 is a MOS transistor including a gate electrode 70, a gate insulating film 68, a polycrystalline silicon layer 63, and source / drain electrodes 69. The capacitance 36 is a variable capacitance whose capacitance value changes according to the concave / convex pattern of the fingerprint. The potential of the fingertip F is set to the reference potential. The sensor electrode 71 is connected to the gate electrode 70 and is configured to transmit a change in the detection capacitance Cd due to the fingerprint unevenness to the signal output element 37 and to sense a change in capacitance by an amplifying action of the drain current flowing through the channel. Has been.

  In order to manufacture the capacitance detection circuit 31 shown in the figure, a base insulating film 62 such as silicon oxide is laminated on an insulating substrate 61, and amorphous silicon is formed thereon to be crystallized. A silicon layer 63 is formed. Next, a gate insulating film 68 and a gate electrode 70 are formed on the polycrystalline silicon layer 63, and impurities are implanted and diffused into the polycrystalline silicon layer 63 in a self-aligning manner to form source / drain regions. Next, after forming the first interlayer insulating film 64, contact holes are opened and source / drain electrodes 69 are formed. Further, the second interlayer insulating films 65 and 66 are stacked to open a contact hole, and a sensor electrode 71 is formed. Finally, the entire surface is covered with a passivation film 67. Here, the reason why the second interlayer insulating films 65 and 66 have a two-layer structure is that the lower second interlayer insulating film 65 ensures flatness and the upper second interlayer insulating film 66 has a desired film thickness. However, a single layer structure may be used.

  In order to form a semiconductor element such as a transistor on the insulating substrate 61, not limited to the above-described manufacturing method, for example, Japanese Patent Laid-Open No. 11-312811 and S. Utsunomiya et. Al. Society for Information Display p. A semiconductor element such as a transistor may be formed on the insulating substrate 61 by applying the peeling transfer technique disclosed in (2000). If the peeling transfer technique is applied, an inexpensive substrate having an appropriate strength such as a plastic substrate or a glass substrate can be adopted as the insulating substrate 61, so that the mechanical strength of the capacitive fingerprint sensor 1 can be increased. .

  Next, an application example of the capacitive fingerprint sensor 1 will be described. FIG. 8 shows a block diagram of the smart card 81, which comprises the above-described capacitive fingerprint sensor 1, an IC chip 82 mounted with a CPU, a memory element, and the like, and a display device 83 such as a liquid crystal display. ing. In the IC chip 82, fingerprint information of the cardholder is registered as biometric information.

  FIG. 9 shows an authentication procedure of the smart card 81. When the card user touches the fingertip with the fingerprint sensor 1 and fingerprint information is input to the smart card 81 (step S1), the fingerprint information is checked against previously registered fingerprint information (step S2). Here, if the fingerprints match (step S2; YES), a personal identification number is issued (step S3). Next, a password is entered by the cardholder (step S4). It is checked whether or not the password issued in step S3 and the password entered in step S4 match (step S5). If they match (step S5; YES), the card is used. Is permitted (step S6).

  In this way, a smart card with high security can be provided by authenticating the person using fingerprint information in addition to the personal identification number. A smart card with a biometrics authentication function can be used for cash cards, credit cards, identification cards, etc. The fingerprint sensor of the present embodiment can be applied to any biometric authentication device for performing personal authentication. For example, as a security system for managing entry / exit into the room, the fingerprint sensor of this embodiment is attached to the door, and the fingerprint information of the occupant input to the fingerprint sensor is compared with the fingerprint information registered in advance, If the two match, the entry is permitted, while if the two do not match, the entry is not permitted and the system can be applied to a security company or the like as necessary. The fingerprint sensor of the present embodiment can also be effectively applied as a biometric authentication device for identity verification in electronic commerce through an open network such as the Internet. Further, the present invention can be widely applied to a user authentication device for a computer terminal device and a management device for a copying machine user of a copying machine.

  In the above description, the fingerprint sensor is illustrated as an embodiment of the capacitance detection device of the present invention. However, the present invention is not limited to this, and the minute uneven pattern of any test object can be changed to the capacitance. It can be applied to devices that read changes. For example, it can be applied to recognition of animal noseprints.

The block diagram of the electrostatic capacitance type fingerprint sensor of 1st embodiment. A data driver for the fingerprint sensor. A scanning driver for the fingerprint sensor. The electrostatic capacitance detection circuit of 1st embodiment. The circuit block diagram of the amplifier circuit of the said fingerprint sensor. FIG. 3 is a cross-sectional structure diagram of a capacitance detection circuit 31. 4 is a timing chart of a data driver and a scanning driver of the fingerprint sensor. An application example with a capacitive fingerprint sensor. The flowchart which shows an authentication procedure. The block diagram of the conventional active matrix drive device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Capacitance type fingerprint sensor 10 ... Data driver (row selection means) 11 ... Data shift register 12 ... Analog switch 20 ... Scan driver (column selection means) 30 ... Active matrix part 31 ... Capacitance detection circuit 32 ... Scanning Line 33 ... Data line 34 ... Low-potential power supply line VSS 35 ... Selection transistor 36 ... Capacitance 37 ... Signal output element 38 ... Reset transistor 70 ... Global data line Cs ... Reference capacitance Cd ... Detection capacitance Ct ... Gate capacitance VSS ... Low-potential power line VDD ... High-potential power line

Claims (5)

In a matrix device in which M row lines and N column lines, and functional elements provided at intersections of the row lines and the column lines are arranged in a matrix of M rows and N columns,
The matrix device includes : a row selection unit that selects a specific row line from M row lines; a column selection unit that selects a specific column line from N column lines; the column selection unit and the row selection unit; And deselecting means for switching to a non-selected state ,
It said column selecting means includes column selection end signal output means for outputting the column selection end signal,
It said row selecting means includes a column selection end signal input means for providing a row reference signal when said column selection end signal selects a particular row line is input, a plurality of output stage the line reference signal is input A scan shift register having,
The scan shift register selects a specific row line by selecting a specific stage from the plurality of output stages, and the specific output stage selected by the input row reference signal is advanced by one stage. And
The deselecting means supplies a reset signal to each stage of the scan shift register, and at least two stages on the input side of the scan shift register are selected by the reset signal, and the other stages are not selected. Matrix device, characterized in that it is configured as described above. 2. The matrix device according to claim 1, wherein the specific output stage is selected for each cycle of the row reference signal. 2. The matrix device according to claim 1, wherein at least two outputs on the input side of the scanning shift register selected by the reset signal are not connected to a functional element. The matrix device according to claim 1, wherein the functional element is formed of a MIS thin film semiconductor. An electronic apparatus comprising the matrix device according to any one of claims 1 to 4.

Images