JP4339813B2 - Voltage-controlled semiconductor device - Google Patents

Description

  The present invention relates to a power semiconductor device that controls a large current, and more particularly to a voltage-controlled semiconductor device having a high withstand voltage.

As a conventional semiconductor device for controlling a large current, a power semiconductor device made of Si (silicon) is used. However, it is difficult to significantly improve the performance due to the limit of the electrical and physical characteristics of Si. ing. Therefore, development of power semiconductor devices using a wide gap semiconductor material, which has superior electrical and physical characteristics compared to Si, has been underway. A typical example of the wide gap semiconductor material is SiC (silicon carbide) having an energy gap of 2.9 to 3.2 eV. A conventional example of a semiconductor device using this SiC is shown in FIGS. FIG. 16 is a cross-sectional view of an SiC accumulation type field effect transistor (ACCUFET), which is disclosed, for example, in the document IEEE Electron Device Letters, Vol. 18, No. 12, December 1997. FIG. 17 is a cross-sectional view of a SiC static induction transistor, which is disclosed in the document Proceedings of IEEE International Symposium on Power Semiconductor Devices and ICs, p.149, 1997.
JP 59-52882 JP 53-50684 JP 3-198382 JP-A-6-224213 JP-A-6-125075 JP 2000-216407 A

  The SiC storage type field effect transistor shown in FIG. 16 has an excellent function of being able to turn off the source S and the drain D even when the gate G voltage is zero. However, because of the MOS gate structure, a large amount of leakage current is generated when the gate insulating film 104 is broken with high electric field strength. For this reason, there is a problem that it is impossible to realize a high breakdown voltage utilizing the high dielectric breakdown electric field inherent to SiC, which is a wide gap semiconductor, and the conventional breakdown voltage is only about 1 kV or less.

  The SiC static induction transistor shown in FIG. 17 cannot be turned off unless a high reverse voltage is applied to the gate G. That is, there is a problem that a high off breakdown voltage cannot be realized with a low reverse voltage. In the example shown in FIG. 17, it is necessary to apply a reverse voltage of 80 V or more to the gate G in order to realize an off breakdown voltage of 5 kV. For this reason, even when the SiC electrostatic induction transistor is not driven, a high voltage for the gate G of about 100 V must be generated, resulting in a problem that the power consumption of the gate circuit increases.

  Regarding the on-resistance, since the SiC storage field effect transistor shown in FIG. 16 has a MOS gate structure, an incomplete crystal structure exists at the interface between the gate insulating film 104 and the SiCn channel region 103. Therefore, there is a problem that the channel mobility of the channel region 103 serving as a current path cannot be increased and the on-resistance is high. In the SiC static induction transistor shown in FIG. 17, since the channel 112A between the gate regions 109 and 110 serving as a current path exists in the bulk crystal of the n-type drift region 112, the voltage of the gate G is lowered and increased. In order to achieve the withstand voltage, the channel 112A has to be made extremely narrow, resulting in a problem that the on-resistance becomes extremely high.

Furthermore, regarding noise, since the SiC storage field effect transistor of FIG. 16 has a MOS gate structure, an incomplete crystal structure exists at the interface between the gate insulating film 104 and the SiCn channel region 103. For this reason, there is a problem that noise is generated due to scattering of electrons at the interface.
In addition, a device constituted by using these transistors has a problem that efficiency is low because the power consumption of the transistors is large, and a cooling facility such as water cooling or air cooling is increased in size.

An object of the present invention is to provide a voltage control semiconductor device having a high breakdown voltage, a low on-resistance and a low noise. In particular, it is an object to provide a semiconductor device that can achieve a high breakdown voltage with a gate voltage of zero (normally-off type) or a low voltage, targeting a wide gap semiconductor device .

The voltage controlled semiconductor device of the present invention is
A drift layer of any one of the first conductivity type and the second conductivity type having a low impurity concentration formed on the semiconductor substrate;
In the internal region including the surface of the drift layer, a plurality of buried voltage control gate semiconductor regions having a conductivity type different from that of the drift layer formed at intervals from each other ,
An active region having the same conductivity type as the drift layer formed on the surface of the central region of the drift layer including the upper surface of each of the plurality of buried voltage control gate semiconductor regions, and having a thickness smaller than that of the drift layer;
A gate contact semiconductor region having a conductivity type different from that of the drift layer, which is in contact with a part of an upper surface of each of the embedded voltage control gate semiconductor regions and formed in an internal region including a surface of the active region;
An internal region including the surface of the active region, located between the gate contact semiconductor region, and formed in the region located on the top of each of the buried voltage controlled gate semiconductor region, the same conductivity as said drift layer Two first semiconductor regions of the mold,
A first electrode formed in the first semiconductor region;
A surface voltage control gate semiconductor region having a conductivity type different from that of the drift layer formed on the surface of the active region;
A gate electrode formed in the surface voltage control gate semiconductor region; and at least a second electrode formed on an opposite surface of the semiconductor substrate having the drift layer;
The first semiconductor region is configured such that the surface thereof is at a lower position than the surface of the surface voltage control gate semiconductor region, and the end portions of both are at the same position.

A voltage-controlled semiconductor device according to another aspect of the present invention includes:
A semiconductor substrate having a high impurity concentration of the first conductivity type;
A drift layer of a first conductivity type having a low impurity concentration formed on the semiconductor substrate;
A plurality of buried voltage control gate semiconductor regions of the second conductivity type formed at intervals in an internal region including the surface of the drift layer;
An active region of a first conductivity type including a top surface of each of the plurality of buried voltage control gate semiconductor regions and formed on a surface of a central region of the drift layer, wherein the thickness is smaller than that of the drift layer;
A gate contact semiconductor region of a second conductivity type formed in an internal region in contact with a part of the upper surface of each of the embedded voltage control gate semiconductor regions and including the surface of the active region;
An internal region including a surface of the active region , the first conductivity type formed in a region located between the gate contact semiconductor regions and located above each of the buried voltage control gate semiconductor regions Two source regions,
A source electrode formed in the source region;
A surface voltage control gate semiconductor region of a second conductivity type formed on the surface of the active region;
A gate electrode formed in the surface voltage control gate semiconductor region, and a drain electrode formed on a surface of the semiconductor substrate opposite to the surface having the drift layer,
The source region is configured such that the surface thereof is at a position lower than the surface of the surface voltage control gate semiconductor region, and both end portions thereof are at the same position.

  As described above, the surface voltage control gate semiconductor region and the buried voltage control gate semiconductor region above and below the thin active layer are composed of semiconductor regions having the opposite polarity to the active region, and the surface of the source region is the surface voltage. A high breakdown voltage can be realized by configuring the control gate at a position lower than the control gate. In particular, by forming the surface voltage control gate semiconductor region with a wide gap semiconductor material, a high breakdown voltage corresponding to a high breakdown electric field can be realized. By forming the surface of the source region at a position lower than the surface voltage control gate semiconductor region, the contact portion between the source region and the semiconductor region constituting the surface voltage control gate semiconductor region is reduced, and the electric field is reduced. Is alleviated, so that a higher breakdown voltage can be obtained.

In the voltage control type semiconductor device of the present invention, a surface voltage control gate semiconductor region is provided on the upper surface of a thin active region, and a buried voltage control gate semiconductor region having a current path is provided at the center of the lower surface of the active region. By forming source regions at both ends of the thin active region, the surface and bottom surfaces of which are lower than the surface voltage control gate semiconductor region and the ends are at the same position, high withstand voltage, low on-resistance and low noise The voltage controlled semiconductor device can be realized.
Further, by forming the surface voltage control gate semiconductor region first, the source region can be formed by self-alignment, and mass productivity is improved.

  Hereinafter, a preferred embodiment of the present invention will be described with reference to FIGS.

<< First Example >>
FIG. 1 is a sectional view of a segment of a SiC junction field effect transistor having a breakdown voltage of 5 kV according to the first embodiment of the present invention. This segment has a long stripe shape in a direction perpendicular to the paper surface of FIG. The structure in which a plurality of segments constituting a large capacity SiC junction field effect transistor are connected by forming a plurality of these segments in the left-right direction in FIG. 1 is the same in the second to ninth embodiments. It is. In FIG. 1, a low impurity concentration n-type SiC drift layer 2 having a thickness of about 50 μm is formed on a drain region 1 of high impurity concentration n-type SiC having a thickness of about 350 μm. As shown in FIG. 2, which is a cross-sectional view taken along the line II-II of FIG. 1, rectangular p-type SiC buried voltage control gate semiconductor regions 5 are formed in both end regions except for the central portion of the upper surface of the drift layer 2. The optimum value of the thickness is 0.7 μm, but it may be in the range of 0.3 μm to 3.0 μm. An n-type active region 3 is formed on the upper surface of the buried voltage control gate semiconductor region 5 and the exposed portion of the drift layer 2, and the optimum thickness is about 0.7 μm. The thickness of the active region 3 may be in the range of 0.2 μm to 3.0 μm. At both ends of the surface region of the active region 3, n-type SiC source regions 4 connected to the source electrode 22 are formed, and the thickness thereof is 0.2 μm. It may be about 5 μm. A p-type surface voltage control gate semiconductor region 7 is formed on the n-type active region 3. Its thickness is about 0.3 μm.

  The junction surface between the n-type source region 4 and the n-type active region 3 is located closer to the drain region 1, which is lower than the junction surface between the p-type surface voltage control gate semiconductor region 7 and the n-type active region 3. The p-type buried voltage control gate semiconductor region 5 desirably protrudes from the n-type source region 4 to the center by about 1 μm, but it only needs to protrude 0.5 μm or more. The distance between the p-type buried voltage control gate semiconductor regions 5 on both sides is optimally 2 μm, but may be 1 μm to 5 μm. A p-type gate contact semiconductor region 6 is formed in an end region on the p-type buried voltage control gate semiconductor region 5, and the buried voltage control gate semiconductor region 5 and the p-type surface voltage control formed thereon. The gate semiconductor region 16 is connected. The gate contact semiconductor region 6 may be separated from the source region 4 by a predetermined distance as shown in FIG. 3, or may be in contact with the source region 4 as shown in FIG. Further, one side may be in contact and the other side may be separated. The embedded voltage control gate semiconductor region 5 and the gate contact semiconductor region 6 may be in the form of a strip that is continuous in the direction perpendicular to the drawing sheet. A gate electrode 23 is provided in the surface voltage control gate semiconductor region 16. A gate electrode 23 is provided in the p-type surface voltage control gate semiconductor region 7 formed on the n-type active region 3 excluding the n-type source region 4. It is desirable to provide a protective layer 70 on the surface. In the present embodiment, the shape of the SiC junction field effect transistor is a stripe shape that is long in the direction perpendicular to the paper surface, but the shape may be, for example, a circle or a rectangle.

An example of a method for manufacturing the junction field effect transistor of this example will be described with reference to the cross-sectional views of FIGS.
As shown in FIG. 5A, first, an n-type drift layer 2 having a thickness of about 50 μm is formed on an n-type SiC substrate having a thickness of about 350 μm functioning as the n-type drain region 1 by an epitaxial growth method or the like. Form. Next, as shown in FIG. 5B, the p-type buried voltage control gate semiconductor region 5 is formed by ion implantation of aluminum or the like except for the central portion of the drift layer 2. Further, as shown in FIG. 5C, a thin n-type active region 3 is formed on the central portion of the drift layer 2 and the buried voltage control gate semiconductor region 5. Then, as shown in FIG. 5D, the p-type gate contact semiconductor region 6 reaching the p-type buried voltage control gate semiconductor region 5 is formed at both ends by an aluminum ion implantation method or the like. A thin p-type surface voltage control gate semiconductor region 7 is formed thereon by a thin film formation method such as an epitaxial growth method.

  Next, a mask is formed on the p-type surface voltage control gate semiconductor region 7 and etched by the photolithography technique, so that the surface voltage control gate semiconductor regions 7 and 16 having a predetermined shape are formed as shown in FIG. Get. By self-alignment using the surface voltage control gate semiconductor regions 7 and 16 as a mask, as shown in FIG. 6B, the n-type source region 4 is formed by an ion implantation method such as nitrogen or a diffusion method. The n-type source region 4 is not necessarily in contact with the p-type gate contact semiconductor region 6. Finally, as shown in FIG. 6C, the gate electrode 23 is formed on the p-type surface voltage control gate semiconductor regions 7 and 16. A source electrode 22 is formed on the n-type source region 4. Further, the drain electrode 21 is formed in the n-type drain region 1 to complete.

  In the SiC junction field effect transistor of the present embodiment, when the potential of the drain D is higher than the potential of the source S and the potential between the gate G and the source S is 0 V, the p-type buried voltage control gate semiconductor region 5 and the p A depletion layer corresponding to a built-in voltage spreads from the junction between the n-type surface voltage control gate semiconductor region 7 and the n-type active region 3 in contact with these regions, so that the n-type active region 3 can be pinched off. As a result, the current between the source S and the drain D can be cut off and normally off. Since the surface of the n-type source region 4 is formed at a position lower than the surface of the p-type surface voltage control gate semiconductor region 7, the contact portion between the n-type source region 4 and the p-type surface voltage control gate semiconductor region 7 is Less. This connection portion is a portion having a high electric field, but by reducing this, the high electric field portion can be reduced, and a high-breakdown-voltage SiC junction field effect transistor can be realized.

  The potential of the drain D is made higher than the potential of the source S, and a voltage equal to or lower than the built-in voltage with respect to the source S is applied to the gate G. As a result, the depletion layer in the n-type active region 3 between the p-type buried voltage control gate semiconductor region 5 and the p-type surface voltage control gate semiconductor region 7 becomes narrow. A current flows from the drain between both the p-type buried voltage control gate semiconductor regions 5, flows into the source S through the n-type active region 3. In this embodiment, since the n-type source region 4 is formed in the n-type active region 3 by self-alignment, the end portion of the p-type surface voltage control gate semiconductor region 7 and the end portion of the n-type source region 4 indicated by an arrow J Is different, and there is no n-type semiconductor region between both ends. Thereby, the resistance of the vertical wall surface portion in contact with the n-type active region 3 in the n-type source region 4 is reduced, and the on-resistance is lowered. If the n-type semiconductor region exists, the inventor has found that it becomes a noise source. By eliminating the n-type semiconductor region, the noise can be reduced. Further, the bottom surface of the n-type source region 4 in contact with the n-type active region 3 is positioned lower than the bottom surface of the p-type surface voltage control gate semiconductor region 7, so that the n-type semiconductor region under the n-type source region 4 is The thickness can be reduced, and the on-resistance can be further reduced and noise can be reduced.

  The breakdown voltage of the junction field effect transistor of this embodiment is about 5.5 kV. The on-resistance was a very low value of about 75 mΩcm 2 when the gate voltage was 2.5V. Noise was also a very low value of 10-9V2 / Hz or less. Further, since the gate voltage of the gate G is set to a value equal to or lower than the built-in voltage (about 2.5 V in SiC), only the current due to the capacity of the depletion layer flows through the gate G, and the driving power can be kept low. Even if the transistor is not normally off due to the thickness or impurity concentration of the n-type active region 3, the p-type buried voltage control gate semiconductor region 5, the p-type surface voltage control gate semiconductor region 7, and the n-type active region 3 with a small gate voltage. The depletion layer spreads from the junction. As a result, the n-type active region 3 is pinched off, and a high breakdown voltage can be realized while driving power is kept low.

  In this embodiment, by forming the n-type source region 4 by self-alignment, there is no n-type semiconductor region between the end of the p-type surface voltage control gate semiconductor region 7 and the end of the n-type source region 4. As a result, low on-resistance and low noise can be achieved simultaneously, and high mass productivity can be obtained. Further, the processes of FIG. 5C and FIG. 5D may be reversed. The manufacturing method can be variously modified without impairing the essence of the present invention.

<< Second Embodiment >>
FIG. 7 is a sectional view of a segment of a junction field effect transistor according to the second embodiment of the present invention. In FIG. 7, the junction field effect transistor of the second embodiment is configured such that the n-type source region 4 penetrates the n-type active region 3 and its bottom surface is in contact with the p-type buried voltage control gate semiconductor region 5. ing. Therefore, the n-type active region 3 does not exist between the n-type source region 4 and the p-type buried voltage control gate semiconductor region 5. Since the other configuration is the same as that of the first embodiment, a duplicate description is omitted. If the active region 3 is present between the n-type source region 4 and the p-type buried voltage control gate semiconductor region 5, thermal noise is generated. In this embodiment, however, there is no active region 3 between the two as described above. No noise was generated and further noise reduction was achieved. Further, since the volume of the n-type source region 4 is large, the source resistance is also reduced, and the on-resistance is further reduced. The breakdown voltage of the junction field effect transistor of this example is about 5.3 kV. The on-resistance was about 65 mΩcm 2 when the gate voltage was 2.5 V, which was a low value. Noise was also a very low value of 4 × 10 −10 V 2 / Hz or less.

<< Third embodiment >>
FIG. 8 is a sectional view of a segment of the SiC junction field effect transistor according to the third embodiment of the present invention. In this embodiment, a p-type second buried voltage control gate semiconductor region 8 is provided between both adjacent p-type buried voltage control gate semiconductor regions 5 of the junction field effect transistor of the second embodiment shown in FIG. ing. There may be a plurality of such areas. As shown in the sectional view (b) of FIG. 8A, the second buried voltage control gate semiconductor region 8 is partially connected by the p-type buried gate semiconductor region 5 and the p-type region 8A as shown in the figure. Yes. The other configuration is the same as that of the second embodiment, and thus a duplicate description is omitted. When turned off, a depletion layer extends from the junction between the second buried voltage control gate semiconductor region 8 and the n-type drift layer 2 in the direction of the p-type buried voltage control gate semiconductor region 5 and the drain region 1. Thereby, the breakdown voltage of the SiC junction field effect transistor can be increased. When on, there are a plurality of channels serving as current paths between the second buried voltage control gate semiconductor region 8 and the p-type buried voltage control gate semiconductor region 5, so that the on-resistance decreases. In this example, the withstand voltage was 6.2 kV and the on-resistance was 78 mΩcm 2.

<< 4th Example >>
FIG. 9 is a sectional view of a segment of a SiC static induction transistor according to the fourth embodiment of the present invention. In this embodiment, the width of the active region 3 sandwiched between the p-type surface voltage control gate semiconductor region 7 and the p-type buried voltage control gate semiconductor region 5 of the junction field effect transistor shown in FIG. 7 of the second embodiment is reduced. To do. As the width of the active region 3 decreases, the width of the segment in the horizontal direction also decreases. Further, the withstand voltage can be improved by narrowing the interval between the two buried voltage control gate semiconductor regions 5 facing each other. Alternatively, the current can be cut off even with a low gate voltage. By reducing the width of the active region 3, the resistance of the active region 3 is reduced.

  In the junction field effect transistor, when a current flows through the active region 3 when it is turned on, the potential at the center of the active region 3 increases in proportion to the resistance of the region. When the flowing current increases, the potential further increases, and the p-type surface voltage control gate semiconductor region 7 and the p-type buried voltage control gate semiconductor region 5 are reverse-biased. A channel is narrowed and current is saturated. However, if the width of the active region 3 sandwiched between the p-type surface voltage control gate semiconductor region 7 and the p-type buried voltage control gate semiconductor region 5 is reduced and the resistance is reduced as in this embodiment, the central portion of the active region 3 is reduced. Therefore, the depletion layer does not spread to the channel, so that an on-state current saturation does not occur. In the structure of this embodiment, since the channel resistance is small, the ratio of the source resistance to the entire resistance between the source S and the drain D increases. Therefore, by forming the bottom surface of the n-type source region 4 so as to be in contact with the p-type buried voltage control gate semiconductor region 5, the source resistance can be reduced. For example, the on-resistance can be lowered to about 57 mΩcm 2. Further, by further narrowing the interval between adjacent p-type buried voltage control gate semiconductor regions 5, a depletion layer is formed in the drain region 1 from the junction between the p-type buried voltage control gate semiconductor region 5 and the n-type drift layer 2 when turned off. Spread towards. Since the depletion layer shares the voltage, the breakdown voltage is improved. In this example, the breakdown voltage was 6.2 kV, and the on-resistance was 48 mΩcm 2.

<< 5th Example >>
FIG. 10 is a sectional view of a segment of a SiC static induction transistor according to a fifth embodiment of the present invention. In the present embodiment, the p-type region 9 is provided in the central portion of the active region 3 in FIG. 9 of the fourth embodiment. The other configuration is the same as that of the fourth embodiment, and a duplicate description is omitted. With this configuration, a depletion layer spreads in the active region 3 from the junction of the p-type buried voltage control gate semiconductor region 5 and the p-type surface voltage control gate semiconductor region 7 and the n-type active region 3. Further, since the depletion layer also spreads from the junction between the p-type region 9 and the n-type active region 3, the n-type active region 3 can be pinched off even when the gate voltage is zero or low. High breakdown voltage can be achieved. In this example, the breakdown voltage was 5.9 kV and the on-resistance was 43 mΩcm 2.

<< Sixth embodiment >>
FIG. 11 is a sectional view of a segment of a SiC junction field effect thyristor according to a sixth embodiment of the present invention. In the figure, an n-type drift layer 2 having a low impurity concentration of 1013 to 1016 atm / cm3 is formed by vapor phase epitaxy or the like on a p-type SiC substrate having a high impurity concentration of 1018 to 1020 atm / cm3 that functions as the anode region 11. . A p-type buried voltage control gate semiconductor region 5 is formed on the drift layer 2 in the same manner as in the second embodiment. Similarly, the n-type active region 3, the p-type gate contact semiconductor region 6, the p-type surface voltage control gate semiconductor regions 7 and 16, and the n-type cathode region 14 are sequentially formed. The bottom of the n-type cathode region 14 is in contact with the voltage control gate semiconductor region 5. The cathode electrode 25 is provided in the cathode region 14, the p-type surface voltage control gate semiconductor region 7, and the gate electrode 23 is provided in the p-type gate contact region 16. Finally, an anode electrode 24 is provided in the anode region 11.

  When the gate G and the cathode K are set to 0 V and a positive voltage is applied to the anode A, the built-in voltage is applied to the n-type active region 3 between the p-type buried voltage control gate semiconductor region 5 and the p-type surface voltage control gate semiconductor region 7. The depletion layer based on swells and the n-type active region 3 is pinched off. Thereby, the withstand voltage property with respect to the forward voltage occurs. When the gate G and the cathode K are set to 0 V and a negative voltage is applied to the anode A, a depletion layer spreads from the junction between the p-type anode region 11 and the drift layer 2 and voltage resistance against a reverse voltage is generated. Therefore, the SiC thyristor of the present embodiment can achieve a high breakdown voltage in both the forward direction and the reverse direction.

  When a positive voltage higher than the built-in voltage is applied to the anode A and a positive voltage lower than the built-in voltage is applied to the gate G with reference to the cathode K, the p-type embedded voltage control gate semiconductor region 5 and the p-type surface voltage control gate The region of the depletion layer in the n-type active region 3 between the semiconductor region 7 becomes narrower, passes from the anode A between both adjacent p-type buried voltage control gate semiconductor regions 5, and passes through the n-type active region 3, n A current flowing to the cathode K flows through the mold cathode region 14. At this time, since holes, which are minority carriers, are injected from the p-type anode region 11 into the n-type drift layer 2 and the n-type active region 3, conductivity modulation occurs and the on-resistance is greatly reduced. Further, since the n-type cathode region 14 is in contact with the p-type buried voltage control gate semiconductor region 5, the cathode resistance between the cathode K and the drift layer 2 can be reduced, and the cathode loss is reduced even at a large current density. be able to. Low noise due to low cathode resistance. In the case of a thyristor with a withstand voltage of 5.3 kV, the on-resistance after the current rising was able to be 6 mΩcm 2 or less.

<< Seventh embodiment >>
FIG. 12 is a sectional view of a segment of an electrostatic induction thyristor using SiC according to the seventh embodiment of the present invention. The thyristor of this embodiment has the polarity of the thyristor shown in FIG. 11 of the sixth embodiment reversed, and the channel is p-type. By reducing the width of the active region 33 sandwiched between the n-type surface voltage control gate semiconductor region 38 and the n-type buried voltage control gate 35 and reducing the distance between the two p-type anode regions 31, the channel resistance is reduced. Thus, an electrostatic induction phenomenon that does not cause saturation of the on-current occurs. In this structure, since the channel resistance is small, the ratio of the anode resistance, which is the resistance of the p-type anode region 31, to the resistance between the anode A and the cathode K increases. In this embodiment, since the bottom surface of the p-type anode region 31 is in contact with the n-type buried voltage control gate semiconductor region 35, the anode resistance can be reduced. In the case of the thyristor of this embodiment, since minority carrier electrons are injected from the n-type cathode region 34 into the p-type drift layer 32, the resistance of the p-type drift layer 32 and the p-type active region 33 is greatly reduced. Therefore, the ratio of the anode resistance is relatively increased, but reducing the anode resistance as described above contributes to reducing the resistance between the cathode K and the anode A. Further, by reducing the interval between the adjacent n-type buried voltage control gate semiconductor regions 35, the depletion layer is located closer to the cathode K from the junction between the n-type buried voltage control gate semiconductor region 35 and the p-type drift layer 32 when turned off. Since the voltage is spread and shared, the withstand voltage is increased.

  In this embodiment, the impurity concentration of the p-type drift layer 32 and the p-type active region 33 is 5 × 10 14 atm / cm 3 and the thickness is 150 μm and 1.2 μm, respectively. The withstand voltage of the thyristor of this embodiment is 15000 V or more in both the forward and reverse directions when the voltage of the gate G is 0 V. Further, the on-resistance after the rise could be a very small value of 32 mΩcm 2 when the gate voltage was 2.5V. In this embodiment, an n-type substrate having a low resistance is used in view of the problem of the current SiC technology that the resistance of the p-type substrate cannot be lowered. As a result, there is an effect that the on-voltage can be lowered at the on-time. For example, the on-state voltage was 4.4 V at a current density of 100 A / cm 2, which was a very low value.

<< Eighth embodiment >>
FIG. 13 is a sectional view of a segment of a junction field effect transistor using SiC according to the eighth embodiment of the present invention. The transistor of this embodiment has a source electrode 40 on the p-type surface voltage control gate semiconductor region 7 and the n-type source region 4 in the same configuration as the junction field effect transistor of the first embodiment of FIG. . The gate electrode 23 is formed on the p-type surface voltage control gate semiconductor region 16. Other configurations are the same as those of the first embodiment. In this embodiment, since the area of the source electrode 40 can be increased, the resistance of the source electrode 40 can be greatly reduced.

<< Ninth embodiment >>
FIG. 14 is a cross-sectional view of a segment of a static induction transistor using SiC according to the ninth embodiment of the present invention. In the transistor of this embodiment, a p-type third embedded voltage control gate semiconductor region 10, an n-type source region 44, and a source electrode 42 are provided in the central portion of the electrostatic induction transistor of the fourth embodiment of FIG. Yes. On both sides of the n-type source region 44, n-type active regions 43 are provided, and respective gate electrodes 46 are provided thereon. The distance between each p-type buried voltage control gate semiconductor region 5 and the p-type third buried voltage control gate semiconductor region 10 is about 2 μm. By adopting this structure, the ratio of the region composed of the n-type active region 43 and the source region 44 to the entire region can be increased, and a reduction in loss can be realized. In this example, a transistor having a withstand voltage of 5.3 kV and an on resistance of 69 mΩcm 2 was obtained.

<< Tenth embodiment >>
FIG. 15 is a circuit diagram showing an example in which a power inverter device is configured using SiC static induction transistors and SiC diodes to which the embodiments of the present invention are applied. Six electrostatic induction transistors SW11, SW12, SW21, SW22, SW31, SW32 and diodes D11, D12, D21, D22, D31, D32 convert direct current into three-phase alternating current. This inverter device includes a pair of DC input terminals 51 and 52 and three AC output terminals 61, 62 and 63 equal to the number of three-phase AC phases. A direct current power source is connected to the direct current input terminals 51 and 52, and the electrostatic induction transistors SW11, SW12, SW21, SW22, SW31, and SW32 are switched to convert the direct current power into alternating current power, and the alternating current output terminal 61, 62 and 63. Between the DC input terminals 51 and 52, both terminals of the electrostatic induction transistors SW11 and SW12, SW21 and SW22, and SW31 and SW32 connected in series are connected. AC output terminals 61, 62, and 63 are taken out from the connection points of the two electrostatic induction transistors in each of the electrostatic induction transistors SW11 and SW12, SW21 and SW22, and SW31 and SW32.
By applying the semiconductor device according to the present invention to the high withstand voltage inverter device, the semiconductor device can have a high withstand voltage, so that the number of semiconductor devices in series can be reduced even if the DC power is high. Further, the semiconductor device has a low loss even at a high breakdown voltage. Therefore, the high voltage inverter device can be made compact, low loss, and low noise. Therefore, low cost and high efficiency of the system using the inverter device can be realized. The present invention can be applied to power conversion devices such as switching power supplies and rectifiers in addition to inverter devices.

The present invention covers more applications or derivative structures.
In each of the above-described embodiments, only the case of an element using SiC has been described as an example. However, the present invention can be effectively applied to a semiconductor element using a wide gap semiconductor material such as diamond or gallium nitride. .
In the first to eighth embodiments, the case where the drift layer 2 is an n-type element has been described. However, when the drift layer 2 is a p-type element, the n-type region of another element is changed to a p-type region. The configuration of the present invention can be applied by replacing the p-type region with the n-type region.

Sectional drawing of the junction field effect transistor of 1st Example of this invention II-II sectional view of FIG. III-III sectional view of FIG. Sectional drawing of the junction type field effect transistor of the other example of 1st Example Sectional drawing which shows the process of the first half of the manufacturing method of the junction field effect transistor of 1st Example of this invention Sectional drawing which shows the latter process of the manufacturing method of the junction type field effect transistor of 1st Example of this invention Sectional drawing of the junction field effect transistor of 2nd Example of this invention (A) is sectional drawing of the junction field effect transistor of 3rd Example of this invention, (b) is bb sectional drawing of (a). Sectional drawing of the electrostatic induction type transistor of 4th Example of this invention. Sectional drawing of the electrostatic induction type transistor of 5th Example of this invention. Sectional drawing of the junction field effect thyristor of 6th Example of this invention Sectional drawing of the electrostatic induction type thyristor of 7th Example of this invention. Sectional drawing of the junction field effect transistor of 8th Example of this invention Sectional drawing of the electrostatic induction type transistor of 9th Example of this invention Circuit diagram of power inverter of tenth embodiment using semiconductor device of the present invention. Sectional view of a conventional storage type field effect transistor ACCUFET Sectional view of a conventional static induction transistor

Reference Signs List 1 drain region 2 drift layer 3 active region 4 source region 5 buried voltage control gate semiconductor region 6, 16 gate contact semiconductor region 7 surface voltage control gate semiconductor region 8 second buried voltage control gate semiconductor region 9 p-type region
10 Third buried voltage control gate semiconductor region 11 Anode region 14 Cathode region 21 Drain electrode 22 Source electrode 23 Gate electrode 24 Anode electrode 25 Cathode electrode 31 Anode region 32 Drift layer 33 Active region 34 Cathode region 35 Embedded voltage control gate semiconductor region 36 , 38 Gate contact semiconductor region 37 Surface voltage control gate semiconductor region 42 Source electrode 43 n-type active region 44 Source region 46 Gate electrode 51, 52 DC input terminal 61, 62, 63 AC output terminal SW11, SW12, SW21, SW22, SW31 , SW32 Static induction transistor D11, D12, D21, D22, D31, D32 Diode 101: Drain region 102: Drift layer 103: Channel layer 104: Gate insulating film 105 : Gate electrode 106: drain electrode 107: source electrode 108: buried region 109, 110: gate region 112: n-type region 112A: channel A: anode D: drain G: gate K: cathode S: source

Claims (6)

A drift layer of any one of the first conductivity type and the second conductivity type having a low impurity concentration formed on the semiconductor substrate;
In the internal region including the surface of the drift layer, a plurality of buried voltage control gate semiconductor regions having a conductivity type different from that of the drift layer formed at intervals from each other ,
An active region having the same conductivity type as the drift layer formed on the surface of the central region of the drift layer including the upper surface of each of the plurality of buried voltage control gate semiconductor regions, and having a thickness smaller than that of the drift layer;
A gate contact semiconductor region having a conductivity type different from that of the drift layer, which is in contact with a part of an upper surface of each of the embedded voltage control gate semiconductor regions and formed in an internal region including a surface of the active region;
An internal region including the surface of the active region, located between the gate contact semiconductor region, and formed in the region located on the top of each of the buried voltage controlled gate semiconductor region, the same conductivity as said drift layer Two first semiconductor regions of the mold,
A first electrode formed in the first semiconductor region;
A surface voltage control gate semiconductor region having a conductivity type different from that of the drift layer formed on the surface of the active region;
A gate electrode formed in the surface voltage control gate semiconductor region; and at least a second electrode formed on an opposite surface of the semiconductor substrate having the drift layer;
The voltage of the first semiconductor region is such that the surface thereof is at a position lower than the surface of the surface voltage control gate semiconductor region, and the end portions of both are at the same position. Control type semiconductor device. A semiconductor substrate having a high impurity concentration of the first conductivity type;
A drift layer of a first conductivity type having a low impurity concentration formed on the semiconductor substrate;
A plurality of buried voltage control gate semiconductor regions of the second conductivity type formed at intervals in an internal region including the surface of the drift layer;
An active region of a first conductivity type including a top surface of each of the plurality of buried voltage control gate semiconductor regions and formed on a surface of a central region of the drift layer, wherein the thickness is smaller than that of the drift layer;
A gate contact semiconductor region of a second conductivity type formed in an internal region in contact with a part of the upper surface of each of the embedded voltage control gate semiconductor regions and including the surface of the active region;
An internal region including a surface of the active region , the first conductivity type formed in a region located between the gate contact semiconductor regions and located above each of the buried voltage control gate semiconductor regions Two source regions,
A source electrode formed in the source region;
A surface voltage control gate semiconductor region of a second conductivity type formed on the surface of the active region;
A gate electrode formed in the surface voltage control gate semiconductor region, and a drain electrode formed on a surface of the semiconductor substrate opposite to the surface having the drift layer,
The source region is configured such that the surface thereof is positioned lower than the surface of the surface voltage control gate semiconductor region, and the end portions of both are at the same position. apparatus.   The voltage control type semiconductor device according to claim 2, wherein the source region is formed so as to be in contact with the buried voltage control gate semiconductor region.   3. The semiconductor device further comprising another buried voltage control gate semiconductor region partially formed in an internal region including the surface of the drift layer between the two buried voltage control gate semiconductor regions and connected to the gate electrode. The voltage controlled semiconductor device described.   3. The voltage control type semiconductor device according to claim 2, wherein the source electrode is formed on an upper surface of the source region and is formed on an upper surface of a surface voltage control gate semiconductor region on the active region. Another buried voltage control gate semiconductor region of the second conductivity type formed between the two buried voltage control gate semiconductor regions in the drift layer; and at least a part of the other buried voltage control gate semiconductor region 3. The voltage controlled semiconductor device according to claim 2, further comprising a source region of the first conductivity type formed in the active region.

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