JP4339731B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device having a multilayer wiring structure. In particular, the present invention relates to a semiconductor device having a structure of multilayer damascene wiring and a connection portion between the wirings.

  The technology that uses copper (Cu), which has lower specific resistance and higher current density than aluminum (Al), which is widely used as a wiring material, as a wiring material, reduces device design rules for semiconductor devices, etc. And with the increase in speed, it is an essential technology. Therefore, wiring using copper (Cu) as a wiring material (hereinafter referred to as “Cu wiring”) is gradually becoming popular in device products that require high integration and device products that require high current density. is doing.

  By the way, when patterning a Cu wiring using a photoresist mask and an etchant gas, corrosion or so-called corrosion occurs due to the influence of the etchant gas and moisture, and the photoresist and the etchant gas are used for the Cu wiring. Not suitable for patterning.

  Therefore, damascene is formed by embedding copper (Cu) as a wiring material in a groove formed in advance in an insulating layer, and then removing unnecessary copper (Cu) by chemical mechanical polishing (hereinafter, CMP (Chemical Mechanical Polishing)) or the like. The law is used. Also, in order to connect the lower layer wiring and the upper layer wiring, copper (Cu), which is also used as a wiring material as a contact conductor in the opening formed in the insulating layer between the upper layer wiring and the lower layer wiring A contact having a structure in which is embedded is used.

  Further, according to the so-called dual damascene method, the contact and the upper layer wiring are formed simultaneously with respect to the lower layer wiring formed by the damascene method. Here, in the dual damascene method, the contact opening and the upper wiring layer groove are sequentially opened in the insulating layer, the contact conductor and the upper wiring metal are embedded in the same process, and then by CMP or the like, This is a manufacturing method in which only the contact conductor and the upper wiring metal, that is, copper (Cu) are left in the openings and grooves in the insulating layer.

  However, in the technique using copper (Cu) as a wiring material using the damascene method and the dual damascene method, the formation of the contact used for connection between the upper layer wiring and the lower layer wiring, stress during wiring or contact formation Due to this, voids grown in the wiring and contact openings, that is, voids caused by poor connection between the upper layer wiring and the lower layer wiring, upper layer wiring and lower layer wiring due to protrusions generated in the wiring and contact opening during the wiring or contact formation process There is a problem of poor connection.

  Conventionally, the following countermeasures have been taken against the above problems.

  Conventional Example 1 relates to an interlayer insulating layer that does not cause aggregation in wiring, and will be described with reference to cross-sectional views shown in FIGS. 19 (a) to 19 (f).

  First, as shown in FIG. 19A, an SiO2 insulating layer 102 is formed on a silicon substrate 101 having device elements by a plasma CVD method. Next, a photoresist 103 is applied, and a trench wiring pattern is formed by a photolithography technique.

  Next, as shown in FIG. 19B, the SiO2 insulating layer 102 is etched by a dry etching technique to form a groove, and then the photoresist 103 is removed by dry ashing and wet stripping.

  Next, as shown in FIG. 19 (c), a tantalum (Ta) layer as a barrier metal 104 is 50 nm, and a copper (Cu) plating seed layer is sputtered to form a copper (Cu) film of 100 nm on the entire surface of the silicon substrate. Form a film. Next, after the trench is filled with the wiring material 105 made of copper (Cu) by electroplating, the copper (Cu) is annealed by heat treatment.

  Then, as shown in FIG. 19D, copper (Cu) and tantalum (Ta) on the insulating film are removed by CMP to form a copper (Cu) wiring 106.

  Next, as shown in FIG. 19 (e), 20 nm of silicon nitride (SiN) is deposited at a low temperature as the first insulating film 107 which functions as a diffusion preventing film. Next, 30 nm of silicon nitride (SiN) is formed as the second insulating film 108 at a high temperature.

  Then, as shown in FIG. 19 (f), an SiO2 film is formed to a thickness of 500 nm by plasma CVD, and an insulating layer 109 is formed.

  Here, the first insulating layer 107, the second insulating layer 108, and the insulating layer 109 constitute the above-described interlayer insulating layer between the upper layer wiring and the lower layer wiring.

(For example, Patent Document 1)
Conventional Example 2 relates to a damascene wiring structure for preventing the generation of voids at the contact portion of a via hole used for connection with an upper layer wiring, and will be described with reference to a plan view shown in FIG.

  First, FIG. 20 shows a wiring groove 115, an insulating layer remaining pattern 116 in the wiring groove 115, a damascene wide wiring 117, a via hole 118, and a metal grain boundary 119 in the damascene wide wiring 117.

  The wiring trench 115 is filled with a wiring metal except for the insulating layer remaining pattern 116 to constitute a damascene wide wiring 117.

  The via hole 118 is surrounded by four insulating layer remaining patterns 116 and is used for connection between the damascene wide wiring 117 and the upper layer wiring.

  Further, the damascene wide wiring 117 has a wiring structure composed of the metal grain boundaries 119 described above. In the periphery of the via hole 118 surrounded by the insulating layer remaining pattern 116, the metal grain boundary 119 has a small shape. In other regions, the metal grain boundary 119 has a large shape.

(For example, Patent Document 2)
Conventional Example 3 relates to a wiring structure for avoiding a problem due to poor formation of the contact used for connecting the upper layer wiring and the lower layer wiring in the peripheral portion of the wafer substrate, and FIGS. 21 (a) to 21 (c). ).

  First, as shown in FIG. 21A, a first etching stopper layer 121 is formed on a base 120, and a first insulating layer 122 is formed thereon. Next, a photoresist layer 123 having an opening pattern for forming a wiring pattern groove is formed on the surface of the first insulating layer 122.

  Next, using the photoresist layer 123 as an etching mask, the first insulating layer 122 is etched by reactive ion etching to form a trench for a wiring pattern. Next, the photoresist layer 123 is removed by ashing using O 2 plasma. Thereafter, the first etching stopper layer 121 exposed in the trench for the wiring pattern is removed by reactive ion etching using a CHF-based etching gas.

  Next, as shown in FIG. 21B, the first barrier metal layer 124 and the first main wiring layer 125 are formed on the structure in which the trench for the wiring pattern is formed. Thereafter, CMP is performed to remove the first main wiring layer 125 and the first barrier metal layer 124 on the surface of the first insulating layer 122.

  Next, as shown in FIG. 21C, a second etching stopper layer 130 is formed on the surface of the semiconductor wafer to protect the first main wiring layer 125. Next, the second insulating layer 126 is formed on the second etching stopper layer 130. Next, CMP is performed on the second insulating layer 126 to planarize the surface. As a result, the second insulating layer 126 is thinner in the wafer ineffective area than in the wafer effective area. Next, a third etching stopper layer 127 is formed on the surface of the second insulating layer 126. Next, a third insulating layer 128 is formed on the surface of the third etching stopper layer 127. Next, a second photoresist layer 129 having a contact opening pattern is formed on the surface of the third insulating layer 128. However, the opening pattern is formed only in the wafer effective area, and the opening pattern is not formed in the wafer ineffective area. Next, reactive ion etching is performed to form contact openings. As a result, an appropriate contact opening is formed in the effective wafer area. On the other hand, no contact opening is formed in the ineffective area of the wafer, and overetching due to the thin second insulating layer 126 does not occur.

(For example, Patent Document 3)
Conventional Example 4 is a document analyzing the generation of voids at the contact portion between the lower layer wiring and the contact, and will be described with reference to FIGS. 22 (a) to 22 (b).

  First, FIG. 22A shows a chain including a lower layer wiring 135, a contact 136 made of a via and a wiring metal, and an upper layer wiring 137. The lower layer wiring 135 is thin, and the upper layer wiring 137 is a wide wiring having a large area.

  FIG. 22B is a perspective view of the chain between A and B shown in FIG. 22A. The wiring metal of the contact 136 is directed from the lower layer wiring 135 toward the upper layer wiring 137 in the direction of the arrow 138. Indicates that you are under stress.

  The above document estimates that the stress due to the tensile stress from the upper layer wiring 137, which is a wide wiring, to the wiring metal in the contact 136 is the cause of the generation of voids in the contact portion between the lower layer wiring 135 and the contact 136. is doing.

(For example, Non-Patent Document 1)
Japanese Patent Laid-Open No. 2002-9150 JP 2001-298084 A JP 2003-17559 A N. Okada, Y. Matsubara, H. Kimura, H. Aizawa and N. Nakamura: Proc. Int. Interconnect Technology Conf., San Francisco, 2002, P15.

  The present invention provides a multilayer wiring that prevents a connection failure from occurring in a connection portion of a damascene wiring or a dual damascene wiring, and a semiconductor device using the multilayer wiring.

In order to solve the above problems, the first invention is
A first insulating layer;
Lower layer wiring,
A diffusion barrier film on the lower wiring;
A second insulating layer on the diffusion barrier film;
With upper layer wiring,
The lower layer wiring is composed of a conductor embedded in a groove in the first insulating layer,
The lower layer wiring has a protrusion formed above the surface of the first insulating layer and formed due to the formation of the diffusion prevention film;
The upper wiring and the lower wiring is embedded in the largest the projection greater than the through hole and the through-hole reaching said lower wiring of the diffusion preventing film and the second insulating layer among said protrusions Provided is a semiconductor device connected by a contact made of a conductor .
Also, the first invention is
Forming a first insulating layer;
Forming a groove in the first insulating layer, filling the groove with a conductor to form a lower layer wiring;
Forming a diffusion barrier film on the lower wiring;
Forming a second insulating layer on the diffusion barrier film;
During the step of forming the diffusion preventive film, a protrusion is formed so as to protrude above the surface of the first insulating layer, and the lower layer in the second insulating layer and the diffusion preventive film Forming a through hole reaching the wiring with a diameter larger than the largest projection among the projections, and burying a conductor in the through hole to form a contact;
Forming an upper wiring on the second insulating layer so as to be connected to the contact;
A method for manufacturing a semiconductor device is provided.

  In the semiconductor device according to the first aspect of the invention, since there is an upper limit on the size of the protrusion generated due to the formation of the diffusion prevention film, the size of the connecting portion connecting the upper layer wiring and the lower layer wiring is made larger than the size of the projection. By setting it large, the connection between the lower layer wiring and the upper layer wiring is ensured in the remaining portion of the connection portion even if the connection portion is arranged on the protrusion on the lower layer wiring. Therefore, if the semiconductor device according to the first invention is employed, the connection failure between the lower layer wiring and the upper layer wiring is greatly reduced. In addition, since the defect rate in wiring connection is reduced, the yield of the semiconductor device is improved.

  In addition, the said connection part does not need to be formed integrally, and may be comprised from several contact, and there exists an effect similar to the above. If the contact opening shape is uniform, it is optimal for the exposure process during the manufacturing process of the semiconductor device.

In order to solve the above problem, the second invention
A first insulating layer;
Lower layer wiring,
A diffusion barrier film on the lower wiring;
A second insulating layer on the diffusion barrier film;
With upper layer wiring,
The lower layer wiring is composed of a conductor embedded in a groove in the first insulating layer,
The lower layer wiring has a protrusion formed above the surface of the first insulating layer and formed due to the formation of the diffusion prevention film;
The lower layer wiring and the upper layer wiring are connected by a plurality of adjacent contacts ,
The contact is composed of a through hole reaching the lower layer wiring in the second insulating layer and the diffusion prevention film, and a conductor embedded in the through hole,
At least one of the contacts in the plurality of contacts is formed on the protrusion, and at least one of the other contacts has the contact arrangement at a position spaced from the protrusion. I will provide a.
In addition, the second invention,
Forming a first insulating layer;
Forming a groove in the first insulating layer, filling the groove with a conductor to form a lower layer wiring;
Forming a diffusion barrier film on the lower wiring;
Forming a second insulating layer on the diffusion barrier film;
During the step of forming the diffusion preventive film, a protrusion is formed so as to protrude above the surface of the first insulating layer, and the lower layer in the second insulating layer and the diffusion preventive film A plurality of through-holes reaching the wiring are formed such that at least one of the through-holes is formed on the protrusion, and at least one of the other through-holes is arranged to be spaced from the protrusion. , Forming a contact by embedding a conductor in the through hole;
Forming an upper layer wiring on the second insulating layer so as to be connected to the plurality of contacts;
A method for manufacturing a semiconductor device is provided.

  In the semiconductor device according to the second invention, since there is an upper limit on the size of the protrusion generated due to the formation of the diffusion prevention film, the arrangement of the contacts constituting the connection portion connecting the upper layer wiring and the lower layer wiring is set as described above. By doing so, even if a part of the contact constituting the connection portion is arranged on the protrusion on the lower layer wiring, the connection between the lower layer wiring and the upper layer wiring is ensured in the other part of the contact constituting the connection portion. . Therefore, if the semiconductor device according to the second invention is employed, the connection failure between the lower layer wiring and the upper layer wiring is greatly reduced. In addition, since the defect rate in wiring connection is reduced, the yield of the semiconductor device is improved.

In order to solve the above problem, the third invention
A first insulating layer;
A diffusion barrier film on the lower wiring;
A second insulating layer on the diffusion barrier film;
With upper layer wiring,
The lower layer wiring is composed of a conductor embedded in a groove in the first insulating layer,
The lower layer wiring has a protrusion formed above the surface of the first insulating layer and formed due to the formation of the diffusion prevention film;
The lower layer wiring and the upper layer wiring are connected by a plurality of adjacent contacts ,
The contact is composed of a through hole reaching the lower layer wiring in the second insulating layer and the diffusion prevention film, and a conductor embedded in the through hole,
At least one of the contacts in the plurality of contacts is formed on the protrusion, and at least one of the other contacts is formed at a position spaced from the protrusion;
Provided is a semiconductor device characterized in that a distance between adjacent contacts is set according to a thickness of a lower layer wiring.

  In the semiconductor device according to the third invention, the size of the protrusion generated due to the formation of the diffusion prevention film depends on the thickness of the lower layer wiring, but has an upper limit depending on the lower layer wiring, and the upper layer wiring and the lower layer wiring If the distance between adjacent contacts of the contact that constitutes the connection part that connects the two is set larger than the size of the protrusion according to the thickness of the lower layer wiring, a part of the contact that constitutes the connection part on the projection on the lower layer wiring Even if is arranged, the connection between the lower layer wiring and the upper layer wiring is ensured in the other part of the contact constituting the connection portion. Therefore, if the semiconductor device according to the third invention is employed, the connection failure between the lower layer wiring and the upper layer wiring is greatly reduced. In addition, since the defect rate in wiring connection is reduced, the yield of the semiconductor device is improved.

In order to solve the above problem, the fourth invention is:
In the semiconductor device according to the second and third inventions,
The conductor constituting the lower layer wiring is composed of a barrier metal layer and a wiring metal,
The first insulating layer and the second insulating layer are formed of at least one of SiN, SiOF, SiOC, and SiC, and provide a semiconductor device.

  According to the semiconductor device of the fourth invention, the protrusion on the lower layer wiring is likely to occur, but there is an upper limit on the size of the protrusion on the lower layer wiring, and the upper layer wiring and the lower layer wiring are connected. If the arrangement of the contacts constituting the connection portion is as described above, even if a part of the contact constituting the connection portion is arranged on the protrusion on the lower layer wiring, the other portion of the contact constituting the connection portion Connection between the wiring and the upper layer wiring is ensured. Therefore, if the semiconductor device according to the fourth aspect of the present invention is employed, the connection failure between the lower layer wiring and the upper layer wiring is greatly reduced. In addition, since the defect rate in wiring connection is reduced, the yield of the semiconductor device is improved.

  According to the multilayer wiring according to the present invention, when connecting the upper layer wiring and the lower layer wiring, the contact failure that occurs when the connection portion is located on the protrusion generated during the process of forming the diffusion prevention film on the lower layer wiring. There is an effect to prevent.

  Further, in the semiconductor device having the multilayer wiring structure described above, the contact failure between the upper layer wiring and the lower layer wiring is remarkably reduced, so that the yield of the semiconductor device is improved.

  The planar configuration of the multilayer wiring according to the present embodiment includes an upper layer wiring, a lower layer wiring, a connection portion connecting the upper layer wiring and the lower layer wiring, and a protrusion on the lower layer wiring. The lower layer wiring and the upper layer wiring are formed by a so-called dual damascene method or damascene method. Further, the protrusion is generated during a process of forming a diffusion prevention film for preventing diffusion of wiring metal constituting the lower layer wiring in the dual damascene method or the damascene method. Furthermore, the connection part that connects the lower layer wiring and the upper layer wiring is composed of a plurality of contacts.

  Here, the contact has a structure in which a metal is embedded in a through hole in an interlayer insulating film between the lower layer wiring and the upper layer wiring, and performs electrical connection between the upper layer wiring and the lower layer wiring.

  And since the connection part is set larger than said protrusion, when said protrusion and a connection part overlap, the remainder part which deducted the overlap part with a protrusion from a connection part remains. Therefore, even if the protrusion and the connection portion overlap with each other, the electrical connection between the lower layer wiring and the upper layer wiring can be ensured.

  By the way, the reason why the connecting portion is composed of a plurality of contacts is as follows. First, when the wiring width is narrow and the wiring interval is narrowed, that is, when a so-called design rule is reduced, the contact opening is also reduced. Therefore, when patterning with a photoresist, it is inconvenient that a contact having a large opening and a contact having a small opening are mixed. On the other hand, in the case of the present embodiment, since the connection portion needs to be larger than the protrusion, the connection portion requires a larger area than a normal contact. Therefore, the connecting portion is constituted by a plurality of contacts.

  Next, the reason why it is inconvenient to mix contacts having a large opening and contacts having a small opening is as follows. First of all, when adjusting the exposure amount for a resist in accordance with a small opening, a large amount of exposure is always secured in a large opening. Tends to be sensitive to quantity.

  On the other hand, when the exposure amount is adjusted in accordance with the large opening portion, the size of the opening tends to be insensitive to the exposure amount in the small opening portion in which the exposure amount tends not to be secured. Then, it is difficult to give a satisfactory exposure amount to both the small opening and the large opening. Therefore, it is inconvenient that a contact having a large opening and a contact having a small opening are mixed.

  As will be described later, since the upper limit of the size of the protrusion on the lower layer wiring is increased according to the lower layer wiring width, the size of the connection portion needs to be increased according to the lower layer wiring width. When the connection portion is composed of a plurality of contacts, the size of the connection portion can be increased by increasing the number of contacts without worrying about the problem of patterning.

  Therefore, according to the multilayer wiring having the above-described connecting portion shown in the present embodiment, the region of the connecting portion constituted by a plurality of contacts is set to be larger than the size of the protrusion generated in the lower layer wiring. The electrical connection between the upper layer wiring and the lower layer wiring can be sufficiently ensured at a portion other than the projection even if the connection portion and the projection overlap. Accordingly, connection failure between the lower layer wiring and the upper layer wiring can be prevented.

(Semiconductor device having a multi-layer wiring connected by a connection portion larger than the protrusion and the state of occurrence of the protrusion)
When copper (Cu) is used as the metal for the wiring material in the multi-layer wiring structure formed by the damascene method or dual damascene method, the diffusion prevents copper from diffusing in the insulating layer on the lower layer wiring. It is necessary to form a prevention film.

  And, usually, during the step of forming the diffusion prevention film on the lower layer wiring composed of copper (Cu), the lower layer wiring is subjected to a heat treatment of about 400 ° C., and with the heat treatment, the copper (Cu) atom The movement may occur, and a protrusion may be formed on the surface of the lower layer wiring.

  In the above case, when the contact for connecting the upper layer wiring and the lower layer wiring overlaps with the projection, immediately after the contact forming process is completed, that is, copper (Cu) for wiring is used for wiring. Immediately after removing excess copper (Cu) on the insulating layer by CMP and filling in the opening of the trench and contact, the upper layer wiring and the lower layer wiring are connected.

  However, due to the stress in the metal wiring generated by the heat treatment during the manufacturing process after the contact formation process, the stress of the current flowing through the contact during use of the semiconductor device having the multilayer wiring structure, Compared to locations other than the protrusions, the protrusions caused by the movement of copper (Cu) atoms are unstable, so relocation of copper (Cu) atoms occurs in all or part of the protrusions that overlap the contact. The inventors have found that voids are likely to occur at the contact portion between the lower layer wiring and the contact. Further, in the case of the contact failure in the peripheral portion of the wafer shown in the conventional example 3, the contact caused by the stress between the lower layer wiring and the upper layer wiring shown in the conventional example 4, and the contact caused by the structure of the wide wiring shown in the conventional example 2 The inventors have found that the contact failure increases as the width of the lower layer wiring increases as compared to the contact failure in the case where the contact is formed in a portion other than the protrusion as shown in the case of the failure. Here, it is presumed that the contact failure mode discovered by the inventors is caused by the fact that the larger the width of the lower layer wiring, the larger the size of the protrusion and the more the number of protrusions generated.

  On the other hand, in Conventional Example 1, if the aggregation of copper (Cu) atoms occurs in the lower layer wiring, the morphology of the surface of the lower layer wiring is deteriorated, so that the aggregation of copper (Cu) atoms is prevented with respect to the lower layer wiring. Adopting the structure of a proper diffusion prevention film. However, the solution of the contact failure mode discovered by the inventors is important, and from the viewpoint different from the countermeasure of the conventional example 1, it is required to solve the contact failure mode.

  Therefore, first, the inventors of the present invention have found that in the multilayer wiring using copper (Cu) as the wiring material, the relationship between the size of the protrusion and the generation of the protrusion due to the movement of the copper (Cu) atom in the lower layer wiring It investigated how it changed according to the thickness of the. As a result, it has been found that there is an upper limit on the size of the protrusion and that the upper limit of the size increases as the thickness of the lower layer wiring increases. It was also discovered that the number of protrusions increased with the thickness of the lower layer wiring. Further, the correlation between the defect rate of the chain composed of the upper layer wiring, the lower layer wiring, and the contact and the thickness of the lower layer wiring is investigated, and if the lower layer wiring is thicker and the contact size is constant, the defect rate I found it expensive. In addition, a semiconductor chip on which a chain composed of wirings and contacts was formed was observed for each division of the manufacturing process. As a result, it was obtained that the generation of protrusions was single-shot on the plane of the lower layer wiring, that is, it did not occur in groups. Moreover, the result that the processus | protrusion by the movement of a copper (Cu) atom generate | occur | produces in the process of forming the diffusion prevention film which is one of the manufacturing processes mentioned later was obtained.

  Here, the contact is the same as the contact described in the best mode for carrying out the invention because the multilayer wiring is formed by the dual damascene method or the damascene method. A case where a through hole is formed in an interlayer insulating film and the through hole is backfilled with a wiring material, an insulating film for an upper layer wiring is formed, a wiring groove is formed, and a wiring is embedded is called a damascene method. The case where a through hole and a wiring groove are formed in the interlayer insulating film and then the wiring material is simultaneously filled in the through hole and the wiring groove is called a dual damascene method.

  FIG. 1 and FIG. 2 show a chain (hereinafter referred to as “contact chain”) composed of an upper layer wiring, a lower layer wiring, and a contact used by the inventors for the investigation. Here, FIG. 1 shows a planar configuration, and FIG. 2 shows a cross-sectional configuration.

  First, FIG. 1 shows a part of a contact chain formed on a semiconductor chip. The contact chain includes a contact 1 indicated by a pattern in which a square is marked with an X, an upper layer wiring 2 indicated by a solid line pattern, and a lower layer wiring 3 indicated by a dotted line pattern. That is, the upper layer wiring 2 and the lower layer wiring 3 are alternately arranged, and the right end portion of the rectangular lower layer wiring 3 is connected to the left end portion of the rectangular upper layer wiring 2 by the arranged contact 1. 2 is connected to the left end of the rectangular lower layer wiring 3 by an arranged contact, and the above is repeated a plurality of times, so that the upper layer wiring 2, the lower layer wiring 3, and the contact 1 are It constitutes a chain.

  The sectional view of FIG. 2 has a sectional structure between E and F shown in the plan view of FIG. 1 and is formed by the following manufacturing process.

  First, in order to form the lower layer wiring 7 by the so-called damascene method, on the semiconductor substrate 5 (including not only the semiconductor substrate but also the lower layer wiring and the insulating layer covering the lower layer wiring below the target lower layer wiring) Then, a lower insulating layer 6 made of silicon oxide (SiO 2) having a thickness of 0.45 μm is formed. Next, a wiring layer groove having a depth of 0.45 μm is formed in the lower insulating layer 6 and a wiring metal is buried to form the lower layer wiring 7. Here, the wiring metal is embedded by sputtering a tantalum nitride (TaN) barrier metal layer 8 having a thickness of about 30 nm by sputtering, and then depositing copper (Cu) as a seed layer and electrolytic plating. The trench is filled with copper (Cu), and unnecessary barrier metal layer and copper (Cu) formed on the lower insulating layer 6 are removed by CMP.

  Next, in order to form the upper layer wiring 12 and the contact 9 by the so-called dual damascene method, first, a first diffusion prevention film 10 and a first insulating film 11 made of silicon oxide (SiO 2) are formed on the lower layer wiring 7. An interlayer insulating layer made of the first diffusion preventing film 10 and the first insulating film 11 is formed. Next, an opening for the contact 9 is formed through the interlayer insulating layer, and then a groove for the upper wiring 12 is formed. Here, the opening for the contact 9 has a height of 0.7 μm after the groove for the upper layer wiring 12 is formed, and the groove for the upper layer wiring 12 has a depth of 0.45 μm.

  Here, the first diffusion prevention film 10 prevents the diffusion of the metal for wiring into the insulating film due to the heat generated when the current passes through the wiring after the subsequent heat treatment process or product completion. The main function. The other functions of the first diffusion prevention film 10 include an etching stopper function for forming an opening for the contact 9 through the interlayer insulating layer, and oxygen (O2 for the purpose of removing the photoresist. It is desirable to have a function of blocking oxygen permeation to the wiring metal when performing the ashing process. Therefore, for example, a silicon nitride (SiN) film formed by a CVD method using a mixed gas such as ammonia (NH 3) -based gas and silane (SiH 4) -based gas is desirable.

  Next, a wiring metal is embedded in the groove for the upper layer wiring 12 and the opening of the contact 9 to form the upper layer wiring 12 and the contact 9. Here, the wiring metal is buried in the same manner as when the lower layer wiring 7 is formed. Next, a second diffusion preventing film 13 is formed for the metal for the upper layer wiring 12, and further, a second insulating film 14 is formed for forming the upper layer wiring thereon.

  Next, FIG. 3A is a plan view relating to a lower layer wiring having a width of 10 μm. FIG. 3B is a plan view relating to a lower layer wiring having a width of 2 μm. Further, FIG. 3C is a plan view relating to a lower layer wiring having a width of 0.8 μm.

  According to FIG. 3A relating to the 10 μm-wide lower layer wiring, the lower layer wiring 15 is obtained by repeatedly arranging a rectangular pattern having a width of 10 μm at a pitch of 40 μm in the vertical direction and a pitch of 15 μm in the horizontal direction. In addition, two contacts are formed at both ends of each rectangle constituting the upper layer wiring. The shape of the opening of the contact is, for example, 0.2 μm square, but is not shown because it is relatively small compared to the lower layer wiring 15. Here, a contact chain is formed from thousands of rectangular patterns that are upper layer wirings, thousands of rectangular patterns that are lower layer wirings 15, and thousands of contacts. The rectangular pattern constituting the upper layer wiring and the rectangular pattern constituting the upper layer wiring overlap each other, but are arranged so as to be shifted by a half pitch. Therefore, the rectangular pattern constituting the upper layer wiring and the rectangular pattern constituting the lower layer wiring 15 share one contact.

  According to FIG. 3B relating to the above-mentioned 2 μm wide lower layer wiring, the lower layer wiring 16 is configured by repeatedly arranging rectangular patterns with a width of 2 μm at a pitch of 5.3 μm in the vertical direction and a pitch of 2.5 μm in the horizontal direction. The shape of the opening of the contact 18 is, for example, 0.2 μm square. Here, except that the rectangular pattern constituting the upper layer wiring is shaped in accordance with the size and pitch of the rectangular pattern constituting the lower layer wiring, the contact chain for the lower wiring of 2 μm width is also a lower layer of 10 μm width. It has the same structure as the contact chain for wiring.

  According to FIG. 3C relating to the lower layer wiring having a width of 0.8 μm, the lower layer wiring 17 is configured by repeatedly arranging a rectangular pattern having a width of 0.8 μm at a pitch of 3.3 μm in the vertical direction and a pitch of 1 μm in the horizontal direction. The shape of the opening of the contact 19 is, for example, 0.2 μm square. Here, except that the rectangular pattern constituting the upper layer wiring is shaped in accordance with the size and pitch of the rectangular pattern constituting the lower layer wiring, the contact chain for the lower layer wiring of 0.8 μm width is also 10 μm wide. It has the same structure as the contact chain for the lower layer wiring.

  Next, FIG. 4A shows the relationship between the count of protrusions on the lower layer wiring and the size of the protrusions, which constitute the contact chain. FIG. 4B shows the relationship between the size of the protrusion and the wiring width. Here, the size and number of the protrusions were detected by a general defect inspection apparatus (for example, a defect inspection apparatus manufactured by KLA-tencor).

  By the way, the above-mentioned protrusion is a place where metal atoms constituting the lower layer wiring formed by the damascene method or the dual damascene method are raised from the surface of the lower layer wiring with respect to a uniform flat place at a specific location. Say.

  Note that metal atoms bulge to specific locations and become protrusions, for example, due to stress between the insulating material forming the insulating layer forming the groove for the lower layer wiring and the metal material forming the lower layer wiring. It is presumed that the metal atoms on the surface of the lower layer wiring move to a specific location and aggregate at the time of the prevention film growth. This is because it is easily estimated that the state of the surface changes due to the process of stress relaxation due to the application of heat or the rearrangement of the material resulting from the generation of heat.

  Here, it is estimated that the stress between the insulating material forming the insulating layer forming the groove for the lower layer wiring and the metal material forming the lower layer wiring is generated due to the formation of the diffusion prevention film on the lower layer wiring.

  This is because, first, there is a difference in the coefficient of thermal expansion between the insulating material and the metal material, and therefore, the volume of the groove for the lower layer wiring and the metal material embedded in the groove by the heat applied to form the diffusion prevention film. There is a difference in volume. Therefore, the metal material pushed into the narrow space is stressed.

  In addition, in the case of “due to the formation of a diffusion prevention film”, not only a process involving heating, which forms a diffusion prevention film, but also a treatment before and after the film formation (for example, surface oxide of the wiring metal before the film formation) This is caused by at least one of the steps including a plasma treatment step with ammonia (NH 3) gas performed for the purpose of reducing the above.

  This is because, firstly, there is a certain probability that a metal atom becomes free on the surface as oxygen is desorbed when reducing the surface oxide. This is because it is also conceivable that metal atoms move to a specific location and aggregate in that state.

  By the way, the reason for “diffusion prevention film formation” is that after the diffusion prevention film is formed on the lower layer wiring, the metal material is closed on all sides and is subjected to some pressure to easily relieve stress. This is because it is not possible to move for this. For this reason, it is presumed that the formation of protrusions is suppressed after the pretreatment relating to the formation of the diffusion prevention film and the initial stage of the formation of the diffusion prevention film.

  First, FIG. 4A shows the contact chain of FIGS. 3A to 3C in which the width of the upper layer wiring and the contact diameter are fixed and the width of the lower layer wiring is set to 0.8 μm, 2 μm, and 10 μm. , The relationship between the number of copper (Cu) protrusions on the lower layer wiring and the size of the copper (Cu) protrusions on the above contact chain is shown from the measurement results for one semiconductor substrate. . Further, the measurement was performed after the diffusion prevention film was formed. Here, the vertical axis indicates the number of copper (Cu) protrusions in logarithmic display, and the horizontal axis indicates the size of the copper (Cu) protrusion. The black circle is for a rectangular pattern width of 0.8 μm, and the black square is for a rectangular pattern width of 2 μm. Furthermore, the black triangle is for a rectangular pattern width of 10 μm.

  When the size of the protrusion increases, the count number decreases exponentially considering that the vertical axis is logarithmic, and it can be seen that the probability of occurrence of a large protrusion decreases exponentially. For example, looking at the wiring width of 10μm, there is only one protrusion with a protrusion size of about 0.26μm, so the number of protrusions with a protrusion size exceeding 0.26μm is less than one, No more protrusions are generated.

  Note that the copper (Cu) protrusion tends to increase in size as the wiring width increases. Therefore, the upper limit value of the protrusion size depends on the wiring width.

  FIG. 4B shows the relationship between the upper limit value of the protrusion size and the width of the lower layer wiring obtained from FIG. Here, the vertical axis shows the size of the copper (Cu) protrusion, and the horizontal axis shows the lower layer wiring width on the logarithmic axis.

  That is, the graph of FIG. 4B shows that there is an upper limit on the size of the copper (Cu) protrusion, and the upper limit depends on the wiring width. For example, when the width of the rectangular pattern is 10 μm, the upper limit of the size of the copper (Cu) protrusion is about 0.26 μm. Further, when the width of the rectangular pattern is 0.8 μm, the upper limit of the size of the copper (Cu) protrusion is about 0.17 μm. Thereby, it is possible to predict the upper limit value of the size of the copper (Cu) protrusion generated from the lower wiring width.

  FIG. 5 shows the lower layer wiring per square centimeter when the width of the rectangular pattern constituting the upper layer wiring and the contact diameter are fixed and the width of the rectangular pattern constituting the lower layer wiring is 0.8 μm, 2 μm and 10 μm. It shows the relationship between the number of copper (Cu) protrusions generated above, that is, the density of copper (Cu) protrusions generated and the width of the rectangular pattern constituting the wiring. Here, the vertical axis represents the generation density of copper (Cu) protrusions, and the horizontal axis represents the wiring width. Further, the black square indicates the case of sample 1, and the white square indicates the case of sample 2. And it is shown that the generation density of copper (Cu) protrusions increases as the width of the rectangular pattern constituting the wiring increases.

The defect rate of the contact chain will be described when the width of the rectangular pattern constituting the lower layer wiring is 0.8 μm and 10 μm. Here, the vertical axis represents the defect rate, and the horizontal axis represents the type of wiring. When the width of the rectangular pattern is 10 μm , the defect rate exceeds 70%, which is significantly higher than that when the width of the rectangular pattern is 0.8 μm . Here, the contact diameter is fixed at 0.2 μm.

From FIG. 3 (a) to FIG. 3 (c), FIG. 4 (a), FIG. 4 (b), FIG. 5, and the above description , the generation density of copper (Cu) protrusions increases as the width of the lower layer wiring increases. It can be seen that there is a correlation between the increase in the size of the copper (Cu) protrusion and the increase in the defect rate of the contact chain.

  Next, FIG. 7 shows a schematic view of the result of actually observing the cross section of the defective portion by identifying the defective portion in the defective contact chain. The schematic diagram of FIG. 7 shows a semiconductor substrate 20, an insulating layer 21 in which a groove for a lower layer wiring is formed, a lower layer wiring 22, a first diffusion prevention film 24, a first insulating layer 25, and an upper layer wiring. 26, a contact 28, a second diffusion preventing film 29a, a second insulating layer 29b, a copper (Cu) protrusion 27, and a void 23 at a contact portion between the contact 28 and the lower layer wiring 22 are shown. . The void 23 is generated at the place where the copper (Cu) protrusion 27 and the contact 28 overlap each other, and the size of the void 23 is larger than the opening of the contact 28, so that the lower layer wiring 22 and the upper layer wiring 26 are poorly connected. It shows that. Further, it is shown that the copper (Cu) protrusions 27 are not generated in a group but isolated.

As shown in FIG. 7, copper (Cu) projection 27 and the contact 28 are overlapped result, it voids 23 are generated, that Do a failure of the contact chain. From the description of the above paragraphs [0084] and [0085], since the contact diameter is fixed, the increase in the size of the copper (Cu) protrusion 27 and the increase in the number of copper (Cu) protrusions 27 are the contact chain. it is seen Rukoto connected to the increase in the failure rate.

  3A to FIG. 3C, FIG. 4A, FIG. 4B, FIG. 5, FIG. 6, and FIG. 7 are the same as the wiring metal. Even if a metal other than (Cu), such as zirconium (Zr), is used, or a mixed metal or alloy of copper (Cu) and zirconium (Zr) is considered to be generated in the same manner. .

  In the above description, tantalum nitride (TaN) is used as the material for the barrier metal layer. However, it is considered that the above contents are generated in the same manner even in tantalum (Ta).

  Furthermore, although the insulating layer and the interlayer insulating film for forming the trench for the lower layer wiring were composed of the SiO2 layer, the semiconductor insulating resin SiLK made of the SiO2 layer and the organic polymer (manufactured by The Dow Chemical Company) Organic SOG (Spin on glass) layer, silicon nitride (SiN) layer, silicon oxyfluoride (SiOF) layer, silicon oxide carbide (SiOC) layer, silicon carbide (SiC) layer, inorganic SOG (Spin on glass) layer The above contents are considered to occur in the same manner even in an insulating layer made of one or a combination thereof.

  This is because the thermal stress during the formation of the diffusion barrier film between the metal wiring material such as copper (Cu) and the insulating film that forms the groove for the lower layer wiring is considered to occur in the same way, although there is a difference depending on the material. This is because it is presumed that metal protrusions such as copper (Cu) are generated on the surface of the lower layer wiring because the reduction treatment, which is one of the diffusion prevention film forming steps, is performed in the same manner.

  Here, the organic SOG is a coating type low dielectric constant interlayer insulating film material, which is mainly composed of an organic polymer, and the inorganic SOG is a coating type interlayer insulating film material, and an inorganic silicate is used. The main component.

  Next, FIG. 8 shows a plan configuration diagram of a multilayer wiring according to the present embodiment. A pattern indicated by a solid line indicates the upper layer wiring 30, and a pattern indicated by a dotted line indicates the lower layer wiring 33. A hatched area indicates a copper (Cu) protrusion 32 on the lower layer wiring 33, and a white square with an X mark indicates one contact 31 constituting a connection portion. That is, a case is shown in which a relatively thin upper layer wiring 30 is connected to a wide lower layer wiring 33 by a single contact 31 constituting a connecting portion larger than the protrusion.

  Here, the connection portion refers to a portion of the multilayer wiring that exists in a place where the lower layer wiring 33 and the upper layer wiring 30 overlap in a plane and electrically connects the lower layer wiring 33 and the upper layer wiring 30 in the multilayer wiring. , Which consists of one or more contacts.

  Next, FIG. 9 shows a schematic diagram of an A-B cross section in FIG. The schematic diagram of FIG. 9 shows a semiconductor substrate 35, an insulating layer 36 in which a trench for a lower layer wiring is formed, a lower layer wiring 37, a first diffusion prevention film 39, a first insulating layer 40, and an upper layer wiring. 41, a contact 43, a second diffusion prevention film 44a, a second insulating layer 44b, a copper (Cu) protrusion 42, and a void 38 at a contact portion between the contact 43 and the lower layer wiring 37 are shown. . A void 38 is generated at a place where the copper (Cu) protrusion 42 and one contact 43 constituting the connecting portion overlap each other. However, the size of the void 38, that is, the size of the copper (Cu) protrusion 42 is smaller than the opening of the contact 43 constituting the connection portion. Therefore, the contact 43 constituting the connection portion still has a remaining portion other than the void 38 (a contact portion that does not overlap the protrusion), and the connection between the lower layer wiring 37 and the upper layer wiring 41 is maintained by the remaining portion. . The manufacturing process is the same as the cross-sectional structure shown in FIG.

  Therefore, according to the semiconductor device having the multilayer wiring of Example 1, the diameter of the opening of one contact 43 constituting the connection portion is sufficiently larger than the size of the copper (Cu) protrusion 42 based on the investigation by the inventors. Since it is set to be large, the electrical connection between the upper layer wiring 41 and the lower layer wiring 37 is sufficiently possible at the remaining portion other than the protrusions. Therefore, even if the generation density of the copper (Cu) protrusions 42 is increased, the electrical connection between the upper layer wiring 41 and the lower layer wiring 37 is ensured in the remaining part other than the above protrusions, so that the defective rate of wiring connection is reduced. It is estimated that the yield of semiconductor devices is improved.

(Semiconductor insulating resin made of an organic polymer in the insulating film that has a connection part larger than the protrusion, the lower layer wiring is formed by the damascene method, the upper layer wiring is formed by the dual damascene method, and the wiring groove is formed. (Semiconductor device having multi-layer wiring using the material of
In the second embodiment, the lower layer wiring is formed by the so-called damascene method, the upper layer wiring is formed by the so-called dual damascene method, and the connection portion is configured by a contact larger than the protrusion. 1 is a multilayer wiring having a configuration similar to the planar configuration of FIG. However, in the cross-sectional configuration, a semiconductor insulating resin SiLK (manufactured by The Dow Chemical Company) made of an organic polymer is used for the insulating film that forms the groove for the upper wiring and the insulating film that forms the groove for the lower wiring. The structure of the multilayer wiring different from the first embodiment in terms of use is shown.

  A second embodiment will be described with reference to FIGS. 10 (a) to 10 (f). Here, FIG. 10A to FIG. 10F show the sectional structure corresponding to FIG. 9 of the first embodiment in the order of the manufacturing process.

  First, as shown in FIG. 10A, an organic layer is formed on a semiconductor substrate 45 (not limited to a semiconductor substrate, including a lower layer wiring and an insulating layer that covers the lower layer wiring, which are further below the target lower layer wiring). After film formation, heat treatment is performed on the polymer semiconductor insulating resin SiLK (manufactured by The Dow Chemical Company) with a spin coating system, so that the thickness is about 0.15 μm. Then, the first SiLK layer 46 is formed. Next, a first SiO 2 layer 47 is formed by a plasma CVD apparatus so as to have a thickness of about 0.1 μm.

  Next, as shown in FIG. 10B, in order to create a groove for the lower layer wiring 48, after applying a resist, a groove pattern is formed by patterning, and by ion reactive etching, the first SiLK layer 46 and The lower insulating layer made of the first SiO layer 47 is etched to the substrate. Next, a metal material for the lower layer wiring 48 such as copper (Cu) is embedded in the groove to form the lower layer wiring 48. Here, the metal for wiring is embedded by forming a first tantalum (Ta) barrier metal layer 49 having a thickness of about 30 nm by sputtering and then forming copper (Cu) as a seed layer. Using copper as an electrode, the groove is filled with copper (Cu) by electrolytic plating, and an unnecessary first tantalum (Ta) barrier metal layer 49 formed on the lower insulating layer and a metal material such as copper (Cu) are formed. It is formed by removing by CMP.

  Here, copper (Cu) was mainly used as the wiring metal, but zirconium (Zr) or the like can also be used, and a mixed metal or alloy of copper (Cu) and zirconium (Zr) There may be.

  Further, in the above description, tantalum (Ta) is used as the material for the barrier metal layer. However, tantalum nitride (TaN) may be used, and the insulating layer for forming the trench for the lower layer wiring is the first SiLK layer 46 and the first layer. 1 SiO layer 47, including one of the above-mentioned insulating layers, SiO2 layer, SiN layer, SiOF layer, SiOC layer, SiC layer, organic SOG layer, inorganic SOG layer or its An insulating layer made of a combination can also be used.

  Next, as shown in FIG. 10C, in order to form an interlayer insulating film between the lower wiring 48 and the upper wiring 54, first, ammonia (NH3) gas is used for the purpose of reducing the surface oxide of the wiring metal. The SiN layer is formed to a thickness of 0.05 μm as the first diffusion prevention film 50 at a film formation temperature of 300 ° C. to 450 ° C. using a low pressure CVD apparatus. Next, the first interlayer SiO 2 layer 51 is formed to a thickness of 0.4 μm using a plasma CVD apparatus. Therefore, since the interlayer insulating film is composed of the first diffusion preventing film 50 and the first interlayer SiO 2 layer 51, the thickness of the interlayer insulating layer is 0.45 μm.

  Next, in order to form an insulating layer for forming a groove for the upper layer wiring 54, a semiconductor insulating resin SiLK made of an organic polymer is subjected to a heat treatment after film formation in a spin coating film forming apparatus, and is completed. The second SiLK layer 52 is formed so as to have a thickness of about 0.15 μm. Next, a second SiO layer 53a is formed with a plasma CVD apparatus so as to have a thickness of about 0.1 μm. Next, a TiN layer 53b for an etching mask is formed.

  Next, as shown in FIG. 10 (d), in order to form a contact 55 for connecting the upper layer wiring 54 and the lower layer wiring 48, after applying a resist, a groove pattern for the upper layer wiring 54 is formed by patterning. By reactive etching, the TiN layer 53b is etched until the second SiO layer 53a is exposed, and the resist is stripped and removed.

  Next, an opening pattern for the contact 55 is formed by patterning, and the second SiO layer 53a and the second SiLK layer 52 are etched. Thereafter, the resist is peeled off.

  Next, the etching of the second SiO layer 53a using the TiN layer 53b as a mask and the etching of the first interlayer SiO2 layer 51 using the second SiLK layer 52 are performed simultaneously.

  Next, the second SiLK layer 52 is removed by etching. Further, in order to connect with the lower layer wiring 48, the first diffusion preventing film 50 is removed by etching.

  As a result, the groove for the interlayer insulating film and upper layer wiring 54 and the through hole penetrating the insulating film for the contact 55 are formed simultaneously.

  Next, as shown in FIG. 10E, the upper layer wiring 54 and the contact 55 are formed by embedding a metal material for the upper layer wiring 54 in the through hole for the groove and the contact 55. Here, the metal for wiring is buried by forming a second tantalum (Ta) barrier metal layer 56 having a thickness of about 30 nm by sputtering and then forming copper (Cu) as a seed layer, Using the copper (Cu) as an electrode, the inside of the groove is filled with a wiring metal such as copper (Cu) by electrolytic plating, and the TiN layer 53b formed on the insulating layer for forming the groove for the upper layer wiring 54 is unnecessary. The tantalum (Ta) barrier metal layer 56 and the wiring metal such as copper (Cu) are removed by CMP.

  Here, the wiring metal and the barrier metal layer can be selected in the same manner as the lower layer wiring, and the insulating layer forming the interlayer insulating film and the upper layer wiring groove is SiO2, SiN, SiOF, SiOC, SiC, organic The same is true in that the insulating layer can be made of one or a combination of SOG and inorganic SOG.

  Next, as shown in FIG. 10 (f), in order to form an interlayer insulating film between the upper layer wiring 54 and the upper layer wiring, a SiN film and a second interlayer SiO2 film 58 are formed as the second diffusion preventing film 57. Form a film. Thereafter, the process is repeated until a desired number of multilayer wirings are obtained in the same order.

  Also in the semiconductor device having the multilayer wiring shown in the second embodiment, as in the first embodiment, the size of the contact opening is determined based on the result of the investigation shown in the first embodiment. Cu) Set to be larger than the size of the protrusion generated by the movement of atoms. Therefore, even if the density of copper (Cu) protrusions is increased, the electrical connection between the upper layer wiring and the lower layer wiring is ensured in a portion other than the above protrusions, so that the defective rate of wiring connection is reduced and the yield of semiconductor devices is reduced. Is estimated to improve.

(Semiconductor device having a multi-layer wiring having a connecting portion larger than a protrusion, a lower wiring formed by a damascene method, and an upper wiring formed by a damascene method)
The third embodiment is a multi-layer wiring different from the second embodiment in that the lower layer wiring is formed by the so-called damascene method and the upper layer wiring is formed by the so-called damascene method. This will be described with reference to (a) to FIG.

  First, as shown in FIG. 11A, the lower layer wiring 60, the insulating layer for forming the groove for the lower layer wiring, the first diffusion prevention film 62 on the lower layer wiring, and the first interlayer SiO 2 film 61 The first diffusion prevention film 62 and the first interlayer SiO 2 film 61 constitute an interlayer insulating film between the upper layer wiring 68 and the lower layer wiring 60, the forming method, the forming process, the structure, etc. are completely the same as those in the second embodiment. It is similar. Needless to say, the lower layer wiring 60, the barrier metal layer, the insulating layer forming the groove for the lower layer wiring 60, the interlayer insulating film, and the like can be selected in the same manner as in the second embodiment.

  Next, as shown in FIG. 11 (b), in order to form a contact 65 that connects the upper layer wiring 68 and the lower layer wiring 60, after applying the resist 63, an opening pattern is formed by patterning, and reactive ion etching is performed. Then, a through hole for the contact 65 penetrating the interlayer insulating film between the upper layer wiring 68 and the lower layer wiring 60 is formed.

  Next, as shown in FIG. 11C, a metal material for the contact 65 is embedded in the through hole for the contact 65 to form the contact 65. Here, the metal material for the contact 65 is embedded by forming a first tantalum (Ta) barrier metal layer 64 having a thickness of about 30 nm by sputtering and then forming a copper (Cu) layer as a seed layer. A copper (Cu) electrode was used to fill the through hole for the contact 65 with a metal material such as copper (Cu) by electrolytic plating, and was formed on the interlayer insulating layer between the upper wiring 68 and the lower wiring 60 The unnecessary first tantalum (Ta) barrier metal layer and wiring metal such as copper (Cu) are removed by CMP. Needless to say, the material of the barrier metal layer can be selected in the same manner as in the second embodiment. In order to prevent the metal material for the contact 65 from diffusing, a SiN layer of 0.1 μm is formed as the second diffusion preventing film 66.

   Next, as shown in FIG. 11D, the insulating layer for forming the groove for the upper wiring 68 is formed by the same process as in the second embodiment, and the structure is also the same. Needless to say, the insulating layer for forming the groove for the upper wiring 68 can be selected in the same manner as in the second embodiment.

  Next, in order to form a groove for the upper layer wiring 68, after applying a resist, a groove pattern is formed by patterning, and an insulating layer composed of the SiLK layer and the SiO layer is formed on the second diffusion prevention film 66 by ion reactive etching. Etch to the surface. Thereafter, the second diffusion preventing film 66 in the groove for the upper wiring 68 is removed by ion reactive etching.

  Next, as shown in FIG. 11E, a metal material for the upper layer wiring 68 is buried in the groove to form the upper layer wiring 68. Here, the metal for wiring is buried by sputtering a second Ta barrier metal layer 67 having a thickness of about 30 nm by sputtering, and then forming copper (Cu) as a seed layer. ) As an electrode, and the inside of the groove is filled with a wiring metal such as copper (Cu) by electrolytic plating, and an unnecessary second barrier metal layer 67 and copper (which are formed on the insulating layer forming the groove for the upper wiring 68 are formed. It is formed by removing wiring metal such as Cu) by CMP.

  Here, it goes without saying that the second barrier metal layer 67 can be selected in the same manner as the lower layer wiring.

  Next, as shown in FIG. 11F, in order to form an interlayer insulating film between the upper layer wiring 68 and the upper layer wiring, a SiN film and a SiO film are formed as diffusion preventing films. Thereafter, the process is repeated until a desired number of multilayer wirings are obtained in the same order. Needless to say, the material of the interlayer insulating film shown in FIG.

  The planar configuration diagram of the multilayer wiring according to the third embodiment is the same as the planar configuration diagram of the multilayer wiring according to the first embodiment.

  Also in the semiconductor device having the multilayer wiring shown in the third embodiment, as in the first embodiment, the size of the contact opening is determined based on the result of the investigation shown in the first embodiment. It is estimated that even if the copper (Cu) projection generation density is set to be larger than the size of the projection generated by the movement of Cu) atoms, the wiring connection failure rate is lowered and the yield of the semiconductor device is improved.

(A semiconductor device having a multilayer wiring in which a connection portion larger than a protrusion is formed by a plurality of contacts)
In the fourth embodiment, the lower layer wiring is formed by the so-called damascene method or the dual damascene method, and the upper layer wiring is further formed by the so-called damascene method or dual damascene method. Or it is the same as that of Example 3. However, it is different in that a connecting portion for connecting the lower layer wiring and the upper layer wiring is formed by a plurality of contacts.

  A fourth embodiment will be described with reference to FIGS. 12 (a) and 12 (b). Here, FIG. 12A shows a case where the upper layer wiring is connected to a relatively thin lower layer wiring, and FIG. 12B shows a case where the upper layer wiring is connected to a relatively thick lower layer wiring. The pattern indicated by the solid line indicates the upper layer wiring 70, and the pattern indicated by the dotted line indicates the lower layer wiring 71. In addition, a hatched area indicates a copper (Cu) protrusion 73 on a lower layer wiring, and a pattern in which a white square is marked with an X indicates a contact 72. Further, a white circle pattern formed by a plurality of contacts 72 indicates a connection portion 74 that connects the upper layer wiring 70 and the lower layer wiring 71.

  First, FIG. 12A shows a plan configuration diagram of a multilayer wiring according to the present embodiment. Then, the case where the upper layer wiring 70 is connected to the relatively thin lower layer wiring 71 is illustrated. Further, since the lower layer wiring 71 is a relatively thin wiring, the size of the copper (Cu) protrusion 73 is smaller than the case where the lower layer wiring 71 is thick, based on the investigation shown in the first embodiment. Accordingly, the size of the connecting portion 74 is also relatively small, and the number of contacts 72 constituting the connecting portion 74 is four. The four contacts 72 are arranged at the vertices of the quadrangle, and even if the copper (Cu) protrusion 73 and the connection portion 74 overlap, at least one of the four contacts is separated from the copper (Cu) protrusion 73. It has become.

  The connection part 74 of the above embodiment is constituted by the plurality of contacts 72 because the wiring width of the upper layer wiring 70 or the lower layer wiring 71 is small and the wiring interval is narrow, that is, the design rule is reduced. This is because it is assumed that a contact 72 having a small opening is required. And, as described in “Best Mode for Carrying Out the Invention”, when patterning with a photoresist, a contact having a large opening and a contact having a small opening are mixed. This is because there is an inconvenience if the design rule is miniaturized.

  According to the configuration of the above-described connecting portion, the upper limit of the size of the copper (Cu) protrusion 73 increases according to the wiring width from the investigation described in the first embodiment, but the size of the opening of the contact 72 is Even if it is constant, the size of the connecting portion 74 formed by the plurality of contacts 72 can be set to a region larger than the upper limit of the size of the copper (Cu) protrusion 73, and the upper layer wiring 70 and the lower layer wiring The electrical connection of 71 can be sufficiently secured in the remaining portion other than the protrusion.

  Next, FIG. 12B illustrates a case where the lower layer wiring 71 is relatively thick. When the lower layer wiring 71 is thick, the size of the connection portion 74 and the number of contacts 72 constituting the connection portion 74 are five. And points to increase. This is because, as described in the first embodiment, the size of the copper (Cu) protrusion is increased according to the wiring, and therefore the size of the connection portion needs to be increased. Of the five contacts 72, four are arranged at the vertices of the rectangle, and one contact is arranged at the center of the rectangle. Therefore, even if the copper (Cu) protrusion 73 and the connection portion 74 overlap, at least one of the five contacts is positioned away from the copper (Cu) protrusion 73.

  By the way, in the plan views in FIGS. 12A and 12B, the contacts 72 are arranged at the vertices of the quadrangle, but the number of the contacts 72 and the copper (Cu) protrusions 73 are arranged. Various arrangements can be taken according to the size. For example, when the number of contacts is 5, even when the copper (Cu) projection 73 and the connection portion 74 overlap with each other, the at least one contact 72 is separated from the copper (Cu) projection 73 even by arranging at the apex of a regular pentagon. It is possible to satisfy the requirement that the positions are separated from each other.

  In the semiconductor device having the multi-layer wiring connected by the connection portion shown in the fourth embodiment, the region of the connection portion 74 constituted by a plurality of contacts 72 is defined in the first embodiment as in the first embodiment. Based on the results of the survey shown, because it is set to be larger than the size of the protrusion 73 generated by the movement of copper (Cu) atoms generated in the lower layer wiring 71, even if the generation density of copper (Cu) protrusions is increased, It is presumed that the defect rate of wiring connection decreases and the yield of semiconductor devices improves.

  12 (a) and 12 (b) show that the number of contacts 72 remaining on the copper (Cu) protrusion 73 is three, it is necessary to stick to three. Absent.

  This is because only one electrical connection may be required if only the electrical connection relationship is desired. However, if the connection failure after “use for a predetermined time” due to, for example, disconnection of the wiring connection part due to electromigration or the like is also considered, the cause of the failure (for example, from the upper layer wiring 70 to the lower layer wiring 71) It is necessary to determine the number of remaining contacts 72 in consideration of the current flowing through the connection portion and the permissible current in consideration of the time until the wiring breaks).

  Therefore, in general, in consideration of securing the connection after using for a predetermined time, the remaining contact 72 from the copper (Cu) protrusion 73 when the copper (Cu) protrusion 73 and the connection portion 74 overlap each other. , The distance between adjacent contacts 72, and the arrangement of contacts 72.

  Here, electromigration means that metal atoms constituting the metal wiring move due to collision with electrons caused by current flow. Further, the term “electromigration” means that stress migration and other causes are included.

(A semiconductor device having a multilayer wiring in which a connection portion larger than the protrusion is formed of a plurality of contacts and the contact arrangement is linear)
The fifth embodiment is the same as the fourth embodiment in that the lower layer wiring is formed by the so-called damascene method or the dual damascene method, and the upper layer wiring is formed by the so-called damascene method or the dual damascene method. . Therefore, the cross-sectional structure is the same as that of the fourth embodiment. Moreover, the point that the number of contacts constituting the connecting portion is also plural is the same, but the difference is that the arrangement of the contacts is linear.

  A fifth embodiment will be described with reference to FIGS. 13 (a) to 13 (b). Here, FIG. 13A shows a case where the upper layer wiring is connected to a relatively thin lower layer wiring, and FIG. 13B shows a case where the upper layer wiring is connected to a relatively thick lower layer wiring. The pattern indicated by the solid line indicates the upper layer wiring 70, and the pattern indicated by the dotted line indicates the lower layer wiring 71. A hatched area indicates a copper (Cu) protrusion 73 on a lower layer wiring, and a pattern in which a white square is marked with an X indicates a contact 72. Further, a white rectangular pattern constituted by a plurality of contacts 72 indicates a connection portion 74 that connects the upper layer wiring 70 and the lower layer wiring 71.

  First, FIG. 13A shows a plan view of a multilayer wiring according to this embodiment. Here, since the lower layer wiring 71 is a comparatively thin wiring, the size of the copper (Cu) protrusion is smaller than the case where the lower layer wiring 71 is thick from the investigation shown in the first embodiment. Therefore, the size of the connecting portion 74 is also relatively small, and the number of contacts constituting the connecting portion 74 is four.

  The opening of the contact 72 is smaller than the size of the copper (Cu) protrusion 73 on the lower layer wiring. However, the connection portion is composed of N contacts 72 (N is an integer of 2 or more) arranged linearly and continuously, and the center of the Nth contact 72 from the center point of the first contact 72. The distance to the point (hereinafter, the distance between the N contacts) is larger than the size of the copper (Cu) protrusion on the lower layer wiring. Then, even if the connecting portion is arranged at a position overlapping the copper (Cu) protrusion, the distance between the N contacts is determined from the investigation result of Example 1 so that at least one contact is separated from the copper (Cu) protrusion. It is set.

  The direction of the straight line connecting the N contacts does not have to coincide with the direction until the upper layer wiring or the lower layer wiring reaches the connection portion. For example, when the lower layer wiring is wide, the thin upper layer wiring is bent at a right angle immediately after it overlaps the lower layer wiring, so that the connection portion is secured, that is, the overlapping portion of the upper layer wiring and the lower layer wiring is relative to the entry direction of the upper layer wiring And may extend in the vertical direction.

  Next, FIG. 13B shows a plan view of the multilayer wiring according to the present embodiment. Here, since the lower layer wiring 71 is wide, the connection portion 74 is composed of seven contacts 72 arranged linearly and continuously, arranged along the lower layer wiring 71, and at least one contact is made of the copper (Cu ) Indicates that the distance between the N contacts is set so as to be separated from the protrusion.

  The reason why the seven contacts 72 are required is that, as described in the first embodiment, when the lower layer wiring is wide, the size of the copper (Cu) protrusion becomes large, so it is necessary to increase the distance between the N contacts. Because there is.

  Here, the multilayer wiring shown in FIG. 13B has the configuration of the multilayer wiring of FIG. 13A except that the lower layer wiring 71 is thick and the connection portion 73 is configured by seven contacts 72. Is the same.

  In the semiconductor device having the multilayer wiring that is connected to the connection portion 74 shown in the fifth embodiment, the connection portion 74 is configured by arranging a plurality of N contacts 72 in a straight line. The size of the connection 74 is set to be larger than the size of the projection 73 generated by the movement of copper (Cu) atoms generated in the lower layer wiring obtained from the results of the survey shown, and the density of copper (Cu) projection generation Even if it goes up, it is estimated that the defective rate of wiring connection is lowered and the yield of the semiconductor device is improved. Further, since the contacts constituting the connecting portion 74 are arranged in a straight line, the shape of the connecting portion 74 becomes elongated, so that the almost granular copper (Cu) protrusion 73 and the connecting portion 74 can be formed with a small number of contacts 72. In the case of overlapping, the remaining portion on the connection portion 74 side can be secured.

  14A and 14B show a first modification of the fifth embodiment. Here, FIG. 14A shows a case where the upper layer wiring is connected to the relatively thin lower layer wiring. FIG. 14B shows a case where the upper layer wiring is connected to the relatively thick lower layer wiring.

  Here, the pattern indicated by the solid line indicates the upper layer wiring 70, and the pattern indicated by the dotted line indicates the lower layer wiring 71. In addition, a hatched area indicates a copper (Cu) protrusion 73 on the lower layer wiring 71, and a pattern in which a white square is marked with an X indicates a contact 72. Further, the white rectangular pattern formed by the two contacts 72 indicates a connection portion 74 that connects the upper layer wiring 70 and the lower layer wiring 71.

  FIG. 14A is a plan view of a multilayer wiring according to this embodiment. In the multilayer wiring composed of the lower layer wiring 71, the upper layer wiring 70, and the connection part 74, the connection part 74 is composed of two contacts 72, and the distance between the two contacts is the same as that of the first embodiment. Based on the result, when one of the contacts 72 overlaps with the copper (Cu) protrusion 73, the other contact 72 is set so as not to overlap with the copper (Cu) protrusion 73.

  Here, since the width of the lower layer wiring 71 is relatively thin, the size of the copper (Cu) protrusion 73 is relatively small from the result of the investigation described in the first embodiment, and therefore the distance between the two contacts is relatively short. .

  Next, FIG. 14B shows a case where the lower layer wiring 71 constituting the multilayer wiring is relatively thick. When the lower layer wiring 71 is wide, it indicates that the distance between the two contacts 72 constituting the connection portion 74 is set wide.

  This is because, as described in the first embodiment, when the lower layer wiring is wide, the size of the copper (Cu) protrusion is increased.

  In the multilayer wiring having the connecting portion 74 shown in the first modification of the fifth embodiment, by arranging the connecting portion 74 in a straight line with two contacts 72 and setting the distance between the contacts 72, The size of the connecting portion 74 is set to be larger than the size of the protrusion 73 generated by the movement of the copper (Cu) atom generated in the lower layer wiring obtained from the result of the investigation shown in Example 1, and the copper (Cu) It is estimated that the defect rate decreases even when the density of protrusions increases. In addition, by arranging the contacts constituting the connection portion 74 in a straight line, the shape of the connection portion 74 becomes elongated. Therefore, even if the number of the contacts 72 is two, the substantially granular copper (Cu) protrusion 74 and When the connecting portion 74 overlaps, the remaining portion on the connecting portion 74 side can be secured.

  In addition, FIG. 15A, FIG. 15B, and FIG. 15C show a second modification of the fifth embodiment. Compared with the first modification of the fifth embodiment, the pattern shape of the upper layer wiring is shown in various forms in order to take the distance between the contacts constituting the connection portion. ) Shows the case where the upper layer wiring is bent obliquely after entering the lower layer wiring to secure the distance between the contacts, and FIG. 15B shows the case after the upper layer wiring enters the lower layer wiring. Fig. 15 (c) shows a case where the distance between the contacts is ensured by bending at a right angle, and both the upper layer wiring and the lower layer wiring are thin, and the upper layer wiring is bent along the lower layer wiring to ensure the distance between the contacts. Indicates when to do.

  15A to 15C, in either case, the distance between the two contacts is based on the investigation result of Example 1, and either one of the contacts overlaps the copper (Cu) protrusion. In this case, the other contact is set so as not to overlap the protrusion.

  Therefore, in the multilayer wiring, which is the second modification of Example 5 shown in FIG. 15A to FIG. 15C, the defect rate is high even if the generation density of copper (Cu) protrusions is increased. It is estimated that it will go down. Even if the number of the contacts 72 is two, when the substantially granular copper (Cu) protrusion 73 and the connection portion 74 overlap, the remaining portion of the connection portion 74 can be easily secured. Furthermore, the form of the connecting portion 74 of the lower layer wiring 71 and the upper layer wiring 70 can be freely set.

(A semiconductor device in which at least one of the multilayer wirings shown in the first to fifth embodiments is used as a power supply line of the semiconductor device)
The multilayer wiring structure shown in the sixth embodiment is one of the multilayer wirings shown in the first to fifth embodiments in that upper layer wiring and lower layer wiring are formed by a so-called damascene method or dual damascene method. It is the same as one. Therefore, the cross-sectional structure is the same as one of the multilayer wirings shown in the first to fifth embodiments.

  The sixth embodiment is an embodiment in which one of the multilayer wirings shown in the first to fifth embodiments is used to configure the power supply wiring of the semiconductor device.

  Example 6 will be described with reference to FIG.

  First, FIG. 16 is a schematic plan view showing the configuration of the main part of the power supply wiring in the semiconductor chip 80. As shown in FIG. A large number of pads 81 are arranged in the peripheral portion of the semiconductor chip 80, some of which are power pads 84. The power supply pad 84 is connected to the power supply wiring 82 for the ground line or the power supply wiring 83 for the circuit drive voltage. Since the main portion of the power supply wiring needs to pass a large current, it needs to be wider than other wirings. In addition, the main portion of the power supply wiring forms an upper layer wiring, and a semiconductor circuit including transistors formed on the semiconductor substrate uses the lower layer wiring to share the power supply.

  FIG. 17 is an individual semiconductor circuit and a wide wiring, which is an upper layer wiring, a main power wiring 85, and a lower layer wiring for supplying power to the individual semiconductor circuit from the main power wiring 85, A power supply line 88 having a relatively narrow width, a connection portion 90, and a copper (Cu) protrusion 92 on the lower layer wiring are shown.

  As an example of an individual semiconductor circuit, a signal transmission circuit composed of three inverters is shown. Each inverter is composed of a P-channel MOS transistor and an N-channel MOS transistor. Further, each MOS transistor connects the transistor field 87, the transistor gate 86, the signal output line 89 composed of the lower layer wiring, the field contact 93 connecting the transistor field 87 and the lower layer wiring, and the transistor gate 86 and the lower layer wiring. And a gate contact 94. Here, an inverter refers to a circuit that inverts and amplifies an input signal to generate an output signal.

  The connection portion 90 is formed at a crossing portion between the power supply line 88 of each transistor and the main power supply wiring 85, and is formed of a plurality of contacts 91. Further, even when a part of the contact 91 constituting the connecting portion 90 overlaps the copper (Cu) protrusion, at least one of the other contacts 91 is arranged so as not to overlap the protrusion. It is set from the survey results.

  That is, one multilayer wiring structure of the first to fifth embodiments is applied to connect the upper layer wiring and the lower layer wiring constituting the power supply wiring.

  According to the semiconductor device of the sixth embodiment, one of the multilayer wiring structures of the first to fifth embodiments is applied to the configuration of the power supply wiring. Even if the copper (Cu) protrusion is generated, there is an effect that the probability that the connection between the upper layer wiring and the lower layer wiring becomes defective becomes very low. Therefore, a semiconductor device can be manufactured with high yield.

(Semiconductor device in which at least one of the multilayer wiring embodiments of the first to fifth embodiments is used for the clock signal wiring of the semiconductor device)
The multilayer wiring structure shown in the seventh embodiment is similar to one of the first to fifth embodiments in that the upper layer wiring and the lower layer wiring are formed by the so-called damascene method or dual damascene method. Accordingly, the cross-sectional structure is the same as that of one of the first to fifth embodiments.

  The seventh embodiment is an embodiment in which one of the multilayer wirings shown in the first to fifth embodiments is used to configure the clock signal wiring of the semiconductor device.

  Example 6 will be described with reference to FIG.

  First, FIG. 18 is a schematic plan view showing a semiconductor chip 98, a clock signal wiring 96, a clock signal generation circuit 97, and a pad 95.

  The clock signal generated by the clock generation circuit 97 composed of a transistor or the like on the semiconductor chip 98 is used to adjust the timing of data input / output between circuits in the semiconductor chip 98 and to the outside of the semiconductor chip 98. It is used in most circuits on a semiconductor chip to adjust the timing of data input / output.

  The clock signal wiring 96 is composed of an upper layer wiring and a lower layer wiring depending on the situation, and one of the multilayer wirings of the first to fifth embodiments is used to connect the upper layer wiring and the lower layer wiring. in use.

  This is because it is very difficult to configure the clock signal wiring 96 with a single layer wiring because of the wiring layout.

  According to the semiconductor device of the seventh embodiment, the clock signal wiring 96 is configured because one multilayer wiring of the first to fifth embodiments is applied to the configuration of the clock signal wiring 96. Even if copper (Cu) protrusions are generated in the lower layer wiring, there is an effect that the probability that the connection between the upper layer wiring and the lower layer wiring becomes defective becomes very low.

  Therefore, a semiconductor device can be manufactured with high yield.

Hereinafter, the features of the invention described in this specification will be added.
(Appendix 1)
A first insulating layer;
Lower layer wiring,
A diffusion barrier film on the lower wiring;
A second insulating layer on the diffusion barrier film;
With upper layer wiring,
The lower layer wiring is composed of a conductor embedded in a groove in the first insulating layer,
The lower layer wiring has a protrusion formed due to the formation of the diffusion prevention film,
The lower layer wiring and the upper layer wiring are connected by a connection portion larger than the protrusion.
(Appendix 2)
In the semiconductor device described in Appendix 1,
The connecting portion is composed of a plurality of adjacent contacts,
The contact reaches the lower layer wiring in the second insulating layer and in the diffusion prevention film, and is smaller than the connection portion and has a through hole having a uniform opening shape,
A semiconductor device comprising a conductor embedded in the through hole.
(Appendix 3)
In the semiconductor device described in Appendix 1,
When the connecting portion is disposed on the protrusion,
The remaining portion of the connecting portion from the protrusion ensures the connection between the lower layer wiring and the upper layer wiring after use for a predetermined time.
(Appendix 4)
A first insulating layer;
Lower layer wiring,
A diffusion barrier film on the lower wiring;
A second insulating layer on the diffusion barrier film;
With upper layer wiring,
It is composed of a conductor embedded in the groove in the first insulating layer in the lower layer wiring,
The lower layer wiring has a protrusion formed due to the formation of the diffusion prevention film,
The lower layer wiring and the upper layer wiring are connected by a connecting portion,
When the connecting portion is disposed on the protrusion,
The connecting portion has a remaining portion from the protrusion;
The semiconductor device is characterized in that the connection between the lower layer wiring and the upper layer wiring is ensured by the remaining portion of the connection portion.
(Appendix 5)
A first insulating layer;
A lower layer wiring and a diffusion preventing film on the lower layer wiring;
A second insulating layer on the diffusion barrier film;
With upper layer wiring,
The lower layer wiring is composed of a conductor embedded in a groove in the first insulating layer,
The lower layer wiring has a protrusion formed during the step of forming the diffusion prevention film,
The lower layer wiring and the upper layer wiring are composed of a plurality of adjacent contacts, and are connected by a connection portion larger than the protrusion,
The contact is composed of a through hole reaching the lower layer wiring in the second insulating layer and the diffusion prevention film, and a conductor embedded in the through hole,
The connecting portion has an arrangement of the contacts in which, when one of the contacts in the plurality of contacts is formed on the protrusion, at least one of the other contacts is separated from the protrusion. A semiconductor device characterized by the above.
(Appendix 6)
In the semiconductor device of appendix 5,
The semiconductor device according to claim 1, wherein the plurality of adjacent contacts constituting the connection portion are linearly arranged.
(Appendix 7)
In the semiconductor device of appendix 5,
The semiconductor device according to claim 1, wherein a connection between the lower layer wiring and the upper layer wiring after use for a predetermined time is ensured by the contact located at a position away from the protrusion.
(Appendix 8)
A first insulating layer;
A lower layer wiring and a diffusion preventing film on the lower layer wiring;
A second insulating layer on the diffusion barrier film;
With upper layer wiring,
The lower layer wiring is composed of a conductor embedded in a groove in the first insulating layer,
The lower layer wiring has a protrusion formed during the step of forming the diffusion prevention film,
The lower layer wiring and the upper layer wiring are composed of a plurality of adjacent contacts, and are connected by a connection portion larger than the protrusion,
The contact is composed of a through hole reaching the lower layer wiring in the second insulating layer and the diffusion prevention film, and a conductor embedded in the through hole,
When one of the plurality of contacts constituting the connecting portion is formed on the projection, the contact is arranged such that at least one of the other contacts is separated from the projection. A semiconductor device characterized by setting a distance between them.
(Appendix 9)
A first insulating layer;
A lower layer wiring and a diffusion preventing film on the lower layer wiring;
A second insulating layer on the diffusion barrier film;
With upper layer wiring,
The lower layer wiring is composed of a conductor embedded in a groove in the first insulating layer,
The lower layer wiring has a protrusion formed during the step of forming the diffusion prevention film,
The lower layer wiring and the upper layer wiring are composed of a plurality of adjacent contacts, and are connected by a connection portion larger than the protrusion,
The contact is composed of a through hole reaching the lower layer wiring in the second insulating layer and the diffusion prevention film, and a conductor embedded in the through hole,
When one of the plurality of contacts constituting the connection portion is formed on the protrusion, at least one of the other contacts is formed at a position away from the protrusion.
A semiconductor device characterized in that a distance between adjacent contacts constituting the connection portion is set according to a thickness of a lower layer wiring.
(Appendix 10)
In the semiconductor device of appendix 8,
The semiconductor device according to claim 1, wherein a connection between the lower layer wiring and the upper layer wiring after use for a predetermined time is ensured by the contact located at a position away from the protrusion.
(Appendix 11)
In the semiconductor device described in appendices 1, 4, 5, 8, and 9,
The conductor constituting the lower layer wiring is composed of a barrier metal layer and a wiring metal.
(Appendix 12)
In the semiconductor device described in appendices 1, 4, 5, 8, and 9,
The conductor constituting the lower layer wiring is composed of a barrier metal layer and a wiring metal,
The semiconductor device characterized in that the first insulating layer and the second insulating layer are composed of at least one of SiN, SiOF, SiOC, and SiC.
(Appendix 13)
In the semiconductor devices of appendices 11 and 12,
The wiring metal is made of at least one of copper and zirconium (Zr), and the barrier metal layer is made of at least one of tantalum and tantalum nitride. A semiconductor device.
(Appendix 14)
In the semiconductor devices described in Appendix 1 to Appendix 11 and 13,
The semiconductor device according to claim 1, wherein the first insulating layer and the second insulating layer are made of at least one material of SiN, SiOF, SiOC, and SiC.
(Appendix 15)
A first insulating layer; a lower layer wiring composed of a conductor embedded in a groove in the first insulating layer; a diffusion prevention film on the lower layer wiring; and a second insulation on the diffusion prevention film In a semiconductor device comprising a layer and an upper layer wiring,
The lower layer wiring has a protrusion formed due to the formation of the diffusion prevention film,
The lower layer wiring and the upper layer wiring are connected by a connecting portion comprising a plurality of adjacent contacts,
The contact is composed of a through hole reaching the lower layer wiring in the second insulating layer and the diffusion prevention film, and a conductor embedded in the through hole,
The connecting portion has an arrangement of the contacts in which, when one of the contacts in the plurality of contacts is formed on the protrusion, at least one of the other contacts is located away from the protrusion. A semiconductor device.
(Appendix 16)
In the semiconductor device described in Appendix 15,
The upper layer wiring and the lower layer wiring constitute a power supply wiring.
(Appendix 17)
In the semiconductor device described in Appendix 15,
The semiconductor device further includes a clock generation circuit,
The lower layer wiring and the upper layer wiring constitute a clock signal line.

These are the figures explaining the chain comprised from the wiring and contact which concern on Example 1. FIG. These are EF sectional drawing explaining the chain comprised from the wiring and contact which concern on Example 1. FIG. (A) is a top view which shows the 0.8 micrometer chain sample comprised from the wiring and contact which concern on Example 1. FIG. FIG. 3B is a plan view showing a 2 μm chain sample composed of wirings and contacts according to the first embodiment. FIG. 3C is a plan view showing a 10 μm chain sample composed of wirings and contacts according to the first embodiment. (A) is a graph showing the number of protrusions vs. the size of protrusions on various chain samples, which are composed of wires and contacts according to Example 1. FIG. FIG. 4B is a graph showing the sizes of various protrusions on the chain sample vs. the wiring width, which are composed of the wirings and contacts according to the first embodiment. FIG. 4 is a graph showing the number of protrusions on various chain samples per one semiconductor substrate, which is composed of wirings and contacts according to Example 1. FIG. These are the graphs which show the defect rate on the various chain samples comprised from the wiring and contact which concern on Example 1. FIG. These are sectional drawings explaining the contact defect of the various chain samples comprised from the wiring and contact which concern on Example 1. FIG. These are top views explaining Example 1. FIG. These are sectional drawings explaining Example 1. FIG. (A), (b), (c), (d), (e), (f) is a figure explaining Example 2 for every process. (A), (b), (c), (d), (e), (f) is a figure explaining Example 3 for every process. (A) is a figure explaining Example 4 about thin wiring. FIG. 12B is a diagram for explaining the fourth embodiment for thick wiring. (A) is a figure explaining Example 5 about thin wiring. FIG. 13B is a diagram illustrating Example 5 for thick wiring. (A) is a figure explaining Example 6 about thin wiring. FIG. 14B is a diagram illustrating Example 6 for thick wiring. (A) is a figure explaining the modification 1 of Example 6. FIG. FIG. 15B is a diagram illustrating a second modification of the sixth embodiment. FIG. 15C is a diagram for explaining a third modification of the sixth embodiment. These are figures explaining the semiconductor device of Example 7. FIG. These are the figures explaining the connection between the power supply wiring which concerns on Example 7. FIG. These are diagrams for explaining the semiconductor device of Example 8. FIG. (A), (b), (c), (d), (e), (f) is sectional drawing explaining a 1st prior art example. These are top views explaining the second conventional example. (A), (b), (c) is sectional drawing of a wafer effective area | region and a wafer ineffective area | region (peripheral part) explaining the 3rd prior art example. (A) is a top view explaining the via chain pattern of the 4th prior art example. FIG. 22B is a cross-sectional view taken along line AB of the via chain pattern of the fourth conventional example.

Explanation of symbols

1 Contact 2 Upper layer wiring 3 Lower layer wiring 5 Semiconductor substrate 6 Lower layer insulating layer 7 Lower layer wiring 8 Barrier metal layer 9 Contact
10 First diffusion barrier film
11 First insulating film
12 Upper wiring
13 Second diffusion barrier film
14 Second insulating film
15, 16, 17 Lower layer wiring
18, 19 contacts
20 Semiconductor substrate
21 Insulating layer
22 Lower layer wiring
23 void
24 First diffusion barrier
25 First insulating layer
26 Upper layer wiring
27 Copper (Cu) protrusion
28 contacts
29a Second diffusion barrier
29b Second insulation layer
30 Upper layer wiring
31 contacts
32 Copper (Cu) protrusion
33 Lower layer wiring
35 Semiconductor substrate
36 Insulation layer
37 Lower layer wiring
38 void
39 First diffusion barrier
40 First insulation layer
41 Upper layer wiring
42 Copper (Cu) protrusion
43 Contacts
44a Second diffusion barrier film
44b Second insulating layer
45 Semiconductor substrate
46 First SiLK layer
47 First SiO2 layer
48 Lower layer wiring
49 First tantalum (Ta) barrier metal layer
50 First diffusion barrier film
51 First interlayer SiO2 layer
52 Second diffusion barrier film
53a Second SiO2 layer
53b TiN film
54 Upper wiring
55 contacts
56 Second tantalum (Ta) barrier metal layer
57 Second diffusion barrier film
58 Second interlayer SiO2 layer
60 Lower layer wiring
61 First interlayer SiO2 layer
62 First diffusion barrier film
63 resist
64 First tantalum (Ta) barrier metal layer
65 contacts
66 Second diffusion barrier film
67 Second tantalum (Ta) barrier metal layer
68 Upper wiring
70 Upper wiring
71 Lower layer wiring
72 contacts
73 Copper (Cu) protrusion
74 Connection
80 Semiconductor chip
81 pads
82 Power supply wiring for ground line
83 Power supply wiring for circuit drive voltage
84 Power pad
85 Core power wiring
86 transistor gate
87 Transistor field
88 Power supply line
89 Signal output line
90 connections
91 contacts
92 Copper (Cu) protrusion
93 Field contact
94 Gate contact
95 pads
96 Clock signal wiring
97 Clock signal generator
98 Semiconductor chip
101 Silicon substrate
102 SiO2 insulation layer
103 photoresist
104 Barrier metal
105 Wiring material
106 Copper (Cu) wiring
107 First insulating film
108 Second insulating film
109 Insulation layer
115 Wiring groove
116 Insulating layer leaving pattern
117 Damascene wide wiring
118 Via hole
119 Metal grain boundaries
120 groundwork
121 First etching stopper layer
122 First insulating layer
123 Photoresist layer
124 First barrier metal layer
125 First main wiring layer
126 Second insulation layer
127 Third etching stopper layer
128 3rd insulation layer
129 Second photoresist layer
130 Second etching stopper layer
135 Lower layer wiring
136 contacts
137 Upper layer wiring
138 arrow

Claims (9)

A first insulating layer;
Lower layer wiring,
A diffusion barrier film on the lower wiring;
A second insulating layer on the diffusion barrier film;
With upper layer wiring,
The lower layer wiring is composed of a conductor embedded in a groove in the first insulating layer,
The lower layer wiring has a protrusion formed above the surface of the first insulating layer and formed due to the formation of the diffusion prevention film;
The upper wiring and the lower wiring is embedded in the largest the projection greater than the through hole and the through-hole reaching said lower wiring of the diffusion preventing film and the second insulating layer among said protrusions A semiconductor device connected by a contact made of a conductor . A first insulating layer;
Lower layer wiring,
A diffusion barrier film on the lower wiring;
A second insulating layer on the diffusion barrier film;
With upper layer wiring,
The lower layer wiring is composed of a conductor embedded in a groove in the first insulating layer,
The lower layer wiring has a protrusion formed above the surface of the first insulating layer and formed due to the formation of the diffusion prevention film;
The lower layer wiring and the upper layer wiring are connected by a plurality of adjacent contacts ,
The contact is composed of a through hole reaching the lower layer wiring in the second insulating layer and the diffusion prevention film, and a conductor embedded in the through hole,
At least one of the contacts in the plurality of contacts is formed on the protrusion, and at least one of the other contacts has the contact arrangement at a position spaced from the protrusion. . A first insulating layer;
A diffusion barrier film on the lower wiring;
A second insulating layer on the diffusion barrier film;
With upper layer wiring,
The lower layer wiring is composed of a conductor embedded in a groove in the first insulating layer,
The lower layer wiring has a protrusion formed above the surface of the first insulating layer and formed due to the formation of the diffusion prevention film;
The lower layer wiring and the upper layer wiring are connected by a plurality of adjacent contacts ,
The contact is composed of a through hole reaching the lower layer wiring in the second insulating layer and the diffusion prevention film, and a conductor embedded in the through hole,
At least one of the contacts in the plurality of contacts is formed on the protrusion, and at least one of the other contacts is formed at a position spaced from the protrusion;
A semiconductor device characterized in that a distance between adjacent contacts is set according to a thickness of a lower layer wiring. The conductor constituting the lower layer wiring is composed of a barrier metal layer and a wiring metal,
The said 1st insulating layer and the said 2nd insulating layer are comprised from at least 1 or more of SiN, SiOF, SiOC, SiC, The any one of Claims 1-3 characterized by the above-mentioned. A semiconductor device according to 1. A plurality of the protrusions are formed,
  Among the plurality of protrusions, the protrusion formed under the contact has a cavity formed therein,
  The semiconductor device according to claim 1, wherein among the plurality of protrusions, the protrusion separated from the contact is made of the conductor of the lower layer wiring. Forming a first insulating layer;
Forming a groove in the first insulating layer, filling the groove with a conductor to form a lower layer wiring;
Forming a diffusion barrier film on the lower wiring;
Forming a second insulating layer on the diffusion barrier film;
During the step of forming the diffusion preventive film, a protrusion is formed so as to protrude above the surface of the first insulating layer, and the lower layer in the second insulating layer and the diffusion preventive film Forming a through hole reaching the wiring with a diameter larger than the largest projection among the projections, and burying a conductor in the through hole to form a contact;
Forming an upper wiring on the second insulating layer so as to be connected to the contact;
A method for manufacturing a semiconductor device, comprising: Forming a first insulating layer;
Forming a groove in the first insulating layer, filling the groove with a conductor to form a lower layer wiring;
Forming a diffusion barrier film on the lower wiring;
Forming a second insulating layer on the diffusion barrier film;
During the step of forming the diffusion preventive film, a protrusion is formed so as to protrude above the surface of the first insulating layer, and the lower layer in the second insulating layer and the diffusion preventive film A plurality of through-holes reaching the wiring are formed such that at least one of the through-holes is formed on the protrusion, and at least one of the other through-holes is arranged to be spaced from the protrusion. , Forming a contact by embedding a conductor in the through hole;
Forming an upper layer wiring on the second insulating layer so as to be connected to the plurality of contacts;
A method for manufacturing a semiconductor device, comprising: The conductor constituting the lower layer wiring is composed of a barrier metal layer and a wiring metal,
The semiconductor device according to claim 6, wherein the first insulating layer and the second insulating layer are composed of at least one of SiN, SiOF, SiOC, and SiC. Manufacturing method.   A plurality of the protrusions are formed,
  Among the plurality of protrusions, the protrusion formed under the contact has a cavity formed therein,
  9. The method of manufacturing a semiconductor device according to claim 6, wherein, of the plurality of protrusions, the protrusion separated from the contact is made of the conductor of the lower layer wiring. 10. .

Images