JP4338937B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device using a thin film transistor (hereinafter referred to as TFT) using a semiconductor film having a crystal structure formed over a substrate, and a method for manufacturing the semiconductor device. Note that a semiconductor device in this specification refers to all devices that function by utilizing semiconductor characteristics, and a semiconductor device manufactured according to the present invention is a display device represented by a liquid crystal display device incorporating a TFT, a semiconductor integrated circuit, or the like. (Microprocessor, signal processing circuit, high frequency circuit, etc.) are included in the category.
[0002]
[Prior art]
In various semiconductor devices including a semiconductor element such as a television receiver, a personal computer, and a mobile phone, a display for displaying characters and images is indispensable as a means for recognizing information by humans. In particular, a flat panel display (flat panel display) typified by a liquid crystal display device using the electro-optical characteristics of liquid crystal has been actively used recently.
[0003]
As one form of a flat panel display, an active matrix driving method is known in which a TFT is provided for each pixel and a video signal is displayed by sequentially writing data signals. The TFT is an essential element for realizing the active matrix driving method.
[0004]
Most TFTs are made using amorphous silicon, but the field effect mobility is low, and it was impossible to operate at the frequency required to process video signals. It was used only as a switching element provided for each pixel. The data line side drive circuit that outputs video signals to the data lines and the scan line side drive circuit that outputs scanning signals to the scanning lines are external ICs mounted by TAB (Tape Automated Bonding) or COG (Chip on Glass) ( Driver IC).
[0005]
However, since the pixel pitch decreases as the pixel density increases, it is considered that the method for mounting the driver IC has a limit. For example, assuming UXGA (the number of pixels is 1200 × 1600), the RGB color method requires 6000 connection terminals even if simply estimated. An increase in the number of connection terminals causes an increase in the probability of contact failure. In addition, the area (frame area) in the peripheral portion of the pixel portion increases, which becomes a factor that impairs the miniaturization and appearance design of a semiconductor device that uses the area. From such a background, the necessity of a display device integrated with a drive circuit has become clear. By integrally forming the pixel portion and the scanning line side and data line side driving circuits on the same substrate, the number of connection terminals can be drastically reduced and the area of the frame region can also be reduced.
[0006]
As means for realizing this, a method of forming a TFT with a polycrystalline silicon film has been proposed. However, even if a TFT is formed using polycrystalline silicon, its electrical characteristics are not comparable to those of a MOS transistor formed on a single crystal silicon substrate. For example, the field effect mobility is 1/10 or less of single crystal silicon. In addition, there is a problem that off-current increases due to defects formed at the grain boundaries.
[0007]
Nevertheless, the data line side driving circuit has a high driving capability (ON current, I _on ) And the hot carrier effect to prevent deterioration and improve reliability, while the pixel portion has a low off-current (I _off ) Is required.
[0008]
A lightly doped drain (LDD) structure is known as a TFT structure for reducing the off-current value. In this structure, an LDD region to which an impurity element is added at a low concentration is provided between a channel formation region and a source region or a drain region formed by adding an impurity element at a high concentration. Further, as an effective structure for preventing deterioration of the on-current value due to hot carriers, an LDD structure in which a part of the LDD region overlaps the gate electrode (hereinafter referred to as GOLD by omitting Gate-drain Overlapped LDD) is known. Yes.
[0009]
[Problems to be solved by the invention]
A TFT is manufactured by stacking a semiconductor film, an insulating film, or a conductive film while etching them into a predetermined shape using a photomask. However, if the structure of the TFT is optimized in order to obtain the characteristics required for the pixel portion and each drive circuit, the number of photomasks increases, the manufacturing process becomes complicated, and the number of processes inevitably increases.
[0010]
It is another object of the present invention to provide a technique for improving TFT characteristics and realizing a TFT having a structure optimal for driving conditions of a pixel portion and a driving circuit with a small number of photomasks.
[0011]
[Means for Solving the Problems]
In order to solve the above problems, a thin film transistor included in a semiconductor device of the present invention includes a semiconductor film, a first electrode, and a first insulating film sandwiched between the semiconductor film and the first electrode. And a second electrode and a second insulating film sandwiched between the semiconductor film and the second electrode. The first electrode and the second electrode overlap with each other with a channel formation region included in the semiconductor film interposed therebetween.
[0012]
In the present invention, reduction of off current is more important than increase of on current. For example, in the case of a TFT formed as a switching element in a pixel portion of a semiconductor device, a constant voltage (common common) is applied to the first electrode. Voltage). Note that this constant voltage is smaller than the threshold value in the case of an n-channel TFT and larger than the threshold value in the case of a p-channel TFT.
[0013]
By applying a common voltage to the first electrode, variation in threshold value can be suppressed as compared with a case where there is one electrode, and off-state current can be suppressed.
[0014]
In the present invention, an increase in on-current is more important than reduction in off-current. For example, in the case of a TFT included in a buffer of a driving circuit of a semiconductor device, the same voltage is applied to the first electrode and the second electrode. Apply.
[0015]
Note that in this specification, a driver circuit is a circuit for generating a signal for displaying an image on a pixel portion, and includes a data line driver circuit and a scan line driver circuit.
[0016]
By applying the same voltage to the first electrode and the second electrode, the depletion layer spreads quickly as if the film thickness of the semiconductor film was substantially reduced, so the subthreshold coefficient (S value) was reduced. In addition, field effect mobility can be improved. Therefore, the on-current can be increased as compared with the case of one electrode. Therefore, the driving voltage can be lowered by using the TFT having this structure in the driving circuit. In addition, since the on-current can be increased, the TFT size (especially the channel width) can be reduced. Therefore, the integration density can be improved. Further, interfacial scattering can be suppressed and the transconductance (gm) can be increased.
[0017]
A circuit diagram of the thin film transistor of the present invention will be described with reference to FIG. Here, only a p-channel TFT is typically shown. In the case of an n-channel TFT, the direction of the arrow is opposite to that of a p-channel TFT. FIG. 31A is a circuit diagram of a general thin film transistor having only one electrode. FIG. 31B is a circuit diagram of a thin film transistor of the present invention, which includes two electrodes with a semiconductor film interposed between them and a constant voltage (here, ground voltage) is applied to one of the electrodes. is there. FIG. 31C is a circuit diagram of a thin film transistor of the present invention which includes two electrodes with a semiconductor film interposed therebetween and in which the two electrodes are electrically connected to each other. In the following description of the present invention, the circuit diagram shown in FIG. 31 is used.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described with reference to FIG. In FIG. 1A, a first electrode 11 is formed over a substrate 10 having an insulating surface. The 1st electrode 11 should just be formed with the substance which has electroconductivity. Typically, it can be formed of one or more alloys or compounds selected from aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), and titanium (Ti). Alternatively, a stack of several conductive films may be used as the first electrode. The first electrode 11 has a thickness of 150 to 400 nm.
[0019]
A first insulating film 12 is formed so as to cover the first electrode 11. Note that in this embodiment mode, a stack of two insulating films (first insulating film A 12 a and first insulating film B 12 b) is used as the first insulating film 12. In FIG. 1, the first insulating film A 12a is formed of a silicon oxynitride film or a silicon nitride film with a thickness of 10 to 50 nm. The first insulating film B 12b is formed using a silicon oxynitride film or a silicon oxide film with a thickness of 0.5 to 1 μm. When a silicon oxynitride film is used, SiH is formed by plasma CVD. _Four , NH _Three , N ₂ A film made of a mixed gas of O and containing 20 to 40 atomic% nitrogen in the film is applied. By using a nitrogen-containing insulating film such as a silicon oxynitride film or a silicon nitride film, diffusion of impurities such as alkali metal from the substrate 10 side can be prevented.
[0020]
The surface of the first insulating film 12 may have unevenness caused by the first electrode 11 formed in advance. The unevenness is flattened by polishing the surface. As a planarization method, chemical-mechanical polishing (hereinafter referred to as CMP) can be given. As the CMP polishing slurry (slurry) for the first insulating film 12, for example, fumed silica particles obtained by thermally decomposing silicon chloride gas in a KOH-added aqueous solution may be used. The first insulating film is removed by about 0.1 to 0.5 μm by CMP to flatten the surface. Note that the surface of the first insulating film is not necessarily polished. The planarized first insulating film preferably has a height difference of unevenness of 5 nm or less on the surface, and more preferably 1 nm or less. By improving the flatness, the first insulating film used as a gate insulating film to be formed later can be thinned, and the mobility of the TFT can be improved. In addition, when flatness is improved, off current can be reduced when a TFT is manufactured.
[0021]
A semiconductor film 13 is formed on the first insulating film 12 whose surface is planarized. The semiconductor film 13 includes a channel formation region 18 and an impurity region 19 that sandwiches the channel formation region 18. A second insulating film 14 is formed on the semiconductor film 13, and a second electrode 15 is formed on the semiconductor film 13 with the second insulating film 14 interposed therebetween.
[0022]
The first electrode 11 and the second electrode 15 overlap each other with the channel formation region 18 interposed therebetween.
[0023]
In addition, the third insulating film 16 and the wiring 17 are provided as necessary.
[0024]
The first electrode 11 and the second electrode 15 may be electrically connected, or a common voltage may be applied to either one of the electrodes.
[0025]
In FIG. 1A, a cross-sectional view taken along line AA ′ in the case where the first electrode 11 and the second electrode 15 are directly connected is shown in FIG.
[0026]
As shown in FIG. 1B, the first electrode 11 and the second electrode 15 are outside the semiconductor film 13, and contact holes 21 formed in the first insulating film 12 b and the second insulating film 14 are formed. Connected through.
[0027]
1A is a cross-sectional view taken along line AA ′ in the case where the first electrode 11 and the second electrode 15 are connected by a wiring 24 formed of the same conductive film as the wiring 17 in FIG. Shown in (C).
[0028]
As shown in FIG. 1C, the first electrode 11 and the wiring 24 are connected to each other through a contact hole 23 formed in the first insulating film 12b, the second insulating film 14, and the third insulating film 16. Connected. Further, the second electrode 15 and the wiring 24 are connected through a contact hole 22 formed in the third insulating film 16.
[0029]
Note that the manner of electrical connection between the first electrode 11 and the second electrode 15 is not limited to the structure illustrated in FIGS. 1B and 1C.
[0030]
The film thickness to be removed by CMP is determined in consideration of the thickness of the first insulating film 12 and its dielectric constant and the thickness of the second insulating film 14. The film remaining here substantially functions as a gate insulating film. Accordingly, when the first insulating film is formed by stacking a plurality of insulating films, only the uppermost insulating film may be polished on the first electrode 11 or the lower insulating film may be exposed. You may grind so that it may.
[0031]
For example, when the first insulating film A 12a and the first insulating film B 12b are formed of a silicon oxynitride film and have a dielectric constant of 7.5, and the second insulating film 14 is formed of a silicon oxide film, the dielectric is used. The rate is 3.9, and there is a difference between the two. In that case, the finished dimensions after CMP may be set such that the thickness of the first insulating film 12 is 150 nm and the thickness of the second insulating film 14 is 110 nm.
[0032]
By applying a common voltage to the first electrode, variation in threshold value can be suppressed as compared with a case where there is one electrode, and off-state current can be suppressed.
[0033]
As the TFT, a top gate type (planar type) and a bottom gate type (reverse stagger type) are known depending on the arrangement of a semiconductor film, a gate insulating film, and a gate electrode. In any case, in order to reduce the subthreshold coefficient, it is necessary to reduce the thickness of the semiconductor film. When a semiconductor film obtained by crystallizing an amorphous semiconductor film to be used in a TFT is applied, the amorphous semiconductor film becomes thin and the crystallinity deteriorates, and the effect of purely reducing the film thickness is obtained. I can't. However, the thickness of the semiconductor film was substantially reduced by electrically connecting the first electrode and the second electrode and overlapping the two electrodes above and below the semiconductor film as shown in FIG. In the same manner as described above, depletion occurs quickly with application of voltage, field effect mobility and subthreshold coefficient can be reduced, and on-current can be increased.
[0034]
Note that when the first electrode 11 and the second electrode 15 are electrically connected, the closer the dielectric constants of the first insulating film 12 and the second insulating film 14 are, the closer the field effect mobility is. In addition, the subthreshold coefficient can be reduced and the on-current can be increased.
[0035]
Further, in the portion where the first electrode 11 and the channel formation region overlap, the thickness when the thickness of the first insulating film 12 film is uniform, the second electrode 15 and the channel formation region, When the thickness of the second insulating film 14 is uniform in the overlapping portion, the closer the film thickness is, the smaller the field effect mobility and the subthreshold coefficient, and the larger the on-current. Can do. If the thickness of the first insulating film in the portion overlapping the first electrode 11 is d1, and the thickness of the second insulating film in the portion overlapping the second electrode 15 is d2, | d1-d2 | / d1 ≦ It is 0.1 and it is desirable to satisfy | d1-d2 | /d2≦0.1. More preferably, | d1-d2 | /d1≦0.05, and it is preferable that | d1-d2 | /d2≦0.05 is satisfied.
[0036]
Most preferably, in the state where the first electrode 11 and the second electrode 15 are not electrically connected, the threshold value of the thin film transistor when a ground voltage is applied to the first electrode 11, The threshold value of the thin film transistor when the ground voltage is applied to the electrode 15 is made substantially the same, and then the first electrode 11 and the second electrode 15 are electrically connected. By doing so, the field-effect mobility and the subthreshold coefficient can be further reduced, and the on-current can be further increased.
[0037]
By adopting such a structure, channels (dual channels) can be formed above and below the semiconductor film, and the characteristics of the TFT can be improved.
[0038]
In addition, a wiring for transmitting various signals or power simultaneously with the first electrode 11 can be formed. Further, when combined with the planarization treatment by CMP, there is no influence on the semiconductor film formed on the upper layer. Further, high density wiring can be realized by multilayer wiring. Hereinafter, a specific example applied to an active matrix driving display device will be described according to an embodiment.
[0039]
【Example】
(Example 1)
A manufacturing process of the semiconductor device of the present invention will be described. Here, a method for simultaneously manufacturing a pixel portion and TFTs (n-channel TFT and p-channel TFT) of a driver circuit provided near the pixel portion over the same substrate will be described in detail. In this embodiment, a common voltage is applied to the first electrode of all TFTs formed in the pixel portion, and the first electrode and the second electrode are connected to the TFT formed in the drive circuit. An example is shown. 2 to 6 used in this embodiment are cross-sectional views illustrating the manufacturing process, and FIGS. 7 to 9 are top views corresponding to the manufacturing steps, and are described using common reference numerals for convenience of description.
[0040]
In FIG. 2A, the substrate 101 can be formed using any material as long as it has an insulating surface and can withstand a processing temperature in a later step. Typically, a glass substrate, a quartz substrate, a ceramic substrate, or the like can be used. Alternatively, a silicon substrate, a metal substrate, or a stainless steel substrate with an insulating film formed thereon may be used. Further, a plastic substrate having heat resistance that can withstand the processing temperature of this embodiment may be used.
[0041]
A first wiring 102 and first electrodes 103 to 107 are formed on the insulating surface of the substrate 101. The first wiring and the first electrode are formed of one or a plurality of conductive materials selected from Al, W, Mo, Ti, and Ta. Although W is used in this embodiment, a laminate of W on TaN may be used as the first wiring and the first electrode.
[0042]
FIG. 7A illustrates a top view of the pixel portion in FIG. The first electrodes 105, 106, and 107 are part of the common wiring 180.
[0043]
After the first wiring 102 and the first electrodes 103 to 107 are formed, the first insulating film 110 is formed. In this embodiment, the first insulating film 110 is formed by stacking two insulating films (a first insulating film A 110a and a first insulating film B 110b). The first insulating film A 110a is formed using a silicon oxynitride film with a thickness of 10 to 50 nm. The first insulating film B 110b is formed using a silicon oxide film or a silicon oxynitride film with a thickness of 0.5 to 1 μm.
[0044]
The surface of the first insulating film 110 may have unevenness caused by the first wiring and the first electrode formed in advance. Preferably, it is desirable to flatten the unevenness. CMP is used as a planarization method. As the CMP polishing slurry (slurry) for the first insulating film 110, for example, fumed silica particles obtained by thermally decomposing silicon chloride gas in a KOH-added aqueous solution may be used. The first insulating film is removed by about 0.1 to 0.5 μm by CMP to flatten the surface.
[0045]
Thus, a planarized first insulating film 112 is formed as shown in FIG. 2B, and a semiconductor layer is formed thereover. The semiconductor layer 113 is formed using a semiconductor having a crystal structure. This is obtained by crystallizing an amorphous semiconductor layer formed over the first insulating film 112. After the amorphous semiconductor layer is deposited, it is crystallized by heat treatment or laser light irradiation. The material of the amorphous semiconductor layer is not limited, but is preferably silicon or silicon germanium (Si _x Ge _1-x ; 0 <x <1, typically x = 0.001 to 0.05).
[0046]
After that, the semiconductor layer 113 is divided into island shapes by etching, and semiconductor films 114 to 117 are formed as shown in FIG.
[0047]
FIG. 7B shows a top view of FIG. The first electrodes 105 and 106 overlap with each other with the semiconductor film 116 and the first insulating film 112 interposed therebetween. The first electrode 107 overlaps with the semiconductor film 116 and the first insulating film 112 interposed therebetween. Note that the semiconductor film 181 is a semiconductor film for forming a capacitor, and overlaps with the first electrode 107 and the first insulating film 112 interposed therebetween.
[0048]
Next, as illustrated in FIG. 3A, a second insulating film 118 is formed to cover the semiconductor films 114 to 117 and 181. The second insulating film 118 is formed of an insulator containing silicon by a plasma CVD method or a sputtering method. The thickness is 40 to 150 nm.
[0049]
A conductive film is formed over the second insulating film 118 in order to form a second gate electrode and a second wiring. In the present invention, the second gate electrode is formed by stacking two or more conductive films. The first conductive film 119 formed over the second insulating film 118 is formed using a nitride of a refractory metal such as molybdenum or tungsten, and the second conductive film 120 formed thereon is formed using a refractory metal or aluminum, It is formed of a low resistance metal such as copper or polysilicon. Specifically, one or a plurality of nitrides selected from W, Mo, Ta, and Ti are selected as the first conductive film, and W, Mo, Ta, Ti, Al, and Cu are selected as the second conductive film. One or more kinds of alloys selected, or n-type polycrystalline silicon is used. For example, the first conductive film 119 may be formed of TaN, and the second conductive film 120 may be formed of W. In the case where the second gate electrode and the second wiring are formed using a three-layer conductive film, the first layer may be Mo, the second layer may be Al, and the third layer may be TiN. The first layer may be W, the second layer may be Al, and the third layer may be TiN. By making the wiring multi-layered, the thickness of the wiring itself increases, so that the wiring resistance can be suppressed.
[0050]
Next, the first conductive film 119 and the second conductive film 120 are etched using the mask 190 to form a second wiring and a second electrode.
[0051]
As shown in FIG. 3B, first-shaped electrodes 121 to 125 having tapered ends are formed by first etching treatment (first conductive films 121a to 125a and second conductive film 121b. ~ 125b). The portion of the second insulating film 118 that is not covered with the first shape electrodes 121 to 125 is thinned by etching about 20 to 50 nm on the surface. Here, in order to distinguish between before etching and after etching, the second insulating film 130 is shown after etching.
[0052]
The first doping treatment is performed by an ion implantation method or an ion doping method in which ions are implanted without mass separation. Doping uses the first-shaped electrodes 121 to 125 as a mask, and forms one-conductivity type impurity regions 126 to 129 having a first concentration in the semiconductor films 114 to 117. The first concentration is 1 × 10 ²⁰ ~ 1.5 × 10 ^{twenty one} /cm ^Three And
[0053]
Next, a second etching process is performed as shown in FIG. 4A without removing the resist mask. In this etching process, the second conductive film is anisotropically etched to form second-shaped electrodes 131 to 135 (consisting of first conductive films 131a to 135a and second conductive films 131b to 135b). . The second shape electrodes 131 to 135 are formed so that the width thereof is reduced by this etching process and the end portions thereof are located inside the one-concentration type impurity regions 126 to 129 (second impurity regions) of the first concentration. To do. As shown in the next step, the length of the LDD is determined by the receding width. The second shape electrodes 131 to 135 function as second electrodes.
[0054]
FIG. 8A shows a top view of FIG. The second shape electrodes 133 and 134 are part of the gate wiring 182. The second shape electrodes 133 and 134 overlap the semiconductor film 116, and the second shape electrode 135 overlaps the semiconductor film 117 with the second insulating film 130 interposed therebetween. Further, the second shape electrodes 133 and 134 and the first electrodes 105 and 106 overlap with each other with the semiconductor film 116 and the second insulating film interposed therebetween. Note that part of the second shape electrode 135 overlaps the semiconductor film 181 with the second insulating film 130 interposed therebetween.
[0055]
Further, the second shape electrodes 131 and 132 and the first electrodes 103 and 104 overlap with each other with the semiconductor films 114 and 115 and the second insulating film 130 interposed therebetween.
[0056]
Then, in this state, the second conductivity treatment is performed on the one conductivity type impurity to add the one conductivity type impurity to the semiconductor films 114 to 117. The one-conductivity type impurity regions (first impurity regions) 195 to 198 of the second concentration formed by this doping treatment are part of the first conductive films 131a to 135a constituting the second shape electrodes 131 to 135. Are formed in a self-aligning manner so as to overlap. Since the impurity added by the ion doping method is added through the first conductive films 131a to 135a, the number of ions reaching the semiconductor film is reduced and inevitably has a low concentration. Its concentration is 1 × 10 ¹⁷ ~ 1x10 ¹⁹ /cm ^Three It becomes.
[0057]
Next, as shown in FIG. 4B, resist masks 139 and 140 are formed, and a third doping process is performed. By this third doping treatment, impurity regions 141 and 142 having a conductivity type opposite to the one conductivity type of the third concentration are formed in the semiconductor films 115 and 117. The impurity region of the conductivity type opposite to the one conductivity type of the third concentration is formed in a region overlapping with the second shape electrodes 132 and 134, and is 1.5 × 10 6. ²⁰ ~ 5x10 ^{twenty one} /cm ^Three The impurity element is added in a concentration range of.
[0058]
Through the steps described above, regions where impurities for the purpose of valence electron control are added to each semiconductor film. The first electrodes 103 to 107 and the second shape electrodes 131 to 135 function as gate electrodes at positions intersecting the semiconductor film.
[0059]
Thereafter, a step of activating the impurity element added to each semiconductor film is performed. This activation is performed using a gas heating type instantaneous thermal annealing method. The temperature of the heat treatment is 400 to 700 ° C. in a nitrogen atmosphere, typically 450 to 500 ° C. In addition, a laser annealing method using the second harmonic (532 nm) of a YAG laser can be applied. In order to perform activation by irradiation with laser light, the semiconductor film is irradiated with the second harmonic (532 nm) of a YAG laser. Of course, the RTA method using a lamp light source is not limited to the laser light, and the semiconductor film is heated by radiation of the lamp light source from both sides or one side of the substrate.
[0060]
Thereafter, as shown in FIG. 5A, a passivation film 143 made of silicon nitride is formed to a thickness of 50 to 100 nm by a plasma CVD method, and heat treatment is performed at 410 ° C. using a clean oven. The semiconductor film is hydrogenated with the released hydrogen.
[0061]
Next, a third insulating film 144 made of an organic insulating material is formed over the passivation film 143. The reason for using the organic insulating material is to planarize the surface of the third insulating film 144. In order to obtain a more complete flat surface, it is desirable to flatten this surface by CMP. When the CMP method is used in combination, a silicon oxide film formed by a plasma CVD method, a SOG (Spin on Glass) formed by a coating method, PSG, or the like can be used as the third insulating film. Note that the passivation film 143 may be regarded as part of the third insulating film 144.
[0062]
A transparent conductive film 145 mainly composed of indium tin oxide is formed to a thickness of 60 to 120 nm on the surface of the third insulating film 144 thus planarized. Since fine irregularities are also formed on this surface, it is desirable to polish and planarize by a CMP method using aluminum oxide as an abrasive.
[0063]
FIG. 8B shows a top view of FIG.
[0064]
Thereafter, the transparent conductive film 145 is etched to form a pixel electrode (third electrode) 146. Then, contact holes are formed in the second insulating film 130, the passivation film 143, and the third insulating film 144, and wirings 147 to 153 are formed. This wiring is formed by laminating a titanium film and an aluminum film.
[0065]
The wiring 147 is connected to the first wiring 102 and the second shape electrode 131. Further, the first wiring 102 and the first electrode 103 are electrically connected.
[0066]
The wiring 148 is connected to the impurity region 126 and the impurity region 141. The wiring 149 is connected to the impurity region 141. The wiring 150 is connected to the impurity region 128 and functions as a source wiring. The wiring 151 is connected to the impurity region 128 and the second shape electrode 135. The wiring 152 is connected to the impurity region 142. The wiring 153 is connected to the impurity region 142 and the pixel electrode 146 and functions as a power supply line.
[0067]
In the above steps, when one conductivity type impurity region is n-type and one impurity type opposite to the one conductivity type is p-type, a driving circuit 200 having an n-channel TFT 202 and a p-channel TFT 203 on the same substrate; A pixel portion 201 having an n-channel TFT 204 and a p-channel TFT 205 is formed.
[0068]
In the driver circuit 200, the pair of gate electrodes 131 and 103 in the n-channel TFT 202 overlap with each other with the channel formation region 160 interposed therebetween. The one-concentration impurity region 195 having the second concentration functions as an LDD, and the one-concentration impurity region 126 having the first concentration functions as a source or drain region. In the driving circuit 200, in the p-channel TFT 203, the pair of gate electrodes 132 and 104 overlap with each other with the channel formation region 161 interposed therebetween. The impurity region 141 opposite to the first conductivity type of the third concentration functions as a source or drain region. The length of the LDD in the channel length direction is 0.5 to 2.5 μm, preferably 1.5 μm. Such an LDD configuration is mainly intended to prevent TFT deterioration due to the hot carrier effect. A shift register circuit, a buffer circuit, a level shifter circuit, a latch circuit, or the like can be formed using the n-channel TFT and the p-channel TFT. In particular, the structure of the first n-channel TFT 201 is suitable for a buffer circuit having a high driving voltage in order to prevent deterioration due to the hot carrier effect.
[0069]
In the pixel portion 201, the pair of gate electrodes 133 and 105 in the n-channel TFT 204 overlap with each other with the channel formation region 162 interposed therebetween. In the n-channel TFT 204, the pair of gate electrodes 134 and 106 overlap with each other with the channel formation region 163 interposed therebetween. The second concentration of one conductivity type impurity region 196 functions as an LDD, and the first concentration of one conductivity type impurity region 128 functions as a source or drain region. The n-channel TFT 204 has a shape in which two TFTs are connected in series with an impurity region of one conductivity type having a first concentration inserted. In the p-channel TFT 205, the pair of gate electrodes 135 and 107 overlap with each other with the channel formation region 164 interposed therebetween. The impurity region 142 opposite to the one conductivity type of the third concentration functions as a source or drain region.
[0070]
In this embodiment, the common voltage is applied to the first electrode by always applying a constant voltage (common voltage) to the common wiring. Note that this constant voltage is smaller than the threshold value in the case of an n-channel TFT and larger than the threshold value in the case of a p-channel TFT. By applying a common voltage to the first electrode, variation in threshold value can be suppressed as compared with a case where there is one electrode, and off-state current can be suppressed. Since the TFT formed as a switching element in the pixel portion of the semiconductor device is more important to reduce the off current than to increase the on current, the above configuration is useful.
[0071]
Further, in this embodiment, in the TFT included in the driving circuit of the semiconductor device, by forming a pair of gate electrodes electrically connected by inserting the semiconductor film, the thickness of the semiconductor film is substantially halved, As the gate voltage is applied, depletion progresses rapidly, increasing the field-effect mobility and lowering the subthreshold coefficient. As a result, the driving voltage can be lowered by using the TFT having this structure in the driving circuit. In addition, the current driving capability is improved, and the TFT size (especially the channel width) can be reduced. Therefore, the integration density can be improved.
[0072]
The pixel portion 201 has a structure applicable to an active matrix light-emitting device, and FIG. 6A shows a state where a light-emitting element is formed over the third insulating film 144. On the third insulating film 144, a partition layer 170 that covers the n-channel TFT 204 and the p-channel TFT 205 is formed. Since the organic compound layer and the cathode cannot be wet-processed (such as chemical etching or water washing), the partition layer 170 formed of a photosensitive resin material on the fourth insulating film in accordance with the pixel electrode 146. Is provided. The partition layer 170 is formed using an organic resin material such as polyimide, polyamide, polyimide amide, or acrylic. The partition layer 170 is formed so as to cover the end portion of the pixel electrode. The end portion of the partition wall layer 170 is formed to have a taper angle of 45 to 60 degrees.
[0073]
FIG. 9 is a top view of the pixel portion in this state. The partition layer 170 is formed in a region surrounded by a dotted line in FIG.
[0074]
The light emitting device of the active matrix driving system shown here is configured by arranging organic light emitting elements in a matrix. The organic light emitting device 174 includes an anode, a cathode, and an organic compound layer formed therebetween. The pixel electrode 146 becomes an anode when formed of a transparent conductive film. The organic compound layer is formed by combining a hole transporting material having a relatively high hole mobility, a reverse electron transporting material, a light emitting material, and the like. They may be formed in layers or mixed.
[0075]
The organic compound material is formed as a thin film layer of about 100 nm in total. Therefore, it is necessary to improve the flatness of the surface of ITO formed as the anode. When the flatness is poor, a short circuit with the cathode formed on the worst organic compound layer occurs. As another means for preventing this, a method of forming an insulating film having a thickness of 1 to 5 nm can be employed. As the insulating film, polyimide, polyimide amide, polyamide, acrylic, or the like can be used. The counter electrode (fourth electrode) 172 can be a cathode by being formed using a material such as alkali metal or alkaline earth metal such as MgAg or LiF.
[0076]
The counter electrode 172 is formed using a material containing magnesium (Mg), lithium (Li), or calcium (Ca) having a low work function. An electrode made of MgAg (a material in which Mg and Ag are mixed at Mg: Ag = 10: 1) is preferably used. Other examples include MgAgAl electrodes, LiAl electrodes, and LiFAl electrodes. Further, an insulating film 173 made of silicon nitride or a DLC film is formed as an upper layer with a thickness of 2 to 30 nm, preferably 5 to 10 nm. The DLC film can be formed by a plasma CVD method, and even when formed at a temperature of 100 ° C. or lower, the DLC film can be formed to cover the end portion of the partition wall layer 622 with good coverage. The internal stress of the DLC film can be reduced by mixing a small amount of argon, and can be used as a protective film. The DLC film is oxygen, CO, CO ₂ , H ₂ Since it has a high gas barrier property such as O, it is suitable as the insulating film 173 used as a barrier film.
[0077]
A cross-sectional view taken along line BB ′ of FIG. 9 is shown in FIG. A capacitor is formed in a portion where the first electrode, the first insulating film 112, and the semiconductor film 181 overlap. Further, a capacitor is formed in a portion where the second shape electrode 135, the second insulating film 130, and the semiconductor film 181 are overlapped.
[0078]
In this embodiment, the first electrode and the second electrode are connected by the wiring formed simultaneously with the source wiring. However, the first electrode and the second electrode may be directly connected. . However, as in this embodiment, when the first electrode and the second electrode are connected by the wiring formed simultaneously with the source wiring, it is not necessary to increase the number of processes and the number of masks can be suppressed.
[0079]
After improving airtightness by processing such as packaging, a connector (flexible printed circuit: FPC) for connecting the terminal routed from the element or circuit formed on the substrate and the external signal terminal is attached as a product Complete.
[0080]
(Example 2)
In this embodiment, a structure different from that of Embodiment 1 of a pixel of a light-emitting device which is one of semiconductor devices of the present invention will be described.
[0081]
FIG. 10 shows a top view of a pixel of the light emitting device of this embodiment. A cross-sectional view taken along the line AA ′ of FIG. 10 is shown in FIG.
[0082]
Reference numeral 501 denotes an n-channel TFT, and 502 denotes a p-channel TFT. The n-channel TFT 501 includes a semiconductor film 503, a first insulating film 520, first electrodes 504 and 505, a second insulating film 521, and second electrodes 506 and 507. The semiconductor film 503 has a first concentration one-conductivity type impurity region 508, a second concentration one-conductivity type impurity region 509, and channel formation regions 510 and 511.
[0083]
The first electrodes 504 and 505 and the channel formation regions 510 and 511 overlap each other with the first insulating film 520 interposed therebetween. The second electrodes 506 and 507 and the channel formation regions 510 and 511 overlap each other with the second insulating film 521 interposed therebetween.
[0084]
The p-channel TFT 502 includes a semiconductor film 530, a first insulating film 520, a first electrode 532, a second insulating film 521, and a second electrode 531. The semiconductor film 530 includes a first conductivity type impurity region 533 having a third concentration and a channel formation region 534.
[0085]
The first electrode 532 and the channel formation region 534 overlap with each other with the first insulating film 520 interposed therebetween. The second electrode 531 and the channel formation region 534 overlap with each other with the second insulating film 521 interposed therebetween.
[0086]
The first electrode 532 and the second electrode 531 are electrically connected through the wiring 540.
[0087]
In this embodiment, even in a TFT in the same pixel, a common voltage is applied to the first electrode of a TFT used as a switching element (in this embodiment, an n-channel TFT 501). By applying a common voltage to the first electrode, variation in threshold value can be suppressed as compared with a case where there is one electrode, and off-state current can be suppressed.
[0088]
In addition, a TFT (p-channel TFT 502 in this embodiment) that flows a larger current than a TFT used as a switching element electrically connects the first electrode and the second electrode. By applying the same voltage to the first electrode and the second electrode, the depletion layer spreads as fast as when the film thickness of the semiconductor film is substantially reduced, so that the subthreshold coefficient can be reduced. Further, the field effect mobility can be improved. Therefore, the on-current can be increased as compared with the case of one electrode. Therefore, the driving voltage can be lowered by using the TFT having this structure in the driving circuit. In addition, since the on-current can be increased, the TFT size (especially the channel width) can be reduced. Therefore, the integration density can be improved.
[0089]
(Example 3)
In this embodiment, an example in which a flip-flop circuit used for a shift register of a driver circuit is formed using a TFT in which a first electrode and a second electrode are electrically connected is described.
[0090]
FIG. 12 shows a circuit diagram of the flip-flop circuit of this embodiment. Note that the flip-flop circuit included in the semiconductor device of the present invention is not limited to the structure shown in FIG. The flip-flop circuit is only an example of the circuit included in the driver circuit, and the semiconductor device of the present invention does not necessarily have the flip-flop circuit. The TFT of the present invention can be used for circuits other than flip-flops.
[0091]
The flip-flop circuit illustrated in FIG. 12A includes clocked inverters 1201 and 1202 and an inverter 1203. A circuit diagram more specifically showing each circuit element of the flip-flop circuit shown in FIG. 12A is shown in FIG.
[0092]
The clocked inverter of this embodiment has two p-channel TFTs and two n-channel TFTs. The first voltage (VDD) is applied to the source of the first p-channel TFT, and the drain is connected to the source of the second p-channel TFT. The drain of the second p-channel TFT is connected to the drain of the second n-channel TFT. The source of the second n-channel TFT is connected to the drain of the first n-channel TFT, and the second voltage (GND) is applied to the source of the first n-channel TFT. The first voltage is higher than the second voltage.
[0093]
A clock signal (CK) is input to the gate electrode of the first n-channel TFT, and an inverted clock that is a signal in which the polarity of the clock signal (CK) is inverted is input to the gate electrode of the first p-channel TFT. A signal (CKb) is input.
[0094]
In the clocked inverter, the polarity of the signal (IN) input to the gate electrodes of the second p-channel TFT and the second n-channel TFT in synchronization with the clock signal (CK) and the inverted clock signal (CKb). An output signal (OUT) in which is inverted is output.
[0095]
In this embodiment, all TFTs included in the clocked inverter illustrated in FIG. 12B include a first electrode and a second electrode which are electrically connected.
[0096]
FIG. 13 shows a top view of the clocked inverter shown in FIG. 1201 and 1202 are clocked inverters, and 1203 is an inverter. The clock signal (CK), the inverted clock signal (CKb), and the input signal (IN) are input to the wirings 1210, 1211, and 1212, respectively. An output signal (OUT) is output from the wiring 1213. The first voltage (VDD) and the second voltage (GND) are applied to the wirings 1214 and 1215, respectively.
[0097]
FIG. 14A shows a cross-sectional view taken along the line AA ′ of FIG. 13, and FIG. 14B shows a cross-sectional view taken along the line BB ′ of FIG.
[0098]
Reference numeral 1220 denotes a first p-channel TFT included in the clocked inverter 1202, and reference numeral 1221 denotes a second p-channel TFT included in the clocked inverter 1202.
[0099]
The first p-channel TFT 1220 includes a first electrode 1230 and a second electrode 1231. The first electrode 1230 and the second electrode 1231 overlap with each other with a channel formation region 1233 included in the semiconductor film 1232 interposed therebetween.
[0100]
The second p-channel TFT 1221 has a first electrode 1234 and a second electrode 1235. The first electrode 1234 and the second electrode 1235 overlap with each other with a channel formation region 1236 included in the semiconductor film 1232 interposed therebetween.
[0101]
The source region 1240 included in the semiconductor film 1232 of the first p-channel TFT 1220 is connected to the wiring 1214. In addition, the drain region 1241 included in the semiconductor film 1232 of the second p-channel TFT 1221 is connected to the wiring 1215.
[0102]
The first electrode 1230 and the second electrode 1231 are connected to a wiring 1211 to which an inverted clock signal (CKb) is input. Therefore, the first electrode 1230 and the second electrode 1231 are electrically connected. Although not illustrated, the first electrode 1234 and the second electrode 1235 are also electrically connected.
[0103]
In the present embodiment, the first electrode and the second electrode are electrically connected by another wiring, but the first electrode and the second electrode may be directly connected. However, in the case where the first electrode and the second electrode are electrically connected by a wiring, the wiring can be formed at the same time as another wiring, so that the number of masks can be reduced.
[0104]
Note that the wirings 1210, 1211, 1214, and 1215 can be formed by stacking a plurality of conductive films. By reducing the length of the wiring by using a multilayer wiring, the wiring resistance can be lowered, and the drive circuit can be more highly integrated.
[0105]
In addition, as shown in this embodiment, the connection between the first electrode and the second electrode of each TFT does not have to be performed for each TFT. In the plurality of TFTs included in the circuit, When either one of the second electrodes is connected to each other, it is only necessary that the first electrode and the second electrode are connected in any one TFT.
[0106]
This embodiment can be implemented by being freely combined with Embodiment 1 or Embodiment 2.
[0107]
(Example 4)
Another embodiment of the present invention will be described with reference to the drawings. Here, an example of a pixel structure and a driving circuit suitable for a liquid crystal display device will be described. FIGS. 15, 16 and 17 used in this embodiment are cross-sectional views for explaining the manufacturing process, and FIGS. 18 and 19 are top views corresponding to the manufacturing steps. To do.
[0108]
In FIG. 15A, a first wiring 302 and first electrodes 303 to 306 are formed over a substrate 301 in the same manner as in the first embodiment. Then, a first insulating film 307 is formed. In this embodiment, three insulating films (a first insulating film A 307a, a first insulating film B 307b, and a first insulating film C 307c) are stacked and used as the first insulating film 307. A first insulating film A 307a formed of a silicon oxynitride film is formed to a thickness of 50 nm, a first insulating film B 307b is formed to a thickness of 1 μm using a silicon oxide film formed of TEOS, and the surface is subjected to CMP. After the planarization, a three-layer structure in which a silicon oxynitride film is formed as the first insulating film C 307c is formed. Of course, the insulating film in FIG. 15 is not limited to this configuration, and may have the same configuration as that of the first embodiment. The semiconductor films 310 to 312 divided into island shapes are formed in the same manner as in the first embodiment.
[0109]
A top view of FIG. 15A is shown in FIG. A cross-sectional view taken along line AA ′ in FIG. 18A corresponds to FIG. The first electrode 305 and the first electrode 306 are included in part of the common wiring 380.
[0110]
Next, as illustrated in FIG. 15B, a second insulating film 350 that covers the semiconductor films 310 to 312 is formed. The second insulating film 350 is formed using an insulator containing silicon by a plasma CVD method or a sputtering method. The thickness is 40 to 150 nm.
[0111]
Second electrodes 313 to 317 are formed thereon. The material for forming the second wiring is not limited, but a first layer formed of a refractory metal nitride such as molybdenum or tungsten, and a refractory metal formed thereon or a low resistance metal such as aluminum or copper Alternatively, it is formed of polysilicon or the like. Specifically, the first layer is selected from W, Mo, Ta, and Ti, and one or more nitrides are selected, and the second layer is selected from W, Mo, Ta, Ti, Al, and Cu. One or more kinds of alloys or n-type polycrystalline silicon is used.
[0112]
A top view of FIG. 15B is shown in FIG. The second electrode 315 and the second electrode 316 are included in part of the gate wiring 381. The second electrode 315 and the second electrode 316 overlap with the first electrodes 305 and 306 with the first insulating film 307, the semiconductor film 312 and the second insulating film 350 interposed therebetween, respectively.
[0113]
Thereafter, impurity regions are formed in each semiconductor film by ion doping as in the first embodiment. Further, heat treatment for activation and hydrogenation is performed. In this heat treatment, a gas heating type RTA method may be used.
[0114]
A passivation film 318 made of a silicon nitride film and a third insulating film 319 made of an organic resin material selected from acrylic, polyimide, polyamide, and polyimide amide are formed. The passivation film 318 may be regarded as part of the third insulating film 319. The surface of the third insulating film is desirably planarized by CMP. Thereafter, openings are formed, and wirings 320 to 323 and a pixel electrode 324 are formed.
[0115]
Thus, the driver circuit 400 including the n-channel TFT 402 and the p-channel TFT 403 and the pixel portion 401 including the n-channel TFT 404 and the capacitor portion 405 are formed over the same substrate.
[0116]
In the driver circuit 400, the semiconductor film 310 has a channel formation region 330 in the n-channel TFT 402. The channel formation region 330 and the first electrode 303 overlap with each other with the first insulating film 307 interposed therebetween. Further, the channel formation region 330 and the second electrode 313 overlap with the second insulating film 350 interposed therebetween. Further, although not illustrated, the first wiring 302 and the first electrode 303 are connected, and the wiring 320 is connected to the first wiring 302 and the second electrode 313. Further, the one-concentration impurity region 334 having the second concentration functions as an LDD, and the one-conductivity type impurity region 335 having the first concentration functions as a source or drain region. The length of the LDD in the channel length direction is 0.5 to 2.5 μm, preferably 1.5 μm. Such an LDD configuration is mainly intended to prevent TFT deterioration due to the hot carrier effect.
[0117]
In the p-channel TFT 403, the semiconductor film 311 has a channel formation region 331. The channel formation region 331 and the first electrode 304 overlap with each other with the first insulating film 307 interposed therebetween. In addition, the channel formation region 331 and the second electrode 314 overlap with the second insulating film 350 interposed therebetween. The impurity region 336 opposite to the one conductivity type of the third concentration functions as a source or drain region.
[0118]
These n-channel TFT 402 and p-channel TFT 403 can form a shift register circuit, a buffer circuit, a level shifter circuit, a latch circuit, or the like. In particular, the structure of the first n-channel TFT 402 is suitable for a buffer circuit having a high driving voltage in order to prevent deterioration due to the hot carrier effect.
[0119]
Further, the present invention can be similarly applied to a circuit based on NMOS or PMOS without using a CMOS structure.
[0120]
In the pixel portion 401, in the n-channel TFT 404, the semiconductor film 312 includes channel formation regions 332 and 340. The first electrode 305 and the second electrode 315 overlap with each other with the channel formation region 332 interposed therebetween. In addition, the first electrode 306 and the second electrode 316 overlap with each other with the channel formation region 340 interposed therebetween. The impurity region 337 having one conductivity type with the second concentration functions as an LDD, and the impurity region 338 having one conductivity type with the first concentration functions as a source or drain region. The n-channel TFT 404 has a shape in which two TFTs are connected in series with an impurity region of one conductivity type having a first concentration inserted.
[0121]
In addition, a capacitor portion connected to the n-channel TFT 404 in the pixel portion 401 is formed by the semiconductor film 312, the second insulating film 350, and the second electrode 317.
[0122]
FIG. 19 is a top view of the pixel portion in FIG. 16A, and the line AA ′ corresponds to FIG. Further, the line BB ′ corresponds to FIG.
[0123]
As described above, according to the present invention, by forming a pair of gate electrodes by inserting a semiconductor film, the thickness of the semiconductor film is substantially halved, and depletion progresses rapidly with the application of the gate voltage. It is possible to increase the mobility and decrease the subthreshold coefficient.
[0124]
After the formation up to FIG. 16A, an alignment film 453 is formed as shown in FIG. 17, and a rubbing process is performed. Although not shown, before the alignment film 453 is formed, columnar spacers for maintaining the substrate interval may be formed at desired positions by patterning an organic resin film such as an acrylic resin film. . Further, instead of the columnar spacers, spherical spacers may be scattered over the entire surface of the substrate.
[0125]
Next, a counter electrode 451 is formed over the counter substrate 450, an alignment film 452 is formed thereon, and a rubbing process is performed. The counter electrode 451 is made of ITO. Then, the counter substrate 450 on which the seal pattern 454 is formed is bonded. Thereafter, a liquid crystal material 455 is injected between both substrates and completely sealed with a sealant (not shown). A known liquid crystal material may be used as the liquid crystal material. Thus, the active matrix driving liquid crystal display device shown in FIG. 17 is completed.
[0126]
This embodiment can be implemented by freely combining with the third embodiment.
[0127]
(Example 5)
In this embodiment, an example of manufacturing a semiconductor film by a method different from that in Embodiment 1 will be described.
[0128]
In FIG. 20A, reference numeral 100 denotes a substrate having an insulating surface. 20A, the substrate 100 can be a glass substrate, a quartz substrate, a ceramic substrate, or the like. Alternatively, a silicon substrate, a metal substrate, or a stainless steel substrate with an insulating film formed thereon may be used. Alternatively, a plastic substrate having heat resistance that can withstand the processing temperature in this step may be used.
[0129]
First, as illustrated in FIG. 20A, first electrodes 102 a and 102 b are formed over a substrate 100. The first electrodes 102a and 102b may be formed of a conductive material. Typically, it can be formed of one or more alloys or compounds selected from aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), and titanium (Ti). Alternatively, a stack of several conductive films may be used as the first electrode.
[0130]
A first insulating film 101 is formed on the insulating surface so as to cover the first electrodes 102a and 102b. The first insulating film 101 is formed of a silicon oxide film, a silicon nitride film, or a silicon oxynitride film (SiO _x N _y ) Etc. A typical example has a two-layer structure as the first insulating film 101, and SiH _Four , NH _Three And N ₂ A first silicon oxynitride film formed using O as a reaction gas is formed in a thickness of 50 to 100 nm, SiH. _Four And N ₂ A structure in which a second silicon oxynitride film formed using O as a reaction gas is formed to a thickness of 100 to 150 nm is employed. Further, as one layer of the first insulating film 101, a silicon nitride film (SiN film) having a thickness of 10 nm or less, or a second silicon oxynitride film (SiN) _x O _y It is preferable to use a film (X >> Y). Since nickel tends to move to a region having a high oxygen concentration during gettering, it is extremely effective to use a silicon nitride film as the first insulating film in contact with the semiconductor film. Alternatively, a three-layer structure in which a first silicon oxynitride film, a second silicon oxynitride film, and a silicon nitride film are sequentially stacked may be used.
[0131]
Next, a first semiconductor layer 103 having an amorphous structure is formed over the first insulating film. For the first semiconductor layer 103, a semiconductor material containing silicon as its main component is used. Typically, an amorphous silicon film, an amorphous silicon germanium film, or the like is applied, and the film is formed to a thickness of 10 to 100 nm by a plasma CVD method, a low pressure CVD method, or a sputtering method. In order to obtain a semiconductor layer having a good crystal structure by subsequent crystallization, the concentration of impurities such as oxygen and nitrogen contained in the film of the first semiconductor layer 103 having an amorphous structure is set to 5 × 10. ¹⁸ /cm ^Three It may be reduced to (atomic concentration measured by secondary ion mass spectrometry (SIMS)) or less. These impurities interfere with subsequent crystallization, and also increase the density of capture centers and recombination centers even after crystallization. Therefore, it is desirable not only to use a high-purity material gas but also to use an ultrahigh vacuum-compatible CVD apparatus equipped with a mirror surface treatment (electropolishing treatment) in the reaction chamber and an oil-free vacuum exhaust system.
[0132]
Next, as a technique for crystallizing the first semiconductor layer 103 having an amorphous structure, here, the technique described in JP-A-8-78329 is used for crystallization. The technology described in this publication is based on a crystal structure in which an amorphous silicon film (also referred to as an amorphous silicon film) is selectively added with a metal element that promotes crystallization, and heat treatment is performed to expand the added region as a starting point. The semiconductor layer which has this is formed. First, on the surface of the first semiconductor layer 103 having an amorphous structure, a nickel acetate salt solution containing 1 to 100 ppm in terms of weight of a metal element (in this case, nickel) having a catalytic action for promoting crystallization is used with a spinner. The nickel-containing layer 104 is formed by coating. (FIG. 20B) As a means other than the method for forming the nickel-containing layer 104 by coating, a means for forming an extremely thin film by sputtering, vapor deposition, or plasma treatment may be used. Although an example in which the coating is performed on the entire surface is shown here, a nickel-containing layer may be selectively formed by forming a mask.
[0133]
Next, heat treatment is performed to perform crystallization. In this case, in crystallization, silicide is formed in the portion of the semiconductor layer in contact with the metal element that promotes crystallization of the semiconductor, and crystallization proceeds using the silicide as a nucleus. Thus, the first semiconductor layer 105 having the crystal structure illustrated in FIG. 20C is formed. Note that the concentration of oxygen contained in the first semiconductor layer 105 after crystallization is 5 × 10 5. ¹⁸ / Cm ^Three The following is desirable. Here, after heat treatment for dehydrogenation (450 ° C., 1 hour), heat treatment for crystallization (550 to 650 ° C. for 4 to 24 hours) is performed. When crystallization is performed by irradiation with strong light, any one of infrared light, visible light, ultraviolet light, or a combination thereof can be used. Typically, a halogen lamp, a metal halide, or the like is used. Light emitted from a lamp, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, or high pressure mercury lamp is used. The lamp light source is turned on for 1 to 60 seconds, preferably 30 to 60 seconds, and this is repeated once to 10 times, and the semiconductor layer is instantaneously heated to about 600 to 1000 ° C. Note that if necessary, heat treatment for releasing hydrogen contained in the first semiconductor layer 105 having an amorphous structure may be performed before irradiation with strong light. In addition, crystallization may be performed by simultaneously performing heat treatment and irradiation with strong light. In consideration of productivity, it is desirable to perform crystallization by irradiation with strong light.
[0134]
In the first semiconductor layer 105 obtained in this manner, a metal element (here, nickel) remains. Although it is not uniformly distributed in the film, if it is an average concentration, it is 1 × 10 ¹⁹ /cm ^Three Remaining at a concentration exceeding Of course, various semiconductor elements including TFT can be formed even in such a state, but the element is removed by the method described below.
[0135]
Next, in order to increase the crystallization rate (the ratio of the crystal component in the total volume of the film) and repair defects remaining in the crystal grains, the first semiconductor layer 105 having a crystal structure is irradiated with laser light (first Laser beam) in the air or oxygen atmosphere. When laser light (first laser light) is irradiated, irregularities are formed on the surface and a thin oxide film 106 is formed. (FIG. 20D) Excimer laser light having a wavelength of 400 nm or less, and second and third harmonics of a YAG laser are used as this laser light (first laser light). Further, instead of excimer laser light, light emitted from an ultraviolet lamp may be used.
[0136]
Further, an oxide film (referred to as chemical oxide) is formed with an ozone-containing aqueous solution (typically ozone water) to form a barrier layer 107 made of an oxide film having a total thickness of 1 to 10 nm, and a rare gas is formed on the barrier layer 107. A second semiconductor layer 108 containing an element is formed (FIG. 20E). Note that here, the oxide film 106 formed when the first semiconductor layer 105 having a crystal structure is irradiated with laser light is also regarded as part of the barrier layer. The barrier layer 107 functions as an etching stopper when only the second semiconductor layer 108 is selectively removed in a later step. Also, chemical oxide can be formed in the same manner by treating with an aqueous solution in which sulfuric acid, hydrochloric acid, nitric acid or the like and hydrogen peroxide are mixed instead of the ozone-containing aqueous solution. As another method for forming the barrier layer 107, ozone may be generated by ultraviolet irradiation in an oxygen atmosphere to oxidize the surface of the semiconductor layer having the crystal structure. As another method for forming the barrier layer 107, an oxide film of about 1 to 10 nm may be deposited by a plasma CVD method, a sputtering method, an evaporation method, or the like to form a barrier layer. As another method of forming the barrier layer 107, a thin oxide film may be formed by heating to about 200 to 350 ° C. using a clean oven. Note that there is no particular limitation on the barrier layer 107 as long as it is formed by any one of the above methods or a combination of these methods, but the nickel in the first semiconductor layer is not formed in the first gettering. It is necessary to make the film quality or film thickness movable to the second semiconductor layer.
[0137]
Here, the second semiconductor layer 108 containing a rare gas element is formed by a sputtering method, and a gettering site is formed. Note that it is desirable to appropriately adjust the sputtering conditions so that a rare gas element is not added to the first semiconductor layer. As the rare gas element, one or more selected from helium (He), neon (Ne), argon (Ar), krypton (Kr), and xenon (Xe) are used. Among them, argon (Ar) which is an inexpensive gas is preferable. Here, a second semiconductor layer is formed using a target made of silicon in an atmosphere containing a rare gas element. There are two meanings of including a rare gas element ion which is an inert gas in the film. One is to form a dangling bond to give strain to the semiconductor layer, and the other is to give strain to the lattice of the semiconductor layer. Distortion between the lattices of the semiconductor layer is remarkably obtained when an element having an atomic radius larger than that of silicon such as argon (Ar), krypton (Kr), or xenon (Xe) is used. In addition, by including a rare gas element in the film, not only lattice distortion but also dangling bonds are formed, contributing to the gettering action.
[0138]
In addition, in the case where the second semiconductor layer is formed using a target containing phosphorus which is an impurity element of one conductivity type, gettering may be performed using the Coulomb force of phosphorus in addition to gettering using a rare gas element. it can.
[0139]
In addition, since nickel tends to move to a region having a high oxygen concentration during gettering, the oxygen concentration contained in the second semiconductor layer 108 is higher than the oxygen concentration contained in the first semiconductor layer. For example 5 × 10 ¹⁸ / Cm ^Three It is desirable to set it above.
[0140]
Next, heat treatment is performed, and gettering for reducing or removing the concentration of the metal element (nickel) in the first semiconductor layer is performed. (FIG. 20F) As the heat treatment for performing gettering, a treatment for applying strong light or a heat treatment may be performed. By this gettering, the metal element moves in the direction of the arrow in FIG. 20F (that is, the direction from the substrate side to the surface of the second semiconductor layer), and the first semiconductor layer covered with the barrier layer 107 is formed. The metal element contained in 105 is removed or the concentration of the metal element is reduced. The distance that the metal element travels during gettering may be at least as long as the thickness of the first semiconductor layer, and gettering can be completed in a relatively short time. Here, all the nickel is moved to the second semiconductor layer 108 so that the nickel does not segregate in the first semiconductor layer 105, and the nickel contained in the first semiconductor layer 105 is hardly present, that is, the nickel concentration in the film is 1 ×. 10 ¹⁸ / Cm ^Three Below, desirably 1 × 10 ¹⁷ / Cm ^Three Getter enough to get:
[0141]
Further, depending on the conditions of the heat treatment for the gettering, the crystallization rate of the first semiconductor layer can be increased simultaneously with the gettering, and defects remaining in the crystal grains can be repaired, that is, the crystallinity can be improved. .
[0142]
In this specification, gettering means that a metal element in a gettering region (here, the first semiconductor layer) is released by thermal energy and moves to a gettering site by diffusion. Accordingly, the gettering depends on the processing temperature, and the gettering proceeds in a shorter time as the temperature is higher.
[0143]
Further, in the case of using a process of irradiating intense light as the heat treatment for gettering, the lamp light source for heating is turned on for 1 to 60 seconds, preferably 30 to 60 seconds, and it is turned 1 to 10 times, preferably 2 Repeat ~ 6 times. The emission intensity of the lamp light source is arbitrary, but the semiconductor layer is instantaneously heated to 600 to 1000 ° C., preferably about 700 to 750 ° C.
[0144]
In the case of performing heat treatment, heat treatment may be performed in a nitrogen atmosphere at 450 to 800 ° C. for 1 to 24 hours, for example, at 550 ° C. for 14 hours. Moreover, you may irradiate strong light in addition to heat processing.
[0145]
Next, using the barrier layer 107 as an etching stopper, only the second semiconductor layer indicated by 106 is selectively removed, and then the barrier layer 107 made of an oxide film is removed. As a method of selectively etching only the second semiconductor layer, ClF _Three Dry etching without plasma by hydrazine, tetraethylammonium hydroxide (chemical formula (CH _Three ) _Four NOH) can be performed by wet etching with an alkaline solution such as an aqueous solution. Further, after removing the second semiconductor layer, the nickel concentration was measured on the surface of the barrier layer by TXRF. Since nickel was detected at a high concentration, it is desirable to remove the barrier layer, and an etchant containing hydrofluoric acid. It may be removed by
[0146]
Next, the first semiconductor layer having a crystal structure is irradiated with laser light (second laser light) in a nitrogen atmosphere or in a vacuum. When laser light (second laser light) is irradiated, the height difference of the irregularities formed by the irradiation of the first laser light (PV value: Peak to Valley, the difference between the maximum value and the minimum value) Is reduced, that is, flattened. Here, the PV value of the unevenness may be observed with an AFM (atomic force microscope). Specifically, the surface where the PV value of the unevenness formed by the irradiation of the first laser beam was about 10 nm to 30 nm is changed to the PV value of the unevenness on the surface by the irradiation of the second laser beam. It can be 5 nm or less, and can be 1.5 nm or less depending on conditions. As this laser light (second laser light), excimer laser light having a wavelength of 400 nm or less, and second and third harmonics of a YAG laser are used. Further, instead of excimer laser light, light emitted from an ultraviolet lamp may be used.
[0147]
The energy density of the second laser beam is larger than the energy density of the first laser beam, preferably 30 to 60 mJ / cm. ² Enlarge. However, the energy density of the second laser beam is 90 mJ / cm higher than the energy density of the first laser beam. ² When the energy density is larger than the above, the surface roughness increases, and further, the crystallinity is lowered or microcrystallized, and the characteristics tend to deteriorate.
[0148]
Note that the irradiation with the second laser light is higher than the energy density of the first laser light, but the crystallinity hardly changes before and after the irradiation. Also, the crystal state such as the grain size hardly changes. That is, it seems that only the flattening is performed by the irradiation of the second laser beam.
[0149]
The merit that the semiconductor layer having a crystal structure is planarized by irradiation with the second laser light is very large. For example, since the planarity is improved, a second insulating film used as a gate insulating film to be formed later can be thinned, and the mobility of the TFT can be improved. In addition, when flatness is improved, off current can be reduced when a TFT is manufactured.
[0150]
In addition, when the gettering site is formed by irradiation with the second laser light, the rare gas element in the semiconductor layer having a crystal structure is removed or reduced when it is also added to the first semiconductor layer. Effect is also obtained.
[0151]
Next, a semiconductor film having a desired shape is formed on the planarized first semiconductor layer 109 using a known patterning technique.
[0152]
This embodiment can be implemented by freely combining with Embodiments 1 to 4.
[0153]
(Example 6)
In this embodiment, an example in which a semiconductor film is formed by a thermal crystallization method using a catalytic element is shown.
[0154]
In the case of using a catalyst element, it is desirable to use the techniques disclosed in Japanese Patent Application Laid-Open Nos. 7-130652 and 8-78329.
[0155]
Here, FIG. 21 shows an example in which the technique disclosed in Japanese Patent Laid-Open No. 7-130652 is applied to the present invention. First, the first electrode 1252 is formed over the substrate 1251. Then, a first insulating film 1253 was formed over the substrate 1251 so as to cover the first electrode 1252, and an amorphous silicon film 1254 was formed thereover. Furthermore, a nickel-containing layer 1255 was formed by applying a nickel acetate salt solution containing 10 ppm of nickel in terms of weight. (FIG. 21 (A))
[0156]
Next, after a dehydrogenation step at 500 ° C. for 1 hour, a heat treatment was performed at 500 to 650 ° C. for 4 to 12 hours, for example, 550 ° C. for 8 hours to form a crystalline silicon film 1256. The crystalline silicon film 1256 obtained in this way had a very good crystal quality. (Fig. 21 (B))
[0157]
Further, the technique disclosed in Japanese Patent Laid-Open No. 8-78329 enables selective crystallization of an amorphous semiconductor film by selectively adding a catalytic element. The case where this technique is applied to the present invention will be described with reference to FIG.
[0158]
First, the first electrode 1302 is formed over the glass substrate 1301. Then, a first insulating film 1303 is provided over the substrate 1301 so as to cover the first electrode 1302, and an amorphous silicon film 1304 is formed thereover. Then, a silicon oxide film 1305 was continuously formed on the amorphous silicon film 1304. At this time, the thickness of the silicon oxide film 1305 was set to 150 nm.
[0159]
Next, the silicon oxide film 1305 was patterned to selectively form contact holes 1306, and then a nickel acetate salt solution containing 10 ppm of nickel in terms of weight was applied. As a result, a nickel-containing layer 1307 was formed, and the nickel-containing layer 1307 was in contact with the amorphous silicon film 1304 only at the bottom of the contact hole 1306. (Fig. 22 (A))
[0160]
Next, a heat treatment was performed at 500 to 650 ° C. for 4 to 24 hours, for example, 570 ° C. for 14 hours to form a crystalline silicon film 1308. In this crystallization process, the portion of the amorphous silicon film in contact with nickel is first crystallized, and the crystallization proceeds laterally therefrom. The crystalline silicon film 1308 thus formed is formed by a collection of rod-like or needle-like crystals, and each crystal grows in a specific direction as viewed macroscopically, so that the crystallinity is uniform. There is an advantage. (Fig. 22 (B))
[0161]
The catalyst elements that can be used in the above two techniques are not only nickel (Ni) but also germanium (Ge), iron (Fe), palladium (Pd), tin (Sn), lead (Pb), cobalt ( Elements such as Co), platinum (Pt), copper (Cu), and gold (Au) may be used.
[0162]
A crystalline TFT semiconductor layer can be formed by forming a crystalline semiconductor film (including a crystalline silicon film and a crystalline silicon germanium film) using the above-described technique and performing patterning. A TFT manufactured from a crystalline semiconductor film by using the technique of this embodiment can obtain excellent characteristics, and therefore high reliability is required. However, by adopting the TFT structure of the present invention, it has become possible to produce a TFT that makes the most of the technique of this embodiment.
[0163]
Next, an example in which a step of removing the catalytic element from the crystalline semiconductor film after forming the crystalline semiconductor film using the catalytic element using the amorphous semiconductor film as an initial film will be described with reference to FIG. I will explain. In the present embodiment, the technique described in Japanese Patent Application Laid-Open No. 10-135468 or Japanese Patent Application Laid-Open No. 10-135469 is used as the method.
[0164]
The technique described in the publication is a technique for removing a catalytic element used for crystallization of an amorphous semiconductor film by using a gettering action of phosphorus after crystallization. By using this technique, the concentration of the catalytic element in the crystalline semiconductor film can be reduced to 1 × 10. ¹⁷ atms / cm ^Three Or less, preferably 1 × 10 ¹⁶ atms / cm ^Three It can be reduced to.
[0165]
Here, an alkali-free glass substrate typified by Corning's 1737 substrate was used. In FIG. 23A, the first electrode 1402 is formed over the substrate 1401. Then, a first insulating film 1403 is provided over the substrate 1401 so as to cover the first electrode 1402, and a crystalline silicon film 1404 is formed thereover.
[0166]
A silicon oxide film 1405 for a mask is formed to a thickness of 150 nm on the surface of the crystalline silicon film 1404, a contact hole is provided by patterning, and a region where the crystalline silicon film is partially exposed is provided. Then, a step of adding phosphorus was performed to provide a region (gettering region) 1406 in which phosphorus was added to the crystalline silicon film.
[0167]
In this state, when heat treatment is performed in a nitrogen atmosphere at 550 to 800 ° C. for 5 to 24 hours, for example, 600 ° C. for 12 hours, a region 1406 in which phosphorus is added to the crystalline silicon film serves as a gettering site, The catalytic element remaining in the porous silicon film 1404 could be segregated in the gettering region 1406 to which phosphorus was added.
[0168]
Then, the silicon oxide film 1405 for the mask and the region 1406 to which phosphorus is added are removed by etching, so that the concentration of the catalytic element used in the crystallization step is 1 × 10. ¹⁷ atms / cm ^Three A crystalline silicon film reduced to the following could be obtained. This crystalline silicon film can be used as it is as a semiconductor layer of the TFT of the present invention.
[0169]
This embodiment can be implemented in combination with the first to fourth embodiments.
[0170]
(Example 7)
In this embodiment, a structure of a semiconductor device of the present invention will be described.
[0171]
FIG. 24 shows a block diagram of a light emitting device which is one of the semiconductor devices of the present invention. The light emitting device corresponds to an OLED panel in which an OLED (Organic Light Emitting Device) formed on a substrate is sealed between the substrate and a cover material. An OLED module in which an IC or the like including a controller is mounted on the OLED panel may be referred to as a light emitting device.
[0172]
The OLED has a layer (hereinafter, referred to as an organic light emitting layer) containing an organic compound (organic light emitting material) capable of obtaining luminescence generated by applying an electric field, an anode layer, and a cathode layer. . Luminescence in organic compounds includes light emission (fluorescence) when returning from the singlet excited state to the ground state and light emission (phosphorescence) when returning from the triplet excited state to the ground state. Any one of the above-described light emission may be used, or both light emission may be used.
[0173]
In this specification, all layers provided between the anode and the cathode of the OLED are defined as organic light emitting layers. Specifically, the organic light emitting layer includes a light emitting layer, a hole injection layer, an electron injection layer, a hole transport layer, an electron transport layer, and the like. Basically, the OLED has a structure in which an anode / light emitting layer / cathode is laminated in this order. In addition to this structure, the anode / hole injection layer / light emitting layer / cathode and the anode / hole injection layer / The light emitting layer / electron transport layer / cathode may be stacked in this order.
[0174]
Note that FIG. 24 illustrates an example of a driving circuit of a light-emitting device that displays an image using a digital video signal. The light-emitting device illustrated in FIG. 24 includes a data line driver circuit 800, a scanning line driver circuit 801, and a pixel portion 802.
[0175]
In the pixel portion 802, a plurality of source wirings, a plurality of gate wirings, and a plurality of power supply lines are formed, and a region surrounded by the source wirings, the gate wirings, and the power supply lines corresponds to a pixel. Note that FIG. 24 representatively illustrates only a pixel including one source wiring 807, one gate wiring 809, and one power supply line 808 among a plurality of pixels. Each pixel includes a switching TFT 803 serving as a switching element, a driving TFT 804, a storage capacitor 805, and an OLED 806.
[0176]
A gate electrode of the switching TFT 803 is connected to the gate wiring 809. One of the source region and the drain region of the switching TFT 803 is connected to the source wiring 807, and the other is connected to the gate electrode of the driving TFT 804.
[0177]
One of the source region and the drain region of the driving TFT 804 is connected to the power supply line 808 and the other is connected to the OLED 806. A storage capacitor 805 is formed by the gate electrode of the driving TFT 804 and the power supply line 808. Note that the storage capacitor 805 is not necessarily formed.
[0178]
The data line driver circuit 800 includes a shift register 810, a first latch 811, and a second latch 812. The shift register 810 is supplied with a clock signal (S-CLK) and a start pulse signal (S-SP) for the data line driver circuit. The first latch 811 is supplied with a latch signal (Latchsignals) and a video signal (Video signals) for determining the latch timing.
[0179]
When a clock signal (S-CLK) and a start pulse signal (S-SP) are input to the shift register 810, a sampling signal that determines the sampling timing of the video signal is generated and input to the first latch 811.
[0180]
Note that the sampling signal from the shift register 810 may be buffered and amplified by a buffer or the like and then input to the first latch 811. Since many circuits or circuit elements are connected to the wiring to which the sampling signal is input, the load capacitance (parasitic capacitance) is large. This buffer is effective in preventing “dullness” of the rise or fall of the timing signal caused by the large load capacity.
[0181]
The first latch 811 has a plurality of stages of latches. In the first latch 811, the input video signal is sampled in synchronization with the input sampling signal, and is sequentially stored in the latch of each stage.
[0182]
The time until video signal writing is completed in all the latches of the first latch 811 is called a line period. Actually, the line period may include a period in which a horizontal blanking period is added to the line period.
[0183]
When one line period ends, a latch signal is input to the second latch 812. At this moment, video signals written and held in the first latch 811 are sent all at once to the second latch 812, and are written and held in the latches of all stages of the second latch 812.
[0184]
In the first latch 811 which has finished sending the video signal to the second latch 812, the video signal is sequentially written based on the sampling signal from the shift register 810.
[0185]
During the second line 1-line period, the video signal written and held in the second latch 812 is input to the source wiring.
[0186]
On the other hand, the scan line driver circuit includes a shift register 821 and a buffer 822. The shift register 821 is supplied with a clock signal (G-CLK) and a start pulse signal (G-SP) for the scanning line driver circuit.
[0187]
When a clock signal (G-CLK) and a start pulse signal (G-SP) are input to the shift register 821, a selection signal for determining the timing for selecting a gate wiring is generated and input to the buffer 822. The selection signal input to the buffer 822 is buffer-amplified and input to the gate wiring 809.
[0188]
When the gate wiring 809 is selected, the switching TFT 803 in which the gate electrode is connected to the selected gate wiring 809 is turned on. Then, the video signal input to the source wiring is input to the gate electrode of the driving TFT 804 via the switching TFT 803 that is turned on.
[0189]
Switching of the driving TFT 804 is controlled based on 1 or 0 information included in the video signal input to the gate electrode. When the driving TFT 804 is on, the potential of the power supply line is applied to the pixel electrode of the OLED 806, and the OLED 806 emits light. When the driving TFT 804 is off, the potential of the power supply line is not applied to the pixel electrode of the OLED 806 and the OLED 806 does not emit light.
[0190]
In the circuit included in the data line driver circuit 800 and the scan line driver circuit 801 in the light-emitting device illustrated in FIG. 24, the first electrode and the second electrode of the TFT are electrically connected. By applying the same voltage to the first electrode and the second electrode, the depletion layer spreads as fast as when the film thickness of the semiconductor film is substantially reduced, so that the subthreshold coefficient can be reduced. Further, the field effect mobility can be improved. Therefore, the on-current can be increased as compared with the case of one electrode. Therefore, the drive voltage can be reduced. In addition, since the on-current can be increased, the TFT size (especially the channel width) can be reduced. Therefore, the integration density can be improved.
[0191]
In the pixel portion 802, a common voltage is applied to one of the first electrode and the second electrode of the switching TFT 803 used as a switching element. As a result, the variation in threshold value can be suppressed as compared with the case of one electrode, and the off-current can be suppressed.
[0192]
A driving TFT 804 for supplying a current to the OLED 806 electrically connects the first electrode and the second electrode. As a result, the on-current can be increased as compared with the case of one electrode. Note that the driving TFT is not limited to this structure, and a common voltage is applied to one of the first electrode and the second electrode without electrically connecting the first electrode and the second electrode. You may do it. Further, a thin film transistor having a general structure and having only one electrode may be provided.
[0193]
Next, FIG. 25 shows a configuration of a general liquid crystal display device. The element substrate illustrated in FIG. 25 includes a data line driver circuit 700, a scanning line driver circuit 701, and a pixel portion 702.
[0194]
In the pixel portion 702, a plurality of source wirings and a plurality of gate wirings are formed, and a region surrounded by the source wirings and the gate wirings corresponds to a pixel. Note that FIG. 25 representatively shows only a pixel including one source wiring 703 and one gate wiring 704 among a plurality of pixels. Each pixel has a pixel TFT serving as a switching element and a liquid crystal cell 706.
[0195]
The liquid crystal cell 706 includes a pixel electrode, a counter electrode, and a liquid crystal provided between the pixel electrode and the counter electrode.
[0196]
A gate electrode of the pixel TFT 705 is connected to the gate wiring 704. One of a source region and a drain region of the pixel TFT 705 is connected to the source wiring 703, and the other is connected to a pixel electrode included in the liquid crystal cell 706.
[0197]
The data line driver circuit 700 includes a shift register 710, a level shifter 711, and an analog switch 712. The shift register 710 is supplied with a clock signal (S-CLK) and a start pulse signal (S-SP) for the data line driver circuit. Video signals (Video signals) are supplied to the analog switch 712.
[0198]
When the clock signal (S-CLK) and the start pulse signal (S-SP) are input to the shift register 710, a sampling signal that determines the sampling timing of the video signal is generated and input to the level shifter 711. The amplitude of the voltage of the sampling signal is increased in the level shifter 711 and input to the analog switch 712. The analog switch 712 samples the input video signal in synchronization with the input sampling signal and inputs it to the source wiring 703.
[0199]
On the other hand, the scan line driver circuit includes a shift register 721 and a buffer 722. The shift register 721 is supplied with a clock signal (G-CLK) and a start pulse signal (G-SP) for the scanning line driver circuit.
[0200]
When a clock signal (G-CLK) and a start pulse signal (G-SP) are input to the shift register 721, a selection signal that determines the timing for selecting a gate wiring is generated and input to the buffer 722. The selection signal input to the buffer 722 is buffered and amplified and input to the gate wiring 704.
[0201]
When the gate wiring 704 is selected, the pixel TFT 705 having the gate electrode connected to the selected gate wiring 704 is turned on. Then, the sampled video signal input to the source wiring is input to the pixel electrode of the liquid crystal cell 706 via the pixel TFT 705 that is turned on. Then, the liquid crystal is driven according to the potential of the video signal, and an image is displayed.
[0202]
In the circuit included in the data line driver circuit 700 and the scan line driver circuit 701 in the liquid crystal display device illustrated in FIG. 25, the first electrode and the second electrode of the TFT are electrically connected. By applying the same voltage to the first electrode and the second electrode, the depletion layer spreads as fast as when the film thickness of the semiconductor film is substantially reduced, so that the subthreshold coefficient can be reduced. Further, the field effect mobility can be improved. Therefore, the on-current can be increased as compared with the case of one electrode. Therefore, the drive voltage can be reduced. In addition, since the on-current can be increased, the TFT size (especially the channel width) can be reduced. Therefore, the integration density can be improved.
[0203]
In the pixel portion 702, a common voltage is applied to one of the first electrode and the second electrode of the pixel TFT 705 used as a switching element. As a result, the variation in threshold value can be suppressed as compared with the case of one electrode, and the off-current can be suppressed.
[0204]
This embodiment can be implemented in combination with the first to sixth embodiments.
[0205]
(Example 8)
In this embodiment, an external view of a light-emitting device will be described using the present invention.
[0206]
26A is a top view of the light-emitting device, FIG. 26B is a cross-sectional view taken along line AA ′ of FIG. 26A, and FIG. 26C is BB of FIG. FIG.
[0207]
A sealant 4009 is provided so as to surround the pixel portion 4002, the data line driver circuit 4003, and the first and second scan line driver circuits 4004 a and 400 b provided over the substrate 4001. A sealing material 4008 is provided over the pixel portion 4002, the data line driver circuit 4003, and the first and second scan line driver circuits 4004a and 4004b. Therefore, the pixel portion 4002, the data line driver circuit 4003, and the first and second scan line driver circuits 4004 a and 400 b are sealed with a filler 4210 by the substrate 4001, the sealant 4009, and the sealant 4008. .
[0208]
The pixel portion 4002, the data line driver circuit 4003, and the first and second scan line driver circuits 4004a and 4004b provided over the substrate 4001 include a plurality of TFTs. In FIG. 26B, a CMOS 4201 included in the data line driver circuit 4003 and a driving TFT (TFT for controlling current to the OLED) 4202 included in the data line driver circuit 4003 and the pixel portion 4002 are typically formed over the base film 4010. Illustrated.
[0209]
In this embodiment, the CMOS 4201 uses a p-channel TFT or an n-channel TFT having the first electrode and the second electrode which are electrically connected according to the present invention, and the driving TFT 4202 includes the present TFT. The p-channel TFT having the first electrode and the second electrode which are electrically connected is used. Further, the pixel portion 4002 is provided with a storage capacitor (not shown) connected to the gate of the driving TFT 4202.
[0210]
A third insulating film 4301 is formed over the CMOS 4201 and the driving TFT 4202, and a pixel electrode (anode) 4203 electrically connected to the drain of the driving TFT 4202 is formed thereon. As the pixel electrode 4203, a transparent conductive film having a large work function is used. As the transparent conductive film, a compound of indium oxide and tin oxide, a compound of indium oxide and zinc oxide, zinc oxide, tin oxide, or indium oxide can be used. Moreover, you may use what added the gallium to the said transparent conductive film.
[0211]
A fourth insulating film 4302 is formed over the pixel electrode 4203, and an opening is formed over the pixel electrode 4203 in the fourth insulating film 4302. In this opening, an organic light emitting layer 4204 is formed on the pixel electrode 4203. A known organic light emitting material or inorganic organic light emitting material can be used for the organic light emitting layer 4204. The organic light emitting material includes a low molecular (monomer) material and a high molecular (polymer) material, either of which may be used.
[0212]
As a method for forming the organic light emitting layer 4204, a known vapor deposition technique or coating technique may be used. The structure of the organic light emitting layer may be a laminated structure or a single layer structure by freely combining a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, or an electron injection layer.
[0213]
On the organic light emitting layer 4204, a cathode 4205 made of a light-shielding conductive film (typically a conductive film containing aluminum, copper or silver as a main component or a laminated film of these with another conductive film) is formed. The In addition, it is desirable to remove moisture and oxygen present at the interface between the cathode 4205 and the organic light emitting layer 4204 as much as possible. Therefore, it is necessary to devise a method in which the organic light emitting layer 4204 is formed in a nitrogen or rare gas atmosphere and the cathode 4205 is formed without being exposed to oxygen or moisture. In this embodiment, the above-described film formation is possible by using a multi-chamber type (cluster tool type) film formation apparatus. The cathode 4205 is given a predetermined voltage.
[0214]
As described above, the OLED 4303 including the pixel electrode (anode) 4203, the organic light emitting layer 4204, and the cathode 4205 is formed. A protective film 4209 is formed on the insulating film 4302 so as to cover the OLED 4303. The protective film 4209 is effective in preventing oxygen, moisture, and the like from entering the OLED 4303.
[0215]
Reference numeral 4005 a denotes a lead wiring connected to the power supply line, and is electrically connected to the source region of the driving TFT 4202. The lead wiring 4005 a passes between the sealant 4009 and the substrate 4001 and is electrically connected to the FPC wiring 4301 included in the FPC 4006 through the anisotropic conductive film 4300.
[0216]
As the sealing material 4008, a glass material, a metal material (typically a stainless steel material), a ceramic material, or a plastic material (including a plastic film) can be used. As the plastic material, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a mylar film, a polyester film, or an acrylic resin film can be used. A sheet having a structure in which an aluminum foil is sandwiched between PVF films or mylar films can also be used.
[0217]
However, when the emission direction of light from the OLED is directed toward the cover material, the cover material must be transparent. In that case, a transparent material such as a glass plate, a plastic plate, a polyester film or an acrylic film is used.
[0218]
As the filler 4210, in addition to an inert gas such as nitrogen or argon, an ultraviolet curable resin or a thermosetting resin can be used. PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicone resin, PVB (Polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. In this example, nitrogen was used as the filler.
[0219]
In order to expose the filler 4210 to a hygroscopic substance (preferably barium oxide) or a substance capable of adsorbing oxygen, a recess 4007 is provided on the surface of the sealing material 4008 on the substrate 4001 side to adsorb the hygroscopic substance or oxygen. A possible substance 4207 is placed. In order to prevent the hygroscopic substance or the substance 4207 capable of adsorbing oxygen from scattering, the concave part cover material 4208 holds the hygroscopic substance or the substance 4207 capable of adsorbing oxygen in the concave part 4007. Note that the concave cover material 4208 has a fine mesh shape, and is configured to allow air and moisture to pass therethrough but not a hygroscopic substance or a substance 4207 capable of adsorbing oxygen. By providing the hygroscopic substance or the substance 4207 capable of adsorbing oxygen, deterioration of the OLED 4303 can be suppressed.
[0220]
As shown in FIG. 26C, the conductive film 4203a is formed so as to be in contact with the lead wiring 4005a at the same time as the pixel electrode 4203 is formed.
[0221]
The anisotropic conductive film 4300 has a conductive filler 4300a. By thermally pressing the substrate 4001 and the FPC 4006, the conductive film 4203a on the substrate 4001 and the FPC wiring 4301 on the FPC 4006 are electrically connected by the conductive filler 4300a.
[0222]
This embodiment can be implemented by being freely combined with Embodiments 1, 2, 3, 6 or 7.
[0223]
Example 9
The semiconductor device of the present invention can be used for various electronic devices.
[0224]
As an electronic device using the present invention, a video camera, a digital camera, a goggle type display (head mounted display), a navigation system, a sound reproduction device (car audio, audio component, etc.), a notebook type personal computer, a game device, a portable information terminal (Mobile computer, mobile phone, portable game machine, electronic book, or the like), an image playback device equipped with a recording medium (specifically, a recording medium such as a digital video disc (DVD) can be played back and the image can be displayed. And a device equipped with a display). Specific examples of these electronic devices are shown in FIGS.
[0225]
FIG. 27A illustrates a display device, which includes a housing 2001, a support base 2002, a display portion 2003, a speaker portion 2004, a video input terminal 2005, and the like. By using the present invention for the display portion 2003 and other circuits, the display device of the present invention is completed. The display device includes all display devices for displaying information such as a personal computer, a TV broadcast reception, and an advertisement display.
[0226]
FIG. 27B illustrates a digital still camera, which includes a main body 2101, a display portion 2102, an image receiving portion 2103, operation keys 2104, an external connection port 2105, a shutter 2106, and the like. By using the present invention for the display portion 2102 and other circuits, the digital still camera of the present invention is completed.
[0227]
FIG. 27C illustrates a laptop personal computer, which includes a main body 2201, a housing 2202, a display portion 2203, a keyboard 2204, an external connection port 2205, a pointing mouse 2206, and the like. By using the present invention for the display portion 2203 and other circuits, the notebook personal computer of the present invention is completed.
[0228]
FIG. 27D illustrates a mobile computer, which includes a main body 2301, a display portion 2302, a switch 2303, operation keys 2304, an infrared port 2305, and the like. By using the present invention for the display portion 2302 and other circuits, the mobile computer of the present invention is completed.
[0229]
FIG. 27E illustrates a portable image reproducing device (specifically, a DVD reproducing device) provided with a recording medium, which includes a main body 2401, a housing 2402, a display portion A2403, a display portion B2404, and a recording medium (DVD or the like). A reading unit 2405, operation keys 2406, a speaker unit 2407, and the like are included. A display portion A2403 mainly displays image information, and a display portion B2404 mainly displays character information. By using the present invention for the display portions A, B 2403, 2404 and other circuits, the image reproducing apparatus of the present invention is completed. Note that an image reproducing device provided with a recording medium includes a home game machine and the like.
[0230]
FIG. 27F illustrates a goggle type display (head mounted display), which includes a main body 2501, a display portion 2502, and an arm portion 2503. By using the present invention for the display portion 2502 and other circuits, the goggle type display of the present invention is completed.
[0231]
FIG. 27G shows a video camera, which includes a main body 2601, a display portion 2602, a housing 2603, an external connection port 2604, a remote control receiving portion 2605, an image receiving portion 2606, a battery 2607, an audio input portion 2608, operation keys 2609, and the like. . By using the present invention for the display portion 2602 and other circuits, the video camera of the present invention is completed.
[0232]
Here, FIG. 27H shows a mobile phone, which includes a main body 2701, a housing 2702, a display portion 2703, an audio input portion 2704, an audio output portion 2705, operation keys 2706, an external connection port 2707, an antenna 2708, and the like. By using the present invention for the display portion 2703 and other circuits, the cellular phone of the present invention is completed.
[0233]
As described above, the applicable range of the present invention is so wide that it can be used for electronic devices in various fields. In addition, this embodiment can be implemented in combination with Embodiments 1 to 8.
[0234]
(Example 10)
In this example, characteristics of a TFT in the case where the first electrode and the second electrode are electrically connected in the TFT of the present invention will be described.
[0235]
FIG. 28A is a cross-sectional view of a TFT in which the first electrode and the second electrode of the present invention are electrically connected. For comparison, a cross-sectional view of a TFT having only one electrode is shown in FIG. FIG. 29 shows the relationship between the gate voltage and the drain current obtained by simulation in the TFT shown in FIGS. 28A and 28B.
[0236]
The TFT illustrated in FIG. 28A includes a first electrode 2801, a first insulating film 2802 in contact with the first electrode 2801, a semiconductor film 2808 in contact with the first insulating film 2802, and a semiconductor film 2808. A second insulating film 2806 in contact with the second insulating film 2806 and a second electrode 2807 in contact with the second insulating film are provided. The semiconductor film 2808 includes a channel formation region 2803, a first impurity region 2804 in contact with the channel formation region 2803, and a second impurity region 2805 in contact with the first impurity region 2804.
[0237]
The first electrode 2801 and the second electrode 2807 overlap with each other with the channel formation region 2803 interposed therebetween. The same voltage is applied to the first electrode 2801 and the second electrode 2807.
[0238]
The first insulating film 2802 and the second insulating film 2806 are formed of silicon oxide. The first electrode and the second electrode 2807 are made of Al. The channel length is 7 μm, the channel width is 4 μm, the thickness of the first insulating film in the portion where the first gate electrode and the channel formation region overlap is 110 μm, the portion where the second gate electrode and the channel formation region overlap The thickness of the second insulating film is 110 μm. The thickness of the channel formation region is 50 nm, and the length of the first impurity region in the channel length direction is 1.5 μm.
[0239]
In the channel formation region 2803, 1 × 10 ¹⁷ / Cm ^Three The p-type impurity is doped, and the first impurity region is 3 × 10 ¹⁷ / Cm ^Three An impurity imparting n-type is doped, and the second impurity region has a concentration of 5 × 10 5. ¹⁹ / Cm ^Three An impurity imparting n-type is doped.
[0240]
The TFT illustrated in FIG. 28B includes a first insulating film 2902, a second insulating film 2906 in contact with the first insulating film 2902, and a second electrode 2907 in contact with the second insulating film. ing. The semiconductor film 2908 includes a channel formation region 2903, a first impurity region 2904 in contact with the channel formation region 2903, and a second impurity region 2905 in contact with the first impurity region 2904.
[0241]
The second electrode 2907 overlaps with the channel formation region 2903.
[0242]
The first insulating film 2902 and the second insulating film 2906 are formed of silicon oxide. The second electrode 2907 is made of Al. The channel length is 7 μm, the channel width is 4 μm, and the thickness of the second insulating film in the portion where the second gate electrode and the channel formation region overlap is 110 μm. The thickness of the channel formation region is 50 nm, and the length of the first impurity region in the channel length direction is 1.5 μm.
[0243]
In the channel formation region 2903, 1 × 10 ¹⁷ / Cm ^Three The p-type impurity is doped, and the first impurity region is 3 × 10 ¹⁷ / Cm ^Three An impurity imparting n-type is doped, and the second impurity region has a concentration of 5 × 10 5. ¹⁹ / Cm ^Three An impurity imparting n-type is doped.
[0244]
In FIG. 29, the horizontal axis represents the gate voltage, and the vertical axis represents the drain current. The value of the drain current with respect to the gate voltage of the TFT in FIG. 28A is indicated by a solid line, and the value of the drain current with respect to the gate voltage of the TFT in FIG.
[0245]
From FIG. 29, the mobility of the TFT in FIG. ² / V · s and an S value of 0.118 V / dec were obtained. In FIG. 28B, the TFT mobility is 86.3 cm. ² / V · s and an S value of 0.160 V / dec were obtained. Therefore, when the first electrode and the second electrode are provided and the second electrode is electrically connected, the mobility is higher and the S value is smaller than when only one electrode is provided. .
[0246]
Example 11
In this embodiment, an example of manufacturing a semiconductor film by a method different from that in Embodiment 1 will be described.
[0247]
In FIG. 30A, reference numeral 600 denotes a substrate having an insulating surface. In FIG. 30A, a substrate 600 can be a glass substrate, a quartz substrate, a ceramic substrate, or the like. Alternatively, a silicon substrate, a metal substrate, or a stainless steel substrate with an insulating film formed thereon may be used. Alternatively, a plastic substrate having heat resistance that can withstand the processing temperature in this step may be used.
[0248]
First, as illustrated in FIG. 30A, first electrodes 602 a and 602 b are formed over a substrate 600. The first electrodes 602a and 602b only need to be formed of a conductive material. Typically, it can be formed of one or more alloys or compounds selected from aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), and titanium (Ti). Alternatively, a stack of several conductive films may be used as the first electrode.
[0249]
A first insulating film 601 is formed on the insulating surface so as to cover the first electrodes 602a and 602b. The first insulating film 601 is formed using a silicon oxide film, a silicon nitride film, or a silicon oxynitride film (SiO _x N _y ) Etc. A typical example has a two-layer structure as the first insulating film 601, and SiH _Four , NH _Three And N ₂ A first silicon oxynitride film formed using O as a reaction gas is formed in a thickness of 50 to 100 nm, SiH. _Four And N ₂ A structure in which a second silicon oxynitride film formed using O as a reaction gas is formed to a thickness of 100 to 150 nm is employed. Further, as one layer of the first insulating film 601, a silicon nitride film (SiN film) having a thickness of 10 nm or less, or a second silicon oxynitride film (SiN) _x O _y It is preferable to use a film (X >> Y). Since nickel tends to move to a region having a high oxygen concentration during gettering, it is extremely effective to use a silicon nitride film as the first insulating film in contact with the semiconductor film. Alternatively, a three-layer structure in which a first silicon oxynitride film, a second silicon oxynitride film, and a silicon nitride film are sequentially stacked may be used.
[0250]
Next, a first semiconductor layer 603 having an amorphous structure is formed over the first insulating film. For the first semiconductor layer 603, a semiconductor material containing silicon as its main component is used. Typically, an amorphous silicon film, an amorphous silicon germanium film, or the like is applied, and the film is formed to a thickness of 10 to 100 nm by a plasma CVD method, a low pressure CVD method, or a sputtering method. In order to obtain a semiconductor layer having a good crystal structure by subsequent crystallization, the concentration of impurities such as oxygen and nitrogen contained in the film of the first semiconductor layer 603 having an amorphous structure is set to 5 × 10. ¹⁸ /cm ^Three It may be reduced to (atomic concentration measured by secondary ion mass spectrometry (SIMS)) or less. These impurities interfere with subsequent crystallization, and also increase the density of capture centers and recombination centers even after crystallization. Therefore, it is desirable not only to use a high-purity material gas but also to use an ultrahigh vacuum-compatible CVD apparatus equipped with a mirror surface treatment (electropolishing treatment) in the reaction chamber and an oil-free vacuum exhaust system.
[0251]
Next, as illustrated in FIG. 30B, the semiconductor layer 603 is crystallized by a laser crystallization method, so that a second semiconductor layer 605 having crystallinity is generated. Here, after the heat treatment for dehydrogenation (450 ° C., 1 hour), the semiconductor layer 603 was crystallized by a laser crystallization method. Note that laser irradiation was performed in air or an oxygen atmosphere. A pulse oscillation type or continuous emission type excimer laser having a wavelength of 400 nm or less, or a YAG laser can be used. Further, instead of excimer laser light, light emitted from an ultraviolet lamp may be used. In the case of using these lasers, it is preferable to use a method in which laser light emitted from a laser oscillator is linearly collected by an optical system and irradiated onto a semiconductor layer. Crystallization conditions are appropriately selected by the practitioner, but when an excimer laser is used, the pulse oscillation frequency is 300 Hz and the laser energy density is 100 to 400 mJ / cm. ² (Typically 200-300mJ / cm ² ). When using a YAG laser, the second harmonic and the third harmonic are used, the pulse oscillation frequency is 30 to 300 kHz, and the laser energy density is 300 to 600 mJ / cm. ² (Typically 350-500mJ / cm ² ) Then, when the laser beam condensed linearly with a width of 100 to 1000 μm, for example 400 μm, is irradiated over the entire surface of the substrate, the superposition ratio (overlap ratio) of the linear laser light at this time is 50 to 90%. Good.
[0252]
When laser light (first laser light) is irradiated, unevenness is formed on the surface of the second semiconductor layer and a thin oxide film 606 is formed. (Fig. 30 (B))
[0253]
Next, the oxide film 606 is removed with an etchant containing hydrofluoric acid.
[0254]
Next, the second semiconductor layer having a crystal structure is irradiated with laser light (second laser light) in a nitrogen atmosphere or in a vacuum. When laser light (second laser light) is irradiated, the difference in height of the irregularities formed by the irradiation of the first laser light (PV value: Peak to Valley, difference between the maximum and minimum heights) Is reduced, that is, planarized, and the third semiconductor layer 607 is formed. Here, the PV value of the unevenness may be observed with an AFM (atomic force microscope). Specifically, the surface where the PV value of the unevenness formed by the irradiation of the first laser beam was about 10 nm to 30 nm is changed to the PV value of the unevenness on the surface by the irradiation of the second laser beam. It can be 5 nm or less. As this laser light (second laser light), excimer laser light having a wavelength of 400 nm or less, and second and third harmonics of a YAG laser are used. Further, instead of excimer laser light, light emitted from an ultraviolet lamp may be used.
[0255]
The energy density of the second laser beam is larger than the energy density of the first laser beam, preferably 30 to 60 mJ / cm. ² Enlarge. However, the energy density of the second laser beam is 90 mJ / cm higher than the energy density of the first laser beam. ² When the energy density is larger than the above, the surface roughness increases, and further, the crystallinity is lowered or microcrystallized, and the characteristics tend to deteriorate.
[0256]
Note that the irradiation with the second laser light is higher than the energy density of the first laser light, but the crystallinity hardly changes before and after the irradiation. Also, the crystal state such as the grain size hardly changes. That is, it seems that only the flattening is performed by the irradiation of the second laser beam.
[0257]
The merit that the semiconductor layer having a crystal structure is planarized by irradiation with the second laser light is very large. For example, since the planarity is improved, a second insulating film used as a gate insulating film to be formed later can be thinned, and the mobility of the TFT can be improved. In addition, when flatness is improved, off current can be reduced when a TFT is manufactured.
[0258]
Next, a semiconductor film having a desired shape is formed on the third semiconductor layer 607 by using a known patterning technique.
[0259]
This embodiment can be implemented in combination with any of Embodiments 1 to 10.
[0260]
Example 12
In this embodiment, a structure different from that of Embodiment 1 of a pixel of a light-emitting device which is one of semiconductor devices of the present invention will be described.
[0261]
FIG. 32 shows a top view of a pixel of the light emitting device of this embodiment.
[0262]
Reference numeral 901 denotes an n-channel TFT, and reference numeral 902 denotes a p-channel TFT. Reference numeral 903 denotes a source wiring, 904 denotes a power supply line, 905 denotes a gate wiring, 906 denotes a common wiring, and 911 denotes a capacitor semiconductor film.
[0263]
In this embodiment, the power supply line 904 and the gate wiring 905 are formed simultaneously from the same conductive film. In other words, the power supply line 904 and the gate wiring 905 are formed in the same layer. The gate wirings 905 included in adjacent pixels are connected to each other through a connection wiring 907 formed in the same layer as the common wiring 906.
[0264]
A part of the gate wiring 905 functions as a second electrode of the n-channel TFT 901. A part of the common wiring 906 functions as a first electrode of the n-channel TFT 901. In addition, one of the source region and the drain region of the n-channel TFT 901 is connected to the source wiring 903, and the other is connected to the first electrode 909 of the p-channel TFT 902 through a connection wiring 908 formed in the same layer as the source wiring 903. Connected to the second electrode 910.
[0265]
One of the source region and the drain region of the p-channel TFT 902 is connected to the power supply line 904 through a connection wiring 912 formed in the same layer as the source wiring 903, and the other is connected in the same layer as the source wiring 903. The pixel electrode 914 is connected to the pixel electrode 914 with the wiring 913 interposed therebetween.
[0266]
The first electrode 909 overlaps with the capacitor wiring 911 with a first insulating film (not shown) interposed therebetween. The capacitor wiring 911 is connected to the power supply line 904.
[0267]
In this embodiment, since the source wiring and the power supply line are formed in different layers, they can be overlapped with each other, and as a result, the aperture ratio can be increased. Note that the present invention is not limited to this structure, and the power supply line may be formed in a layer above the source wiring. Further, either the source wiring or the power supply line may be formed in the same layer as the common wiring.
[0268]
In this embodiment, even in a TFT in the same pixel, a TFT used as a switching element (in this embodiment, an n-channel TFT 901) applies a common voltage to the first electrode. By applying a common voltage to the first electrode, variation in threshold value can be suppressed as compared with a case where there is one electrode, and off-state current can be suppressed.
[0269]
In addition, a TFT (p-channel TFT 902 in this embodiment) that flows a larger current than a TFT used as a switching element electrically connects the first electrode and the second electrode. By applying the same voltage to the first electrode and the second electrode, the depletion layer spreads as fast as when the film thickness of the semiconductor film is substantially reduced, so that the subthreshold coefficient can be reduced. Further, the field effect mobility can be improved. Therefore, the on-current can be increased as compared with the case of one electrode. Therefore, the driving voltage can be lowered by using the TFT having this structure in the driving circuit. In addition, since the on-current can be increased, the TFT size (especially the channel width) can be reduced. Therefore, the integration density can be improved.
[0270]
(Example 13)
In this embodiment, an example of a thin film transistor included in a semiconductor device of the present invention will be described with reference to FIGS.
[0271]
FIG. 33 shows a cross-sectional view of the thin film transistor of this example. The thin film transistor illustrated in FIG. 33 includes a first electrode 3001, a first insulating film 3002 in contact with the first electrode 3001, a semiconductor film 3008 in contact with the first insulating film 3002, and a second film in contact with the semiconductor film 3008. Insulating film 3006 and second electrode 3007 in contact with the second insulating film. The semiconductor film 3008 includes a channel formation region 3003, a first impurity region 3004 in contact with the channel formation region 3003, and a second impurity region 3005 in contact with the first impurity region 3004.
[0272]
The concentration of one conductivity type impurity added to the first impurity region 3004 is lower than the concentration of one conductivity type impurity added to the second impurity region 3005.
[0273]
The first electrode 3001 and the second electrode 3007 overlap with each other with the channel formation region 3003 interposed therebetween. The same voltage is applied to the first electrode 3001 and the second electrode 3007.
[0274]
In the thin film transistor of this embodiment, the tapered portion of the first electrode 3001 overlaps with the first impurity region 3004. The first electrode 3001 is almost flat in a portion overlapping with the channel formation region 3003. With the above structure, the first electrode and the channel formation region overlap with each other with a substantially constant interval. In this state, the thickness of the first insulating film in the portion where the first electrode and the channel formation region overlap with each other and the thickness of the second insulating film in the portion where the second electrode and the channel formation region overlap with each other. If the film thickness is made substantially the same, the S value can be made smaller.
[0275]
This example can be implemented in combination with Examples 1-12.
[0276]
(Example 14)
In this embodiment, an actual measurement value of a drain current Id with respect to a voltage difference (gate voltage Vgs) between a second electrode and a source region in a TFT having two electrodes of the present invention will be described. Note that actual measurement values were obtained in each case when the first electrode was set to GND and when the first electrode and the second electrode were electrically connected. For comparison, the measured value of the drain current Id with respect to the gate voltage of the TFT without the first electrode was also obtained.
[0277]
A specific structure of the TFT used in this embodiment is shown in FIG. FIG. 37A shows a top view of a TFT having two electrodes of the present invention, and FIG. 37B shows a cross-sectional view taken along line AA ′ of FIG. FIG. 37C shows a top view of a TFT having only a second electrode for comparison, and FIG. 37D shows a cross-sectional view taken along line BB ′ of FIG.
[0278]
37A and 37B, a base film 901 using a SiNO film is formed with a thickness of 50 nm on a glass substrate 900, and W of 100 nm is first formed on the base film 901. The electrode 902 is formed. A first insulating film 903 that functions as a gate insulating film is formed over the base film 901 so as to cover the first electrode 902. Note that the first insulating film 903 was formed of a 110 nm SiNO film.
[0279]
A semiconductor film 904 having a thickness of 54 nm is formed over the first insulating film 903. Next, a second insulating film 905 having a thickness of 115 nm using a SiNO film was formed. A second electrode 906 including two conductive films 906a and 906b is formed over the second insulating film 905. In this embodiment, the second electrode 906 is formed by stacking 50 nm of TaN and 370 nmW. Further, an impurity is added to the semiconductor film 904, and the semiconductor film 904 includes a channel formation region 907 and an impurity region 908 sandwiching the channel formation region.
[0280]
The TFTs shown in FIGS. 37C and 37D are different from the TFTs shown in FIGS. 37A and 37B only in that the first electrode 902 is not provided.
[0281]
FIG. 34 shows measured values of the drain current Id with respect to the voltage difference (gate voltage Vgs) between the second electrode and the source region of the TFT shown in FIGS. 37C and 37D. In the TFTs shown in FIGS. 37A and 37B, when the first electrode 902 is set to GND, the drain current Id with respect to the voltage difference (gate voltage Vgs) between the second electrode and the source region. The measured value of is shown in FIG. In the TFT shown in FIGS. 37A and 37B, a voltage difference (gate voltage) between the second electrode and the source region when the first electrode 902 and the second electrode 906 are electrically connected to each other. The measured value of the drain current Id with respect to (Vgs) is shown in FIG. In each graph, the solid line indicates the drain current Id, and the broken line indicates the mobility.
[0282]
From the comparison between FIG. 34 and FIG. 35 and FIG. 36, the threshold value is closer to 0 and the S value is improved when the first electrode is provided, compared with the case where the first electrode is not provided. I understand. Further, from the comparison between FIG. 35 and FIG. 36, the on-current is higher when the first electrode and the second electrode are electrically connected than when the first electrode is grounded. You can see it gets higher.
[0283]
【The invention's effect】
In the present invention, by applying a common voltage to the first electrode, variation in threshold value can be suppressed as compared with the case where there is one electrode, and off current can be suppressed.
[0284]
In addition, by applying the same voltage to the first electrode and the second electrode, the depletion layer spreads quickly in the same way as the thickness of the semiconductor film is substantially reduced, so the subthreshold coefficient is reduced. And field effect mobility can be further improved. Therefore, the on-current can be increased as compared with the case of one electrode. Therefore, the driving voltage can be lowered by using the TFT having this structure in the driving circuit. In addition, since the on-current can be increased, the TFT size (especially the channel width) can be reduced. Therefore, the integration density can be improved.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view illustrating a structure of a TFT of the present invention.
FIG. 2 is a cross-sectional view illustrating a manufacturing process of a driver circuit and a pixel portion in a light-emitting device.
FIG. 3 is a cross-sectional view illustrating a manufacturing process of a driver circuit and a pixel portion in a light-emitting device.
FIG. 4 is a cross-sectional view illustrating a manufacturing process of a driver circuit and a pixel portion in a light-emitting device.
FIG. 5 is a cross-sectional view illustrating a manufacturing process of a driver circuit and a pixel portion in a light-emitting device.
FIG. 6 is a cross-sectional view illustrating a manufacturing process of a driver circuit and a pixel portion in a light-emitting device.
FIG. 7 is a top view illustrating a manufacturing process of a pixel portion of a light-emitting device.
FIG. 8 is a top view illustrating a manufacturing process of a pixel portion of a light-emitting device.
FIG 9 is a top view illustrating a structure of a pixel portion of a light-emitting device.
FIG 10 is a top view illustrating a structure of a pixel portion of a light-emitting device.
11 is a cross-sectional view illustrating a structure of a pixel portion of a light-emitting device.
FIG. 12 is a circuit diagram of a flip-flop circuit.
FIG. 13 is a top view of a flip-flop circuit.
FIG. 14 is a cross-sectional view of a flip-flop circuit.
FIG. 15 is a cross-sectional view illustrating a manufacturing process of a driver circuit and a pixel portion in a liquid crystal display device.
FIG. 16 is a cross-sectional view illustrating a manufacturing process of a driver circuit and a pixel portion in a liquid crystal display device.
FIG 17 is a cross-sectional view illustrating a structure of a liquid crystal display device.
FIG. 18 is a top view illustrating a manufacturing process of a pixel portion in a liquid crystal display device.
FIG 19 is a top view illustrating a structure of a pixel portion of a liquid crystal display device.
FIG. 20 is a diagram showing a step of crystallizing a semiconductor layer.
FIG. 21 is a diagram showing a step of crystallizing a semiconductor layer.
FIG. 22 shows a step of crystallizing a semiconductor layer.
FIG. 23 is a diagram showing a step of crystallizing a semiconductor layer.
FIG 24 is a block diagram illustrating a structure of a light-emitting device.
FIG 25 is a block diagram illustrating a structure of a liquid crystal display device.
FIG 26 illustrates an external view and a cross-sectional view of a light-emitting device.
27 is a diagram of an electronic device using a semiconductor device of the invention. FIG.
FIG. 28 is a diagram showing a structure of a TFT used for simulation.
FIG. 29 is a graph showing characteristics of TFTs obtained by simulation.
FIG. 30 is a diagram showing a step of crystallizing a semiconductor layer.
FIG. 31 shows a circuit diagram of a general thin film transistor and a circuit diagram of a thin film transistor of the present invention.
FIG. 32 is a top view illustrating a structure of a pixel portion of a light emitting device.
FIG. 33 is a cross-sectional view of a thin film transistor of the present invention.
FIG. 34 shows measured values of Id-Vgs characteristics of a general TFT.
FIG. 35 shows measured values of Id-Vgs characteristics of the TFT of the present invention.
FIG. 36 shows measured values of Id-Vgs characteristics of the TFT of the present invention.
FIG. 37 is a top view and a cross-sectional view of a TFT for which an actual measurement value is obtained.

Claims (7)

A semiconductor device having a first thin film transistor, a second thin film transistor, and a light emitting element,
The first and second thin film transistors include a first electrode, a first insulating film formed in contact with the first electrode, a semiconductor film formed in contact with the first insulating film, A second insulating film formed in contact with the semiconductor film; and a second electrode formed in contact with the second insulating film;
The first electrode and the second electrode overlap with each other with a channel formation region of the semiconductor film interposed therebetween,
The light emitting element includes a third electrode, a fourth electrode, and a light emitting layer provided between the third electrode and the fourth electrode,
The video signal input to the second electrode of the second thin film transistor is controlled by the first thin film transistor,
A drain current of the second thin film transistor is controlled by a video signal input to the second electrode;
The drain current is input to the third electrode;
The first thin film transistor is an n-channel thin film transistor;
The second thin film transistor is a p-channel thin film transistor,
A constant voltage is applied to the first electrode of the first thin film transistor;
The semiconductor device, wherein the first electrode and the second electrode of the second thin film transistor are electrically connected to each other. A semiconductor device having a first thin film transistor, a second thin film transistor, and a light emitting element,
The first and second thin film transistors include a first electrode, a first insulating film formed in contact with the first electrode, a semiconductor film formed in contact with the first insulating film, A second insulating film formed in contact with the semiconductor film; and a second electrode formed in contact with the second insulating film;
The first electrode and the second electrode overlap with each other with a channel formation region of the semiconductor film interposed therebetween,
The light emitting element includes a third electrode, a fourth electrode, and a light emitting layer provided between the third electrode and the fourth electrode,
The video signal input to the second electrode of the second thin film transistor is controlled by the first thin film transistor,
A drain current of the second thin film transistor is controlled by a video signal input to the second electrode;
The drain current is input to the third electrode;
The first thin film transistor is an n-channel thin film transistor;
The second thin film transistor is a p-channel thin film transistor,
A constant voltage is applied to the first electrode of the first thin film transistor;
The first electrode and the second electrode of the second thin film transistor are electrically connected through a contact hole formed in the first insulating film and the second insulating film. A semiconductor device characterized by the above. In claim 1 or claim 2 ,
A semiconductor device, wherein a constant voltage lower than a threshold voltage of the first thin film transistor is applied to the first electrode of the first thin film transistor. In any one of Claims 1 thru | or 3 ,
The first insulating film and the second insulating film have the same dielectric constant,
The film thickness of the portion of the first insulating film overlapping the first electrode is the same as the film thickness of the second insulating film overlapping the second electrode. Semiconductor device. In any one of Claims 1 thru | or 3 ,
The film thickness of the first insulating film in the portion where the channel formation region and the first electrode overlap is defined as d1, and the second portion in the portion where the channel formation region and the second electrode overlap. A semiconductor device characterized by satisfying | d1-d2 | /d1≦0.1 and | d1-d2 | /d2≦0.1, where d2 is the thickness of the insulating film. In any one of Claims 1 thru | or 3 ,
The film thickness of the first insulating film in the portion where the channel formation region and the first electrode overlap is defined as d1, and the second portion in the portion where the channel formation region and the second electrode overlap. A semiconductor device characterized in that | d1-d2 | /d1≦0.05 and | d1-d2 | /d2≦0.05 are satisfied, where d2 is the thickness of the insulating film. A display device, a digital still camera, a notebook personal computer, a mobile computer, an image reproducing device, a goggle type display, a video camera, or the like characterized by using the semiconductor device according to any one of claims 1 to 6. mobile phone.

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