JP4319110B2 - Wireless communication device - Google Patents

Description

  The present invention relates to a wireless communication apparatus that obtains a stable reference signal by electronically and automatically controlling the frequency and phase of a reference oscillator and a PLL (Phase-Locked Loop) circuit.

In the prior art, a transmission PLL frequency synthesizer configured to cancel a frequency component affected by the feedback action is used, and a transmission signal output from the transmission PLL frequency synthesizer loop is transmitted by a single reference oscillator to the transmission PLL frequency. Stable modulation that is not affected by the feedback action of the synthesizer loop is performed. And a receiving PLL frequency synthesizer configured to cancel the modulation signal component, and the intermediate frequency reference signal output from the receiving PLL frequency synthesizer loop by the one reference oscillator is not affected by the modulation signal. I am doing so. (For example, refer to Patent Document 1).
Japanese Patent Laid-Open No. 9-8688 (page 7, FIG. 1)

In such a wireless communication device, an AFC (Automatic Frequency Control) operation circuit that normally operates in a reception mode is provided in the reception circuit.
In a wireless communication apparatus having both the AFC operation circuit and the PLL operation circuit as shown in the above cited example, the technology that is the background of the present invention is shown in FIGS. The following description will be given as a conventional technique.

First, FIG. 2 includes, as a conventional example, one reference oscillator, a local oscillation PLL circuit for transmission and reception, a transmission intermediate frequency PLL circuit, and an AFC operation function that operates in a reception mode. It is a block diagram of the radio | wireless communication apparatus provided with the orthogonal modulator.
In FIG. 2, 1 is a reception mixer (Rx Mix) that receives a received signal and converts the frequency into an intermediate frequency signal, 8 is a transmission mixer (Tx Mix) that synthesizes a transmission carrier, and 17 is a local oscillation frequency in Rx Mix1 and Tx Mix8. A local voltage controlled oscillator (Lo VCO (Voltage controlled oscillator)) 18 is connected to the Lo VCO 17 and is a local low pass filter (Lo LPF) as a loop filter of a PLL frequency synthesizer having a transmission / reception local oscillation frequency. A transmission intermediate frequency voltage controlled oscillator (Tx IF VCO) that oscillates and supplies a transmission intermediate frequency to Mix8, 6 is connected to the Tx IF VCO 20 and is a transmission intermediate frequency low-pass filter as a loop filter of a PLL frequency synthesizer of the transmission intermediate frequency Tx IF LPF) and 4b are integrated circuits having two PLL synthesizer main circuits, one is a PLL frequency synthesizer combined with Lo VCO 17 and Lo LPF 18 to form a phase-locked loop, and the other is Tx IF VCO 20 and Tx IF LPF 6 The dual phase lock loop integrated circuit (Dual PLL-IC), 5c, which is a PLL frequency synthesizer that forms a phase lock loop in combination with the frequency control so as to match the frequency of the received signal by the AFC operation output from the demodulator A reference oscillator which oscillates the PLL reference frequency to the Dual PLL-IC 4b and supplies the output to the Dual PLL-IC 4b, and 19 is a combined transmission carrier output of Tx Mix8 for each of the I-phase and Q-phase. Frequency modulation by modulation signal Others are quadrature modulator phase modulation is performed.

  Next, FIG. 3 shows, as another conventional example, one reference oscillator, separate local oscillation PLL circuits for transmission and reception, a transmission intermediate frequency PLL circuit, and an AFC operation function that operates in the reception mode. It is a block diagram of the radio communication equipment principal part provided with the circuit system and the quadrature modulator.

Description of the same block numbers as those shown in the block diagram of FIG. 2 is omitted.
In FIG. 3, 2 is a reception local voltage controlled oscillator (Rx Lo VCO) that oscillates and supplies a local oscillation frequency to Rx Mix 1 and 3 is connected to Rx Lo VCO 2 and is received as a loop filter of a PLL frequency synthesizer of the reception local oscillation frequency. A local low pass filter (Rx Lo LPF), 9c is an integrated circuit of a PLL frequency synthesizer main circuit, and a phase locked loop integrated circuit (PLL) which is a PLL frequency synthesizer that is combined with Rx Lo VCO2 and Rx Lo LPF3 to form a phase locked loop. -IC) 10 is a transmission local voltage controlled oscillator (Tx Lo VCO) that oscillates and supplies a local oscillation frequency to Tx Mix 8, 11 is connected to Tx Lo VCO 10 and is transmitted as a loop filter of a PLL frequency synthesizer of the transmission local oscillation frequency Local law The filter (Tx Lo LPF), 4c is an integrated circuit having two PLL frequency synthesizer main circuits, one of which is combined with the Tx Lo VCO 10 and the Tx Lo LPF 11 to form a phase locked loop, and the other is the Tx Lo synthesizer. Dual phase-locked loop integrated circuit (Dual PLL-IC), 5d, which is a PLL frequency synthesizer that forms a phase-locked loop in combination with IF VCO 20 and Tx IF LPF6. And a reference oscillator that oscillates the PLL reference frequency to the PLL-IC 9c and the Dual PLL-IC 4c and supplies the output thereof.

The circuit configurations of FIGS. 2 and 3 include a mixer circuit, an AFC operation function, a quadrature modulator, and a reference oscillator common to transmission and reception as an oscillation source of a reference oscillation frequency supplied to the PLL of the transmission / reception circuit. This is advantageous in that the circuit configuration is relatively simple and that an analog audio signal and a digital data signal can be modulated because a quadrature modulator is used. On the other hand, if a phase error or amplitude deviation occurs in the modulation signal (I-phase / Q-phase component signals), the modulated wave includes several percent of the AM modulation component at the output end of the quadrature modulator.
When this is combined with a non-linear amplifier suitable for high power amplification, the modulated wave is distorted and communication information is not accurately transmitted. Since a non-linear amplifier is used in the transmitter of a radio unit having a high power output of 3 W or more, it causes a significant deterioration in the adjacent channel leakage power characteristic of the amplified signal, and in particular, it is required to keep the adjacent channel leakage power low. This is not suitable for communication systems such as the TDMA system (time division multiple access).

Further, FIG. 4 is a block diagram of a main part of a direct modulation type radio communication apparatus in which a modulation signal is directly supplied to a VCO at a transmission intermediate frequency stage and modulated as another conventional example.
Description of the same block numbers as those shown in the block diagram of FIG. 3 is omitted. 7 is a modulation transmission intermediate frequency voltage controlled oscillator (Tx IF VCO (M)) that oscillates a transmission intermediate frequency, performs frequency modulation or phase modulation with a modulation signal, and supplies the modulated signal to Tx Mix 8, and 5e is a modulation signal in the transmission mode. The Tx IF VCO (M) 7 has a direct modulation method that can perform frequency or phase modulation at the same time, and in the reception mode, the output frequency of the Rx Lo VCO 2 matches the frequency of the received signal by AFC operation. And a reference oscillator that oscillates a PLL reference frequency to the PLL-IC 9c and the Dual PLL-IC 4c and supplies the output thereof.

The modulation circuit of the circuit of FIG. 4 is a direct modulation system in which frequency or phase modulation is directly applied to the VCO (Tx IF VCO (M) 7) of the PLL circuit by a modulation signal. As in FIGS. 2 and 3, the oscillation source of the reference oscillation frequency supplied to the PLL of the transmission / reception circuit is provided with one reference oscillator common to transmission and reception.
The direct modulation performed by the VCO (Tx IF VCO (M) 7) is suitable for the modulation of an analog audio signal that is a relatively high frequency band in the modulation signal band. However, when modulating a digital data signal that is a relatively low frequency band (about DC to 300 Hz) in the modulation signal band, direct modulation of the VCO requires transmission of a direct current component. A loop LPF of a PLL circuit with a cutoff of several Hz is required, which slows down the response speed of the PLL frequency synthesizer, and is not suitable for a system that requires high-speed transmission.

  As a circuit technique for solving this problem, as shown in FIG. 4, the cut-off of the loop LPF of the PLL circuit is set to about 300 Hz, and the high frequency components (300 Hz˜ 3KHz) is modulated by the VCO, and the low frequency component (300 Hz or less) of the digital data signal is modulated on the reference oscillator 5e side having a low frequency modulation characteristic, so that a band of several Hz to 3 KHz is obtained. Some modulation signals are realized with flat frequency characteristics and modulated and synthesized by a PLL circuit.

  However, while the circuit of FIG. 4 can modulate both an analog audio signal and a digital data signal, the transmission IF circuit (Tx IF VCO (M) 7) is included in the mixer circuit (Tx Mix8) on the transmission side. Since the output of the reference oscillator 5e subjected to the low frequency modulation is supplied to both the transmission local oscillation circuit (Tx Lo VCO 10), an unnecessary frequency fluctuation may occur in the output signal of the mixer circuit (Tx Mix 8). Therefore, the circuit of FIG. 4 has a disadvantage that a desired modulated wave cannot be obtained.

Further, FIG. 5 shows that, as another conventional example, two reference oscillators, a reference oscillator 5f for supplying a reference oscillation frequency to the Dual PLL-IC 4d and a reference oscillator 5g for supplying a reference oscillation frequency to the PLL-IC 9d, are provided. A description of the same block number as that shown in the block diagram of FIG. 4 is omitted. 4d is an integrated circuit having two PLL frequency synthesizer main circuits, one of which is combined with Rx Lo VCO2 and Rx Lo LPF3 to form a phase locked loop, and the other is Tx IF VCO (M) 7 and Tx Dual phase-locked loop integrated circuit (Dual PLL-IC), which is a PLL frequency synthesizer that forms a phase-locked loop in combination with IF LPF6, and 5f can perform frequency or phase modulation on Tx IF VCO (M) 7 by a modulation signal It has a direct modulation method that can be modulated at the same time, and has an AFC operation function that can match the output frequency of the Rx Lo VCO 2 with the frequency of the received signal in the reception mode, and the PLL reference frequency is set to the Dual PLL-IC 4d. Oscillates and supplies its output A reference oscillator. 9d is an integrated circuit of a PLL frequency synthesizer main circuit, and is a phase locked loop integrated circuit (PLL-IC) that is a PLL frequency synthesizer that is combined with the Tx Lo VCO 10 and the Tx Lo LPF 11 to form a phase locked loop. The reference oscillator has an input terminal capable of frequency control from the outside, oscillates the PLL reference frequency to the PLL-IC 9d, and supplies the output thereof.

  The circuit of FIG. 5 is a transmission-only PLL frequency that receives a reference oscillation signal output from a reference oscillator (reference oscillator (1) 5g) and outputs a transmission local oscillation frequency signal generated from a transmission local oscillator (Tx Lo VCO 10). A synthesizer, a reference oscillation signal output from a reference oscillator (reference oscillator (2) 5f) is input to a dual PLL-IC 4d for transmission and reception, and a transmission / transmission modulated wave (output of Tx IF VCO (M) 7) and a receiving station section And a PLL frequency synthesizer for generating respective signals of the oscillation frequency signal (output of Rx Lo VCO2), and the modulation signal inputted in the transmission mode is the reference oscillator (2) 5f and Tx IF VCO (M ) 7. As described above, the reference oscillator (2) 5f modulates the low frequency component of the digital data signal, and the Tx IF VCO (M) 7 modulates the analog audio signal component and the high frequency component of the digital data signal. It can be applied.

The output signal of the reference oscillator (2) 5f is synthesized by the Tx IF VCO (M) 7, the synthesized wave is inputted to the transmission mixing circuit (Tx Mix8), and the output is frequency-converted and outputted as a transmission signal.
In this case, since the output frequency of the reference oscillator (1) 5g and the output frequency of the reference oscillator (2) 5f are independent oscillation frequencies, even if the frequencies are the same, they are not in a synchronous relationship.

  In the reception mode, the reference oscillator (2) 5f is controlled by the AFC operation, and the reception local oscillation signal (output of RX Lo VCO2) is controlled to match the frequency of the reception signal to obtain a reception intermediate frequency signal. . For this reason, the output frequency of the reference oscillator (2) 5f is different from the output frequency of the reference oscillator (1) 5g by a frequency controlled by the AFC operation.

Further, FIG. 6 shows another conventional example in which the transmission frequency conversion circuit in FIG. 5 is omitted and the output of the transmission modulator is directly used as a transmission signal.
Description of the same block numbers as those shown in the block diagram of FIG. 5 is omitted.
Reference numeral 21 denotes a modulation transmission voltage controlled oscillator (Tx VCO (M)) that oscillates the transmission frequency itself and performs frequency modulation or phase modulation with the modulation signal to output as a transmission signal.
A transmission low-pass filter (Tx LPF) 22 is connected to the Tx VCO (M) 21 as a loop filter of a PLL synthesizer having a transmission frequency.
Reference numeral 4e denotes an integrated circuit having two PLL frequency synthesizer circuits therein. One is a reception PLL frequency synthesizer which is combined with Rx Lo VCO2 and Rx Lo LPF3 to form a reception phase lock loop, and the other is a Tx VCO ( M) A dual phase-locked loop integrated circuit (Dual PLL-IC) which is a transmission PLL frequency synthesizer that is combined with 21 and Tx LPF 22 to form a transmission phase-locked loop.
Reference numeral 5h denotes a reference oscillator that is subjected to frequency or phase modulation by the low frequency component of the modulation signal in the transmission mode, and that is controlled by the AFC operation in the reception mode.

The circuit of FIG. 6 is a prior art example that does not include a mixer circuit in a transmission system circuit but includes a VCO (Tx VCO (M) 21) that directly oscillates and modulates a transmission signal.
Since this circuit is a VCO direct modulation, it has an advantage of less deterioration of the adjacent channel leakage power characteristics, and there is no inconvenience in AFC operation that it is one reference oscillator 5h.
However, since the transmission VCO output frequency is used as it is as the transmission signal frequency, the effect of fogging of the output frequency signal from the antenna interferes with the feedback loop circuit to each transmission / reception VCO in the case where full power transmission is started up at high speed. The output frequency fluctuation of each VCO is generated, and once it occurs, the time required for convergence becomes longer.
Therefore, a configuration like this circuit cannot be applied to a TDMA (time division multiple access) communication system that requires high-speed operation. If the mixer system is used, this phenomenon of output frequency fluctuation can be avoided.

Each of the circuits used in the conventional radio communication apparatus shown in FIGS. 2 to 6 described above has the following drawbacks.
In the conventional circuit configuration examples of FIGS. 2 and 3, when a phase error or amplitude deviation occurs in the modulation signal (I-phase / Q-phase component signals), AM-PM conversion (amplitude-phase conversion) occurs. Therefore, the adjacent channel leakage power characteristic of the modulated wave is deteriorated at the output terminal of the quadrature modulator. This is disadvantageous particularly in a system that is required to keep adjacent channel leakage power characteristics low. An example of the characteristic value of adjacent channel leakage power when this quadrature modulator is used is about −57.4 dB (measurement at the antenna terminal).

  In the conventional circuit configuration example of FIG. 4, an unnecessary frequency fluctuation may occur in the output signal of the mixer circuit (Tx Mix8). For this reason, the circuit of FIG. 4 has a drawback that a desired modulated wave having a stable frequency cannot be obtained.

In the conventional circuit configuration example of FIG. 5, in the reception mode, the output frequency of the reference oscillator (2) 5f is different from the output frequency of the reference oscillator (1) 5g by the amount controlled by the AFC operation.
In order to perform high-accuracy data communication, it is necessary to make the radio frequency of transmission / reception between the local station and the partner station an error of about 0.1 ppm. An example of the characteristic value of the adjacent channel leakage power using FIG. 5 is about −68 dB (measurement at the antenna terminal).

  In the conventional circuit configuration example of FIG. 6, when full power transmission is started up at high speed, the output frequency fluctuation of each VCO occurs due to the influence of fogging on the feedback loop to each VCO of the transmission output, In particular, it is not suitable for a TDMA communication system.

  An object of the present invention is to solve the above-mentioned drawbacks of the prior art and to provide a radio communication device having good adjacent channel leakage power characteristics with little deterioration of adjacent channel leakage power characteristics of a transmission signal.

In order to achieve this object, the wireless communication device of the present invention adapts a reception mixer that converts a reception signal input in the reception mode to a reception intermediate frequency signal, and a reception channel desired for the reception mixer. A receiving station originating PLL frequency synthesizer for supplying the receiving station originating signal;
A transmission mixer that converts a transmission intermediate frequency signal of a predetermined frequency into a transmission signal in a transmission mode; a transmission station-generated PLL frequency synthesizer that supplies a transmission station-generated signal that matches a desired transmission channel to the transmission mixer; A transmission intermediate frequency PLL circuit that supplies the transmission mixer with a transmission intermediate frequency signal of the predetermined frequency that is high-frequency modulated by a modulation signal;
A first reference oscillator that supplies a first reference frequency signal that has been low-frequency-modulated by the modulation signal and that has undergone AFC operation to the PLL frequency synthesizer from the receiving station and the transmission intermediate frequency PLL circuit;
A wireless communication device comprising a second reference oscillator for supplying a second reference frequency signal to the PLL frequency synthesizer originating from the transmitting station;
A reference oscillation PLL circuit configured to synchronize the second reference frequency signal with the first reference frequency signal after an AFC operation performed under predetermined conditions in the reception mode is completed;
When the synchronization is established, the control voltage obtained from the reference oscillation PLL circuit is temporarily stored. At the time of the temporary storage, the loop of the reference oscillation PLL circuit is disconnected, and the temporarily stored control voltage is read, By applying the second reference oscillator to the second reference oscillator, the second reference oscillator is not affected by the first reference frequency signal that is the output of the first reference oscillator that has been low-frequency modulated in the transmission mode, And a control circuit configured to synchronize the second reference frequency signal with the first reference frequency signal after the AFC operation.

When the present invention is carried out, the following effects are exhibited.
(1) Compared with the adjacent channel leakage power characteristics of the conventional circuit using the quadrature modulator, the present invention can obtain better characteristics. For example, in comparison with FIG. 5, it is an improvement effect of 10 dB (measurement at the antenna terminal). (2) The transmission frequency conversion circuit which is the mixer system of the present invention can cope with high-speed switching of transmission and reception required by the TDMA system, As an example, the high-speed transmission rise follows 250 μsec to 350 μsec.
(3) Although the transmission circuit of the present invention has two systems of the reference oscillator and the PLL circuit, a stable modulated transmission wave transmission signal without frequency fluctuation can be obtained even after mixing.
(4) Since the signals modulated by the two circuits of the reference oscillator and the VCO are synthesized by the PLL circuit, both the analog audio signal and the digital data signal can be dealt with.
(5) Since the two reference oscillators can be synchronized, the frequency difference between both reference oscillation frequencies is kept at a high accuracy of 0.03 ppm, and a transmission signal with high modulation accuracy can be obtained.

FIG. 1 is a block diagram of a wireless communication apparatus as an embodiment of the present invention. It consists of the following parts.
Reference numeral 1 denotes a reception mixer (Rx Mix) that receives a reception signal and converts the frequency into a reception intermediate frequency signal. Reference numeral 2 denotes a reception local voltage controlled oscillator (Rx Lo VCO) that oscillates and supplies a reception station oscillation signal suitable for a desired reception channel to Rx Mix1. Reference numeral 3 denotes a reception local low-pass filter (Rx Lo LPF) which is connected to the Rx Lo VCO 2 and functions as a loop filter of the reception station originating PLL frequency synthesizer.
4a is an integrated circuit including two PLL circuits, and one PLL circuit (PLL-IC (1-1)) is combined with Rx Lo VCO2 and Rx Lo LPF3 to form a phase locked loop, A receiving channel frequency selection control signal is inputted from the outside, and a receiving station originating PLL frequency synthesizer circuit is formed. The other PLL circuit (PLL-IC (1-2)) is combined with Tx IF VCO (M) 7 and Tx IF LPF 6 to form a phase-locked loop, thereby forming a transmission intermediate frequency PLL circuit. This is a dual phase-locked loop integrated circuit (Dual PLL-IC (1); first PLL) including these two PLL circuits.

5a has a control voltage terminal. In the reception mode, an AFC signal is input to the control voltage terminal, and a first reference oscillation frequency signal whose AFC operation is controlled is transmitted to and output from the PLL frequency synthesizer from the receiving station. In addition, the modulation signal is input to the control voltage terminal in the transmission mode, and the first reference oscillation frequency signal phase-modulated or frequency-modulated by the low frequency component is oscillated and output to the transmission intermediate frequency PLL circuit. is there. This output is connected to a first reference oscillator (for example, TCXO; temperature controlled crystal oscillator) which is a PLL-IC (3) 9b and a Dual PLL-IC (1) 4a.
5b oscillates the second reference frequency to supply the second reference frequency to the PLL frequency synthesizer originating from the transmitting station, and the connection destination of this signal is PLL-IC (2) 9a and PLL-IC (3) 9b. A second reference oscillator.

Reference numeral 6 denotes a transmission intermediate frequency low-pass filter (Tx IF LPF) which is connected to the Tx IF VCO (M) 7 and functions as a loop filter of a transmission intermediate frequency PLL circuit for transmission intermediate frequency signals.
Reference numeral 7 oscillates a transmission intermediate frequency, and the oscillation frequency signal is subjected to frequency modulation or phase modulation by a high frequency component of an input modulation signal. A modulation transmission intermediate frequency voltage controlled oscillator (Tx IF VCO (M)) for supplying an intermediate frequency signal to Tx Mix8.
Reference numeral 8 denotes a transmission mixer (Tx Mix) which converts the frequency of the input transmission intermediate frequency signal and the signal transmitted from the transmission station into a transmission signal and outputs it.

9a is an integrated circuit which is a part of the PLL frequency synthesizer originating from the transmission station, which is combined with the Tx Lo VCO 10 and the Tx Lo LPF 11 to form a phase lock loop, and a transmission channel frequency selection control signal is inputted from the outside. A phase-locked loop integrated circuit (PLL-IC (2); second PLL) serving as a PLL frequency synthesizer originating from the transmitter.
Reference numeral 9b denotes an integrated circuit that is a part of the reference oscillation PLL circuit. The branch output of the first reference frequency signal, which is the output of the first reference oscillator 5a, is used as an input as a reference frequency, and the output of the second reference oscillator 5b is used. A phase-locked loop integrated circuit (PLL-IC (3); second circuit) is configured such that a branch output of a second reference frequency signal is input as a controlled frequency and combined with the LPF 12 to form a phase-locked loop to form a reference oscillation PLL circuit. 3 PLL).

Reference numeral 10 denotes a transmission local voltage controlled oscillator (Tx Lo VCO) that oscillates a transmission station oscillation signal suitable for a desired transmission channel and supplies it to Tx Mix8.
Reference numeral 11 denotes a transmission local low-pass filter (Tx Lo LPF) that functions as a loop filter provided in a transmission station originating PLL frequency synthesizer that is connected to the Tx Lo VCO 10 to obtain a transmission station originating signal.
12 is a combination of the second reference oscillator 5b, the PLL-IC (3) 9b, and the SW15 to form a reference oscillation PLL circuit. The second reference frequency is phase-frequency controlled to obtain the first reference frequency. It is a low pass filter (LPF) that functions as a loop filter of a reference oscillation PLL circuit to be synchronized.
Reference numeral 13 denotes an A / D converter that performs analog / digital conversion so that the output of the LPF 12 is branched after being passed through the SW 15 and is taken into the CPU 16 as a PLL control voltage.

14a reads out again the PLL control voltage taken into the CPU 16 by the A / D converter 13 and stored in the memory, converts it from digital to analog, and uses the second reference as phase control / frequency control information via SW15. This is a D / A converter supplied to the oscillator 5b.
Reference numeral 14b denotes a D / A converter which receives AFC operation data indicating the control voltage value of the AFC operation output from the CPU 16, converts it into an analog value, and outputs it as an AFC operation signal.
Reference numeral 15 is a circuit for switching the reference oscillation PLL circuit to form a loop or to be disconnected from the loop. When the reference oscillation PLL circuit is disconnected from the loop, it is synchronized with the PLL control voltage fetched by the CPU. This SW (switch) operates to supply the output of the A converter 14a to the second reference oscillator 5b.

  16 receives and processes the received message, outputs AFC operation data indicating the control voltage value of the AFC operation, supplies this to the D / A converter 14a, and performs PLL control during the loop operation of the reference oscillation PLL circuit A voltage is taken in through the A / D converter 13 and stored in the memory. Further, the storage circuit outputs the stored data, supplies it to the D / A converter 14a, and outputs a switching control signal to the SW 15. CPU (central processing unit).

Next, the circuit operation of the characteristic part of the present invention will be described.
The first reference oscillator 5a is frequency-controlled so that the first reference frequency signal matches the frequency of the reception signal by the control voltage value of the AFC operation input to the control voltage terminal in the reception mode. The first reference frequency signal is sometimes phase-modulated or frequency-modulated by the modulation signal input to the control voltage terminal.
The Dual PLL-IC 4a (hereinafter referred to as the first PLL 4a) is a dual PLL type, and the first reference frequency signal is input as a reference frequency signal.
The PLL-IC (1-1), which is one PLL of the first PLL 4a, has a function of performing AFC control so that the oscillation frequency of the reception local voltage controlled oscillator (Rx Lo VCO2) matches the reception channel.
The PLL-IC (1-2), which is the other PLL of the first PLL 4a, performs PLL control on the oscillation frequency of the transmission intermediate frequency voltage controlled oscillator (Tx IF VCO (M)) 7 to generate a transmission intermediate frequency signal. To work.

  The first reference oscillator 5a modulates a low frequency component by a modulation signal input in the transmission mode. The signal modulated here is further input to a transmission intermediate frequency PLL circuit, and phase modulation or frequency modulation modulation of a high frequency component of the modulation signal is performed by a transmission intermediate frequency voltage controlled oscillator (Tx IF VCO (M)) 7. Is done. As a result, the modulated wave of the low frequency component and the modulated wave of the high frequency component are combined by the transmission intermediate frequency voltage controlled oscillator (Tx IF VCO (M)) 7.

The PLL-IC 9a (hereinafter referred to as the second PLL) uses the output from the second reference oscillator 5b as a reference frequency signal, and a transmission station originating PLL frequency synthesizer is configured by a combination of the Tx Lo VCO 10 and the Tx Lo LPF 11, In accordance with a transmission channel designation signal input from the outside, the PLL control is performed to obtain a transmission station originating signal.
The PLL-IC 9b (hereinafter referred to as a third PLL) uses the first reference frequency signal as a reference frequency signal, constitutes a reference oscillation PLL circuit with the LPF 12, and operates to synchronize the second reference frequency signal.
If the switch 15 is provided between the output terminal of the LPF 12 and the control input terminal of the second reference oscillator 5b, and the switching control signal supplied from the CPU 16 to the SW 15 is, for example, logic (H), the output terminal of the LPF 12 Are connected to the control input terminal of the second reference oscillator 5b. At this time, the reference oscillation PLL circuit operates as a PLL circuit.

On the other hand, if the switching control signal supplied to SW15 is, for example, logic (L), the control input terminal of the second reference oscillator 5b and the output terminal of the D / A converter 14a are connected. At this time, the reference oscillator 5b is under the control of the CPU 16.
Logic (H) is a switching control signal while the reference oscillation PLL circuit is operated after the AFC operation function is completed, and logic (L) outputs the output of the D / A converter 14a to the second reference oscillator 5b. It operates as a switching control signal during supply.
The timing at which the reference oscillation PLL circuit operates as a PLL circuit is a timing when the reception mode rises, and the other timing (steady state) is an operation under the control of the CPU 16.

Further, the circuit operation of the characteristic part of the present invention will be described. First, the AFC operation will be described.
The voltage value of the AFC operation and the voltage value of the modulation signal are input to the control voltage terminal of the first reference oscillator 5a as a voltage value synthesized by the adder circuit. In the reception mode, the voltage value during the AFC operation appears, and the modulation signal does not appear. In the transmission mode, the voltage value based on the modulation signal is added to the DC voltage value after the control of the AFC operation and is input to the first reference oscillator 5a.

The operation in the reception mode and transmission mode will be further described below.
First, the AFC operation that operates in the reception mode is a condition obtained at a predetermined timing of reception (for example, at the rise of the control channel in the reception mode) (for example, the monitoring result of the code error situation of the demodulated reception message). And the correlation between the frequency deviation of the received signal and the received signal can be calculated.
In other words, when the AFC operation loop operation is performed so that the code error of the received message on the control channel is minimized, the frequency of the signal originating from the receiving station is considered to match the frequency of the received signal. Arithmetic processing is performed by the CPU 16.

  As a calculation result of the CPU 16, the control voltage value of the AFC operation is output as AFC operation data from the CPU 16, is input to the D / A converter 14b, and is converted into an analog voltage value. This analog voltage value is input to the first reference oscillator 5a as an AFC operation signal. The first reference frequency output, which is the oscillation frequency of the first reference oscillator 5a, is controlled by the AFC operation to change the oscillation frequency, and as a result, the frequency of the reception station oscillation signal matches the frequency of the reception signal. AFC operation.

Therefore, the Rx Mix 1 is converted into an intermediate frequency signal matched to the frequency of the received signal, and the AFC operation loop operates to maintain the frequency of the received signal so as to obtain an optimal reception state.
(Demodulated data ⇒ Sign error detection ⇒ AFC operation control voltage value ⇒ Reference oscillator AFC operation control ⇒ Receiving station originating PLL frequency synthesizer ⇒ AFC operation receiving station originating signal ⇒ AFC operation receiving intermediate frequency signal ⇒ Demodulated data)

Next, the synchronization operation of the first reference oscillator 5a and the second reference oscillator 5b will be described.
Further, following the reception mode, the contact point of SW15 is selected so that the logic level of the switching control signal output from the CPU 16 is set to “H” and the output of the LPF 12 is connected to the input of the second reference oscillator 5b. .
At this time, in the third PLL 9b, a PLL loop of the reference oscillation PLL circuit is configured by the circuit of the LPF 12 and the second reference oscillator 5b.
As a result, the second reference frequency signal, which is the oscillation frequency of the second reference oscillator 5b, becomes the PLL frequency to the first reference frequency signal, which is the oscillation frequency of the first reference oscillator 5a that has been controlled in the previous AFC operation. Locked and synchronized.
Thus, when the second reference frequency signal is synchronized with the first reference frequency signal by the PLL loop of the reference oscillation PLL circuit, this synchronized PLL control voltage, that is, the LPF 12 when the PLL frequency is locked. Is output to the second reference oscillator 5b and branched to the A / D converter 13 to convert an analog value into a digital value to be converted into digital control voltage data, which is taken into the CPU 16 And stored in the memory.
(First reference frequency signal ⇒ third PLL 9 b ⇒ LPF 12 ⇒ PLL control voltage ⇒ SW 15 ⇒ second reference oscillator 5 b ⇒ second reference frequency signal)
(PLL control voltage ⇒ A / D converter 13 ⇒ digital control voltage data ⇒ CPU 16)
The AFC operation of the first reference oscillator 5a and the synchronization operation of the second reference oscillator 5b are completed in order between extremely short timings at the time of rising of the reception mode.

Next, the securing of the synchronization state of the second reference oscillator 5b in the reception mode and the transmission mode after the completion of each of the AFC operation and the synchronization operation will be described.
The CPU 16 reads out the PLL control voltage data that has been fetched and stored in the memory, and outputs the data to the D / A converter 14a. The D / A converter 14a converts the input PLL control voltage data into an analog value and outputs the analog value.
Therefore, the switching control signal output from the CPU 16 is set to the logic level “L”, the contact of the SW15 is switched, and the control input terminal of the second reference oscillator 5b is connected to the output terminal of the D / A converter 14a. Thus, the second reference oscillator 5b is switched to a configuration that operates under the control of the CPU 16 instead of the configuration of the reference oscillation PLL circuit.
Since the data of the PLL control voltage is taken into the CPU 16 in this way, even when the PLL loop of the reference oscillation PLL circuit is disconnected, the same control voltage as when the PLL circuit is locked is maintained. The second reference oscillator 5b can be kept in a synchronized state. That is, the second reference oscillator 5b ensures a state synchronized with the first reference oscillator 5a that has completed the control of the AFC operation.

Furthermore, the mode is switched from the reception mode to the transmission mode, and the operation in the transmission mode will be described.
The control voltage terminal of the first reference oscillator 5a receives a superimposed voltage corresponding to the voltage change caused by the low frequency component of the modulation signal with the control voltage of the AFC operation as the center value. By this superimposed voltage, the first reference oscillator 5a is modulated by phase shift or frequency shift, and its output is supplied as a first reference frequency signal to the transmission intermediate frequency PLL circuit.
On the other hand, since the second reference oscillator 5b is under the control of the CPU 16, it is not affected by the modulated first reference frequency signal, and sends the second reference frequency signal to the transmitting station-derived PLL frequency synthesizer. Can do.
In the circuit of the transmitting station originating PLL frequency synthesizer, a transmitting channel is designated from the outside, and its output is output from the Tx Lo VCO 10 as a transmitting station originating signal. Since this transmitting station signal is not affected by modulation, it is a pure single frequency component. Therefore, even if a mixer operation is performed with Tx Mix8, a stable desired modulated wave can be obtained from the output transmission signal.
That is, in the transmission mode, even if the first reference oscillator 5a is modulated, the transmitting station-generated PLL frequency synthesizer that generates the transmitting station-generated signal is not affected by the modulation.

As an example, the bit length representing the conversion accuracy of the A / D converter 13 and the D / A converter 14a is 10 bits, and the control accuracy of the first reference oscillator 5a and the second reference oscillator 5b is 1.5V ± 1V. When ± 10 ppm is set and the control voltage range is 3 V, the resolution of each converter is 3 V / 1024 = 2.9 mV. As a result, the output frequency accuracy of both reference oscillators is generally kept at 0.03 ppm in synchronization.
Further, when the SW15 is switched, the voltage waveform output from the D / A converter 14a may cause distortion in the voltage waveform due to the transient response of the SW15 contact switching. If the control is performed by the CPU 16, it is possible to prevent distortion of the voltage waveform by performing waveform correction in advance.
The characteristic value of the adjacent channel leakage power of the present invention is -78 dB (measured at the antenna terminal).

With the above configuration, the wireless communication device of the present invention controls the AFC operation to match the reception frequency of the reception signal of the wireless communication device of the present invention with the transmission frequency transmitted by the wireless communication device (base station) as the counterpart. On the other hand, since the transmission frequency of the wireless communication device of the present invention is PLL-synchronized with the reception frequency of the wireless communication device of the present invention, the transmission signal is transmitted to the transmission frequency transmitted by the partner wireless communication device (base station). Since the frequency match of the radio frequencies between the lines is maintained, high-quality data with very little code error (Error Rate) even when used in a TDMA system that requires a high-speed transmission / reception switching operation. It can communicate.
The control channel signal that arrives from the base station and is received by the wireless communication apparatus of the present invention is received and demodulated, and a received message is output as demodulated data. The CPU monitors the error status at this time, and the CPU calculates the error status and converts it into control data for the AFC operation to obtain a control voltage for the AFC operation. In this way, the control operation of the AFC operation is performed so that the occurrence state of the code error is minimized, thereby matching the radio frequency of the base station.
In addition, since the signal transmitted from the transmitting station that is not affected by the modulation operation is input to the Tx Mix8 circuit, the frequency conversion efficiency of the mixer is high, the generation of unnecessary frequency components is suppressed, the frequency components of the original sum and difference are generated, A stable transmission signal (modulated wave) can be obtained.

  The present invention is applied to a radio communication system used for mobile communication or fixed communication and can be used for a communication business or the like.

FIG. 1 is a block diagram of a wireless communication apparatus as an embodiment of the present invention. FIG. 2 is a block diagram of a wireless communication apparatus using a quadrature modulator, in which the transmission unit is a mixer circuit system, as a conventional example. FIG. 3 is a block diagram of a wireless communication apparatus using a quadrature modulator, in which the transmission unit is a mixer circuit system, as a conventional example. FIG. 4 is a block diagram of a wireless communication apparatus using a VCO direct modulation method as a conventional example in which the transmission unit is a mixer circuit method. As a conventional example, FIG. 5 is a block diagram of a wireless communication apparatus having a transmitter unit of a mixer circuit system, a VCO direct modulation system, and two reference oscillators. FIG. 6 is a block diagram of a wireless communication apparatus using a VCO direct modulation system as a conventional example.

Explanation of symbols

1 Rx Mix
2 Rx Lo VCO
3 Rx Lo LPF
4a, 4b, 4c, 4d, 4e Dual PLL-IC
5a, 5b, 5c, 5d, 5e, 5f, 5g, 5h Reference oscillator 6 Tx IF LPF
7 Tx IF VCO (M)
8 Tx Mix
9a, 9b, 9c, 9d, 9e PLL-IC
10 Tx Lo VCO
11 Tx Lo LPF
12 LPF
13 A / D converter
14a, 14b D / A converter
15 SW
16 CPU
17 Lo VCO
18 Lo LPF
19 Quadrature modulator 20 Tx IF VCO
21 Tx VCO (M)
22 Tx LPF

Claims (1)

A reception mixer that converts a reception signal input in the reception mode to a reception intermediate frequency signal; a reception station-derived PLL frequency synthesizer that supplies the reception mixer with a reception-station-generated signal that matches a desired reception channel;
A transmission mixer that converts a transmission intermediate frequency signal of a predetermined frequency into a transmission signal in a transmission mode; a transmission station-generated PLL frequency synthesizer that supplies a transmission station-generated signal that matches a desired transmission channel to the transmission mixer; A transmission intermediate frequency PLL circuit that supplies the transmission mixer with a transmission intermediate frequency signal of the predetermined frequency that is high-frequency modulated by a modulation signal;
A first reference oscillator that supplies a first reference frequency signal that has been low-frequency-modulated by the modulation signal and that has undergone AFC operation to the PLL frequency synthesizer from the receiving station and the transmission intermediate frequency PLL circuit;
A wireless communication device comprising a second reference oscillator for supplying a second reference frequency signal to the PLL frequency synthesizer originating from the transmitting station;
A reference oscillation PLL circuit configured to synchronize the second reference frequency signal with the first reference frequency signal after an AFC operation performed under predetermined conditions in the reception mode is completed;

When the synchronization is established, the control voltage obtained from the reference oscillation PLL circuit is temporarily stored, and at the time of the temporary storage, the loop of the reference oscillation PLL circuit is disconnected, and the temporarily stored control voltage is read out, By applying the second reference oscillator to the second reference oscillator, the second reference oscillator is not affected by the first reference frequency signal that is the output of the first reference oscillator that has been low-frequency modulated in the transmission mode, And a control circuit configured to synchronize the second reference frequency signal with the first reference frequency signal after the AFC operation.

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