JP4309898B2 - Base sequence analyzer - Google Patents

Description

  The present invention relates to a base sequence analyzer for detecting and analyzing base sequences by automatic processing.

  In the current detection type DNA chip, a chemical substance called an intercalating agent that selectively adsorbs on a double strand of DNA and generates an oxidation current in electrolysis is used. That is, after hybridization between the probe and the target is completed, the presence or absence of target adsorption is determined by immersing the electrode in the intercalating agent and detecting the oxidation current of the intercalating agent through the electrode.

  The above-described conventional current detection type DNA chip has two problems. The first is that a current other than the signal derived from the binding between the target and the probe is detected by an electrode (hereinafter referred to as a detection electrode) to which the probe is fixed, and the second is the time dependency of the amount of adsorbent insertion and This is the effect of the degradation of the intercalating agent itself on the measurement.

  Originally, the intercalating agent is selectively adsorbed on the double strands of DNA. However, since the insertion agent is actually adsorbed to portions other than the double strands in the vicinity of the detection pole, a signal is generated from this adsorption site and is superimposed on the measurement signal. This is the first problem. With regard to the first problem, a dedicated electrode (hereinafter referred to as a control electrode) for detecting a signal irrelevant to the presence or absence of DNA in the specimen is provided, and it is originally detected from the difference between signals obtained from this electrode and the probe. You have to get a signal to power.

  Here, the adsorbing amount of the intercalating agent requires a certain time until it is saturated. Also, the properties of the intercalating agent deteriorate with time. This phenomenon may affect the difference between signals obtained from the two electrodes depending on the measurement method. That is, the conditions between the paired electrodes are different. In particular, the amount of adsorbent adsorbed accumulated from the time when the electrode was immersed in the intercalating agent to the time when the measurement of the target electrode was started, or the intercalating agent deteriorated. A mismatch of conditions will occur between the pair of electrodes to be subjected to. This is the second problem.

  FIG. 18 is a diagram showing the relationship between the oxidation current in the cell 13 and the insertion agent immersion time. As can be seen from this figure, the oxidation current varies greatly depending on the immersion time.

  The second problem is not limited to the comparison between the detection electrode and the control electrode, but also when comparing probes. For example, when it is intended to determine whether MxA88, which is known as one of the single nucleotide polymorphisms of a human gene, is GG homotype, TT homotype, or GT heterotype, the probe uses G type. And T-types must be used to test the difference in signal obtained from both. For this reason, it is essential to increase measurement accuracy that each of the G-type detection probe, the T-type detection probe, and the GT-type detection probe is measured under the same conditions.

  The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a base sequence analyzing apparatus for detecting and analyzing base sequences with high accuracy by automatic processing.

In order to solve the above-described problems, a base sequence analyzer of the present invention is a base sequence analyzer comprising a base sequence analysis chip and a computer,
The base sequence analysis chip includes a substrate, a plurality of detection electrodes formed on the substrate, on which probes having a base sequence complementary to a target base sequence to be detected are immobilized, and on the substrate A control electrode formed and a probe having a base sequence complementary to the target base sequence is not immobilized; a first measurement unit formed on the substrate and measuring an electrochemical signal of the plurality of detection electrodes; A second measurement unit formed on the substrate and configured to measure an electrochemical signal of the reference electrode; and a second measurement value formed on the substrate from the first measurement value of the first measurement unit and the second measurement value of the second measurement unit. A subtractor for subtracting, and a controller for simultaneously controlling the measurement of the first measurement unit and the second measurement unit based on a signal from the outside of the substrate and controlling the subtraction of the subtraction unit, The plurality of detection poles include at least two detections. The reference electrode is formed of a set of reference electrode groups including at least two reference electrodes, and the first measurement unit is provided for each of the plurality of detection electrode groups. A plurality of second measuring units are provided for each of the plurality of reference electrode groups, the control unit simultaneously controls the measurements of the plurality of first measuring units, and a plurality of the second measuring units are provided. Simultaneously controlling the measurement of the second measurement unit of
The computer is communicably connected to the base sequence analysis chip, transmits a control command for controlling the operation of the control unit to the base sequence analysis chip, and sends a subtraction result in the subtraction unit from the base sequence analysis chip. It is characterized by receiving.

Further, the base sequence analysis apparatus of the present invention is a base sequence analysis apparatus comprising a base sequence analysis chip and a computer,
The base sequence analysis chip includes a substrate, a plurality of detection electrodes formed on the substrate, on which probes having a base sequence complementary to a target base sequence to be detected are immobilized, and on the substrate A control electrode formed and a probe having a base sequence complementary to the target base sequence is not immobilized; a first measurement unit formed on the substrate and measuring an electrochemical signal of the plurality of detection electrodes; A second measurement unit formed on the substrate and configured to measure an electrochemical signal of the reference electrode; and a second measurement value formed on the substrate from the first measurement value of the first measurement unit and the second measurement value of the second measurement unit. A subtracting section for subtracting, and a control section for simultaneously controlling the measurement of the first measuring section and the second measuring section based on a signal from the outside of the substrate and for controlling the subtraction of the subtracting section. , A plurality of the reference electrodes are provided, and the first measurement Are provided one by one for each of the plurality of detection electrodes, the second measurement unit is provided by one for each of the plurality of reference electrodes, and the control unit has a plurality of Simultaneously controlling the measurement of each of the first measurement unit and the plurality of second measurement units,
The computer is communicably connected to the base sequence analysis chip, transmits a control command for controlling the operation of the control unit to the base sequence analysis chip, and sends a subtraction result in the subtraction unit from the base sequence analysis chip. It is characterized by receiving.

  As described above in detail, according to the present invention, a base sequence analyzing apparatus capable of automatically detecting and analyzing a base sequence with high accuracy is provided.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a diagram showing an example of a base sequence analyzing apparatus according to an embodiment of the present invention. As shown in FIG. 1, the computer 1 and a base sequence analysis chip 2 electrically connected to the computer 1 are configured.

  The base sequence analysis chip 2 detects an electrochemical signal from an electrode formed on the chip based on a command from the computer 1, and performs signal processing such as current-voltage conversion, AD conversion, and average value calculation of the detection signal, Subtraction, base sequence determination, and the like are performed, and data such as the obtained determination result is output to the computer 1.

  The base sequence analysis chip 2 includes an electrode 12 having a laminated structure such as Ti and Au formed on a substrate 11 made of semiconductor, glass or the like, a current-voltage conversion circuit, an AD conversion circuit formed on the substrate 11, Peripheral circuits such as a signal processing circuit, a subtraction circuit, and a control circuit for controlling the operation of these circuits are formed by using a semiconductor microfabrication technique. In addition, on each electrode 12, a cell 13 is provided that accommodates a sample, a chemical solution, and the like and causes an electrochemical reaction between the sample or the chemical solution and the probe on the electrode 12.

  The formation of the peripheral circuit can be realized by forming circuit wiring based on the logic design on the logic gate corresponding to the number of gates necessary for forming these circuits on the substrate 11 in advance using a semiconductor microfabrication technique. . Of course, the gate array may be formed by other custom IC development processes. In the example of FIG. 1, the case where the electrode 12 and the cell 13 are arranged on the entire surface of the base sequence analysis chip 2 is shown, but it is arranged in a part of the region, and a peripheral circuit is formed in the other region. It may be.

  In the following embodiments, the base sequence of DNA to be detected is referred to as a target base sequence. A base sequence that is complementary to the target base sequence and selectively reacts with the target base sequence is called a target complementary salt sequence. The DNA probe containing this target complementary base sequence is immobilized on the detection electrode of the base sequence analysis chip 2. The sample (specimen solution) introduced into the cell 13 of the base sequence analysis chip 2 contains a substance having a base sequence such as DNA to be tested. The base sequence of the DNA to be tested is referred to as the sample base sequence.

  That the target base sequence and the probe base sequence are complementary means that a continuous partial base sequence in the target nucleic acid sequence has 50% to 100% complementarity to the probe base sequence. More preferably, it means having 100% complementarity. In addition, the parameter | index which shows complementarity shows the ratio of the number of bases which corresponds between two comparison object with respect to all the base sequences to compare.

  The base sequence analysis chip 2 of this embodiment hybridizes the sample base sequence and the target-complementary base sequence of the immobilized probe in the cell 13 and monitors the presence or absence of the reaction after introducing the intercalating agent into the sample. It is a chip for determining whether or not a target base sequence is included.

FIG. 2 is a diagram showing an example of an electrode structure provided on the surface of the base sequence analysis chip 2. 2, _n detection electrode systems 21 _{1 to} 21 _n each provided with one detection electrode 201, one reference electrode 202, and one counter electrode 203, one reference electrode 204, one reference electrode 205, and one counter electrode 206 are provided. One provided reference electrode system 22 is arranged. One reference electrode system 22 is provided corresponding to the plurality of detection electrode systems 21 _{1 to} 21 _n . These electrode systems such as the detection electrode systems 21 _{1 to} 21 _n and the reference electrode system 22, that is, combinations of the three electrodes of the detection electrode 201, the reference electrode 202 and the counter electrode 203, and the control electrode 204, the reference electrode 205 and the counter electrode 206 A three-electrode measurement circuit such as a potentiostat is connected to the electrode combination, and an electrochemical measurement signal is obtained in each of the electrode systems 21 and 22.

  The detection electrode 201 and the reference electrode 204 are electrodes for detecting a reaction current in the cell 23. A DNA probe having a target complementary base sequence complementary to the target base sequence is immobilized on the detection electrode 201.

  The control electrode 204 detects a background current that is a current other than the current derived from the hybridization of the target DNA to be detected and the probe DNA, and then subtracts the background current from the current detected by the detection electrode 201. This is an electrode for eliminating the influence of superposition of the background current. In the control electrode 204, a probe that is not complementary to the target base sequence and has a base sequence that does not cause a hybridization reaction with the target base sequence is immobilized, or the probe is used without being immobilized.

  The counter electrodes 203 and 206 are electrodes that supply a current into the cell 23 by applying a predetermined voltage between the detection electrode 201 and the reference electrode 204.

  The reference electrodes 202 and 205 are electrodes that negatively feed back the electrode voltage to the counter electrode 203 or 206 in order to control the voltage between the reference electrode 202 and the detection electrode 201 to a predetermined voltage characteristic. With the reference electrodes 202 and 205, the voltage by the counter electrode 203 or 206 is controlled, and highly accurate oxidation current detection can be performed regardless of various detection conditions in the cell 23.

The electrode arrangement shown in FIG. 2 is merely an example for explaining the features of the present invention, and various changes can be made to the electrode arrangement, electrode correspondence, and the like. For example, the reference electrodes 202 and 205 are one reference electrode common to each of the detection electrode systems 21 _{1 to} 21 _n and the reference electrode system 22, and the one reference electrode is associated with the plurality of detection electrodes 201 and the reference electrode 204. May be used. Further, one reference electrode is associated with the detection electrode systems 211 and 212, another reference electrode is associated with the detection electrode systems 213 and 214, and so on. Two reference electrodes may be arranged corresponding to each other. Further, the counter electrodes 203 and 206 can be changed in the same manner as the reference electrode, and the counter electrodes 203 and 206 can be shared and used for the plurality of detection electrodes 201 and the reference electrode 204. Further, a plurality of detection electrodes 201 or a plurality of reference electrodes 204 may be arranged on one electrode system 21 or 22. In this way, one reference electrode or one counter electrode may be associated with the plurality of detection electrodes 201 and the reference electrode 204.

  In the implementation of FIG. 2, a case where one detection electrode is provided for one type of probe and one reference electrode is provided for one negative control is shown. This embodiment is effective when the reliability of each measurement with one electrode is sufficient. In actual measurement, the measurement result may fluctuate due to some factors such as the uniformity of the solution. In order to compensate for this fluctuation, it is effective to use a plurality of electrodes of the same type for both the probe and the negative control and to take an average of these electrodes.

  FIG. 3 is a block diagram illustrating an example of a circuit configuration of the base sequence analysis chip 2.

The probe modules 31 _{1 to} 31 _n have a configuration corresponding to the detection pole systems 21 _{1 to} 21 _n . Although the case where one negative control module 32 is provided is shown, when a plurality of reference electrode systems 22 are provided, one negative control module 32 is provided corresponding to each.

Each of the probe modules 31 _{1 to} 31 _n has detection electrode systems 21 _{1 to} 21 _n , functions as a sensor for detecting an electrochemical signal obtained from the detection electrode 201 in the cell 13, and the sensed electrochemical signal. This is a circuit in which functions such as signal processing and data analysis are integrated.

  The negative control module 32 has a reference electrode system 22, functions as a sensor for detecting an electrochemical signal obtained from the reference electrode 204 in the cell 13, signal processing of the sensed electrochemical signal, data analysis, and the like. Is a circuit in which the functions are integrated.

  The base sequence analysis chip 2 is a current detection type chip that detects a current obtained from the detection electrode 201 and the reference electrode 204. In the case of a current detection type chip, data analysis is performed while comparing the data obtained at the detection electrode 201 and the reference electrode 204. In the example of FIG. 1, electrodes having these two different functions are mounted as separate modules. Realized in form.

The probe modules 31 _{1 to} 31 _n and the negative control module 32 are connected to a common global instruction bus 33, global address bus 34, and global data bus 35, respectively.

An interface circuit 41 for performing data input / output control with the computer 1 is connected to the computer 1 via, for example, an external terminal via a signal line. A signal received by the interface circuit 41 from the computer 1 is output to the decoder 42. The decoder 42 controls the probe modules 31 _{1 to} 31 _n and the negative control module 32 based on a control procedure generated with reference to the global control circuit 43 based on the received signal. More specifically, the decoder 42 outputs a global instruction signal and a global address signal to the global instruction bus 33 and the global address bus 34 based on the generated control procedure. The probe modules 31 _{1 to} 31 _n or the negative control module 32 addressed by the global address signal execute the command specified by the global command signal and output the obtained data to the global data bus 35. The interface circuit 41 outputs the data on the global data bus 35 to the computer 1.

The processing result in the negative control module 32 is used for subtraction or comparison in each of the probe modules 31 _{1 to} 31 _n . Accordingly, data is output from the negative control module 32 to each of the probe modules 31 _{1 to} 31 _n via the global data bus 35.

The designation of the module for executing the process and the type of the process to be executed are given from the decoder 42 to each of the modules 31 _{1 to} 31 _n and 32 through the global address bus 34 and the global instruction bus 33.

As an example, it is assumed that the data obtained from each of the probe modules 31 _{1 to} 31 _n is subtracted by the data obtained from the negative control module 32. In this case, after the oxidation current measurement is simultaneously performed by each of the probe modules 31 _{1 to} 31 _n , data obtained from the negative control module 32 is sent to each of the probe modules 31 _{1 to} 31 _n via the global data bus 35. In each of the probe modules 31 _{1 to} 31 _n , negative control data is acquired from the global data bus 35 and subtracted. Accordingly, the subtraction is also performed simultaneously in each of the probe modules 31 _{1 to} 31 _n . Since the global buses 33 to 35 are signal lines common to all the modules 31 _{1 to} 31 _n and 32, the data is actually transferred sequentially from the negative control module 32 to the probe modules 31 _{1 to} 31 _n. At the same time, subtraction starts.

  The type of command signal input from the outside to the base sequence analysis chip 2 is, for example, (1) stop (2) no operation (3) measurement start (4) data read (5) negative control module subtraction (6) average ( 7) There are nine types of subtraction: (8) inter-module subtraction (9) reset. The instruction signals (1) to (9) are composed of a combination of an instruction code and an address code, and an instruction can be given to each component by these.

  Further, in addition to these nine types of signals, (10) hardware reset signal (11) operation start signal (12) operation stop signal and the like are provided as control signals. The signals shown in (1) to (12) are input from the computer 1 to the interface circuit 41 and directly input to the control target without going through the bus, and directly control the hardware to be controlled.

  The signal output to the outside from the base sequence analysis chip 2 includes (1) data (2) measurement abnormality flag (3) operation end flag and the like. Flags such as a measurement abnormality flag and an operation end flag are bits for indicating the internal state of the arithmetic storage device 450 to the outside.

  The decoder 42 acquires a global instruction signal and a global address signal corresponding to the instructions shown in (1) to (9) from the global control circuit 43 and outputs them to the global instruction bus 33 and the global address bus 34.

  When the base sequence analysis chip 2 is used outside the chip, that is, from the computer 1, a sequential execution method for executing the instructions shown in (1) to (9) one by one while communicating with the computer 1 and a program memory A program execution system is conceivable in which one area, program counter, and logic circuit for controlling the calculation procedure are arranged at any location in the base sequence analysis chip 2 and the processing procedure is written in the chip 2 for automatic processing.

  In the case of this program execution method, a write command to the program memory may be added in addition to (1) to (9). The program memory area, the program counter, and the logic circuit are preferably mounted in the global control circuit 43, for example. The processing procedure written in the program memory area differs depending on the design conditions such as the function of the base sequence analysis chip 2, the type and number of probes immobilized on the detection electrode 201, and the number of electrodes. Therefore, the computer 1 preferably includes a utility program that generates a processing procedure written in the program memory area based on the chip function information. Thereby, automatic processing can be realized in the base sequence analysis chip 2 having any function and configuration.

  An example of a flowchart of electrochemical signal detection and detection data analysis processing using the base sequence analysis chip 2 shown in FIG. 3 is shown in FIG.

  First, after a DNA probe having a target complementary base sequence complementary to the target base sequence is immobilized on the detection electrode 201, the cell 13 is filled with a sample and kept at a predetermined temperature. As a result, the DNA probe causes a hybridization reaction with the sample DNA in the sample (s1).

  Next, after the DNA probe and the inside of the cell 13 are washed with a buffer solution, the cell 13 is filled with an insertion agent. The measurement is performed with the intercalating agent introduced (s2).

  In this measurement process, first, the interface circuit 41 outputs a measurement start signal from the computer 1 to the decoder 42. The decoder 42 receives the measurement start signal, acquires a global instruction and a global address corresponding to the instruction, and sends them to the global instruction bus 33 and the global address bus 34.

Since this measurement is performed simultaneously in each of the modules 31 _{1 to} 31 _n and 32, the addresses of all these modules are designated. The probe modules 31 _{1 to} 31 _n and the negative control module 32 start measurement by receiving a global command in which the global address is specified. The obtained measurement data is stored in 31 _{1 to} 31 _n and 32, respectively.

  The principle of simultaneous measurement will be described more specifically.

Since the measurement is simultaneously performed in each of the modules 31 _{1 to} 31 _n and 32, the control unit including the decoder 42 and the global control circuit 43 controls the simultaneity. The global control circuit 43 generates an address of a module to start measurement. The generated address is transmitted to each module through a dedicated communication line. This signal is decoded by a local control decoder 51, which will be described later, in each module. As a result of this decoding, it is determined whether or not to execute the measurement command simultaneously transmitted to the module. The address-dedicated communication line can be realized by a bus system as shown in FIG. In this case, the address at which the measurement is started is written to the global address bus 34 by this control unit, and is read by each of the modules 31 _{1 to} 31 _n and 32.

  A global communication line that can broadcast a code indicating an address all at once may be used.

  For example, three types of codes indicating addresses written to the global address bus 34 for simultaneous measurement can be set. Specifically, a code for designating individual modules one by one, a code for designating a part of two or more of a plurality of modules, and a code for designating all modules. As a code designating a part of the modules, for example, a code designating probes having the same or the same kind of base sequence can be considered.

These three kinds of codes are simultaneously decoded by the modules 31 _{1 to} 31 _n and 32, and the designated modules can start measurement simultaneously. The operation for decoding the code indicating the address is hereinafter referred to as address decoding.

  When only the address code designating the individual module is included in the specification, the generation of the address by the global control circuit 43 sequentially generates the addresses of the modules to be measured at the same time. In response to this, the designated module starts sequential measurement, so that almost simultaneous measurement is realized within a certain finite time lag.

  In the case of the sequential execution method, the computer 1 outputs various instructions necessary for executing the detailed steps of the sequential measurement to the decoder 42 until the measurement data is stored after the measurement start signal is input from the computer 1. The decoder 42 decodes these various instructions with reference to the global control circuit 43 and sends a global instruction signal to the global instruction bus 33 and a global address signal to the global address bus 34. Thereafter, the same operation is repeated until the control of the base sequence analysis chip 2 by the computer 1 is completed.

Next, the computer 1 outputs an average signal to the decoder 42. The decoder 42 sends a global command signal and a global address signal for calculating an average value based on the average signal to the probe modules 31 _{1 to} 31 _n via the global command bus 33 and the global address bus 34. Thereby, the probe modules 31 _{1 to} 31 _n execute an average value calculation process (s3).

The average value calculation is a process of calculating an average value of measurement data obtained by the probe modules 31 _{1 to} 31 _n . In this average value calculation processing, as a first calculation method, for example, measurement data is transferred from one probe module 31 to another specific probe module 31 via the global data bus 35, and the specific one probe module 31 It can be executed by calculating an average value for all the acquired probe modules 31 and outputting the obtained average value data to all other probe modules 31 via the global data bus 35. In addition, as a second calculation method, a process of calculating an average value for a combination of a predetermined number of probe modules 31 and further calculating an average value with the representative probe module 31 based on the average values is repeated. Thus, the average value can also be calculated.

Moreover, it is not necessary to calculate the average value of all the probe modules 31 _{1 to} 31 _{n, and} the average value of specific types of probe modules 31 is calculated according to the type of DNA probe immobilized on the detection electrode 201. You may make it do. For example a probe module 31 _{1-31 4} probe having a first nucleotide sequence is immobilized, if the probe module 31 _{5-31 8} the probe having a second nucleotide sequence is immobilized, the probe module 31 ₁ calculates the average value for the -31 _4, this to be able to be configured to calculate an average value for the probe module ₃₁ 5-31 ₈ Apart. Thereby, the average value for every kind of probe is computable.

In the example shown in FIG. 3, since only one negative control module 32 is provided, it is not necessary to calculate the average value on the negative control side. When a plurality of negative control modules 32 are provided, a control signal for performing the same average value calculation as that performed on the probe modules 31 _{1 to} 31 _n is output to each negative control module 32.

Further, in the example of FIG. 3, for each of the respective probe module 31 ₁ to 31 _n 1 one by detecting electrode 201 shows a case where being arranged, an example of performing averaging between probes, each When a plurality of detection electrodes 201 are arranged on the module, an average value of measurement data obtained from the plurality of detection electrodes 201 can be taken. In this case, there is no need to transfer data to other modules.

Next, the computer 1 outputs an intermodule subtraction signal to the decoder 42. Based on the inter-module subtraction signal, the decoder 42 sends a global instruction signal and a global address signal for performing inter-module subtraction to the probe modules 31 _{1 to} 31 _n and the negative control module 32 and the global instruction bus 33 and the global address signal. It is transmitted via the address bus 34. Thereby, the probe modules 31 _{1 to} 31 _n and the negative control module 32 execute inter-module subtraction processing (s4).

This inter-module subtraction process is a process of subtracting the measurement data obtained by the negative control module 32 from the average value data obtained by the probe modules 31 _{1 to} 31 _n . When a plurality of negative control modules 32 are provided, the probe average value data is subtracted from the average value data of each negative control module 32.

Specifically, the decoder 42 instructs the negative control module 32 to send the measurement data (or average value data) to the global data bus 35, and the probe modules 31 _{1 to} 31 _n. It consists of a second process for instructing acquisition of the transmitted measurement data and a third process for instructing subtraction of the acquired measurement data from the average value in the module.

When the average value of the probe modules 31 _{1 to} 31 _n is calculated for each type of probe, the measurement data from the negative control module 32 is subtracted from the average value for each type of probe. In this case, it is not necessary to perform subtraction for all the probe modules 31 _{1 to} 31 _n , and it is sufficient that any _{one of} the probe modules 31 _{1 to} 31 _n represented for each probe type performs subtraction. Of course, all the probe modules 31 _{1 to} 31 _n may perform subtraction. The obtained subtraction value data is stored in each of the probe modules 31 _{1 to} 31 _n .

Next, the computer 1 outputs a signal for making a determination to the decoder 42. A signal for making this determination is generated by sequentially combining the aforementioned (1) to (9). Based on the signal for making this determination, the decoder 42 sends a global instruction signal and a global address signal for making the determination to the probe modules 31 _{1 to} 31 _n via the global instruction bus 33 and the global address bus 34. Depending on the content of the determination process, the same global command signal and global address signal are output to the negative control module 32. Thereby, the probe modules 31 _{1 to} 31 _n and the negative control module 32 execute the determination calculation process (s5).

As an example of the determination calculation process, there is a determination calculation process for determining the base sequence of the SNP position of the single nucleotide polymorphism. In this determination calculation process, at least two types of candidates to be detected are set as target base sequences. Then, a first DNA probe that is complementary to each of the two target base sequences and a second DNA probe that is different from the first DNA probe in the base at the SNP position are immobilized on the detection electrode 201. Then, the subtraction value data obtained for each type of DNA probe is compared in the probe modules 31 _{1 to} 31 _n , and it is determined that the base sequence type is complementary to the base sequence of the DNA probe having the larger value. To do. Data indicating the determination result is stored in the probe modules 31 _{1 to} 31 _n . Of course, since it is only necessary to obtain one determination result for each type of DNA probe to be compared, it is not necessary to perform determination processing in modules other than the determination.

  In this embodiment, when comparing the signal intensity obtained from the detection electrode 201 on which the first DNA probe is immobilized and the detection electrode 201 on which the second DNA probe is immobilized, In addition to the DNA probe and the second DNA probe, a control electrode 204 to which a negative control that does not detect any target base sequence (that is, does not cause hybridization) is immobilized is disposed. At the control electrode 204, signal components unrelated to gene detection are detected. When performing type determination using these three electrodes, the signal intensities obtained from the first DNA probe and the second DNA probe are finally compared, and the difference in signal intensity or the ratio of signal intensities is used as a basis. The determination result is obtained. Prior to the comparison of the signal intensities, the signal obtained from the control electrode 204 is subtracted from the signal obtained from the detection electrode 201 for each of the first DNA probe and the second DNA probe. This subtraction makes it possible to compare net signals related to DNA detection.

  By simultaneously performing measurements performed on the first and second DNA probes and the three electrodes corresponding to the negative control, it is possible to make a comparison that excludes the influence of fluctuations in the current value observed depending on the measurement time.

  Here, it is desirable that the detection electrode 201 and the reference electrode 204 are provided on the same substrate in order to avoid the influence due to the mismatch of the uniformity of the electrolyte. More preferably, the detection electrode 201 and the reference electrode 204 are spatially close to each other.

Next, the computer 1 outputs a data read signal to the decoder 42 via the interface circuit 41. The decoder 42 sends a global command signal and a global address signal for reading data based on the data read signal to the probe modules 31 _{1 to} 31 _n via the global command bus 33 and the global address bus 34. Accordingly, the probe modules 31 _{1 to} 31 _n send data indicating the determination result to the global data bus 35 (s6). In addition to the determination result, other analysis data such as a subtraction value and an average value may be sent together. Data sent to the global data bus 35 is output to the computer 1 via the interface circuit 41. The computer 1 outputs the acquired data to a display device, for example.

  The base sequence analysis operation is thus completed.

FIG. 5 is a block diagram showing an example of a detailed configuration of each of the probe modules 31 _{1 to} 31 _n . Each of the modules 31 _{1 to} 31 _n has the same configuration, and one of the modules will be described with reference to FIG. The probe module 31 and the negative control module 32 have the same configuration except for the difference in configuration between the detection electrode 201 and the reference electrode 204.

  The probe module 31 includes a digital function generator 410, a D / A converter 420, a potentiostat 430, an A / D converter 440, and an arithmetic storage device 450.

  The digital function generator 410 generates a voltage pattern to be applied to the counter electrode 203 of the potentiostat 430 as a digital value. The digital function generator 410 is realized by a circuit similar to a normal counter. The voltage value is changed every moment in synchronization with the timing control signal. The D / A converter 420 converts the digital function generated by the digital function generator 410 into an analog signal and outputs the analog signal to the potentiostat 430. As a result, the voltage pattern generated by the digital function generator 410, which changes every moment, is output to the potentiostat 430 in analog form. The digital function generator 410 and the D / A converter 420 realize cyclic voltammetry in the potentiostat 430.

  The potentiostat 430 applies a voltage to the counter electrode 203 based on the analog voltage pattern waveform from the D / A converter 420, thereby detecting an oxidation current generated between the counter electrode 203 and the detection electrode 201 to perform A / D conversion. To the device 440. More specifically, a compensator 431 is connected to the counter electrode 203 of the potentiostat 430, and this compensator 431 obtains the analog voltage pattern signal from the D / A converter 420 at the reference electrode 202. A signal obtained by negatively feeding back the detected voltage signal is amplified and output to the counter electrode 203. The detected voltage obtained at the reference pole 202 is connected to the non-inverting input terminal of the voltage follower amplifier 432, and the inverting input terminal is negatively fed back to the output of the digital function generator 410. Thereby, the voltage detected by the reference electrode 202 can be fed back to the voltage pattern generated by the digital function generator 410 to control the voltage of the counter electrode 203.

  The detection electrode 201 of the cell 13 is connected to the inverting input terminal of the trans-impedance amplifier 433. The non-inverting input terminal of the transimpedance amplifier 433 is grounded, and its output terminal is connected to the A / D converter 440. The signal obtained from the detection electrode 201 is subjected to current / voltage conversion by the transformer / impedance amplifier 433 and output to the A / D converter 440. The A / D converter 440 performs A / D conversion on the electrochemical signal obtained from the detection electrode 201 of the potentiostat 430 and outputs the result to the arithmetic storage device 450. Since the conversion operation of the A / D converter 440 is sequentially performed in synchronization with the timing control signal, the detection data is sequentially output to the arithmetic storage device 450.

  The arithmetic storage device 450 outputs timing control signals to the digital function generator 410, the D / A converter 420, and the A / D converter 440 based on the control signals and the command signals given from the global command bus 33, and outputs them. Controls circuit measurement timing. In addition, measurement in the probe module 31 is performed by instructing the arithmetic storage device 450 by the global instruction bus 33 and the global address bus 34, and data obtained as a result of the measurement is externally transmitted via the global data bus 35. Is output to other modules, the interface circuit 41, and the like.

  In addition to the measurement by the potentiostat 430, the arithmetic storage device 450 executes various arithmetic processes such as a peak detection operation, an average operation, a subtraction operation, and a determination operation. Data necessary for this arithmetic processing is acquired from other probe modules 31 and the negative control module 32 via the global data bus 35. In addition, a forced control signal such as reset or interrupt or a signal indicating timing is input from the interface circuit 41 to the arithmetic storage device 450 as a control signal. Further, the arithmetic storage device 450 outputs a flag signal indicating the internal state in the arithmetic storage device 450 to the outside to the interface circuit 41.

  A detailed flow of the measurement operation (s2) by the arithmetic storage device 450 shown in FIG. 5 will be described with reference to FIG.

  When the timing control signal generated by the arithmetic storage device 450 is output to the digital function generator 410, the digital function generator 410 increments the digital value of the voltage input to the potentiostat 430 (s21). As a result, the voltage input to the counter electrode 203 of the potentiostat 430 increases. The oxidation current between the counter electrode 203 and the detection electrode 201 in the cell 13 when the input voltage changes is detected by the detection electrode 201 and converted into a current / voltage by the trans-impedance amplifier 433 (s22). It is output to the D converter 440. The A / D converter 440 converts the measurement signal converted into a voltage into a digital value (s23) and outputs the digital value to the arithmetic storage device 450. The arithmetic storage device 450 compares the input digital value with the already stored peak value, and extracts the larger value as the peak value (s24). If the measurement is not completed at this stage, the process returns to (s21) to acquire a digital value obtained by incrementing the input voltage, and the process up to the extraction of the peak value is repeated. Thereby, the voltage waveform which increases in steps can be generated, and cyclic voltammetry can be realized. When it is determined that the measurement is finished, the peak value is stored (s26), and the measurement operation is finished.

  FIG. 7 is a block diagram showing an example of a detailed configuration of the arithmetic storage device 450 of FIG. As shown in FIG. 7, the arithmetic storage device 450 includes a local control decoder 51, an arithmetic and logic circuit 52 (ALU), a general purpose register 53, a result storage dedicated register 54, a local bus R1, R2 and W.

  A general function of the arithmetic storage device 450 will be described.

  The calculation storage device 450 can execute a peak detection operation, an average operation, a subtraction operation, and a determination calculation.

  The local control decoder 51 decodes the address of the global address bus 34. When the decoded address designates the address of the individual arithmetic storage device 45 including the local control decoder 51, the control signal corresponding to the instruction is decoded by decoding the instruction designated by the global instruction bus 33. Are output to the local buses R1, R2, W, etc., in order to control the arithmetic logic circuit 52 and the bus. Thereby, the arithmetic logic operation of the arithmetic logic operation circuit 52 is controlled, and the decoded instruction is sequentially executed in the operation storage device 45. More specifically, the local control decoder 51 sequentially and automatically executes the sequence of steps shown in FIGS. 6, 8, and 9 by controlling the arithmetic logic circuit 52, for example. The local control decoder 51 outputs a timing control signal for controlling the operation timing of the digital function generator 410, the D / A converter 420, and the A / D converter 440 to the outside. Further, the local control decoder 51 outputs a flag signal indicating the state after the arithmetic processing of the arithmetic logic operation circuit 52 based on the output from the arithmetic logic operation circuit 52.

  The local control decoder 51 is composed of a general logic memory, a resist, and the like, and outputs a signal sequence representing a control procedure. More specifically, the local control decoder 51 includes a microprogram counter, a microprogram memory, and the like, and can realize microprogramming and the like.

  The arithmetic logic operation circuit 52 performs an arithmetic operation or a logical operation based on the two data of the read-only local buses R1 and R2, and sends the operation result to the local control decoder 51 and the write-only local bus W.

  The general-purpose register 53 stores arbitrary data such as the operation result of the arithmetic logic operation circuit 52 via the write-only local bus W, and sends the stored data to the local buses R1 and R2 so that they can be read.

  The result storage dedicated register 54 stores the operation result of the arithmetic logic circuit 52 and the output data (measurement data) of the A / D converter 440 via the write-only local bus W, and stores the stored data locally. The data is sent to the buses R1 and R2 so as to be readable.

  Data from the global data bus 35 is output to the local bus R2 so as to be readable. The output data of the A / D converter 440 is sent to the local bus W so as to be writable.

  In addition, although the example which transfers data between the arithmetic logic circuit 52, the general purpose register 53, and the result storage exclusive register 54 using the local buses R1, R2, and W is shown, the local buses R1, R2, and W are replaced. Thus, a selector accessible from the arithmetic logic circuit 52, the general-purpose register 53, and the result storage dedicated register 54 may be arranged. This selector selects read data and write data and exchanges data with each component, thereby making data control relatively easy.

  FIG. 7 shows a case where one general-purpose register 53 and one result storage-dedicated register 54 are provided for convenience of explanation. May be.

  Arithmetic logic operation circuit 52 can change its device configuration depending on the type of data processing to be executed, etc., but in order to reduce the circuit scale, the functions to be implemented are limited to addition, subtraction, right shift, load, and store instructions. Is desirable. Of course, you may implement so that the command which performs other four arithmetic operations and logic operations may be performed. By limiting the number of executable instructions, the circuit scale of the arithmetic logic circuit 52 can be reduced, and the number of gates used can be reduced. Of course, the local control decoder 51, the general-purpose register 53, and the result storage dedicated register 54 can also achieve the same effect by reducing the circuit scale.

  Thus, local heat generation can be flattened temporally by reducing the number of gates and keeping the operating frequency low. As a result, it is possible to reduce the influence of heat generation on the oxidation current detection condition in the cell 13.

  Next, detailed operation of each process using the arithmetic storage device 450 shown in FIG. 7 will be described.

  Details of the calculation of the peak value of (s24) in the flow of FIG. 6 will be described using the flowchart of FIG. 8 as an example. As an example of calculating the peak value, a case where four general-purpose registers 53 in FIG. 7 are arranged will be described. Assume that the addresses of the four general-purpose registers 53 are # 0, # 1, # 2, and # 3. The # 0 general-purpose register 53 is used to store current measurement data, # 1 is used to store previous measurement data, # 2 is used to store incremental data relative to the previous data of the current data, and # 3 is used to store peak candidate data. And

  First, the i-th measurement data is stored in the # 0 general-purpose register 53 (s241). Next, the arithmetic logic circuit 52 reads the previous measurement data from the # 1 general-purpose register 53 and the current measurement data from the # 0 general-purpose register 53 using the local buses R1 and R2, and # 0 data. The subtracted # 1 data is stored in the general register 53 of # 2 via the local bus W (s242).

  Next, in order to shift the data of the previous time point by one, the data of # 0 is substituted into the stored value of the general register 53 of # 1 (s243). Next, the arithmetic logic circuit 52 determines whether or not the # 2 data is negative (s244), and if negative, determines whether or not the # 3 data is smaller than the # 0 data (s245). . If the data of # 2 is not negative, since the measurement data is small, it is considered that the peak value is not extracted from the measurement data. Therefore, i = i + 1 without updating the data of # 3, The processing of (s241) to (s244) is repeated for the (i + 1) th measurement data.

  If the data of # 3 is not smaller than the data of # 0, the current measured data is equal to or smaller than the extracted peak value, so it is considered that the peak value is not updated. Without updating, i = i + 1, and the processing of (s241) to (s244) is repeated for the i + 1th measurement data. If the # 3 data is smaller than the # 0 data, the # 0 data is substituted into the # 3 general-purpose register 53 in order to update the # 3 peak value with the current measurement data.

  Such peak value detection processing is repeated for the increment of the input voltage, and it is determined whether or not the measurement is finished each time (s247). If the measurement is finished, it is temporarily stored in the general-purpose register 53 of # 3. The provisional peak value is substituted into the dedicated register 54 and stored as the final peak value (s248). Note that the determination of whether or not the measurement is completed as shown in (s247) may also be performed in the case where the process proceeds to NO in (s244) or (s244).

  Next, a detailed flow of the average operation shown in (s3) of FIG. 4 will be described along the flowchart of FIG.

As shown in FIG. 9, first, all values of a sample are added as a denominator for obtaining an average. Therefore, measurement data for taking an average is obtained from modules other than the probe module 31 that calculates the average value 2 ⁿ −. Measurements obtained by the probe module 31 which is stored in the general-purpose register 53 via the global data bus 35 and the local bus R2 and adds each measurement data using the arithmetic logic circuit 52 and calculates the average value. The data is added (s31), and the addition result is stored in the general-purpose register 53 (s32). Next, the arithmetic logic operation circuit 52 acquires the addition result from the general-purpose register 53 via the local bus R1 or R2, and performs an n-digit right shift operation. By this right shift operation, a value obtained by dividing the addition result by n is obtained. The obtained calculation result is stored in the result storage dedicated register 54 (s34). Such arithmetic control can be easily realized using, for example, microprogramming or a state machine.

Incidentally, the average value calculation, an example of calculating an average value of the measured data obtained from a plurality of modules of each probe module 31 ₁ to 31 _n, at all even when the negative control module 32 there are a plurality The same applies.

  Further, when a plurality of detection poles 201 correspond to one probe module 31, the above-described processing can be applied to an operation of obtaining an average value of a plurality of measurement data stored in the one probe module 31. Of course.

Next, the subtraction processing between modules shown in (s4) of FIG. 4 will be described with reference to the flowchart of FIG. Measurement data (subtraction data) from the negative control module 32 is sent to the global data bus 35 (s41). The decoder 42 of FIG. 3 designates the module on which the subtraction is performed among the probe modules 31 _{1 to} 31 _n by referring to the global control circuit 43 (s42). Next, of the probe modules 31 _{1 to} 31 _n , the module whose address is specified performs address decoding (s43), and stores the subtraction data in the general-purpose register 53 (s44). Then, the arithmetic logic circuit 52 reads the subtraction data of the general-purpose register 53 and the measurement data such as the average value data stored in the probe module 31 of the other general-purpose register 53 (s45), and the negative control is performed from the probe data. Subtraction for subtracting data is executed (s46), and the subtraction result is stored in the dedicated register 54 (s47).

Next, the read process shown in (s6) of FIG. 4 will be described with reference to the flowchart of FIG. The decoder 42 in FIG. 3 selects a module from which data is to be read from 31 _{1 to} 31 _n and 32, and addresses the module (s61). The addressed module among the modules 31 _{1 to} 31 _n and 32 sends analysis data such as a determination result, a subtraction result, a peak value, and an average value to the global data bus 35 (s62). The data sent to the global data bus 35 is output to the computer 1 via the interface circuit 41 (s63).

  The operation of the local control decoder 51 described above is only an example, and various changes can be made. For example, the peak detection operation of (s24) may be performed using a digital filter.

  Further, although an example in which subtraction processing is performed after peak detection is shown, subtraction processing may be performed for each incremented input voltage, and peak detection may be performed on the subtraction result.

  Moreover, although the case where the subtraction of the probe module 31 and the negative control module 32 is performed between digital values is shown, it may be performed with the analog value as it is. In addition, a selector is provided before and after the A / D converter 440 of the probe module 31 and the negative control module 32 or in the arithmetic storage device 450, and a plurality of detection electrodes 201 or reference electrodes 204 are provided in one module 31 or 32. It is also possible for the selector to perform calculation by switching signals from a plurality of electrodes.

  In order to reduce the circuit scale, the arithmetic logic operation circuit 52 may be configured by a series circuit in which a plurality of circuits such as a full adder and a register are connected in series.

  It is desirable to adopt an appropriate configuration for these according to boundary conditions such as the number of electrodes, chip area, circuit scale, and heat generation. When parallelism of operations is not required so much, only A / D conversion of the detected electrochemical signal is performed and stored in the general-purpose register 53, and one calculation processing unit provided in the base sequence analysis chip 2 is used. A method of performing the above-described various operations serially is also conceivable. The calculation processing unit here corresponds to the decoder 42 and the global control circuit 43 shown in FIG.

  As described above, according to the present embodiment, the difference between the signal of the detection electrode and the reference electrode can be efficiently calculated in parallel. In addition, the average value of data detected from a plurality of electrodes can be calculated efficiently. In addition, peak current value detection and determination operations can be efficiently performed in parallel. In addition, measurements can be processed consistently and automatically. In addition, since data can be extracted from digital data, data from an external semiconductor element can be used efficiently. Therefore, the chip 2 can be used as a general-purpose gene analyzer component. In addition, by performing A / D conversion on the chip 2, it is possible to reduce the influence of external noise. Furthermore, by providing a sensor, a measurement and analysis circuit on one chip, an electrical signal generated during signal propagation between chips as occurs when a measurement and analysis circuit is provided separately from the substrate on which the sensor is provided. Noise can be reduced.

  A modification of the probe module 31 shown in FIG. 5 is shown in FIG. The probe module 31 shown in FIG. 5 can be replaced with the probe module 31 'shown in FIG.

  As shown in FIG. 12, the probe module 31 ′ includes a plurality of detection pole systems 21, a decode / control circuit 701, a potentiostat 702, a current / voltage conversion circuit 703, an A / D converter 704, It comprises a peak extraction circuit 705, a selector 706, a register 707, an NC (negative control) register 708, a selector 709, and a differentiator 710. One potentiostat 702 is provided for the plurality of detection pole systems 21. The same number of potentiostats 702, current / voltage conversion circuits 703, A / D converters 704, and peak extraction circuits 705 are provided. Further, the same number of registers 707 as the detection pole systems 21 are provided. In FIG. 12, four detection pole systems 21 are provided, and two potentiostats 702 detect four currents from the 34 detection pole systems 21. Therefore, one potentiostat 702 acquires current from the two detection pole systems 21. Switching of the current value is performed by a selector provided in the potentiostat 702.

  The decode / control circuit 701 controls the operations of the potentiostat 702, the selector 706, and the selector 709 based on the global instruction bus 33, the global address bus 34, and the control signal from the decoder 42.

  The potentiostat 702 applies a voltage to the counter electrode 203 of the corresponding detection electrode system 21 and detects an oxidation current signal from the detection electrode 201 under the control of the decode / control circuit 701. The detected oxidation current signal is converted into a voltage by the current / voltage conversion circuit 703 and output to the A / D converter 704, converted into a digital signal, and output to the peak extraction circuit 705. Since the peak extraction process of the peak extraction circuit 705 is the same process as the method of (s24) described above, the details are omitted. The obtained peak extraction value is output to the decode / control circuit 701 and the selector 706.

  The decode / control circuit 701 controls the operations of the selector 706 and the selector 709 in response to the input of the peak extraction value from the peak extraction circuit 705. The selector 706 selects one of the plurality of registers 707 and outputs the peak extraction value for each detection pole system 21 that is sequentially input. In the example of FIG. 12, the selector 706 selects and outputs an output signal to the four registers 707 based on the three inputs of the feedback signal from the differentiator 710 and the signal from the peak extraction circuit 705. Which register 707 is stored is designated by an address signal and a command signal from the decode / control circuit 701.

  The plurality of registers 707 store peak extraction values for each detection pole system 21.

  When performing the subtraction, the selector 709 selects the peak extraction value input from the outside to the NC register 708 as a first output, and selects any one of the plurality of registers 707 as a second output. The selector 709 is a circuit that selects two output signals from four inputs from the register 707 and one input from the NC register 708. Which two signals are output is specified by an address signal and a command signal from the decode / control circuit 701.

  The differencer 710 subtracts the peak extraction value from the negative control from the peak extraction value from the probe, and outputs the calculation result to the selector 706. The selector 706 stores the input calculation result in the register 707 corresponding to each detection pole system 21. As a result, the calculation result for each detection pole system 21 is held in the register 707.

  The selector 709 selects the operation result held in the register 707 and sends it to the global data bus 35 as a data output. Thereby, the calculation result is transmitted from the probe module 31 'to the outside.

  Thereby, it is possible to acquire data that has undergone current-voltage conversion, A / D conversion, peak extraction, and subtraction on the electrochemical signal detected from the detection electrode 201.

  Further, when the determination is performed, the decoding / control circuit 701 changes the control procedure of the selectors 706 and 709 and outputs a control signal to the selectors 706 and 709, which can be easily realized.

  For example, when comparing the calculation results (subtraction results) obtained for each detection electrode system 21 and specifying the base sequence of DNA contained in the sample solution, the selector 709 should be used as a comparison reference stored in the register 707. Two calculation results are output to the differentiator 710. The differencer 710 subtracts these two calculation results and outputs a difference value. By determining whether the difference value is positive or negative, the base sequence can be specified. By outputting the difference value positive or negative determination result or the difference value positive / negative determination result from the selector 709, the computer 1 can check the determination result of the base sequence.

  The present invention is not limited to the above embodiment.

FIG. 2 shows an example in which one reference electrode system 22 is arranged for a plurality of detection electrode systems 21 _{1 to} 21 _n , but the present invention is not limited to this. For example, as shown in FIG. 13, the reference electrode systems 22 _{1 to} 22 _n may correspond to the detection electrode systems 21 _{1 to} 21 _n and arranged in the vicinity thereof. Further, in the example shown in FIG. 13, the detection electrode systems 21 _{1 to} 21 _n and the corresponding reference electrode systems 22 _{1 to} 22 _n are integrated to form a detection electrode 201, a reference electrode 202, a counter electrode 203, and a reference electrode 204. One electrode system may be used. In this case, various circuits in the negative control module 32 of FIG. 3 are arranged in the probe modules 31 _{1 to} 31 _n . In this case, if a circuit such as a selector for switching signals for selecting the signal from the detection electrode 201 and the signal from the reference electrode 204 is arranged, current measurement and average value calculation are performed inside each of the modules 31 _{1 to} 31 _n. , Processing such as subtraction can be performed in parallel. Thereby, when subtracting the data obtained by negative control from the data obtained by the probe module, it is possible to reflect the difference in measurement conditions such as the state of the electrolyte solution in the vicinity of each detection electrode 201.

In the example of FIG. 13, a probe module or a negative control module is arranged corresponding to each of the detection electrode systems 21 _{1 to} 21 _n and each of the control electrode systems 22 _{1 to} 22 _n . In this case, each probe module and each negative control module are connected by one common global data bus 35.

When data obtained in each of the control electrode systems 22 _{1 to} 22 _n is tested for position dependency in real space and the average value thereof is calculated, serial data transfer and average by the common global data bus 35 are performed. In addition to the value calculation method, the negative control modules corresponding to the reference electrode systems 22 _{1 to} 22 _n may be connected by a dedicated communication line. As a result, since the data obtained at each reference electrode 204 can be exchanged in parallel, the number of signal lines for exchanging data increases, but the time required for data exchange is shortened. As a result, the time required for the average value calculation process can be shortened.

In the example of FIG. 3, each of the probe modules 31 _{1 to} 31 _n and the negative control module 32 are connected to one common global data bus 35, but the present invention is not limited to this. A dedicated communication line for connecting the negative control module 32 and each of the probe modules 31 _{1 to} 31 _n in parallel may be provided.

  FIG. 4 shows an example of processing in the order of current measurement, averaging operation, subtraction operation, and determination calculation, but this is only an example. By simply changing the control procedure of the control signal input from the computer 1 to the decoder 42, the order of these processes can be changed. Further, it is not always necessary to perform a determination operation, and it can also be established as a base sequence analysis chip that outputs a subtraction result obtained by performing a subtraction operation to the computer 1.

  Moreover, although FIGS. 3, 5, 7 and 12 show the case where each module is connected via a bus, the present invention is not limited to this. For example, each module is connected in parallel. When processing is simultaneously executed by a plurality of modules, a command or a control signal may be transmitted by a broadcast method from a control unit such as a decoder that controls the modules.

  Moreover, although the case where it uses for the single nucleotide polymorphism type | mold determination was shown in the above-mentioned embodiment, this apparatus can be utilized for another purpose.

  For example, when gene expression analysis is performed, a group of probes for detecting a plurality of transcripts expected to be expressed are immobilized on the same substrate and used as detection electrodes. Using these detection electrodes and one control electrode, measurement of each detection electrode and control electrode is performed simultaneously. Thereby, this apparatus can be used also for gene expression analysis. Of course, this apparatus can be used for other analysis purposes required by the simultaneity of measurement.

  In this embodiment, a DNA chip in which a base sequence detection sensor and a measurement / calculation circuit are integrated on the same substrate is used. Thereby, the feasibility is greatly improved, and the problem of the time difference in the measurement of the DNA chip can be solved. In this embodiment, one probe module 31 includes one detection electrode 201 and one negative control module 32 includes one reference electrode 204. However, when one probe module 31 includes a plurality of detection electrodes 201, the present invention can be applied even when one negative control module 32 includes a plurality of reference electrodes 204.

  Three types of configurations of the embodiment are shown below.

  (A) One negative control module 32 or one series, that is, a set of a plurality of modules is provided on the base sequence analysis chip 2. Measurements in each probe module 31 and negative control module 32 must be performed simultaneously. When this system is used, comparison between the detection electrodes after measurement can be performed for any combination.

  (B) A configuration in which a plurality of processing units in which a plurality of probe modules 31 and one negative control module 32 are combined are provided on the base sequence analysis chip 2. The measurement at the electrode may be performed at least simultaneously for each processing unit. When comparison, averaging, etc. between probes are performed as post-processing using this analysis system, a set of probes included in the processing of comparison, averaging, etc. belong to the same processing unit.

  (C) A configuration in which one-to-one electrode pairs that allocate a dedicated negative control module 32 to one probe module 31 are arranged. Measurement is performed simultaneously for at least each electrode pair. When comparison, averaging, etc. between probes are performed as post-processing using this analysis system, a set of probes included in the target of the comparison, averaging, etc. is measured simultaneously.

  The conceptual diagram of the module shown to these (A)-(C) is shown in FIG. 14A is a diagram of the embodiment (A), FIG. 14B is a diagram of the embodiment (B), and FIG. 14C is a diagram of the embodiment (C).

  As shown in FIG. 14A, in the embodiment (A), an electrode structure including one negative control module 32 and n probe modules 31 is used.

  As shown in FIG. 14B, the embodiment (B) includes a negative control module 32 at addresses # 0 to # n−1 and a plurality of probe modules associated with each of the plurality of negative control modules 32. 31 is arranged.

  As shown in FIG. 14C, in the embodiment (C), n negative control modules 32 of addresses # 0 to # n−1 and addresses corresponding to the negative control modules 32 at a ratio of 1: 1 are shown. N probe modules 31 of # 0 to # n−1 are arranged.

  As described above, in the electrochemical measurement, the three actions of analog data acquisition, analog / digital conversion, and peak determination are repeated. While the comparison between the probe modules 31 is executed after a series of measurement operations is completed, the comparison, that is, the subtraction between the negative control module 32 and each probe module 31 is performed by (1a) analog calculation after obtaining analog data. (2a) Perform digitally after A / D conversion. (3a) Three types are conceivable, which are performed after obtaining peak data at each electrode. (1a) is particularly applicable to the case of FIG. 14C in which the reference electrode 204 and the detection electrode 201 are paired. Other than that, it is applicable in any case.

  Work timing charts are shown in FIGS. The timing described as “measurement + nc subtraction” in the figure is negative by either the method (1a) or (2a) during the series of operations of analog data acquisition, A / D conversion, and peak determination. An operation for performing subtraction between signals from the control side and the probe side is shown. When the difference between the negative control module 32 and the probe module 31 is obtained by the method (3a), the calculation is performed at any time in the same manner as the comparison between normal probes. More specifically, “measurement” includes at least one of steps of detecting a current signal at a terminal, current / voltage conversion, A / D conversion, peak extraction, and average value manipulation. “Comparison” corresponds to a step of performing determination for determining a base sequence, for example, by comparing data between modules.

  However, the selection of (1a), (2a), and (3a) is determined according to the accuracy of peak value detection. Normally, when measuring with a genetic analysis device using electrolysis, the input voltage of the potentiostat that gives the peak current value, which is a representative value of electrolysis measurement, is uniquely determined for the insertion agent that immerses the electrode. Is done. Therefore, the same result can be obtained whether the detection electrode and the control electrode are subtracted before the peak is detected, or if the subtraction is performed after the peak detection. In actual measurement, the input voltage giving the peak may vary. When this variation is large, it is effective to perform the subtraction after the peak detection (3a). On the other hand, if the variation is so small that it can be ignored, an optimal one of (1a), (2a), and (3a) may be selected in consideration of factors such as calculation load, power consumption, and chip area where transistors can be arranged. Therefore, for example, FIG. 12 shows the method (3a), but it is only an example, and the embodiment is not limited to the configuration of FIG.

  As shown in FIG. 15, in the case of the embodiment (A), the negative control module 32 and the probe module 31 are simultaneously measured and n. c. Subtraction needs to be done. n. c. In the subtraction process, the negative control module 32 sends subtraction data to each probe module 31, each probe module 31 acquires this subtraction data, and subtracts the measurement data measured in advance by this subtraction data. Execute the process. After the subtraction, any two probe modules 31 are compared for base sequence determination. The comparison may be performed in parallel at the same timing after measurement in all the probe modules 31, or may be performed serially as shown in FIG. 15 so that data indicating the comparison result is sequentially sent to the computer 1. May be.

  As shown in FIG. 16, in the case of the embodiment (B), the measurement and n.e. for each processing unit (four probe modules and one negative control module in the example of FIG. 1616) to be subtracted from each other. c. Subtraction must be performed, but need not be simultaneous with other processing units. Further, the same comparison process as in the case of FIG. 15R> 5 is executed for an arbitrary combination of probe modules in each processing unit. If one processing unit is viewed, the same measurement operation as in the example of FIG. 15 is performed.

  As shown in FIG. 17, in the case of Example (C), one set of negative control module 32 and probe module 31 are simultaneously measured and n. c. Subtraction is performed. In FIG. 17, each module pair is measured at a separate timing and n. c. Although the case where subtraction is performed is shown, it is not limited to this. In particular, when the processes such as averaging and comparison are performed between the probe modules 31, the probe modules 31 to be processed such as averaging and comparison are measured at the same timing.

  By providing a large number of units capable of performing measurement and subtraction as a hardware configuration, the measurement of FIGS. 15 to 17 and the measurement of the reference electrode can be performed simultaneously in parallel. In this case, the identity of the conditions between the measurement blocks can be further increased.

  When sweeping a voltage range of 1.0 V at 100 mV / s by cyclic voltammetry, it takes 10 seconds. When 100 probe electrodes are used, assuming that measurements are performed in series without using this system, the total measurement time is 1000 seconds. From the experimental data, it can be seen that a difference of about 10 nA may occur during this period due to the difference in Hoechst adsorption. In this system, by increasing the simultaneity of measurement, it is possible to measure without such errors.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

The figure which shows an example of the base sequence analyzer which concerns on one Embodiment of this invention. The figure which shows an example of the electrode structure provided in the base sequence detection chip | tip surface concerning the embodiment. The block diagram of an example of the circuit structure of the base sequence analysis chip concerning the embodiment. The figure which shows an example of the flowchart of the analysis process of the electrochemical signal detection and detection data using the base sequence analysis chip concerning the embodiment. The block diagram which shows an example of a detailed structure of the probe module which concerns on the embodiment. The figure which shows the detailed flow of measurement operation | movement (s2) by the arithmetic storage device which concerns on the same embodiment. The block diagram which shows an example of a detailed structure of the arithmetic storage device which concerns on the same embodiment. The figure which shows the flowchart of calculation of the peak value which concerns on the same embodiment. The figure which shows the detailed flowchart of the average operation which concerns on the same embodiment. The figure which shows the flowchart of the subtraction process between modules which concerns on the same embodiment. The figure which shows the flowchart of the read-out process which concerns on the same embodiment. The figure which shows the modification of the probe module which concerns on the same embodiment. The figure which shows the modification of the electrode structure which concerns on the same embodiment. The conceptual diagram of the module which concerns on the same embodiment. The figure which shows the timing chart of the module which concerns on the same embodiment. The figure which shows the timing chart of the module which concerns on the same embodiment. The figure which shows the timing chart of the module which concerns on the same embodiment. The figure which shows the relationship between the oxidation current in a cell, and insertion agent immersion time.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Computer, 2 ... Base sequence analysis chip | tip, 11 ... Board | substrate, 12 ... Electrode, 13 ... Cell, 21 ... Detection electrode system, 22 ... Control electrode system, 201 ... Detection electrode, 202, 205 ... Reference electrode, 203,206 ... counter, 204 ... control electrode, ₃₁ 1 to 31 n _... probe module, 32 ... negative control module, 33 ... global instruction bus, 34 ... global address bus, 35 ... global data bus, 41 ... interface circuit, 42 ... decoder, DESCRIPTION OF SYMBOLS 43 ... Global control circuit, 51 ... Local control decoder, 52 ... Arithmetic logic operation circuit, 53 ... General-purpose register, 54 ... Result storage-only register, 410 ... Digital function generator, 420 ... D / A converter, 430 ... Potency- Stat, 440, A / D converter, 450, arithmetic storage device, 701, decode / control circuit Path, 702... Potentiostat, 703... I / V conversion circuit, 704... A / D converter, 705... Peak extraction circuit, 706, 709 ... selector, 707, 708.

Claims (3)

A base sequence analysis device comprising a base sequence analysis chip and a computer,
The base sequence analysis chip is
A substrate,
A plurality of detection electrodes formed on the substrate and to which probes having a base sequence complementary to a target base sequence to be detected are immobilized;
A control electrode formed on the substrate and not immobilized with a probe having a base sequence complementary to the target base sequence;
A first measurement unit formed on the substrate and measuring electrochemical signals of the plurality of detection electrodes;
A second measuring unit formed on the substrate and measuring an electrochemical signal of the reference electrode;
A subtracting unit formed on the substrate and subtracting a second measurement value of the second measurement unit from a first measurement value of the first measurement unit;
Based on a signal from the outside of the substrate, a control unit that simultaneously controls measurement of the first measurement unit and the second measurement unit, and controls subtraction of the subtraction unit;
Comprising
The plurality of detection poles includes a set of detection pole groups including at least two detection poles,
The reference electrode comprises a set of reference electrode groups comprising at least two reference electrodes;
A plurality of the first measurement units are provided, one for each of the plurality of detection electrode groups,
A plurality of the second measurement units are provided, one for each of the plurality of reference electrode groups,
The control unit simultaneously controls the measurement of the plurality of first measurement units, and simultaneously controls the measurement of the plurality of second measurement units;
The computer is communicably connected to the base sequence analysis chip, transmits a control command for controlling the operation of the control unit to the base sequence analysis chip, and sends a subtraction result in the subtraction unit from the base sequence analysis chip. A base sequence analyzing apparatus characterized by receiving. A plurality of the subtracting units are provided, one for each of the plurality of first measuring units,
The base sequence analysis apparatus according to claim 1, wherein the control unit controls subtraction of a plurality of the subtraction units simultaneously. A base sequence analysis device comprising a base sequence analysis chip and a computer,
The base sequence analysis chip is
A substrate,
A plurality of detection electrodes formed on the substrate and to which probes having a base sequence complementary to a target base sequence to be detected are immobilized;
A control electrode formed on the substrate and not immobilized with a probe having a base sequence complementary to the target base sequence;
A first measurement unit formed on the substrate and measuring electrochemical signals of the plurality of detection electrodes;
A second measuring unit formed on the substrate and measuring an electrochemical signal of the reference electrode;
A subtracting unit formed on the substrate and subtracting a second measurement value of the second measurement unit from a first measurement value of the first measurement unit;
Based on a signal from the outside of the substrate, a control unit that simultaneously controls the measurement of the first measurement unit and the second measurement unit, and controls the subtraction of the subtraction unit;
Comprising
A plurality of reference electrodes are provided, a plurality of first measurement units are provided for each of the plurality of detection electrodes, and a second measurement unit is provided for each of the plurality of control electrodes. A plurality of the control unit, the control unit controls the measurement of each of the plurality of first measurement unit and the plurality of second measurement unit simultaneously,
The computer is communicably connected to the base sequence analysis chip, transmits a control command for controlling the operation of the control unit to the base sequence analysis chip, and sends a subtraction result in the subtraction unit from the base sequence analysis chip. A base sequence analyzing apparatus characterized by receiving.

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