JP4308226B2 - Error correction coding device - Google Patents

Description

  The present invention relates to an encoding apparatus, and more particularly to an error correction code.

  Encoding technology is widely used in various fields. For example, in data transmission, data to be transmitted by a transmission source device is encoded and transmitted to a communication path, and a reception device receives and decodes the encoded data. When data is stored in a storage device, the data is encoded and written to a disk or the like. The encoded data is decoded when it is read from the disk. Note that encoding generally refers to converting an information source data sequence into a different data sequence, and a new data sequence obtained by the conversion is referred to as a code.

  Incidentally, when encoded data is transmitted, an error may occur in the communication path. An error may also occur when reading and reproducing the data from the storage device that stores the encoded data. In order to detect the occurrence of such an error or to correct the error, an error correction code is often used.

  A convolutional code is known as one of error correction codes. In the convolutional code, every time n bits of data are input, m (m> n) bits of data determined according to the n bits of data and the s bits of data input immediately before the n bits of data are output. Is done. That is, in the convolutional code, “mn” bits of data are added for error correction to the data to be transmitted. This increases the redundancy of data, so that the decoding error rate at the time of decoding can be lowered.

The ratio between the amount of data to be transmitted (the number of bits of source data) and the amount of data obtained by encoding (the number of bits of output data) is generally called a coding rate (or information rate) R. Is given by:
R = n / m
This coding rate R is always smaller than 1 in the error correction code. In general, the coding rate R is one of the parameters that determines the error correction capability in the decoding apparatus. For example, when the coding rate R is small, the error correction capability is high.

  FIG. 20 is a block diagram of an example of an existing error correction coding apparatus using a convolutional code. This error correction coding apparatus 500 includes two convolution units 501 and 502 provided in parallel with each other. As described above, an encoding apparatus including a plurality of convolution units provided in parallel with each other is often referred to as a “turbo encoding apparatus”.

  The error correction coding apparatus 500 generates a data sequence x and parity data sequences y1 and y2 for correcting the data sequence x for the source data d. The data series x and the parity data series y1 and y2 are multiplexed and output. This output is the encoded data of the source data d. Hereinafter, an operation when encoding N-bit source data d will be described.

  The source data d is output as it is as a data series x and is given to the convolution unit 501 and the interleaver 503. The convolution unit 501 performs convolutional coding on the source data d and outputs a parity data sequence y1. The interleaver 503 once holds the input N-bit source data d, and then reads and outputs the held source data d in an order different from the input order. As a result, the source data d is randomized. The output of the interleaver 503 is given to the convolution unit 502. Then, convolution section 502 performs convolutional coding on the output of interleaver 503 and outputs parity data sequence y2.

  With the above operation, error correction coding apparatus 500 generates N-bit data series x, N-bit parity data series y1, and N-bit parity data series y2 for N-bit source data d. These data series x and parity data series y1 and y2 are multiplexed, for example, bit by bit and output as encoded data. Therefore, in this case, the error correction coding apparatus 500 outputs 3 × N-bit data with respect to the N-bit input, so that the coding rate R becomes 1/3.

  FIG. 21 is a block diagram of a modification of the error correction coding apparatus shown in FIG. Error correction coding apparatus 510 is realized by providing selection section 511 with respect to error correction coding apparatus 500 shown in FIG. The selection unit 511 selects the parity data sequences y1 and y2 generated by the convolution units 501 and 502, respectively, according to a predetermined selection pattern, and outputs them as a parity data sequence Z. Note that the operation of the selection unit 511 may be referred to as “Puncturing”.

  The selection unit 511 alternately selects the outputs of the convolution units 501 and 502 bit by bit. The output series Z of the selection unit 511 is shown in Table 1. Here, “y1 (i)” is the output of the convolution unit 501 corresponding to the i-th data element of the source data d, and “y2 (i)” is the i-th data of the source data d. This is the output of the convolution unit 502 corresponding to the element. As described above, when the N-bit source data d is input to the error correction coding apparatus 510, the selection unit 511 outputs the N-bit output sequence Z (y1 (1), y2 (2), y1 (3), y2 (4), ..., y1 (N-1), y2 (N)).

選択部５１１によるパンクチャリング動作は、下記に示す式で表すことができる。

The puncturing operation by the selection unit 511 can be expressed by the following equation.

出力系列Ｚは、データ行列Ｄとパンクチャリング行列Ｐとの掛け算により得られる。例えば、ソースデータｄの第ｉ番目のデータエレメントに対しては、データ行列Ｄの第１行とパンクチャリング行列Ｐの第１列との積により「ｙ１(i) 」が得られる。また、ソースデータｄの第ｉ＋１番目のデータエレメントに対しては、データ行列Ｄの第２行とパンクチャリング行列Ｐの第２列との積により「ｙ２(i+1) 」が得られる。したがって、選択部５１１が畳込み部５０１および５０２の出力を交互に１ビットずつ選択する動作は、上記演算を繰り返し実行する動作として表される。

The output sequence Z is obtained by multiplying the data matrix D and the puncturing matrix P. For example, for the i-th data element of the source data d, “y1 (i)” is obtained by the product of the first row of the data matrix D and the first column of the puncturing matrix P. For the (i + 1) th data element of the source data d, “y2 (i + 1)” is obtained by the product of the second row of the data matrix D and the second column of the puncturing matrix P. Therefore, the operation in which the selection unit 511 alternately selects the outputs of the convolution units 501 and 502 bit by bit is expressed as an operation in which the above calculation is repeatedly executed.

  With the above configuration, error correction coding apparatus 510 generates N-bit data sequence x and N-bit parity data sequence Z for N-bit source data d. These data series x and parity data series Z are multiplexed bit by bit and output as encoded data. Therefore, in this case, the error correction coding apparatus 510 outputs 2 × N-bit data with respect to the N-bit input, so that the coding rate R is ½.

  The error correction coding apparatus shown in FIGS. 20 and 21 is disclosed in detail in US Pat. No. 5,446,747.

  By the way, there is a demand to make the data length M of the output sequence of the encoding device with respect to the data length N (number of bits) of the source data d arbitrary. For example, in a mobile communication system, generally, audio data or the like divided for each predetermined data length is stored and transmitted in a frame having a predetermined data length. That is, when a code is used in a mobile communication system, audio data or the like divided for each predetermined data length is encoded and stored in a frame.

  However, the coding rate R of the conventional error correction coding apparatus shown in FIG. 20 or FIG. 21 is fixed. Therefore, when creating data of a predetermined fixed length (a frame in the above example), meaningless information has to be stored in the data storage area of the frame.

  FIG. 22A is a diagram for explaining processing when the source data is encoded using the error correction encoding apparatus 500 shown in FIG. 20 and stored in a fixed-length frame. Here, the source data d is 333 bits, and the data storage area of the frame is 1500 bits. In this case, since the error correction coding apparatus 500 generates the 333-bit data sequence x, the 333-bit parity data sequence y1, and the 333-bit parity data sequence y2, in order to fill the data storage area of the frame, As shown in FIG. 22B, 501 bits of dummy data must be stored in the frame. Therefore, if the frame is transmitted through the network, useless data is transmitted, and network resources are wasted.

  FIG. 23A is a diagram for explaining processing when the source data is encoded using the error correction encoding apparatus 510 shown in FIG. 21 and stored in a fixed-length frame. Here, the source data d is 666 bits, and the frame data storage area is 1500 bits. In this case, the selection unit 511 generates a parity data sequence Z from the parity data sequence y1 and the parity data sequence y2 by puncturing processing. Therefore, the error correction coding apparatus 510 generates the 666-bit data sequence x and the 666-bit parity data sequence Z. Therefore, in order to fill the frame data storage area, as shown in FIG. 168 bits of dummy data must be stored in the frame. Therefore, as in the example shown in FIG. 22, useless data is transmitted.

  As described above, since the existing error correction encoding apparatus including a plurality of convolution units provided in parallel with each other cannot set the encoding rate to a desired value, the source data is encoded to generate a predetermined frame. The efficiency was poor when storing in

  An object of the present invention is to obtain a desired coding rate in an error correction coding apparatus including a plurality of convolution units provided in parallel to each other.

  The encoding apparatus of the present invention includes a first encoder that encodes source data to generate first parity data, an interleaver that performs interleaving processing on the source data to generate randomized data, and the randomization A second encoder that encodes data to generate second parity data, and a coding rate that is determined based on the data length of the source data and the data length of the output sequence included in the transmission frame. Selecting means for selecting first and second selection data by selecting the same number or almost the same number of data elements of the number of bits from the first and second parity data, respectively;

  In an error correction coding apparatus that codes source data, a desired coding rate (information rate) can be obtained. Therefore, if this apparatus is used in a communication system, it is not necessary to transmit meaningless data, so that transmission efficiency is improved and decoding characteristics are improved.

The error correction coding apparatus of the present invention can be applied to various fields, and can be used in, for example, a communication system and a data storage device.
FIG. 1 is a configuration diagram of a mobile communication system to which the error correction coding apparatus of the present embodiment is applied. The radio system is, for example, CDMA. The base station 10 includes an encoder 11 that encodes data (data A) to be transmitted to the mobile device 20, a modulator 12 that modulates the encoded data, and a transmitter 13 that transmits the modulated data. The radio signal transmitted from the base station 10 is received by the receiver 21 of the mobile device 20, demodulated by the demodulator 22, and decoded by the decoder 23. The base station 10 also includes a receiver 14 that receives a signal transmitted from the mobile device 20, a demodulator 15 that demodulates the received signal, and a decoder 16 that decodes the demodulated data. The mobile device 20 encodes data (data B) to be transmitted to the base station 10 using the encoder 24, modulates it using the modulator 25, and transmits it using the transmitter 26.

In the communication system, the error correction coding apparatus according to the present embodiment corresponds to the encoder 11 provided in the base station 10 or the encoder 24 provided in the mobile device 20.
FIG. 2 is a configuration diagram of a storage device to which the error correction coding apparatus of this embodiment is applied. The storage device 30 includes an encoder 31 that encodes data to be written to the data storage unit 33, and a write control unit 32 that writes the encoded data to the data storage unit 33. The data storage unit 33 includes, for example, a storage medium such as an optical disk, a magnetic disk, or a semiconductor memory. The storage device 30 also includes a read control unit 34 that reads data from the data storage unit 33 and a decoder 35 that decodes the read data.

In the above storage device, the error correction coding device of this embodiment corresponds to the encoder 31.
FIG. 3 is a block diagram of an error correction coding apparatus according to an embodiment of the present invention. The basic configuration of this error correction encoding apparatus is the same as that of the conventional error correction encoding apparatus shown in FIG. The puncturing unit of the error correction encoding apparatus of the present embodiment corresponds to the selection unit 511 of the conventional error correction encoding apparatus shown in FIG. However, the puncturing unit has a function different from that of the selection unit 511. The error correction coding apparatus according to the present embodiment realizes a desired coding rate by puncturing processing. Hereinafter, the configuration and operation of the error correction coding apparatus of the present embodiment will be described.

  The error correction encoding device 40 encodes the source data u using a systematic code. In the systematic code, data to be transmitted and data for correcting an error that occurs when the data is transmitted (hereinafter referred to as “parity data”) are separated from each other. That is, when the error correction coding apparatus 40 receives the source data u, it adds the parity data z to the source data u and outputs it. Note that the error correction encoding device 40 encodes N-bit source data u. Further, the error correction coding apparatus 40 outputs the source data u as “data series Xk”. Parity data is output as “parity data series Zk”.

  The input I / F unit 41 provides the received source data u to the multiplexing unit 47, the first convolution unit 43, and the interleaver 42. The source data u given from the input I / F unit 41 to the multiplexing unit 47 is referred to as “data series Xk”.

  The interleaver 42 randomizes the input source data u. The interleaver 42 includes a memory for temporarily storing N-bit source data u. The input N-bit source data u is written into the memory bit by bit. The data written to the memory is read bit by bit in an order different from the order of writing to the memory. As a result, the source data u is randomized.

  The purpose of providing the interleaver 42 is to give different convolutional data series to the convolution units 43 and 44. Therefore, in FIG. 3, an interleaver is provided only in the preceding stage of the second convolution unit 44, but an interleaver is provided for each of the first convolution unit 43 and the second convolution unit 44. Also good. However, in that case, the randomizing processes executed by the two interleavers need to be different from each other.

  The first convolution unit 43 performs a convolution process on the input source data u. On the other hand, the second convolution unit 44 performs a convolution process on the source data u randomized by the interleaver 42. The first convolution unit 43 and the second convolution unit 44 may have the same configuration or may have different configurations. In the following, it is assumed that the configurations of these two folding parts 43 and 44 are the same.

  The first convolution unit 43 includes a plurality of memories M connected in series with each other, and one or more adders. Each memory M is, for example, a flip-flop, and holds 1-bit data. The memories M connected in series constitute a shift register. The adder is, for example, an exclusive OR calculator or a mod2 adder. In the configuration shown in FIG. 3, the first convolution unit 43 includes two memories M and three adders. In this case, since the amount of data held by the memory M is 2 bits, the constraint length = 2. In this specification, the constraint length of the convolution circuit is equal to the number of bits of data stored in the memory of the convolution circuit.

  Each time the first convolution unit 43 receives the data element of the source data u, the first convolution unit 43 outputs the data element of the parity data sequence Y1k corresponding to the received data element. The data element of the parity data Y1k is obtained by the sum of the data element newly input to the first convolution unit 43 and the data element held in the memory M at the timing when the data element is input. . That is, in this convolution process, a data element corresponding to a newly input data element is generated and output based on one or more previously input data elements and the newly input data elements. The

  Each memory M of the first convolution unit 43 is set to “0” as an initial value. When an N-bit data sequence is input, the first convolution unit 43 outputs an N-bit parity data sequence, and further outputs a termination bit (tail bit) following the parity data sequence. The data length of the termination bit is the same as the number of memories M, for example, “2”.

  The configuration and operation of the second convolution unit 44 are basically the same as the configuration and operation of the first convolution unit 43 described above. However, the second convolution unit 44 performs a convolution process on the source data u randomized by the interleaver 42 to generate a parity data sequence Y2k.

Note that the convolution process is a known technique and is well known to those skilled in the art, so a detailed description thereof will be omitted here.
The first puncturing unit 45 selects each data element of the parity data sequence Y1k generated by the first convolution unit 43 according to a predetermined pattern and outputs it as a parity data sequence Z1k. Similarly, the second puncturing unit 46 selects each data element of the parity data sequence Y2k generated by the second convolution unit 44 according to a predetermined pattern and outputs it as a parity data sequence Z2k. A feature of the convolutional coding apparatus 40 shown in FIG. 3 is a data element selection method by these puncturing units. The data element selection method will be described in detail later.

  The multiplexing unit 47 receives the data sequence Xk given from the input I / F unit 41, the parity data sequence Z1k given from the first puncturing unit 45, and the parity data sequence Z2k given from the second puncturing unit 46. Multiplex and output. The output series C from the multiplexing unit 47 is encoded data for the source data u. The multiplexing unit 47 has a function of adjusting the timings of the three input data series. Thereby, when each data element of the source data u (data series Xk) is output, each data element of the parity data series Z1k and Z2k corresponding to the data element of the source data u is the data element of the source data. Output in association with.

  As described above, when the source data u is input, the error correction coding apparatus 40 converts the parity data series Z1k and Z2k for error correction into the data series Xk that is the same data series as the data series of the source data u. Is output.

  Next, the operations of the first puncturing unit 45 and the second puncturing unit 46 will be described and explained. Here, it is assumed that the data length of the source data u is N bits and the data length of the output series C is M bits. In this case, the error correction coding apparatus 40 is required to have a coding rate = N / M. The data lengths of the source data u and the output sequence C are determined by the specifications of the communication system, for example, when this error correction coding apparatus is used in the communication system. In particular, the data length of the output sequence C is determined by the format of the frame transmitted by the communication system.

FIG. 4 is a block diagram of the first puncturing unit 45. The second puncturing unit 46 has basically the same configuration.
The latch circuit 51 holds the parity data series Y1k output from the first convolution unit 43 bit by bit. That is, the latch circuit 51 is updated each time a data element of the parity data series Y1k is output from the first convolution unit 43. The CPU 52 executes a program stored in the memory 53 to generate a data element of parity data Z1k from the data element held in the latch circuit 51. The parity data Z1k data element is sent to the multiplexing unit 47 via the output port 54.

  The memory 53 stores a program executed by the CPU 52 and a puncturing table used by the program. This program will be described later.

  FIG. 5 is a diagram illustrating an example of a puncturing table. The puncturing table stores selection information (puncturing pattern information) indicating whether to select each data element of the parity data sequence Y1k. Therefore, the data length of this selection information is the same as the data length of the output data series from the first convolution unit 43. The first convolution unit 43 outputs an N-bit parity data sequence Z1k when the data length of the source data u is N bits. Therefore, in this case, the data length of the selection information is N bits.

  When the first convolution unit 43 receives the source data u, the first convolution unit 43 outputs a parity data sequence Y1k and then outputs a termination bit. However, the puncturing process is not executed for this termination bit. That is, the termination bit is sent to the multiplexing unit 47 without being input to the puncturing unit.

  In FIG. 5, selection information = “0” indicates that an input data element is not selected, and selection information = “1” indicates that an input data element is selected. For example, the selection information shown in FIG. 5 includes second, fourth, fifth,. . . , Nth data element is selected. That is, when the puncturing process is executed using this puncturing table, the parity data sequence Y1k = Y11, Y12, Y13, Y14, Y15,. . . Are entered in order, Y12, Y14, Y15,. . . Will be selected. The selected data element is output to the multiplexing unit 47 as a parity data sequence Z1k.

  The second puncturing unit 46 is basically the same as the first puncturing unit 45. Further, the puncturing table provided in the second puncturing unit 46 is basically the same as the puncturing table provided in the first puncturing unit 45. However, the selection information set in these two tables is not necessarily the same.

  Note that the CPU 52 and the memory 53 shown in FIG. 4 can be shared by the first puncturing unit 45 and the second puncturing unit 46. Furthermore, one puncturing pattern may be prepared as selection information, and the first puncturing unit 45 and the second puncturing unit 46 may share the selection information.

  The puncturing table is stored in a RAM area in the memory 53. Therefore, the selection information can be changed as necessary. As a result, a desired coding rate can be obtained. It is also possible to change the data length of the selection information according to the data length of the source data or according to the data length of the output sequence of the convolution unit.

  Next, a method for creating a puncturing table (that is, a method for creating selection information) will be described. In the following, it is assumed that the data length of the source data u is required to be N bits and the data length of the output sequence C is required to be M bits. In this case, coding rate R = N / M is required. Note that the termination bit generated by each of the first convolution unit 43 and the second convolution unit 44 is sufficiently shorter than the data length of the source data u, and is therefore ignored in the following description. Shall.

When the data length of the source data u is “N”, the data sequence Xk, the parity data sequence Y1k generated by the first convolution unit 43, and the parity data sequence generated by the second convolution unit 44 The data length of Y2k is “N”. Therefore, in order to set the data length of the output sequence C to M bits, the data lengths of the parity data sequences Z1k and Z2k respectively generated by the first puncturing unit 45 and the second puncturing unit 46 are set to “ In the case of “K1” and “K2”, the following expressions must be satisfied.
N + K1 + K2 = M
Here, if K1 = K2 = K, the following equation is obtained.
K = (MN) / 2 (where M> N, N> K)
That is, in this case, the first puncturing unit 45 selects K data elements from the parity data sequence Y1k composed of N data elements and outputs them as the parity data sequence Z1k. Similarly, the second puncturing unit 46 selects K data elements from the parity data sequence Y2k composed of N data elements and outputs the selected data data as a parity data sequence Z2k.

  When selecting K from N data elements, a puncturing table is used. As described above, the selection information stored in the puncturing table indicates whether or not to select each data element of the input sequence. Therefore, in order to select K data elements, the selection information in the N-bit selection information It is only necessary to assign “1: selected” to the K bits and “0: not selected” to the other bits. A specific example of a method of assigning “1” to K bits in N bits is shown below.

(1) Create a plurality of seed sequences k / n. “K / n” is an n-bit sequence in which k “1” s are evenly allocated. Note that k = 1, 2, 3,. . . , N = 1, 2, 3,. . . It is. Further, n> k. For example, the seed sequence is created with the maximum value of “n” being 10 and the maximum value of “k” being 9. A part of the seed series is shown. Note that “0” is assigned to the first bit of each seed sequence.
k / n = 2/7: (0001001)
1/3: (001)
3/8: (00100101)
2/5: (00101)
3/7: (0010101)
4/9: (001010101)
5/9: (010101011)
1/2: (01)
4/7: (0110101)
3/5: (01101)
5/8: (01110101)
3/4: (0111)
4/5: (01111)
5/6: (011111)
(2) Select an optimal seed sequence. Specifically, under the condition “K / N” ≧ “k / n”, search for “k / n” that minimizes the value r obtained by the following equation.

たとえば、ソースデータｕのデータ長Ｎが「３００」であり、パンクチャリング処理によって３００個のデータエレメントから１５５個を選択する場合には、Ｋ／Ｎ＝１５５／３００を代入すれば、「k/n 」として「１／２」が得られる。また、この場合、ｒ＝０．０１６６６が得られる。

For example, when the data length N of the source data u is “300” and 155 pieces are selected from 300 data elements by puncturing processing, if K / N = 155/300 is substituted, “k / N” “1/2” is obtained as “n”. In this case, r = 0.01666 is obtained.

  (3) A base pattern of selection information to be written in the puncturing table is created using the seed sequence selected in (2) above. Specifically, a base pattern of data length = N is created by repeating the selected seed sequence. For example, when a seed sequence of k / n = 1/2 is selected as in the above example, a 300-bit base pattern is obtained by repeating the seed sequence (01).

  (4) The selection information is obtained by correcting the base pattern. Specifically, first, A = r · N is calculated. Then, in the base pattern created in (4) above, A “0” s are equally selected and replaced with “1”. The first bit of the base pattern is not selected. For example, in the case of the above-described example, A = 0.1666 × 300 = 5 is obtained, so five “0” s are replaced with “1” in the base pattern (01010101... 0101).

The pattern obtained by the above processing is stored in the puncturing table as selection information (puncturing pattern information).
The puncturing tables provided in the first puncturing unit 45 and the second puncturing unit 46 are the same as each other as an example, but the two tables are not necessarily the same as each other. . However, it is desirable that the numbers of “1” included in the selection information stored in the two tables are the same or close to each other. If the difference in the number of “1” included in each selection information is greatly different from each other, the decoding characteristics may be deteriorated.

  The reason for setting the first bit of the selection information to “0” is as follows. Whether the first bit of the selection information selects the first data element of the parity data sequence Y1k generated by the first convolution unit 43 (or the parity data sequence Y2k generated by the second convolution unit 43) Represents The first data element of the parity data series Y1k is generated by the first convolution unit 43 by adding the head data element of the source data u and the initial value stored in the memory M shown in FIG. However, since the initial value is generally “all 0”, the head data element of the parity data series Y1k is the head data element of the source data u itself. That is, the effect of “convolution” cannot be obtained. Therefore, by assigning “1” to the first bit of the selection information, even if the first data element of the parity data sequence Y1k is selected and sent to the receiving device, it contributes to improving the error correction capability in the decoding process. do not do.

  For this reason, in this embodiment, “1” in the selection information is assigned to select a data element other than the head, thereby improving the error correction capability in the decoding process.

  Next, puncturing processing using a puncturing table will be described. Each time the first puncturing unit 45 receives a data element of the parity data sequence Y1k, the first puncturing unit 45 refers to the puncturing table and determines whether to select the data element. The selected data element is sent to the multiplexing unit 47 as a parity data sequence Z1k. On the other hand, data elements that are not selected are discarded without being sent to the multiplexing unit 47. This process is the same in the second puncturing unit 46.

  FIG. 6 is a flowchart of the puncturing process. This process is executed each time the data element of the parity data series Yk generated by the convolution unit is written in the latch circuit 51. Note that the parity data sequence Yk represents the parity data sequence Y1k or Y2k. That is, when the processing of this flowchart represents the operation of the first puncturing unit 45, Yk = Y1k, and when the processing of this flowchart represents the operation of the second puncturing unit 46, Yk = Y2k.

  In step S1, a data element is acquired from the latch circuit 51. In step S2, the counter for counting the number of data elements in the parity data series Yk is incremented by the counter written in the latch circuit 51. This count value k corresponds to the position information or sequence number of the data element. This counter is reset every time processing for one set of source data is completed.

  In step S3, the puncturing table shown in FIG. 5 is referred to using the count value k of the counter. As a result, selection information P (k) relating to the data element written in the latch circuit 51 is obtained. In step S4, it is checked whether the selection information P (k) obtained in step S3 is “1” or “0”. If the selection information P (k) = 1, the data element written in the latch circuit 51 is sent to the multiplexing unit 47 via the output port 54 in step S5. At this time, the count value k used when referring to the puncturing table is also sent to the multiplexing unit 47. On the other hand, if the selection information P (k) = 0, the data element written in the latch circuit 51 is discarded in step S6.

  In step S7, it is checked whether or not the count value k has reached “N”. If the count value k has reached “N”, it is considered that the processing for one set of source data has been completed, and the counter is reset in step S8.

  In this way, the first puncturing unit 45 and the second puncturing unit 46 select and output K bits from the input N-bit parity data sequence Yk. This selection process is realized by causing the CPU 52 to execute a program describing the above steps S1 to S8.

  Table 2 shows examples of outputs from the first puncturing unit 45 and the second puncturing unit 46.

この出力は、入力されるソースデータｕが９ビットであり、また、第１のパンクチャリング部４５および第２のパンクチャリング部４６におけるパンクチャリングパターンＰが共に（００１１０１００１）であった場合に得られる。

This output is obtained when the input source data u is 9 bits and both the puncturing patterns P in the first puncturing unit 45 and the second puncturing unit 46 are (001110001). .

  FIG. 7 is a block diagram of the multiplexing unit 47. The multiplexing unit 47 is generated by the buffer 61 for holding the data sequence Xk, the memory 62 for holding the parity data sequence Z1k generated by the first puncturing unit 45, and the second puncturing unit 46. The memory 63 and the buffer 61 for holding the parity data series Z2k, and the read control unit 64 that reads and outputs the data elements from the memories 62 and 63 are provided.

  The data elements of the data series Xk are written in the buffer 61 in order. The parity data sequence Z1k is a data element selected by the first puncturing unit 45. These data elements are written in the memory 62 in association with the sequence number. The sequence number corresponding to each data element is indicated by, for example, the count value k of the counter described with reference to FIG. The memory 62 is set to “valid / invalid display” indicating whether or not each data element is written for each sequence number. The configuration of the memory 63 is the same as that of the memory 62.

The read control unit 64 reads and outputs one data element from any one of the buffer 61 and the memories 62 and 63 at predetermined intervals. Specifically, the data element is read by repeatedly executing the following procedures (1) to (4).
(1) Read the data element of the specified sequence number from the buffer 61.
(2) When the data element of the specified sequence number is stored in the memory 62, it is read out.
(3) If the data element of the specified sequence number is stored in the memory 63, it is read out.
(4) Designate the next sequence number.

When the buffer 61 and the memories 62 and 63 are in the state shown in FIG. 7, when the above steps (1) to (4) are repeatedly executed, the output series C is as follows. Output series C = (X1, X2, X3, Y13, Y23, X4, Y14, Y24, X5,...)
As described above, the error correction coding apparatus 40 shown in FIG. 3 uses the selection information (puncturing pattern) stored in the puncturing section to calculate the amount of parity data added for error correction. Can be changed. That is, a desired coding rate R is obtained according to the selection information setting.

  Next, a decoding device for decoding the data series encoded by the error correction encoding device 40 will be briefly described. Various methods are known as the decoding process. Basically, the data series is decoded by executing the encoding process in the reverse procedure.

  FIG. 8 is a block diagram of the decoding apparatus. Here, it is assumed that the first puncturing unit 45 and the second puncturing unit 46 of the error correction coding apparatus 40 have performed puncturing processing on the parity data Y1k and Y2k using the same selection information. To do. Although not specifically shown, this decoding apparatus has a function of separating the data series X and the parity data series Z multiplexed in the error correction encoding apparatus 40.

  The serial / parallel converter 71 separates the received parity data sequence Z into parity data sequences Z1k and Z2k. The parity data sequences Z1k and Z2k are sequences generated by the first puncturing unit 45 and the second puncturing unit 46 provided with the error correction coding device 40, respectively.

  The first depuncturing section 72 and the second depuncturing section 73 have the same table as the puncturing table of the error correction coding apparatus 40, respectively, and “depuncture” is applied to the parity data sequences Z1k and Z2k, respectively. "Charing process" is executed.

  An example of the depuncturing process will be described with reference to FIG. Here, it is assumed that the parity data sequence Z1k = (Z11, Z12, Z13, Z14, Z15) is input. Further, it is assumed that selection information shown in FIG. 10 is stored in the puncturing table. Hereinafter, the process of the first depuncturing unit 72 will be described, but the process of the second depuncturing unit 73 is the same.

When receiving the parity data sequence Z1k, the first depuncturing unit 72 first checks selection information corresponding to the sequence number = “1” in the puncturing table. In this case, since the selection information = “0”, the first depuncturing unit 72 outputs “0”. Subsequently, the selection information corresponding to the sequence number = “2” in the puncturing table is checked. In this case, since selection information = “1”, the first depuncturing section 72 outputs “Z11”, which is the first data element of the parity data sequence Z1k. Hereinafter, similarly, the first depuncturing section 72 outputs “0” when the selection information = “0”, and outputs the data element of the parity data sequence Z1k when the selection information = “1”. Are sequentially output one by one. As a result, the first depuncturing unit 72 outputs the following data series.
Output series: (0, Z11, 0, Z12, 0, Z13, 0, Z14, Z15)
This output sequence is given to the first decoder 74 as a parity data sequence Y1k. Similarly, the second depuncturing section 73 generates a parity data sequence Y2k and gives it to the second decoder 75.

  FIG. 10 is a flowchart of the depuncturing process. Here, the case where the data series Y is produced | generated with respect to the input data series Z is demonstrated. The data elements of the data series Z and the data series Y are represented as “Zi” and “Yk”, respectively.

  In step S11, the puncturing table is searched using “k”, and the corresponding selection information is acquired. In step S12, it is checked whether the selection information acquired in step S11 is “1” or “0”. If the acquired selection information is “1”, in step S13, one data element of the data series Zi is output as the data element of the data series Yk. In step S14, “i” is incremented. On the other hand, if the acquired selection information is “0”, “0” is output as the data element of the data series Yk in step S15.

  Subsequently, in step S16, “k” is incremented. In step S17, it is checked whether or not “k” has reached “N”. “N” is the data length of the source data. If “k” has not reached “N”, the process returns to step S11. If “k” has reached “N”, “k” and “i” are reset.

  Returning to FIG. The parity data sequence Y1k generated by the first depuncturing unit 72 is provided to the first decoder 74. Similarly, the parity data sequence Y2k generated by the second depuncturing unit 73 is provided to the second decoder 75. The first decoder 74 decodes the received data sequence Xk using the parity data sequence Y1k. The second decoder 75 decodes the output of the first decoder 74 using the parity data sequence Y2k.

  The output of the second decoder 75 is compared with a predetermined threshold value in the determination unit 76. Then, the deinterleaver 77 performs a deinterleaving process (a process reverse to the randomizing process in the error correction coding apparatus 40) on the comparison result, and outputs the result as decoded data.

  Note that the decoding process excluding the process of generating the parity data series can be realized using a known technique. For example, it is described in US Pat. No. 5,446,747. Accordingly, detailed description of the decoding process is omitted here.

  In order to improve the decoding accuracy, as shown in FIG. 11, the decoding devices having the above-described configuration may be connected in series. In this case, the decoding device shown in FIG. 8 corresponds to one decoding module. Each decoding module receives a received data sequence (data sequence X and parity data sequence to be decoded) and a predicted value (sequence T) of the data sequence X in the preceding decoding module, generates decoded data S, and newly A data series X is predicted. This newly predicted data series X is passed to the next decoding module.

  In the above configuration, the decoding accuracy is improved by increasing the number of decoding modules connected in series. For example, the decoded data S output from the decoding module 70-4 has higher decoding accuracy than the decoded data S output from the decoding module 70-1. The operation of this configuration is described in US Pat. No. 5,446,747.

  In the configuration shown in FIG. 11, the serial / parallel converter 71, the first depuncturing unit 72, and the second depuncturing unit 73 shown in FIG. 8 are connected to the decoding module 70-1 at the first stage. Should be provided.

  Next, an error correction coding apparatus according to another embodiment of the present invention will be described. As described above, the conventional error correction coding apparatus generally has a fixed coding rate. For example, in the configuration shown in FIG. 20, the coding rate R = 1/2, and in the configuration shown in FIG. 21, the coding rate = 1/3. In the error correction coding apparatus described below, an arbitrary coding rate can be obtained. In particular, an arbitrary coding rate smaller than 1/3 can be obtained.

  FIG. 12 is a diagram showing a difference in output between the error correction coding apparatus 40 of the present embodiment and the conventional apparatus. Here, the apparatus shown in FIG. 21 is taken up as a conventional apparatus. In the conventional apparatus, as described with reference to FIG. 23, for example, when the data length of the source data is 666 bits and the requested output data length is 1500 bits, the encoded data has 168 bits. Bit dummy data is added. In this case, the parity data used to correct the error is 666 bits.

  On the other hand, when the error correction coding apparatus 40 is used, as shown in FIG. P1, 417-bit parity data sequences Z1K and Z2K are generated from the 666-bit parity data sequences Y1K and Y2K, respectively. As a result, the parity data used to correct the error is 834 bits. That is, the amount of data used to correct errors is increased compared to conventional devices. Therefore, in this embodiment, the decoding capability is increased.

  FIG. 13 is a configuration diagram of an error correction coding apparatus 80 according to another embodiment of the present invention. In FIG. 13, the interleaver 42, the first convolution unit 43, the second convolution unit 44, and the multiplexing unit 47 are the same as those shown in FIG. In FIG. 13, the input I / F unit 41 is omitted.

  A feature of the error correction coding apparatus 80 is that a bit duplication unit 81 is provided. The bit duplication unit 81 duplicates a predetermined number of data elements in the source data u in order to obtain a desired coding rate.

  The operation of the bit overlap unit 81 will be described. In the following, it is assumed that the data length of the source data u is N bits and the data length of the output data series is M bits. Further, it is assumed that M> 3N. That is, a case where a value smaller than 1/3 is required as the coding rate is assumed.

Assuming that the data series Xk is obtained by duplicating r bits in the source data u in the bit duplication unit 81, the data lengths of the data series Xk, the parity data series Y1k, and the parity data series Y2k are “N + r”, respectively. "become. Therefore, in order to set the data length of the output data series to M bits, the number of bits to be duplicated in the bit duplication unit 81 is obtained by the following equation.
(N + r) × 3 = M
∴r = M / 3−N
For example, assuming that the data length of the source data u is 250 bits and the data length of the required output sequence is 900 bits, r = 50 is obtained by substituting N = 250 and M = 900 into the above equation.

  The bit duplication unit 81 preferably duplicates the data element of the source data u for each “constraint length + 1” bit. Here, the constraint length is the number of bits of data held in the memory in the convolution process. For example, in the configuration shown in FIG. 13, since the constraint length = 2, the data element of the source data u is duplicated every 3 bits.

  As described above, when a data sequence in which predetermined data elements are overlapped is encoded and transmitted, the accuracy of decoding processing for subsequent data elements in a portion where the data elements overlap is improved as is known in the encoding technology. To do.

  FIG. 14 is a diagram illustrating an operation example of the bit duplication unit 81. Here, a case is shown where the data length of the source data u is 7 bits, the constraint length = 2, and the data length of the required output sequence is 27 bits. In this case, two data elements are duplicated. In addition, data elements are duplicated every 3 bits. By this processing, the coding rate of the error correction coding apparatus 80 becomes “7/27”.

  FIG. 15 is a flowchart for explaining the operation of the bit duplication unit 81. Here, it is assumed that source data u (u0, u1, u2, u3,..., Ui,...) Has been input. The number of data elements that should be duplicated is “r”. Furthermore, data elements are duplicated every x bits.

  In step S21, the data element ui of the source data u is acquired. Hereinafter, “i” is referred to as a sequence number. In step S22, it is checked whether or not the bit overlap number j has reached “r” which is the number of data elements to be overlapped. The bit duplication number j represents the number of times bit duplication has already been executed in the source data u. If j> r, it is considered that the necessary number of bit duplications have already been completed, and in step S23, the acquired data element ui is output as it is. On the other hand, if j ≦ r, it is considered that further bit duplication needs to be performed, and the process proceeds to step S24.

  In step S24, it is checked whether or not the sequence number i is an integer multiple of “x”. If the sequence number i is not an integer multiple of “x”, no bit duplication is performed, and the process proceeds to step S23. On the other hand, when the sequence number i is an integral multiple of “x”, bit duplication is performed. That is, the data element ui is output in steps S25 and S26, respectively. As a result, the data element ui is duplicated. Subsequently, in step S27, the bit overlap number j is incremented.

  In step S28, it is checked whether or not the sequence number i has reached “N”. If the sequence number i has not reached “N”, the sequence number i is incremented in step S29, and the process returns to step S21 to acquire the next data element. On the other hand, if the sequence number i has reached “N”, it is considered that the processing of steps S21 to S29 has been performed for all the data elements of the source data, and “i” and “j” are determined in step S30. The process ends after resetting.

  As described above, the error correction coding apparatus 80 shown in FIG. 13 overlaps a predetermined number of data elements in the source data in order to obtain a desired coding rate. In other words, a desired coding rate can be obtained by overlapping a predetermined number of data elements in the source data. In addition, since the duplicate bits are used in the decoding process, the error rate of the transmission path can be reduced.

  Note that the decoding apparatus that decodes the data series encoded by the error correction encoding apparatus 80 may have a function of executing the process by the bit duplication unit 81 in the reverse procedure after executing the normal decoding process. .

  FIG. 16 is a configuration diagram of an error correction coding apparatus 90 according to still another embodiment of the present invention. In FIG. 16, the interleaver 42, the first convolution unit 43, the second convolution unit 44, and the multiplexing unit 47 are the same as those shown in FIG.

  The feature of the error correction coding apparatus 90 is that a dummy bit insertion unit 91 is provided. The dummy bit insertion unit 91 inserts a predetermined number of dummy bits into the source data u in order to obtain a desired coding rate.

  The operation of the dummy bit insertion unit 91 will be described. In the following, it is assumed that the data length of the source data u is N bits and the data length of the output data series is M bits. Further, it is assumed that M> 3N. That is, a case where a value smaller than 1/3 is required as the coding rate is assumed.

When the data sequence Xk is obtained by inserting r dummy bits into the source data u in the dummy bit insertion unit 91, the data lengths of the data sequence Xk, the parity data sequence Y1k, and the parity data sequence Y2k are respectively “N + r”. Therefore, in order to set the data length of the output data series to M bits, the number of bits to be inserted in the dummy bit insertion unit 91 is obtained by the following equation.
(N + r) × 3 = M
∴r = M / 3−N
The dummy bit insertion unit 91 preferably inserts a dummy bit having the same length as the constraint length. As described above, the constraint length is the number of bits of data held in the memory in the convolution process. Therefore, in the configuration shown in FIG. 13, dummy bits are inserted into the source data u with 2 bits as one unit.

  As the dummy bit, “1” or “0” is used. Here, if “1” is used as a dummy bit, “11” is inserted as dummy data when the constraint length = 2. For example, if the data length of the source data u is 250 bits and the data length of the required output sequence is 900 bits, r = 50 is obtained. That is, it is required to insert 50 dummy bits into the source data u. Here, assuming that the constraint length = 2, “11” is inserted into the source data u at 25 locations. It is desirable that the insertion positions are evenly distributed.

  As described above, when a data series in which “1” is inserted as dummy data is encoded and transmitted, the accuracy of the decoding process for the data element subsequent to the dummy bit is improved, as is known in the encoding technology.

  As described with reference to FIGS. 22 and 23, dummy data is often used also in the conventional error correction coding apparatus. However, in the conventional method, dummy data is added to the encoded data series, whereas in the error correction coding apparatus 90, dummy bits are inserted into the source data, and the dummy bits are inserted. The source data is encoded. That is, in the conventional method, the dummy data is “meaningless data”. However, in the error correction coding apparatus 80, the dummy bit is used as a prior probability likelihood in the decoding process, and thus useful. It is a lot of data.

  FIG. 17 is a diagram illustrating an operation example of the dummy bit insertion unit 91. Here, a case is shown where the data length of the source data u is 7 bits, the constraint length = 2, and the data length of the required output sequence is 27 bits. In this case, the coding rate = 7/27 is realized by inserting 2 dummy bits into the source data u.

  As described above, the error correction coding apparatus 90 shown in FIG. 16 inserts a predetermined number of dummy bits in the source data in order to obtain a desired coding rate. In other words, a desired coding rate can be obtained by inserting a predetermined number of dummy bits in the source data. In addition, since the inserted dummy bits are used in the decoding process, the error rate of the transmission path can be reduced.

Note that the decoding device that decodes the data sequence encoded by the error correction encoding device 90 may be provided with a function of removing dummy bits after executing a normal decoding process.
The error correction coding apparatus shown in FIGS. 3, 13, and 16 has a configuration including two convolution units connected in parallel to each other, but the present invention is limited to this configuration. It is not a thing. That is, the present invention can be applied to a device having a plurality of convolution units connected in parallel to each other.

  FIG. 18 is a block diagram of an error correction coding apparatus 100 including m convolution units. The convolution units 101-1 to 1-1-m each perform a convolution process on the source data. Different interleavers are provided for the convolution units 101-2 to 1-1-m. As a result, different sequences are given to the convolution units 101-1 to 1-1-m.

  The puncturing unit 102 selects and outputs a predetermined number of data elements from the parity data sequences Y1k to Ymk respectively output from the convolution units 101-1 to 1-1-m. For example, when the data length of the source data u is N bits and the data length of the output sequence C is M bits, that is, when the coding rate is N / M, the puncturing unit 102 performs the data element as follows: Select. Here, each convolution unit 101-1 to 1-1-m outputs N-bit parity data when an N-bit sequence is given.

When the puncturing unit 102 selects K1 to Km data elements from the parity data series Y1k to Ymk, respectively, the following equations are obtained.
N + K1 + K2 + K3 +... + Km = M
Here, if K1 = K2 = K3 =... = Km = K, the following equation is obtained.
K = (MN) / m
∴Coding rate R = N / M = (M−m · K) / M (where M> N, N> K)
As described above, the coding rate R of the error correction coding apparatus can be determined according to the number of convolution units provided in parallel and the number of data elements to be selected from the N-bit sequence.

  In the above embodiment, the error correction coding apparatuses shown in FIGS. 3, 13, and 16 have been described as being independent of each other. However, these apparatuses can be arbitrarily combined. For example, the bit duplication unit 81 shown in FIG. 13 or the dummy bit insertion unit 91 shown in FIG. 16 may be provided in the input unit of the error correction coding apparatus 40 shown in FIG.

  In addition, the error correction coding apparatus of the above embodiment employs a configuration that executes a convolution process while employing a systematic code. However, the present invention is not limited to this configuration. That is, the error correction coding apparatus of the present invention is not necessarily limited to the systematic code, and is not necessarily limited to the configuration including the convolution unit.

  FIG. 19 is a block diagram of an error correction coding apparatus that is not limited to systematic codes. The error correction coding apparatus 110 has a plurality of encoders 111 for coding the source sequence. Each encoder 111 may be a convolutional code or another block code (for example, a Hamming code, a BCH code, etc.). Also, an interleaver 112 is provided so that the sequences given to the encoders 111 are different from each other. For the puncturing process and the multiplexing process, the configuration of the above-described embodiment can be used.

1 is a configuration diagram of a mobile communication system to which an error correction coding apparatus of the present embodiment is applied. It is a block diagram of the memory | storage device with which the error correction encoding apparatus of this embodiment is applied. It is a block diagram of the error correction coding apparatus of one Embodiment of this invention. It is a block diagram of a puncturing unit. It is a figure which shows an example of a puncturing table. It is a flowchart of a puncturing process. It is a block diagram of a multiplexing part. It is a block diagram of a decoding apparatus. It is a figure explaining a depuncturing process. It is a flowchart of a depuncturing process. It is a block diagram of an example of the decoding apparatus which improved the decoding precision. It is a figure which shows the difference between the output of the error correction coding apparatus of this embodiment, and the output of the conventional apparatus. It is a block diagram of the error correction coding apparatus of the other form of this invention. It is a figure explaining operation | movement of a bit duplication part. It is a flowchart explaining operation | movement of a bit duplication part. It is a block diagram of the error correction coding apparatus of the further another form of this invention. It is a figure explaining operation | movement of a dummy bit insertion part. It is a block diagram of an error correction coding apparatus provided with m convolution parts. It is a block diagram of an error correction coding apparatus not limited to a systematic code. It is a block diagram of an example of the existing error correction encoding apparatus using a convolutional code. FIG. 21 is a block diagram of a modified example of the error correction coding apparatus shown in FIG. 20. (A) is a figure explaining the process in the case of encoding source data using the error correction encoding apparatus shown in FIG. 20, and storing in a fixed length frame. (B) is a diagram schematically showing data stored in a frame. (A) is a figure explaining the process in the case of encoding source data using the error correction encoding apparatus shown in FIG. 21, and storing in a fixed length frame. (B) is a diagram schematically showing data stored in a frame.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Base station 11, 24 Encoder 20 Mobile device 30 Memory | storage device 31 Encoder 40 Error correction coding apparatus 41 Input I / F part 42 Interleaver 43 1st convolution part 44 2nd convolution part 45 1st puncturing Unit 46 second puncturing unit 47 multiplexing unit 81 bit duplication unit 91 dummy bit insertion unit

Claims (1)

A first encoder that encodes a source data sequence to generate a first parity data sequence ;
An interleaver that generates a randomized data sequence by performing an interleaving process on the source data sequence ;
A second encoder for generating a second parity data sequence by encoding the randomized data sequence,
The number of bits determined corresponding to the coding rate determined based on the data length of the source data sequence and the data length of the output sequence included in the transmission frame for each of the first and second parity data sequences Acquisition means for acquiring selection information for selecting a data element of
Selection means for generating the first and second selection data by selecting the same or substantially the same number from the first and second parity data series based on the selection information acquired by the acquisition means ;
An encoding device.

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