JP4307604B2 - Computer circuit system and method using partial cache cleaning - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present embodiment relates to a computer use environment that realizes one or more cache memories.
[0002]
[Problems to be solved by the invention]
Cache circuits are frequently used in modern computing systems (eg, microprocessors) to increase system performance by reducing the potential length of time required to access information. It is an important component. Normally, a cache circuit includes various components such as a tag memory, which is generally a random access memory (RAM). The tag RAM generally stores so-called tag information corresponding to the cache data stored in the individual cache data RAM. The tag information includes cached data, such as the actual address where cached data can be found in some other memory device (such as an external memory structure). Various features corresponding to are included. Another component of the circuit is a hit detection circuit associated with the tag RAM. (The N-way set associative cache circuit has n circuits) The hit detection circuit receives the actual address stored as part of the tag information and the incoming call Compare addresses (incoming addresses). If this comparison matches, there is a hit in the cache circuit. In other words, the data searched for by this incoming address can be directly searched from the cache data RAM. On the contrary, if this comparison does not match, there is a mistake in the cache circuit. That is, the data searched for at this incoming address is not located in the cache data RAM or cannot be relied on for some other reason. In the case of a cache miss, data must be retrieved from the upper memory of the memory hierarchy, such as main memory (ie, external memory), or another cache memory located at the upper level of the system. Therefore, data access after a cache miss requires a very long time compared to the access time in the case of a cache hit. In fact, in the case of an access for retrieving from external memory, the required time will be considerably longer than the access time when a cache hit occurs.
[0003]
The above description shows that cache memory is generally considered advantageous, but as computers and computer usage environments become more complex, the cache operation will be scrutinized in more detail to add more efficiency. It is necessary to decide whether or not to do so. In this regard, the inventor has confirmed that several clock cycles can be reduced in the context of certain operations of the cache circuit. Reducing the clock cycles used in connection with cache operations improves system speed. This reduction in clock cycles also reduces overall system power consumption, which is a major problem in many modern systems, such as portable computers.
[0004]
[Problems to be solved by the invention]
In one preferred embodiment is a method of operating a computing system. The computing system includes a cache memory, which has a predetermined number of cache lines. Initially, the method writes data to a cache memory at a position corresponding to each of the plurality of write addresses. The method then cleans a selected number of lines in the cache memory. If the cleaning step evaluates the dirty indicator corresponding to the data in that line for each selected number of lines, and the dirty indicator indicates that the data in that line is dirty Copies data from that line to another memory. Finally, the number of lines to be selected is less than the predetermined number of cache lines. In addition, other circuits, systems, and methods are disclosed and specified in the claims.
[0005]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows a preferred embodiment of a typical wireless data platform 10 in which the various cache embodiments described herein can be implemented. In addition, this wireless data platform can be used, for example, to implement a smartphone or a portable computer. The wireless data platform 10 includes a general purpose (host) processor 12 having an instruction cache 12a and a data cache 12b each having a corresponding instruction memory management unit (MMU) 12c, 12d, and a buffer circuit 12e and operation. Although the core 12f is also shown, all these circuits communicate using the system bus SBUS. SBUS includes the conductors of data SBUSd, address SBUSa and control SBUSc. A digital signal processor (DSP) 14a having its own internal cache (not shown) and a peripheral device interface 14b are connected to the SBUS. Although not shown, various peripheral devices including a digital-to-analog converter (DAC) or a network interface can be connected to the peripheral device interface 14b. The DSP 14 a and the peripheral device interface 14 b are connected to the DMA interface 16, and the DMA interface 16 is further connected to the DMA controller 18. The DMA controller 18 is connected to the SBUS in the same manner as the video or LCD controller 20 that communicates with the LCD or video display 22. The DMA controller 18 is connected to the main memory via an address bus 24a, a data bus 24d and a control bus 24c, the main memory of this preferred embodiment being a synchronous dynamic random access memory (SDRAM) 24. Similarly, the DMA controller 18 is connected to one (or a plurality of) flash memories 26 via an address bus 26a, a data bus 26d, and a control bus 26c.
[0006]
The general operational aspects of the wireless data platform 10 are understood in connection with the concepts of the present invention by explaining that the wireless data platform 10 uses both a general purpose processor 12 and a DSP 14a. . Thus, since there are multiple cores sharing a single memory, it will be understood that the method of the present invention described later provides various improvements in system performance, such as a multi-core system. It may be a system different from the wireless data platform 10). It should also be noted that many of the aspects of the invention described below can also improve the operation of a single processor system.
[0007]
Turning attention now to the cache aspect of the preferred embodiment, FIG. 2 shows, by way of example, the architecture of the data cache 12b of the general purpose processor 12 of FIG. Prior to discussing this structure in detail, the various teachings of the present invention will further explain the instruction cache 12a, one or both caches of the DSP 14a, or the platform 10 (such as an integrated cache). It should be understood that it can be implemented in connection with other caches, such as another cache. Also, the various teachings of the invention described below can be used with processing devices including smart phones, PDAs, palmtop computers, notebook computers, desktop computers, etc. that would benefit from cache memory. Finally, various details regarding the data cache 12b are provided below, but many of these details (eg, set association, array size, address and storage length, etc.) are for clarity of explanation. Please note that this is only.
[0008]
Next, paying attention to the details of the data cache 12b shown in FIG. 2, the data cache 12b includes a cache controller 28 that receives a memory address. In this case, the memory address is a 32-bit data address. This part of DA [31: 0] indicates that the cache control unit 28 that receives the memory address receives bits “4” to “11” from the 32-bit address. Similarly, bits “[11: 4]” and bits DA [1: 0] indicating that bits “1” are received from bits “0” of the 32-bit address are included. The cache controller 28 is connected to the virtual tag array 30v and stores tags corresponding to the lines of the data array 32. With respect to this point and discussion of the discussion that follows, virtual tag array 30v stores dirty bits for each line in data array 32, in which case the display of dirty data is the data array. It is well known in the cache technology that the data stored in 32 is changed, but the changed copy is not output to the upper memory of the memory system (for example, main memory). is there. Also, the indications included corresponding to each line of the data array 32 are the LRU bit in the LRU indicator array 34 (a bit indicating that it has not been used at all recently) and the validity indicator array 36. Validity bit.
[0009]
In the preferred embodiment, the data cache 12b is arranged as a two-way set associative cache, so the tag array 30v has two planes 30av and 30bv, respectively. Similarly, the data array 32 has two memory planes 32a and 32b. In the illustrated embodiment, each plane 32a, 32b is 1024.times.32 bits (ie, 4 bytes), so four consecutive addresses are required to form a 16 byte line. The outputs of the planes 30av and 30bv are output to the respective comparators 38a and 38b. DA [31:12] is also connected to both comparators 38a and 38b. Each of the comparators 38a and 38b generates a 1-bit output named Way 1 hit (Hit way 1) and Way 2 hit (Hit way 2), respectively. The way 1 hit signal and the way 2 hit signal are connected to the control inputs of the respective transfer gates 40a and 40b, and each transfer gate has 32 bits of data DD [31: 0] in the data array whose address is specified as an output. give.
[0010]
Since the operation of set associative caches is well known in the art, in order to give the cache cleaning process a context with a detailed description that can be understood in more detail and later in the discussion, only read operations will be discussed here. It is summarized. Focusing on the read operation, when the address DA [31: 0] is received for memory access, the address bits DA [11: 4] are the addresses to the respective plain planes 30av, 30bv of the virtual tag array 30v. Used as. Each plane 30av, 30bv outputs a tag bit Tag_DA [31:12] corresponding to its address. In this case, the tag includes an indication of the address of the data stored in the data array 32. It is. Bits DA [31:12] are then compared to the tag via comparators 38a, 38b to determine whether they match (ie, hit), and if so, which of comparators 38a, 38b These outputs enable the way 1 hit signal or the way 2 hit signal, respectively. During this same process, the index portion of the address, which in this example is bits DA [11: 4], is applied to the planes 32a, 32b of the data array. Therefore, when both planes output information from the index and the way 1 hit signal or the way 2 hit signal becomes operable, the output of any one of these planes is output as output data DD [31: 0]. appear. Needless to say, when a cache miss occurs (that is, neither the way 1 hit signal nor the way 2 hit signal becomes operable), the addressed information is searched from the memory above the cache 12b in the memory hierarchy. Finally, recall that each memory address in the tag memory has a corresponding validity bit in the array indicator 36. These bits indicate whether the data at the corresponding location in the cache is valid. The bits in the LRU array indicator 34 determine which line of the planes 32a, 32b is updated after a cache miss.
[0011]
The data cache 12b also includes a cache clean function, which greatly improves the efficiency of the cache operation, as will first be described in functional detail with reference to the block diagram of FIG. be able to. In particular, FIG. 3 shows the cache controller 28 in greater detail as far as the cache clean function is concerned. The cache controller 28 includes an address register 42 for storing the value of the address named I_MAX, as will be seen later, this address register 42 is provided by an additional circuit described below. Controlled and stores several copies of the data address index (ie DA [11: 4]). The address input of the address register 42 is connected to the output of a transfer gate 44, which has a data input connected to receive the address index DA [11: 4]. The address index DA [11: 4] is connected to the input of the comparator 46, and the comparator 46 is connected to receive the value of I_MAX stored in the address register 42. For reasons explained in detail below, when a cache hit occurs in response to a write to the data cache 12b, the comparator 46 determines whether or not the value of I_MAX is larger than the incoming address index DA [11: 4]. If it is larger, the control input of the transfer gate 44 is enabled, so that the incoming address index DA [11: 4] at that time is copied to the address register 42 and the value of I_MAX is updated.
[0012]
To supplement FIG. 3, the cache controller 28 includes a cache clean processing circuit 48, which receives the dirty bit as one input provided by the virtual tag array 30v. And connected to receive a CACHE_CLEAN signal that enables the functions described in detail below. Note that the CACHE_CLEAN signal is actually connected to clear the value of I_MAX in register 42. The value of I_MAX in the register 42 is an input to the cache / clean processing circuit 48. The structure of the cache clean processing circuit 48 can be selected by those skilled in the art from various alternative circuits provided with the function of the cache clean processing circuit 48, as will be understood from the description of FIGS.
[0013]
FIG. 4 shows a flow diagram of a method, generally designated by the reference numeral 50, which describes the preferred operation of the cache controller 28 with respect to the writing of the data array 32; This is achieved through the operation of the circuit block shown in FIG. Method 50 begins at step 52 where the value of I_MAX (in register 42) is cleared to zero. Note that in the preferred embodiment, this step can be accomplished by raising the CACHE_CLEAN signal. Further in this regard, it can be seen from the conclusion of the discussion of method 50 that the present embodiment provides improvements in relation to operation involving context switches. Although not shown, in practice step 52 may be an important role in the initialization of the data cache 12b in response to a response to the first context switch. Although context switches are terms well known to those skilled in the art, after describing these alternatives, it will be helpful for the reader of this specification to examine the meaning of context switches. Context switches occur in response to various events, such as external interrupts frequently executed by the operating system or the expiration of a clock timer. The fact that this switch is associated with a process change can be seen in the platform 10 or in other processor controlled systems where the various operations are divided into multiple processes. Each process is defined by various items (matters), which include the area of memory used by the process, process input / output mapping, process memory management such as address translation, and usually Often includes a process that characterizes the value stored in the general-purpose register. A context switch occurs when the current process is changed to a new process. For this reason, if you need to store information that describes each of these aspects of this latest process so that the next process (or some other process) will work correctly, If something is switched again, this information can be retrieved so that the process becomes the latest process again.
[0014]
Returning now to method 50, after step 52, flow continues to step 54. Step 54 represents that a write address is issued to the memory system that includes the data cache 12b. Accordingly, looking briefly at FIG. 1, the SDRAM 24 includes a data cache 12b at a lower level because the example of step 52 occurs when the core 12f issues an address to write data to the SDRAM 24. Note that it is higher in the memory system. The method 50 then continues from step 54 to step 56.
[0015]
Step 56 determines whether a hit occurs in the data cache 12b in response to the write address issued in step 54. If no cache hit occurs (ie, a cache miss occurs), the method 50 continues from step 56 to step 58. Conversely, method 50 continues from step 56 to step 60 when a cache hit occurs. Each of these alternative paths is described below.
[0016]
Focusing on the case of step 58 and recognizing that step 58 occurs in response to a cache miss, step 58 operates alone, as is well known in the cache technology. In particular, step 58 writes data to an address location in a storage circuit other than the data cache 12b. For example, on the platform 10, this writing is performed to an appropriate address in the SDRAM 24.
[0017]
Focusing on the case of step 60 executed when a cache hit occurs, step 60 determines whether the value of the current address index DA [11: 4] is greater than the value of I_MAX. Note that returning to FIG. 3 for some time, the operation of step 60 may be accomplished by the comparator 46. If the value of the address index DA [11: 4] is greater than the value of I_MAX, the method 50 continues from step 60 to step 62; otherwise, the method 50 proceeds to step 64, but first performs the operation of step 62. This is discussed below after consideration. Since the value of the address index DA [11: 4] is larger than the value of I_MAX, the already reached step 62 stores the latest address index DA [11: 4] as the new value of I_MAX. There are two things to note about this point. First, if step 60 is reached for the first time since the value of I_MAX is cleared in step 52, and the value of address index DA [11: 4] is not zero, step 60 steps through the method flow. Since it should have moved to 62, the value of I_MAX has increased to the latest address index. Second, returning to FIG. 3 again, step 62 is performed by the output of the comparator 46 and the control of the comparator 46 over the transfer gate 44. In particular, when executing step 60, if the comparator 46 determines that DA [11: 4] is equal to or greater than the value of I_MAX, DA [11: 4] is copied to the register 42, and DA [11: 4] becomes the new value of I_MAX, the output of the comparator 46 enables the transfer gate 44. The method 50 then continues from step 62 to step 64.
[0018]
Step 64 writes the data in question to the data array 32 at the address specified in step 54. Further, the dirty bit in the virtual tag array 30v and the cache line corresponding to the written data are set in a dirty state. The method 50 then continues from step 64 to step 66. Step 66 represents a wait state where the method 50 waits for one of two events, the two events being the issue of another write address or context switch. If another write address is issued, method 50 returns from step 66 to step 54. Those skilled in the art will then understand that if the preceding step occurs again and the index of the newly issued write address is greater than the latest value of I_MAX, the index will be the new value of I_MAX. I will. In practice, this loop operation will occur for a number of consecutive writes, and I_MAX will increase because the preceding step operates each time. Turning now to the effect of the latest context switch, method 50 continues with the preceding steps and continues from step 66 to step 68, so that the value of I_MAX at this time is the value after the last context switch and before the latest context switch. It should be understood from the foregoing that it represents the maximum value of the address index written to
[0019]
Step 68 represents a cache clean process, but as will be seen later, this cache clean process can dramatically improve performance and efficiency as opposed to conventional techniques. More specifically, step 68 represents the following. That is, step 70 occurs for the L loop from the L value equal to I_MAX until the L value equals 0, and each cache line with an address equal to L is cleaned. Represents. In other words, the value of L decreases starting at I_MAX, and consistently until it reaches zero, and decreases every time it comes to step 68, the flow continues with the cleaning operation of step 70, and the next iteration Therefore, the process returns to step 68 and loops. Turning to step 70, cache line cleaning is known to those skilled in the art, and the tag (or tags) of the line is evaluated to determine which data in the line is dirty. To be included. This operation in this embodiment is controlled by the cache clean processing circuit 48 of FIG. 3, which is enabled by the CACHE_CLEAN signal. This process determines whether the line contains dirty data, and if so, the data (or the entire line) is written to upper memory. Conversely, if a dirty bit (or multiple dirty bits) for a given line indicates that the entire line is clean, the dirty bit (or multiple dirty bits) Bit) is not written to the upper memory.
[0020]
From the above description, in particular, from the effect of I_MAX and steps 68 and 70, after the context switch, the data cache 12b is cleaned, but the cleaning process is written from the cache address 0 to before the context switch. It should be understood by those skilled in the art that only the top level cache address (ie, stored in I_MAX) is contrasted. This method will be better understood by showing an example. After step 52, assume that there are five consecutive cache writes for each index address 0, 2, 4, 6, and 8, and that there are context switches after these writes. Thus, the value of I_MAX at this time is equal to 8, and steps 68 and 70 are only cleaning the data array 32 from address 0 to address 32 in response to the context switch. Next, note that such operation is quite different from the prior art. In particular, in the prior art, the entire cache is cleaned in response to the context switch. Accordingly, each cache line is evaluated to determine whether the contents of each cache line are dirty, and if they are dirty, the contents of those dirty lines are written to the upper memory. It should be understood by those skilled in the art that this difference makes the embodiments of the present invention fairly efficient. For purposes of explanation, assume that the cache contains up to 255 addresses as a means of returning to the example of five consecutive addresses. In such a case, the prior art would use extra time to evaluate and clean each of the addresses from 9 to 255, but as long as there is one clock cycle for each addressable line. It is natural. In contrast, the preferred embodiment stops the cleaning operation at some point less than the entire cache, but the stop point in the embodiment just described is the highest address written before the context change. After the cleaning is completed (in the present example, the address is 8). Therefore, the total number of clock cycles required for the cleaning operation can be greatly reduced, and the overall power consumption is also reduced by this reduction in the number of clock cycles. Also, in an environment where context switches occur frequently, such as in an environment that actually occurs on the platform 10, the efficiency of the preferred embodiment is accumulated each time each context switch occurs. If there are only a few cache writes between context switches, this overall efficiency can be asserted to be very effective.
[0021]
Also note from the above discussion regarding step 68 that step 68 advances the cleaning process to address 0. This method is desirable because it is independent of the size of the cache. Therefore, in any case, for such a method, it is assumed that when the cleaning operation up to address 0 is completed, a line having dirty data is written to the main memory. However, it should be noted that because of this observation, two alternative methods can be used if the data at or near address 0 does not appear to change. Each of these two alternative methods is described below.
[0022]
In a first alternative to the I_MAX method discussed above, the value of the second address is determined to determine the lowest address index that causes a cache hit for a given context switch, This second value is used with the value. Therefore, if this second value is named I_MIN, this value is initially set to a large value (eg, the highest address of the cache) and the lowest value that will cause a cache hit during a given context switch. You may make it small to the value of an address index. Thus, by way of example, the top index address of the cache is 255, and there are five consecutive cache writes for each index address 8, 16, 24, 32 and 40, after which these context switches There shall be. In this example, initially I_MAX is equal to 0 and I_MIN is equal to 255. Based on 5 accesses, I_MAX increases with each access until it equals 40. On the other hand, the first access to address 8 reduces the value of I_MIN to the value 8, but the remaining accesses are index addresses higher than the updated value of I_MIN, so the remaining accesses Will not affect the value. To conclude this alternative method, step 70 is all lines between the I_MIN address and the I_MAX address, and the entire line containing these addresses is cleaned to be less than the total number of lines in the cache. Step 60 would be modified to clean some lines again.
[0023]
In a second alternative to the I_MAX method discussed above, different address values are established to determine the lowest address index that causes a cache hit for a given context switch, And used to clean up to the highest address of the cache. Simply put, this is the opposite of a process that uses the value of I_MAX. Again, if you decide to name this different address as I_MIN, initially set this value to a large value (for example, the highest address in the cache) and the lowest level that will cause a cache hit during a given context switch. The address index value may be reduced. However, when step 68 is executed, step 68 will be modified so that step 70 cleans all lines from the address value of I_MIN to the top of the cache, ie the top address of the cache. Let's go.
[0024]
Since the loop operation is limited from the viewpoint of the value of I_MAX, another embodiment as shown in FIG. 5 is included in the scope of the present invention. In this alternative method, shown as method 50a, the function of comparator 46 of FIG. 3 is not used, but is associated with the current context to determine the value of I_MAX at the time of the context switch. The address value held by the operating system is used. This difference is described below for step 72, but the remaining steps shown in FIG. 5 are the same as the steps shown in FIG.
[0025]
Referring to method 50a, steps 52 through 66 have been discussed above and will not be described in detail here. Thus, paying attention to step 72, step 72 sets the value of I_MAX, which here is set based on a value that is accessible during the execution of the operating system. In particular, certain operating systems maintain a maximum value for the cache line for a given context. Thus, satisfying the condition of step 66 will allow the operating system to use the highest address of the cache line corresponding to the context switch that is terminating (ie, from which the switch is occurring). Step 72 sets the value of I_MAX equal to the highest address of this cache line. Thus, if method 50a continues to step 68, provided that the highest address of this cache line is less than the total number of cache lines, the loop operation generated by step 68 and step 70 is again Since the data cache lines are cleaned, the number of lines to be cleaned in this cache is less than the total number of cache lines.
[0026]
It will be appreciated from the above description that the above embodiments reduce the number of clock cycles associated with cache cleaning operations after a context switch and provide various improvements over the prior art. Although this embodiment has been described in detail, it should be noted that in addition to the above teachings, various alternatives, modifications, or changes to the above description can be made without departing from the scope of the present invention. For example, the occurrence of a context switch in the preferred embodiment is to trigger a reset of I_MAX and limit the reset of I_MAX in response to a subsequent context switch, but some other When the first event occurs, the value of I_MAX is reset, and when the second event occurs, the upward adjustment of the value of I_MAX is finished, and then the last save is performed from the smallest address. One skilled in the art will be able to confirm cleaning the cache again to the I_MAX value given. As another example, FIGS. 4 and 5 show a general sequential method through flowcharts, but various circuits may be used to implement such operations, such as a state machine that performs these steps. It should be understood that the flow can go from each state to another alternative state, rather than being sequential as shown in this flow chart, as it can be used. As yet another example, data cache 18b has been used to illustrate various aspects, but many of the teachings of the present invention also apply to various other cache architectures. As a final example, platform 10 is for illustration only, platform 10 can be further modified, and many creative aspects are realized in another system having one or more cache memories. It should also be understood that this can be done. Accordingly, the foregoing description, these examples, and others that can be ascertained by one of ordinary skill in the art having learned the teachings of the present invention should serve to illustrate the scope of the invention as defined by the claims. It is.
[Brief description of the drawings]
FIG. 1 is a block diagram of a wireless data platform that can implement the present embodiment.
2 illustrates a block diagram of a cache architecture that can be used in the platform and other process devices of FIG.
FIG. 3 is a block diagram of portions of the cache controller of FIG. 2, which are used in the method of cleaning the cache of this preferred embodiment.
FIG. 4 is a flow diagram of a first embodiment that reduces the clock cycles required in connection with cache clean that occurs during the context switch of the general purpose processor of FIG. Is determined by the highest address written to the cache before the context switch.
FIG. 5 shows a flow diagram of a second embodiment for reducing the clock cycles required in connection with cache clean that occurs during the context switch of the general purpose processor of FIG. It is determined by the highest address that can be used by the operating system to write to the cache before the context switch.
[Explanation of symbols]
10 Data platform
12 processor
12a instruction cache
12b data cache
12c, 12d Instruction memory management unit (MMU)
12e input buffer circuit
12f operating core
14a DSP core
14b Peripheral device interface
16 DMA interface
18 DMA controller
18a FIFO
18b storage device
18c timer
20 Video or LCD controller
22 LCD or video
24 Main memory (synchronous DRAM)
24a, 26a Address bus
24b, 26b Data bus
24c, 26c Control bus
26 Flash memory
28 Cache control device
30av, 30bv virtual tag array memory plane
30v virtual tag array
32 Data array
32a, 32b Data array memory plane
34 LRU indicator array
36 Effectiveness Indicator Array
38a, 38b comparator
40a, 40b, 44 Transfer gate
42 Address register
46 Comparator
48 Cache Clean Processing Circuit
50 methods
64 Writing data to the cache memory and setting the state to dirty
68 Cleaning the selected line of the cache memory

Claims (11)

A method of operating a computing system including a cache memory having a predetermined number of cache lines, comprising:
First, for a plurality of write addresses, writing data to a location in the cache memory corresponding to each of the plurality of write addresses;
Second, cleaning a selected number of lines of the cache memory in response to a context switch by the computing system;
For the selected number of lines, the cleaning step comprises:
Evaluating a dirty indicator corresponding to the data in the line;
Copying the data from the line to another memory if the dirty indicator indicates that the data in the line is dirty;
The number of selected lines is less than a predetermined number of cache lines, and the method of operating the computing system comprises:
Holding a value in the address indicator;
According to each of the plurality of write addresses, an index indicating a position in the cache memory corresponding to the write address is compared with a value held in the address indicator, and the index is larger than a value held in the address indicator. In the case, the step of setting the value of the address indicator to the same value as the index, and when the comparison and setting for a plurality of write addresses is completed, the value of the address indicator indicates the latest value and is selected. The step of setting, wherein the number of defined lines corresponds to the latest value;
Method. A method of operating a computing system including a cache memory having a predetermined number of cache lines, comprising:
A step of comparing the index indicating the position of the cache line where the write data related to the write request is written with the value held in the address indicator each time the write data related to the write request is written to the cache memory; ,
As a result of the comparing step, when the index indicating the position of the cache line to which the write data is written is larger than the value held in the address indicator, the cache data to which the write data is written is written. Setting an index indicating the position of the line as a new value held in the address indicator;
Evaluating the cache line dirty indicator for all cache lines having a value greater than or equal to 0 and less than or equal to the value held in the address indicator when cleaning the cache memory; ,
Copying cache line data indicating that the evaluated dirty indicator is dirty to another memory;
Having a method. A computing system,
A cache memory having a predetermined number of cache lines;
A circuit for writing data to a location in the cache memory corresponding to each of the plurality of write addresses in response to the plurality of write addresses;
A circuit for cleaning a selected number of lines of the cache memory,
Circuitry for evaluating a dirty indicator corresponding to the data in the line for each of the selected number of lines;
A circuit for copying data from the line to another memory if the dirty indicator indicates that the data in the line is dirty;
A circuit for cleaning, comprising:
Including
The number of selected lines is less than a predetermined number of cache lines;
Furthermore, the circuit for cleaning is
An address indicator to hold the value;
In response to each of the plurality of write addresses, the index indicating the position in the cache memory corresponding to the write address and the value of the address indicator are compared, and when the index is smaller than the value held in the address indicator, A circuit for setting the value of the address indicator to the same value as the index, the circuit for setting indicating the value of the address indicator indicating the latest value when the comparison and setting for a plurality of write addresses are completed; ,
And the number of selected lines depends on the latest value,
Calculation system.   2. The method of claim 1, wherein the cleaning step includes cleaning all lines between the first address of the cache memory and the latest value.   5. The method of claim 4, wherein the first address is cache memory address 0.   4. The computing system according to claim 3, wherein the circuit for cleaning includes a circuit for cleaning all lines including the last address of the cache memory to the latest value. 7. The computing system according to claim 6 , wherein the last address is the highest address of the cache memory. A method of operating a computing system including a cache memory having a predetermined number of cache lines, comprising:
First, for a plurality of write addresses, writing data to a location in the cache memory corresponding to each of the plurality of write addresses;
Second, cleaning the selected number of lines in the cache memory, wherein the number of selected lines is less than the predetermined number of cache lines. Including
For each of the selected number of lines, the cleaning step comprises:
Evaluating a dirty indicator corresponding to the data in the line;
Copying the data from the line to another memory if the dirty indicator indicates that the data in the line is dirty;
Including
Further, the cleaning step includes
Holding a value in the first address indicator;
Holding a value in the second address indicator;
According to each of the plurality of write addresses, the index indicating the position in the cache memory corresponding to the write address is compared with the value of the first address indicator, and the index is held in the first address indicator. If the value is greater than the value, the step of setting the value of the first address indicator to the same value as the index, and when the comparison and setting for a plurality of write addresses is completed, the value of the first address indicator The setting step indicating the latest value of 1;
In accordance with each of the plurality of write addresses, the index indicating the position in the cache memory corresponding to the write address is compared with the value of the second address indicator, and the index is held in the second address indicator. And setting the second address indicator value to the same value as the index when the value is smaller than the value, and when the comparison and setting for a plurality of write addresses is completed, the second address indicator value is The setting step indicating the latest value of 2;
Including
The number of selected lines depends on the first and second latest values;
Method. The method of claim 8, wherein the step of cleaning, the method comprising cleaning all lines including from the second most recent value of the cache memory to the first most recent value. A computing system,
A cache memory having a predetermined number of cache lines;
A circuit for writing data to a location in the cache memory corresponding to each of the plurality of write addresses in response to the plurality of write addresses;
A circuit for cleaning a selected number of lines of the cache memory, wherein the number of selected lines is less than a predetermined number of cache lines and for each of the selected number of lines; And
A circuit for evaluating a dirty indicator corresponding to the data in the line;
A circuit for copying data from the line to another memory when the dirty indicator indicates that the data in the line is dirty;
A circuit for cleaning, comprising:
Including
Furthermore, the circuit for cleaning is
A first address indicator holding a value;
A second address indicator holding a value;
According to each of the plurality of write addresses, the index indicating the position in the cache memory corresponding to the write address is compared with the value of the first address indicator, and the index is held in the first address indicator. A circuit for setting the value of the first address indicator to the same value as the index when the value is larger than the value, and when the comparison and setting for a plurality of write addresses are completed, the value of the first address indicator The setting circuit in which indicates the first latest value;
In accordance with each of the plurality of write addresses, the index indicating the position in the cache memory corresponding to the write address is compared with the value of the second address indicator, and the index is held in the second address indicator. A circuit that sets the value of the second address indicator to the same value as the index when the value is smaller than the value, and when the comparison and setting for a plurality of write addresses is completed, the value of the second address indicator The setting circuit indicating the latest value of 2;
Including
The number of selected lines depends on the first and second latest values;
Calculation system. In computing system of claim 10, the circuit for the cleaning includes circuitry for cleaning all lines including the second most recent value of the cache memory to the first most recent value, calculated system.

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