JP4295234B2 - FIR type digital filter - Google Patents

Description

  The present invention relates to a technique for enabling a pipeline processing of operations with a simple hardware configuration in an FIR digital filter that performs a filtering process on a data string input in time series.

  Conventionally, an FIR digital filter 10 shown in FIG. 29 is used to perform various filtering processes on a data string.

  The FIR type digital filter 10 includes a data storage unit 11 and a product-sum operation unit 15.

  The data storage unit 11 includes latch circuits 12 (1) to 12 (N) connected in series in a plurality of N stages, and data d (0), d (1),. d (N−1) is sequentially shifted from the latch circuit 12 (1) at the first stage to the latch circuit 12 (N) at the last stage, and the latest N pieces of data are always stored.

  The product-sum operation unit 15 receives the data latched by the latch circuits 12 (1) to 12 (N) by the multipliers 16 (1) to 16 (N), respectively, and outputs the coefficient a output from the coefficient setting unit 17. (0), a (1),..., A (N−1) are multiplied, the sum of the multiplication results is obtained by the sum calculator 18 and the result D (i) is output as the processing result.

  The FIR digital filter 10 having this configuration performs a filtering process determined by the number of stages N (the number of delay stages) of the latch circuit 12 of the data storage unit 11 and the values of the coefficients a (0) to a (N−1).

  In the FIR type digital filter having such a basic configuration, when the number of delay stages is large, the number of multipliers 16 necessary for the product-sum operation increases accordingly, and there is a problem that the hardware becomes enormous.

  In order to solve this problem, a technique for performing pipeline processing for arithmetic processing is disclosed in the following Patent Document 1.

Japanese Patent No. 2513218

  In this document, a series of M latch circuits (registers) is set as a set, data (or input data) stored in the M latch circuits is selected in a time series by a multiplexer, and a coefficient is assigned to the selected data. The multiplication process is repeated M times to obtain the total value, which is input to the multiplexer together with the other sets of total values, and the total value is selected in time series to obtain the sum. Therefore, the number of multipliers is one per M latch circuits.

  However, in the configuration in which the data stored in the latch circuit is sequentially selected by the multiplexer as described above, M multiplexers are indispensable, and there is little effect in terms of simplifying the hardware configuration by reducing the number of multipliers.

An object of the present invention is to solve this problem and provide an FIR type digital filter that can be realized with a simpler hardware configuration , operates with a small number of clocks, and has high versatility .

In order to achieve the above object, the FIR type digital filter according to claim 1 of the present invention comprises:
Data storage unit (21) for storing the latest plural N data (N is an integer equal to 2 × m × p or 2 × m × p−1 for plural m and integer p) input in time series And a product-sum operation unit (40) that multiplies a predetermined number of N data stored in the data storage unit by a predetermined coefficient, and calculates and outputs the sum,
Wherein the data storage unit,
Memory blocks (22a to 22d) consisting of dual-port RAMs with the number of addresses m that can independently read and write data are connected in p stages in series, receive new data, and count from the newest of the N consecutive data. A first memory group (22) for storing m × p data,
Memory blocks (23a to 23d) consisting of dual-port RAMs with the number of addresses m that can independently read and write data are connected in p stages in series, receive data read from the first memory group, and receive the continuous N A second memory group (23) for storing m × p data counted from the oldest of the data,
A state in which data is stored in descending order in each memory block of one of the first memory group and the second memory group and data is stored in ascending order in each memory block of the other memory group is an initial state From the initial state, the first memory group and the second memory group are instructed to read while sequentially changing the addresses, and the consecutive N data are sequentially read in 2p divided into m times, Data reading means (30a) for outputting to the product-sum operation unit;
Each time data reading by the data reading means is performed a predetermined number of times, each memory block of the first memory group is instructed to write to the address of the oldest stored data, and each data at the address is transferred to the subsequent stage. And first data writing means (30b) for writing new data to the memory block in the first stage,
Each time data reading by the data reading means is performed a predetermined number of times, each memory block in the second memory group is instructed to write the read data to the address, and each data at the address is written to the subsequent stage. And a second data writing means (30c) for writing data read from the first memory group at the time of data writing by the first data writing means to the first-stage memory block,
Said data reading means, said first data writing means and the second data writing means, so that at the stage of the writing from an initial state of the m new data has been completed to switch the address to return to the initial state Composed of
The first data writing means immediately after the data reading means instructs to read by designating the address of the oldest data among the data stored in each memory block of the first memory group. It is configured to instruct writing to the corresponding address of each memory block of the memory group,
The second data writing means is configured such that each of the memories in the second memory group immediately after the data reading means designates an address of data stored in each memory block of the second memory group and instructs reading. It is configured to instruct to write data to the address of the block,
further,
A latch circuit (24) is provided between the first memory group and the second memory group;
The first data writing means writes the data read from the memory block at the last stage to the latch circuit when instructing writing to each memory block of the first memory group,
The second data writing means is configured to write the data stored in the latch circuit to the first-stage memory block when instructing writing to each memory block of the second memory group. It is characterized by.

Furthermore, FIR type digital filter according to claim 2 of the present invention,
Data storage unit (21) for storing the latest plural N data (N is an integer equal to 2 × m × p or 2 × m × p−1 for plural m and integer p) input in time series And a product-sum operation unit (40) that multiplies a predetermined number of N data stored in the data storage unit by a predetermined coefficient, and calculates and outputs the sum,
The data storage unit
Memory blocks (22a to 22d) consisting of dual-port RAMs with an address number m that can independently read and write data are connected in series in p stages, receive new data, and count from the newest of the N consecutive data. A first memory group (22) for storing m × p data,
Memory blocks (23a to 23d) consisting of dual-port RAMs with the number of addresses m that can independently read and write data are connected in p stages in series, receive data read from the first memory group, and receive the continuous N A second memory group (23) for storing m × p data counted from the oldest of the data,
A state in which data is stored in descending order in each memory block of one of the first memory group and the second memory group and data is stored in ascending order in each memory block of the other memory group is an initial state From the initial state, the first memory group and the second memory group are instructed to read while sequentially changing the addresses, and the consecutive N data are sequentially read in 2p divided into m times, Data reading means (30a) for outputting to the product-sum operation unit;
Each time data reading by the data reading means is performed a predetermined number of times, each memory block of the first memory group is instructed to write to the address of the oldest stored data, and each data at the address is transferred to the subsequent stage. And first data writing means (30b) for writing new data to the memory block in the first stage,
Each time the data reading by the data reading means is performed a predetermined number of times, the memory block of the second memory group is instructed to write the read data to the address, and each data at the address is written to the subsequent stage. And a second data writing means (30c) for writing data read from the first memory group at the time of data writing by the first data writing means to the first-stage memory block,
The data reading means, the first data writing means, and the second data writing means switch addresses so as to return to the initial state when m new data has been written from the initial state. Composed of
The first data writing means immediately after the data reading means instructs to read by designating the address of the oldest data among the data stored in each memory block of the first memory group. It is configured to instruct writing to the corresponding address of each memory block of the memory group,
The second data writing means is configured such that each of the memories in the second memory group immediately after the data reading means designates an address of data stored in each memory block of the second memory group and instructs reading. It is configured to instruct to write data to the address of the block,
further,
A buffer (25) comprising a dual port RAM having the same number of addresses m as the memory block, storing data read from the first memory group, and outputting the stored data to the second memory group;
A data switch (26) for selecting any of the data output from the last stage and at least the previous memory block among the memory blocks of the first memory group and inputting the selected data to the buffer;
When data is written by the first data writing means, data corresponding to an address specified for each memory block of the first memory group is selected by the data switch and input to the buffer, and the address is input to the buffer. When the data is written by the second data writing means, m new data from the data in the first memory block at the write target address is read from the buffer and the first memory is written. Buffer control means (30d) for input to the block, and
By the data reading means, the first data writing means, the second data writing means, and the buffer control means, the even tap type filter processing, the odd tap type filter processing, and the filter processing obtained by adding decimation processing thereto. It is characterized in that it can be adapted to both .

Furthermore, FIR type digital filter according to claim 3 of the present invention, in the FIR-type digital filter 請 Motomeko 2,
Of the data in the last memory block of the first memory group, the data in the last memory block in the first memory group and the data in the first memory block in the second memory group do not overlap. The state in which the oldest data is replaced with m older data is stored in the buffer as the initial state, and when the new data has been written, the initial state is restored and the time series continues. The buffer address and the switch are controlled so that one product-sum operation result of 2 × m × p data is obtained, and even tap 1 / m decimation type filter processing is performed . .

The FIR digital filter according to claim 4 of the present invention is the FIR digital filter according to claim 2 ,
The oldest data of the last memory block of the first memory group and the newest data of the first memory block of the second memory group are common, and the last memory block and the buffer of the first memory group The initial state is the state where the stored contents are the same, and when the writing of m new data is completed, the initial state is restored, and the product-sum operation of 2 × m × p−1 data continuous in time series An odd tap type filter process is performed by controlling the read address of the buffer and the switch so that m results are obtained .

The FIR digital filter according to claim 5 of the present invention is the FIR digital filter according to claim 2 ,
The oldest data in the last memory block of the first memory group and the newest data in the first memory block of the second memory group are common, and the data of the memory block in the last memory block of the first memory group Among them, the state in which the data obtained by replacing the oldest data with m new data is stored in the buffer is set as an initial state, and when the writing of m new data is completed, the initial state is restored, and time series Odd tap 1 / m decimation type filter processing is performed by controlling the read address and the switch of the buffer so that one product-sum operation result of 2 × m × p−1 continuous data is obtained. It is characterized by that.

Moreover, the FIR type digital filter of Claim 6 of this invention is the FIR type digital filter in any one of Claims 1-5,
The product-sum operation unit
A coefficient memory (41) for storing coefficients for multiplying the continuous N pieces of data;
Coefficient selection means (42) for selecting, from the coefficient memory, coefficients corresponding to the data read by the data reading means from the first memory group and the second memory group, respectively.
A product-sum operation is performed using the data read by the data reading means in increments of 2p and the coefficients selected by the coefficient selection means .
Furthermore, the FIR type digital filter according to claim 7 of the present invention is the FIR type digital filter according to claim 6,
In the coefficient memory, among the consecutive N pieces of data stored in the first memory group and the second memory group, each of the sets of data in which the rank counted from the newest and the rank counted from the oldest is the same. The coefficient of
The data reading means is configured to read data having a common coefficient from the first memory group and the second memory group by p pieces,
The product-sum operation unit adds data having common coefficients to each other by p adders (43a to 43d), and outputs the addition results to p multipliers (44a to 44d), respectively. And the sum of the multiplication results of the p multipliers is obtained by a sum calculator (45).

  As described above, the FIR type digital filter of the present invention forms the first memory group and the second memory group by the memory block composed of the dual port RAM, and one of the data groups is in descending order with respect to the address. Data that contains almost half of the data and reads the data from the first memory group and the second memory group, and data that includes new data, with the initial state being almost half of the data stored in ascending order with respect to the address. And the product-sum operation result for N consecutive data is obtained.

  Therefore, filtering processing can be performed with a simple hardware structure and simple address designation and read / write instruction for the memory group.

  Further, in the case where a latch circuit is provided between the first memory group and the second memory group, there are m stages without providing an extra clock for data update with respect to an input rate of 1 / m of the device speed. Filtering can be done with this pipeline processing.

  In addition, a buffer and data switch consisting of a dual port memory are provided so that buffer address control and input data selection can be performed by the buffer control means. Various decimation processing, correspondence to odd taps, even taps, etc. Easy to use and extremely versatile.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows a configuration of an FIR type digital filter 20 to which the present invention is applied.

  This FIR type digital filter 20 has the latest N pieces of time inputted in time series (N is equal to N = 2 × m × p or N = 2 × m × p−1 for a plurality of m and an integer p). The data d (i) to d (i + N-1), and the N data stored in the data storage unit 21 are multiplied by a predetermined coefficient, and the sum is calculated and output. And a product-sum operation unit 40.

  FIG. 1 shows a configuration example where N = 24, p = 4, and m = 3. In addition, the coefficients to be multiplied by the data are commonly multiplied by coefficients a (0) to a (N−1) that are respectively multiplied by N data in order from the oldest, and N data are commonly multiplied in order from the newest. (Even tap symmetric type).

  The data storage unit 21 includes a first memory group 22, a second memory group 23, and a controller 30.

  The first memory group 22 is configured by p (= 4) stages of serially connected memory blocks 22a to 22d composed of a dual port RAM with the number of addresses being m (= 3).

  The dual port RAM has two data ports so that data can be read and written independently. Here, one is for data writing and the other is for data reading, which are connected in series. . Further, the address ports of the memory blocks 22a to 22d are connected in parallel so that the address can be designated for reading and writing and common to all the memory blocks 22a to 22d, and the new data d is transferred to the first memory block. 22a is received.

  The second memory group 23 is a memory block 23a composed of a dual-port RAM, which has a data input port and an output port independently and has an address number m (= 3), just like the first memory group 22. .About.23d are connected in series in p (= 4) stages. In addition, the address ports of the memory blocks 23a to 23d are connected in parallel so that addresses can be designated for reading and writing and common to all the memory blocks 23a to 23d. Data output from the last memory block 22d of one memory group 22 is received.

  The controller 30 is for performing address designation and read / write control with respect to the first memory group 22 and the second memory group 23. The data read means 30a, the first data write means 30b, and the second data write means. 30c.

  The data reading means 30a stores data in descending order in each memory block of one of the first memory group 22 and the second memory group 23 (first memory group 22 in this example), and the other memory group (this example In this case, the state in which data is stored in ascending order in each memory block of the second memory group 23) is set as an initial state, and from this initial state, addresses common to the first memory group 22 and the second memory group 23 are set in a predetermined order. Reading is instructed while changing, and the consecutive N data are sequentially read out in 2p divided into m times and output to the product-sum operation unit 40, and the read data is output to the subsequent memory block.

  As described above, since the coefficient used for the product-sum operation is an even-tap symmetric type, the data reading unit 30a transfers the data having the same coefficient from the first memory group 22 and the second memory group 23 p times m times. Read separately.

  The first data writing unit 30b stores the oldest data stored in each of the memory blocks 22a to 22d of the first memory group 22 every time the data reading unit 30a reads data K a predetermined number of times. Is written, and each data at the address is written and shifted to the subsequent stage, and new data d (24) is written to the memory block 22a at the first stage. In this embodiment, the case where K = m will be described.

  Further, the second data writing means 30c is set to the address of the read data among the memory blocks 23a to 23d of the second memory group 23 every time the data reading means 30a reads the data K a predetermined number of times. Is written, and each data at the address is written and shifted to the subsequent stage, and is read from the first memory group 22 when the first data writing means 30b updates the data in the first stage memory block 23a. Written data.

  The data reading means 30a switches the address so as to return to the initial state at the stage where the reading of N pieces of continuous data and the writing of m pieces of new data are completed from the initial state.

  On the other hand, the product-sum operation unit 40 includes a coefficient memory 41, coefficient selection means 42, p adders 43 a to 43 d, p multipliers 44 a to 44 d, and a sum calculator 45.

  The coefficient memory 41 stores N / 2 (= 12) coefficients a (0) to a (11) for multiplying N consecutive data, and the coefficient selecting means 42 is a data reading means 30a. The coefficient corresponding to the data read out by is selectively read out from the coefficient memory 41 and output to the multipliers 44a to 44d.

  The adders 43a to 43d add data having common coefficients, and output the addition results to the multipliers 44a to 44d, respectively. The multiplication results are input to the sum calculator 45. The sum calculator 45 obtains the sum of the multiplication results that are input m times in increments of p, and outputs this sum as one processing result D for N consecutive data.

Next, the operation of the FIR type digital filter 20 having the above configuration will be described.
As an initial state, as shown in FIG. 1, 24 input data d (0) to d (23) are divided into 8 sets of 3 pieces in the input order, and the old 4 sets are divided into the first set. 2 stored in four memory blocks 23a to 23d of the memory group 23 in ascending order of addresses, and the new four sets are stored in the four memory blocks 22a to 22d of the first memory group 22 in descending order of addresses. And

  From this state, the data reading means 30a adds the address Aa = 2 to the first memory group 22 and the address Ab = 2 to the second memory group 23 as shown in FIG. Four pieces of data d (2) to d (11) and d (12) to d (21) are read out.

  Among the eight data read out, data that have the same rank from the oldest and the new one, [d (2), d (21)], [d (5), d ( 18)], [d (8), d (15)], [d (11), d (12)] are added by the product-sum operation unit 40, and a common coefficient a (2), a (5), a (8), and a (11) are multiplied, and the sum S1 of the multiplication results is obtained by the following calculation.

S1 = a (2). [D (2) + d (21)]
+ A (5). [D (5) + d (18)]
+ A (8). [D (8) + d (15)]
+ A (11). [D (11) + d (12)]

Next, the data reading means 30a designates the address Aa = 1 for the first memory group 22 and the address Ab = 1 for the second memory group 23 as shown in FIG. Four sets of data d (1) to d (10) and d (13) to d (22) are read out.
Among the eight data read out, data that have the same rank from the oldest and the new one from the new one, [d (1), d (22)], [d (4), d ( 19)], [d (7), d (16)], [d (10), d (13)] are added by the product-sum operation unit 40, and the coefficient a (1), a (4), a (7), and a (10) are multiplied, and a sum S2 of those multiplication results and the previous sum S1 is obtained by the following calculation.

S2 = a (1) · [d (1) + d (22)]
+ A (4). [D (4) + d (19)]
+ A (7). [D (7) + d (16)]
+ A (10). [D (10) + d (13)]
+ S1

  Further, as shown in FIG. 2 (c), the address Aa = 1 is designated for the first memory group 22, and the address Ab = 1 is designated for the second memory group 23. Data d (0) to d (9) and d (14) to d (23) are read.

  Among the eight data read out, data having the same rank order from the oldest and the newest rank, [d (0), d (23)], [d (3), d ( 20)], [d (6), d (17)], [d (9), d (14)] are added by the product-sum operation unit 40, and the coefficient a (0), a (3), a (6), and a (9) are multiplied and obtained by the next calculation of the sum S3 of the multiplication results and the previous sum S2.

S3 = a (0) · [d (0) + d (23)]
+ A (3). [D (3) + d (20)]
+ A (6). [D (6) + d (17)]
+ A (9) · [d (9) + d (14)]
+ S2

  The final sum S3 obtained by this arithmetic processing is output as the first processing result D (0) obtained for N consecutive data d (0) to d (23).

  The above-described arithmetic processing of the sums S1 to S3 is performed by pipeline processing, but after the third set of data has been read by the data reading means 30a, update processing with newly input data d (24) is executed. Is done.

  That is, as shown in FIG. 3, the address Aa = 2 where the oldest data is stored is designated as the update target for each of the memory blocks 22a to 22d of the first memory group 22 by the data reading means 30a. Also for each memory block 23a to 23d of the second memory group 23, the address Aa = 0 in which the oldest data is stored is designated as an update target, and a read instruction is given immediately thereafter (within a clock cycle). The first data writing means 30b and the second data writing means 30c are instructed to write data.

  Since each memory block is composed of a dual port RAM, if a write instruction is given immediately after a read instruction as described above, the stored data when the read instruction is issued is output from the output port. The data written from the input port is held internally, and is output to the output port when the next read instruction is issued.

By this processing, new input data d (24) is written to the memory block 22a, data d (21) is written to the memory block 22b, data d (18) is written to the memory block 22c, and data d (15 ) Is written to the memory block 22d.
Data d (12) is written to the memory block 23a of the second memory group 23, data d (9) is written to the memory block 23b, data d (6) is written to the memory block 23c, and data d ( 3) is written into the memory block 23d.

  Each written data can be read when each memory block is instructed to be read next.

  After the data writing process is completed, the data reading process by the data reading unit 30a is performed again.

  That is, as shown in FIG. 4 (a), the addresses Aa = 1 and Ab = 0 are switched, the read instruction is given to the first memory group 22 and the second memory group 23, and eight data d (3), d (6), d (9), d (12), d (13), d (16), d (19), d (22) are read out and the next sum S1 is obtained in the same manner as described above.

S1 = a (2). [D (3) + d (22)]
+ A (5). [D (6) + d (19)]
+ A (8). [D (9) + d (16)]
+ A (11). [D (12) + d (13)]

  Next, as shown in FIG. 4B, the address Aa = 0 and Ab = 2 are switched, the read instruction is given to the first memory group 22 and the second memory group 23, and the eight data d (2) , D (5), d (8), d (11), d (14), d (17), d (20), d (23) are read out, and the next sum S2 is obtained in the same manner as described above.

S2 = a (1). [D (2) + d (23)]
+ A (4). [D (5) + d (20)]
+ A (7). [D (8) + d (17)]
+ A (10). [D (11) + d (14)]
+ S1

  Further, as shown in FIG. 4C, the address Aa = 2 and the address Ab = 1 are switched, the read instruction is given to the first memory group 22 and the second memory group 23, and eight data d (1) , D (4), d (7), d (10), d (15), d (18), d (21), d (24) are read out and the next sum S3 is obtained in the same manner as described above.

S3 = a (0) · [d (1) + d (24)]
+ A (3). [D (4) + d (21)]
+ A (6). [D (7) + d (18)]
+ A (9). [D (10) + d (15)]
+ S2

  The final sum S3 obtained by this arithmetic processing is output as the second processing result D (1) obtained by inputting the data d (24).

  Next, for the next data update, as shown in FIG. 5, the address Aa = 1 and the address Ab = 1 storing the oldest data at this time are designated as update targets, and reading is instructed. Immediately thereafter, writing is instructed.

  By this processing, four data d (25) to d (16) including new input data d (25) are written in the memory blocks 22a to 22d, respectively, and the four data d (13) to d (4) are written. The data is written in the memory blocks 23a to 23d, respectively.

  From this state, the data reading means 30a performs the data reading process for each 8 pieces of data three times as described above to obtain the third processing result D (2). After the third data reading is completed, the data update by the next new data d (26) is performed with the addresses Aa = 0 and Ab = 2 designated as shown in FIG. Is made.

  The state of FIG. 6 is equivalent to the initial state of FIG. 1 although the data values are different, and the processing result D (i) is obtained for each new data by repeating the above processing.

  As described above, the FIR type digital filter 20 according to the embodiment is not a conventional latch circuit as an element for storing input data, but includes a dual-port RAM and a plurality of m (m = 3 in this embodiment). The first memory group 22 and the second memory group 23 are constituted by memory blocks capable of storing data, and the data read process and the data update process for new input data are performed by controlling the addresses.

  This eliminates the need for a multiplexer, and the number of multipliers is only one in m (one in every 2m in the even-tap symmetric type), so that the hardware configuration can be greatly simplified.

  In addition, since the address designation for each memory block of the first memory group 22 and the second memory group 23 can be performed in common, complicated address switching is unnecessary and the control itself can be easily performed.

  In the case of an asymmetric type with even taps, as in the FIR type digital filter 50 shown in FIG. 7, the adder is omitted and multipliers 44e to 44h are added, and each data is multiplied by a coefficient, and the multiplication is performed. Find the sum of the results. In this case, since it is not necessary to consider the combination of the data of the common coefficients for the data reading by the data reading means 30a, the address designation for the first memory group 22 and the second memory group 23 can be arbitrarily performed in a combination that does not overlap. Good. The configuration of the product-sum operation unit 40 can be applied even in the case of coefficient asymmetry in each embodiment described later.

  In the above-described embodiment, data writing is performed all at once at a timing (clock) different from the reading of the data to be calculated. However, like the FIR digital filter 60 shown in FIG. By inserting a latch circuit 24 for storing one piece of data between the memory group 23, data writing can be performed at the same clock timing as data reading.

  That is, when the data storage state shown in FIG. 8 is set to the initial state, and the new data d (24) is input as shown in FIG. 9A, the data reading means 30a causes the first memory group. 22 designates addresses Aa = 2 and Ab = 2 to instruct reading, and immediately after that, the first data writing means 30b instructs writing.

  As a result of this processing, the four data d (12) to d (21), d (2), which are the sets of additions stored immediately before the write instruction, are sent from the first memory group 22 and the second memory group 23. ) To d (11) are read out, and similarly to the above, the product-sum operation unit 40 adds the data of the common coefficients and multiplies the coefficients to calculate the sum.

  In addition, four data d (24) to d (15) including new data are written to the address Aa = 2 of each of the memory blocks 22a to 22d of the first memory group 22, respectively. Data d (12) output from the memory block 22d is stored. Note that the latch circuit 24 latches input data by a signal instructing the writing of the first data writing means 30b.

  Next, as shown in FIG. 9B, the address Aa = 1 and Ab = 1 are designated by the data reading means 30a, the data reading is instructed, and four pieces of data d (13 ) To d (22) and d (1) to d (10) are read out, and similarly to the above, the product-sum operation unit 40 adds the data of the common coefficients, and multiplies the coefficients to calculate the sum. Is done.

  Subsequently, as shown in FIG. 9C, the address Aa = 0 and Ab = 0 are designated by the data reading unit 30a, the data reading is instructed, and immediately after that, the second data writing unit 30c writes the data. Is instructed.

  By this processing, four pieces of data d (14) to d (23) and d (0) to d (9) that are a set of additions are read out, and are similarly shared by the product-sum operation unit 40 as described above. The coefficient data are added together, and the coefficients are multiplied to calculate the sum.

  Data d (9) to d (3) of the previous memory blocks 23a to 23c are written in the memory blocks 23b to 23d of the second memory group 23, respectively, and the latch circuit 24 is stored in the first memory block 23a. The data d (12) stored in is written.

  N consecutive data d (0) to d (23) are read by the above three times of data reading, and the data update for the new data d (24) is performed.

  Next, as shown in FIG. 10 (a), when new data d (25) is input, the data reading means 30a designates addresses Aa = 1 and Ab = 0 and instructs reading. Immediately after that, writing is instructed by the first data writing means 30b.

  As a result of this processing, the four data d (13) to d (22), d (3), which are the sets of additions stored immediately before the write instruction, are sent from the first memory group 22 and the second memory group 23. ) To d (12) are read out, and, similarly to the above, the product-sum operation unit 40 adds the data of the common coefficients and multiplies the coefficients to calculate the sum.

  Also, four data d (25) to d (16) including new data are respectively written in the address Aa = 2 of each of the memory blocks 22a to 22d of the first memory group 22, and the data d is stored in the latch circuit 24. (13) is stored.

  Next, as shown in FIG. 10B, the address Aa = 0 and Ab = 2 are designated by the data reading means 30a, the data reading is instructed, and four pieces of data d (14) each forming a set of additions are given. ) To d (23) and d (2) to d (11) are read out, and similarly to the above, the product-sum operation unit 40 adds the data of the common coefficients and multiplies the coefficients to calculate the sum. Is done.

  Subsequently, as shown in FIG. 10C, the address Aa = 2 and Ab = 1 are designated by the data reading means 30a, the data reading is instructed, and immediately after that, the second data writing means 30c writes the data. Is instructed.

  By this processing, four pieces of data d (15) to d (24) and d (1) to d (10) that are a set of additions are read out. The coefficient data are added together, and the coefficients are multiplied to calculate the sum.

  Further, data d (10) to d (4) of the preceding memory blocks 23a to 23c are written in the memory blocks 23b to 23d of the second memory group 23, respectively, and the latch circuit 24 is stored in the first memory block 23a. The data d (13) stored in is written.

  N consecutive data d (1) to d (24) are read by the above three times of data reading, and the data update for the new data d (25) is performed.

  Next, as shown in FIG. 11 (a), when new data d (26) is input, the data reading means 30a designates addresses Aa = 0 and Ab = 1 to instruct reading. Immediately after that, writing is instructed by the first data writing means 30b.

  As a result of this processing, the four data d (14) to d (23), d (4), which are the sets of additions stored immediately before the write instruction, are sent from the first memory group 22 and the second memory group 23. ) To d (13) are read out, and similarly to the above, the product-sum operation unit 40 adds the data of the common coefficients and multiplies the coefficients to calculate the sum.

  In addition, four data d (26) to d (17) including new data are respectively written in the address Aa = 0 of each of the memory blocks 22a to 22d of the first memory group 22, and the data d is stored in the latch circuit 24. (14) is stored.

  Next, as shown in FIG. 11B, the address Aa = 2 and Ab = 0 are designated by the data reading means 30a, the data reading is instructed, and four pieces of data d (15 ) To d (24) and d (3) to d (12) are read out, and similarly to the above, the product-sum operation unit 40 adds the data of the common coefficients, and multiplies the coefficients to calculate the sum. Is done.

  Subsequently, as shown in FIG. 11 (c), the address Aa = 1 and Ab = 2 are designated by the data reading unit 30a, the data reading is instructed, and immediately after that, the second data writing unit 30c performs the writing. Is instructed.

  Through this processing, four pieces of data d (16) to d (25) and d (2) to d (11), each of which is a set of additions, are read out and shared by the product-sum operation unit 40 in the same manner as described above. The coefficient data are added together, and the coefficients are multiplied to calculate the sum.

  Data d (11) to d (5) of the previous memory blocks 23a to 23c are written in the memory blocks 23b to 23d of the second memory group 23, respectively, and the latch circuit 24 is stored in the first memory block 23a. The data d (14) stored in is written.

  N consecutive data d (2) to d (25) are read by the above three times of data reading, and the data update for the new data d (26) is performed.

  Thus, by providing the latch circuit 24, data can be read and written within the same clock, an extra clock for data update is not required, and the input rate is 1/3 of the device speed. Data can be filtered. When the coefficient is an even-tap asymmetric type, as described above, there is no need to consider the combination of addition, so the product-sum operation unit 40 is changed as shown in FIG. Data can be read from 23 in the order of arbitrary addresses.

  In the above embodiment, every time one new data is input, one product-sum operation result for consecutive N data including the new data is output, that is, the operation when the input rate and the output rate are equal. However, when performing so-called decimation processing that lowers the output rate with respect to the input rate, or when performing odd tap processing, the latch circuit 24 is similar to the FIR digital filter 70 shown in FIG. Instead of this, a buffer 25 composed of a dual-port RAM having the same configuration as each memory block constituting the first memory group 22 and the second memory group 23 is provided. A data switch 26 is provided for selectively inputting either the output of the last-stage memory block 22d or the preceding-stage (third-stage) memory block 22c. It controls the buffer 25 and the data switch 26 by the buffer control means 30d of the controller 30.

  The buffer control means 30d selects the data corresponding to the address designated for each memory block of the first memory group 22 at the time of data writing by the first data writing means 30b by the data switch 26 and inputs it to the buffer 25, and The address is designated in the buffer 25 to instruct writing. In addition, when data is written by the second data writing means 30c, m pieces (three in this case) of new data from the data in the first stage memory block at the address to be written are read from the buffer 25 and the first stage memory block 23a is read out. To enter.

  Next, the operation when the 1/3 decimation process is performed by the FIR digital filter 70 having this configuration will be described.

  In this case, the data storage state shown in FIG. 12 is set as an initial state, and address 2 is designated from the initial state to the first memory group 22 and the second memory group 23 as shown in FIG. The read address 0 and the write address 2 are designated for the buffer 25, and the first memory group 22, the second memory group 23 and the buffer 25 are instructed to read.

  As a result, four pieces of data d (12) to d (21) and d (2) to d (11), each of which is a set of additions, are read out and processed.

  Immediately after the read instruction, a write instruction is issued to the first memory group 22, the second memory group 23, and the buffer 25.

  As a result, four data d (15) to d (24) including new data are respectively written at address 2 of each memory block of the first memory group 22, and each memory block of the second memory group 23 is written. Four data d (5) to d (14) including data stored in the buffer 25 are respectively written in the address 2, and the last memory of the first memory group 22 is written in the address 2 of the buffer 25. Data d (12) read from the block 22d is written.

  Next, as shown in FIG. 13B, address 1 is designated for the first memory group 22 and the second memory group 23, and read address 1 and write address 1 are designated for the buffer 25. The first memory group 22, the second memory group 23, and the buffer 25 are instructed to read.

  As a result, four pieces of data d (13) to d (22) and d (1) to d (10), which are a set of additions, are read out and processed.

  Immediately after the read instruction, a write instruction is issued to the first memory group 22, the second memory group 23, and the buffer 25.

  As a result, four data d (16) to d (25) including new data are respectively written in the address 1 of each memory block of the first memory group 22, and each memory block of the second memory group 23 is written. Four data d (4) to d (13) including the data stored in the buffer 25 are written to the address 1, respectively, and the third stage of the first memory group 22 is written to the address 1 of the buffer 25. Data d (16) read from the memory block 22c is written.

  Finally, as shown in FIG. 13C, the address 0 is designated for the first memory group 22 and the second memory group 23, and the read address 2 and the write address 0 are designated for the buffer 25. The first memory group 22, the second memory group 23, and the buffer 25 are instructed to read.

  As a result, four pieces of data d (14) to d (23) and d (0) to d (9), which are a set of additions, are read out and processed.

  Immediately after the read instruction, a write instruction is issued to the first memory group 22, the second memory group 23, and the buffer 25.

  As a result, four data d (17) to d (26) including new data are respectively written at address 0 of each memory block in the first memory group 22, and each memory block in the second memory group 23 is written. The four data d (3) to d (12) including the data stored in the buffer 25 are respectively written in the address 0, and the third stage of the first memory group 22 is stored in the address 0 of the buffer 25. Data d (17) read from the memory block 22c is written.

  Through the above three reading processes, a product-sum operation result for N (even) continuous data d (0) to d (23) is obtained. Further, although the state of FIG. 13C is equal to the data array of FIG. 12, the stored N data are d (3) to d (26). As a result, a product-sum operation result for the data d (3) to d (26) is obtained.

  That is, the product-sum operation results for the consecutive N pieces of data d (1) to d (24) and d (2) to d (25) are omitted, and the rate is once every three times when new data is input. This is a 1/3 decimation process in which one product-sum operation result is obtained.

  Next, an operation in the case of performing odd-tap symmetric processing in the FIR digital filter 70 having the above configuration will be described.

  As shown in FIG. 14A, the first memory group 22 stores the newer 12 pieces of data d (11) to d (22) including the odd-numbered intermediate data d (11). The two memory groups 23 store the twelve old data d (0) to d (11) including the intermediate data d (11), and the buffer 25 stores the last memory block of the first memory group 22. It is assumed that the same data d (11) to d (13) as 22d are stored, and this is the initial state.

  From this initial state, the controller 30 designates the address 2 to the first memory group 22 and the second memory group 23 and instructs the buffer 25 to read data, as shown in FIG. Even after that, the address 22 is designated, and immediately after that, the first memory group 22 and the buffer 25 are instructed to write data.

  As a result, similarly to the above, four pieces of data d (11) to d (20) and d (2) to d (11) that are a set of additions are read and output to the product-sum operation unit 40. Arithmetic processing is performed.

  Note that the intermediate data d (11) read from the first memory group 22 and the second memory group 23 is multiplied in the product-sum operation unit 40 by 1/2 of the original coefficient. The

  Also, four data d (14) to d (23) including new data are respectively written in the address 2 of each memory block of the first memory group 22, and the data switch 26 is written in the address 2 of the buffer 25. The data d (14) of the memory block 22c of the first memory group 22 is written via

  Next, as shown in FIG. 15 (a), address 1 is designated for the first memory group 22 and the second memory group 23, and four pieces of data d (12) to d (12) that form a set of additions. 21), d (1) to d (10) are read out and output to the product-sum operation unit 40 for arithmetic processing.

  Further, as shown in FIG. 15B, the address 0 is designated for the first memory group 22 and the second memory group 23, and four pieces of data d (13) to d (22) that form a set of additions. ), D (0) to d (9) are read out, output to the product-sum operation unit 40 and processed, and all N (odd) pieces of continuous data d (0) to d (22) are processed. The product-sum operation result is obtained.

  Further, at the time of reading data three times, an address 1 is designated for the buffer 25 and a read instruction is given, and a write instruction for the second memory group 23 is given immediately thereafter. As a result, data d (3) to d (12) are written to address 0 of each memory block of the second memory group 23, respectively.

  Next, as shown in FIG. 16A, address 1 is designated for the first memory group 22, address 0 is designated for the second memory group 23, and data read is instructed. 1 is specified.

  As a result, the four pieces of data d (12) to d (21) and d (3) to d (12), which are the sets of additions, are read out and output to the product-sum operation unit 40 for arithmetic processing. .

  At this time, for the intermediate data d (12) read from the first memory group 22 and the second memory group 23, the product-sum operation unit 40 uses the original coefficient of 1 for the addition result as described above. / 2 is multiplied.

  In addition, four data d (15) to d (24) including new data are written in the address 1 of each memory block of the first memory group 22, and the data switch 26 is set in the address 1 of the buffer 25. Thus, the data d (15) of the third-stage memory block 22c of the first memory group 22 is written.

  Subsequently, as shown in FIG. 16 (b), address 0 is designated for the first memory group 22, and address 2 is designated for the second memory group 23, and four pieces of data d each forming a set of additions. (13) to d (22) and d (2) to d (11) are read and output to the product-sum operation unit 40 for arithmetic processing.

  Further, as shown in FIG. 17A, the address d is designated for the first memory group 22 and the address 1 is designated for the second memory group 23, and data d (14) to d which are added groups. (23), d (1) to d (10) are read out, output to the product-sum operation unit 40 and processed, and all N (odd) consecutive data d (1) to d (23) are obtained. ) Is obtained.

  At this time, the address 0 is designated and read from the buffer 25, and immediately after that, a write instruction to the second memory group 23 is given.

  As a result, four pieces of data d (4) to d (13) are written to address 1 of each memory block in the second memory group 23.

  Next, as shown in FIG. 17B, the address 0 is specified for the first memory group 22, the address 1 is specified for the second memory group 23, and data reading is instructed. Address 0 is designated for the first memory group, and immediately after that, writing to the first memory group 22 and the buffer 25 is instructed.

  As a result, four pieces of data d (13) to d (22) and d (4) to d (13) as a set of addition are read from the first memory group 22 and the second memory group 23. Are processed. Also, four data d (16) to d (25) including new input data d (25) are written at address 0 of each memory block of the first memory group 22, and address 0 of the buffer 25 is written at address 0 of the buffer 25. The data d (16) of the memory block 22c of the first memory group 22 is written through the data switch 26.

  Subsequently, as shown in FIG. 18A, the address 2 is designated for the first memory group 22 and the address 0 is designated for the second memory group 23, so that each of four pieces of data d forming an addition set is obtained. (14) to d (23) and d (3) to d (12) are read and output to the product-sum operation unit 40 for arithmetic processing.

  Further, as shown in FIG. 18B, the address 1 is designated for the first memory group 22 and the address 2 is designated for the second memory group 23, and four pieces of data d (4) each forming a set of additions. 15) to d (24) and d (2) to d (11) are read out and output to the product-sum operation unit 40 for arithmetic processing, and all N (odd) consecutive data d (2) The product-sum operation result for ˜d (24) is obtained.

At the time of reading, address 0 is designated for the buffer 25 and a reading instruction is given. Immediately thereafter, writing of data is instructed to the second memory group 23.
As a result, four pieces of data d (5) to d (14) are written in the address 2 of each memory block of the second memory group 23, respectively.

  The data arrangement at this time is the same as the initial state of FIG. 14A, and by repeating the above operation, for the data input at a rate of 1/3 of the device speed, odd taps are performed. Symmetric filtering can be performed without delay.

  When the 1/3 decimation processing is performed with the odd tap symmetric type, the first memory group 22 and the second memory group are started from the initial state shown in FIG. 19A as shown in FIG. 19B. 23 and the buffer 25 are designated with an address 2 and reading / writing is instructed in the same manner as described above, whereby four pieces of data d (11) to d (20) and d (2) to d ( 11) Read and write for update.

  Next, as shown in FIG. 20A, address 1 is designated for the first memory group 22 and second memory group 23, read address 0 is designated for the buffer 25, readout is instructed, and a set of addition 4 The individual data d (12) to d (21) and d (1) to d (10) are read, and the first memory group 22, the second memory group 23, and the buffer 25 (write address 1) are read. Instruct to write, and write for update.

  Finally, as shown in FIG. 20B, the address 0 is designated for the first memory group 22 and the second memory group 23, the read address 1 is designated for the buffer 25, the readout is instructed, and the set of addition 4 The individual data d (13) to d (22) and d (0) to d (9) are read out, and the first memory group 22, the second memory group 23, and the buffer 25 (write address 0) are read. Instruct to write, and write for update.

  The state shown in FIG. 20B is equivalent to the initial state shown in FIG. 19A. Hereinafter, by repeating this process, an odd-tap symmetric 1/3 decimation filtering process is performed.

  In each of the above embodiments, the number of addresses m of each memory block is 3, but this does not limit the present invention. For example, as shown in FIG. If it is 6, various decimation processes can be performed with a larger number of taps.

  In this case, the data switch 26 is configured so that data read from the second-stage memory block 22b of the first memory group 22 can also be selected.

  FIG. 21A shows an initial state when the data input rate is 1/3 of the apparatus speed and 48 taps and 1/2 decimation processing is performed.

  In this case, in the four memory blocks of the first memory group 22, the newer 24 data d (24) to d (47) out of 48 data are stored in descending order by six, In the four memory blocks of the two memory group 23, the older 24 data d (0) to d (23) are stored in ascending order by six, and the addresses 0, 2, and 4 of the buffer 25 are stored in the addresses 0, 2, and 4, respectively. The data d (29), d (27), and d (25) of the addresses 0, 2, and 4 of the last memory block of the first memory group 22 are stored.

  Starting from this initial state, as shown in FIG. 21B, data d (24) to d (42) and d (5) to d (23) at address 5 in the first memory group 22 and the second memory group 23. ) Is read and product-sum operation processing is performed, and immediately after that, writing to the first memory group 22 and the buffer 25 is instructed, and data d (48) including new data d (48) at address 5 of the first memory group 22 is instructed. 30) to d (48) are written, and data d (24) is written to address 5 of the buffer 25 (step 1).

  Next, as shown in FIG. 22A, the data d (26) to d (44) and d (3) to d (21) at the address 3 of the first memory group 22 and the second memory group 23 are read. The sum of products is processed (step 2).

  In the next step, as shown in FIG. 22B, the data d (28) to d (46) and d (1) to d (19) of the address 1 of the first memory group 22 and the second memory group 23 are displayed. ) Is read and sum-of-products calculation processing is performed. At this time, data d (7) to d (25) including the data of the address 4 of the buffer 25 are written to the address 1 of the second memory group 23 (step 3).

  Next, as shown in FIG. 23A, the data d (25) to d (43) and d (4) to d (22) at the address 4 of the first memory group 22 and the second memory group 23 are read. Then, the product-sum operation process is performed, and immediately after that, writing to the first memory group 22 and the buffer 25 is instructed, and the data d (31) to d including the new data d (49) at the address 4 of the first memory group 22 d (49) is written, and data d (31) is written to address 4 of the buffer 25 (step 4).

  Next, as shown in FIG. 23B, the data d (27) to d (45) and d (2) to d (20) at the address 2 of the first memory group 22 and the second memory group 23 are read. The sum of products is processed (step 5).

  Subsequently, as shown in FIG. 24, the data d (29) to d (47) and d (0) to d (18) at the address 0 of the first memory group 22 and the second memory group 23 are read out and summed up. At this time, data d (6) to d (24) including data at address 5 in the buffer 25 are written into address 0 in the second memory group 23 (step 6).

  By reading the data six times, the reading of the 48 data d (0) to d (47) stored in the initial state is completed, and the product-sum operation result for the 48 data is obtained.

Hereinafter, although not shown, the following processing is performed.
(Step 7) Reading (data sum operation) of each data of the address 3 of the first memory group 22 and the address 1 of the second memory group 23, which is a set of addition, and new data d (50) for the first memory group 22 Write data to be included and write data d (26) to address 3 of the buffer 25.

  (Step 8) Reading each data of the address 1 of the first memory group 22 and the address 5 of the second memory group 23, which is a set of addition (product-sum operation).

  (Step 9) Reading (data sum operation) of each data of the address 5 of the first memory group 22 and the address 3 of the second memory group 23 and the data of the address 2 of the buffer 25 with respect to the second memory group 23 as a set of addition Write data including d (27).

(Step 10) Reading (data sum operation) each data of the address 2 of the first memory group 22 and the address 0 of the second memory group 23, which is a set of addition, and new data d (51) for the first memory group 22 Write data to be included and write data d (33) to address 2 of the buffer 25.
(Step 11) Reading each data of the address 0 of the first memory group 22 and the address 4 of the second memory group 23, which is a set of addition (product-sum operation).

  (Step 12) Reading of each data of the address 4 of the first memory group 22 and the address 2 of the second memory group 23 (product-sum operation) as a set of addition, and the address 2 of the buffer 25 for the second memory group 23 Write data including data d (26).

  Reading of the 48 pieces of data d (2) to d (49) is completed by the processing in the above steps 7 to 12, and the final product-sum operation result for the 48 pieces of data is obtained.

Then, from this state, the following processing is performed as described above.
(Step 13) Reading of each data of the address 1 of the first memory group 22 and the address 3 of the second memory group 23 (product-sum operation) as a set of addition, new input data d (52) to the first memory group 22 And data d (28) from memory block 22d to address 1 of buffer 25.

  (Step 14) Reading of each data of the address 5 of the first memory group 22 and the address 1 of the second memory group 23 as a set of addition (product-sum operation).

  (Step 15) Reading of each data of the address 3 of the first memory group 22 and the address 5 of the second memory group 23 (product-sum operation) and the data of the address 0 of the buffer 25 with respect to the second memory group 23 as a set of addition Write including d (29).

  (Step 16) Reading (data sum operation) each data of the address 0 of the first memory group 22 and the address 2 of the second memory group 23 as a set of addition, and new data d (53) for the first memory group 22 Write data including and write data d (35) from memory block 22c to address 0 of buffer 25.

  (Step 17) Reading of each data of the address 4 of the first memory group 22 and the address 0 of the second memory group 23 as a set of addition (product-sum operation).

  (Step 18) Reading of each data of the address 2 of the first memory group 22 and the address 4 of the second memory group 23 (product-sum operation) and the data of the address 1 of the buffer 25 with respect to the second memory group 23 as a set of addition Write data including d (28).

  Reading of the 48 pieces of data d (4) to d (51) is completed by the processing of steps 13 to 18, and the product-sum operation result for the 48 pieces of data is obtained. Further, the data arrangement at this time is the same as the initial state of FIG.

  In the above steps 1 to 18, the product-sum operation of 48 pieces of data d (0) to d (47), data d (2) to d (49) and data d (4) to d (51) is performed. Results will be obtained sequentially.

  Therefore, the filtering process can be performed with 1/2 decimation by repeating the processes of steps 1 to 18 described above.

  Next, an odd-tap symmetric type process using the above-described memory block having 6 addresses and a buffer 25 will be described.

  FIG. 25A shows an initial state of the storage of the data. The first memory group 22 includes a new data including intermediate data d (23) out of 47 (odd number N) data. Data d (23) to d (46) is stored in four memory blocks in descending order, and the second memory group 23 stores the old data d (23) including the intermediate data d (23). 0) to d (23) are stored in ascending order in four memory blocks, six by six. The buffer 25 stores data d (22), d (27), d (20), d (25), d (18), d (23) in ascending order of addresses.

From this state, the following series of processing is performed.
(Step 101) Reading the data at the address 5 of the first memory group 22 and the address 5 of the second memory group 23 as a set of addition (product-sum operation. However, for intermediate data, the original coefficient Writing data including new data d (47) to the first memory group 22 and writing data d (29) from the memory block 22c to address 5 of the buffer 25.

  (Step 102) Reading of each data of the address 3 of the first memory group 22 and the second memory group 23 which is a set of addition (product-sum operation).

  (Step 103) Reading of each data at the address 1 of the first memory group 22 and the second memory group 23 (multiply-accumulate operation) and the data d at the address 3 of the buffer 25 for the second memory group 23 (25) ) Write data at address 1.

  By the processing of steps 101 to 103, the data arrangement is in the state shown in FIG. 25B, and the next processing is performed from this state.

  (Step 104) Reading (data sum operation) of each data at the address 4 of the first memory group 22 and the second memory group 23 as a set of addition, and data writing including new data d (48) to the first memory group 22 Further, the data d (24) is written from the memory block 22d to the address 4 of the buffer 25.

  (Step 105) Reading of each data of the address 2 of the first memory group 22 and the second memory group 23 which is a set of addition (product-sum operation).

  (Step 106) Reading (data sum operation) of each data at the address 0 of the first memory group 22 and the second memory group 23 as a set of addition and data d (24 of the address 25 of the buffer 25 for the second memory group 23) ) Including data writing.

  Through the processing of steps 101 to 106 described above, reading of 47 pieces of data d (0) to d (46) is completed, and a product-sum operation result for the 47 pieces of data is obtained. The data arrangement at this time is as shown in FIG. 26A, and the next processing is performed from this state.

  (Step 107) Reading (data sum operation) each data of the address 3 of the first memory group 22 and the address 1 of the second memory group 23, which is a set of addition, and new data d (49) for the first memory group 22 Write data including and write data d (31) from memory block 22c to address 3 of buffer 25.

  (Step 108) Reading out each data of the address 1 of the first memory group 22 and the address 5 of the second memory group 23, which is a set of addition (product-sum operation).

  (Step 109) Reading of each data of the address 5 of the first memory group 22 and the address 3 of the second memory group 23 (product-sum operation) as a set of addition, and data of the address 1 of the buffer 25 for the second memory group 23 Write data including d (27).

  By the processing in steps 107 to 109 described above, the data arrangement becomes the state shown in FIG. 26B, and the next processing is performed from this state.

  (Step 110) Reading (data sum operation) each data of the address 2 of the first memory group 22 and the address 0 of the second memory group 23, which is a set of addition, and new data d (50) for the first memory group 22 Write data including and write data d (26) from memory block 22d to address 2 of buffer 25.

  (Step 111) Reading of each data of the address 0 of the first memory group 22 and the address 4 of the second memory group 23 which is a set of addition (product-sum operation).

  (Step 112) Reading of each data of the address 4 of the first memory group 22 and the address 2 of the second memory group 23 (product-sum operation) as a set of addition and data of the address 2 of the buffer 25 for the second memory group 23 Write data including d (26).

  Through the processing of steps 110 to 112 described above, reading of 47 pieces of data d (2) to d (48) is completed, and a product-sum operation result for the 47 pieces of data is obtained. The data arrangement at this time is in the state shown in FIG. 27A, and the next processing is performed from this state.

  (Step 113) Reading (data sum operation) of each data of the address 1 of the first memory group 22 and the address 3 of the second memory group 23, which is a set of addition, and new data d (51) for the first memory group 22 Write data including and write data d (33) from memory block 22c to address 1 of buffer 25.

  (Step 114) Reading of each data of the address 5 of the first memory group 22 and the address 1 of the second memory group 23 which is a set of addition (product-sum operation).

  (Step 115) Reading (data sum operation) of each data of the address 3 of the first memory group 22 and the address 5 of the second memory group 23 and the data of the address 5 of the buffer 25 with respect to the second memory group 23 as a set of addition Write data including d (29).

  As a result of the processing in steps 113 to 115 described above, the data arrangement becomes the state shown in FIG. 27B, and the next processing is performed from this state.

  (Step 116) Reading (data sum operation) each data of the address 0 of the first memory group 22 and the address 2 of the second memory group 23 as a set of addition, and new data d (52) for the first memory group 22 Write data including and write data d (28) from memory block 22d to address 0 of buffer 25.

  (Step 117) Reading each data of the address 4 of the first memory group 22 and the address 0 of the second memory group 23, which is a set of addition (product-sum operation).

  (Step 118) Reading of each data of the address 2 of the first memory group 22 and the address 4 of the second memory group 23 to be a set of addition (product-sum operation) and data of the address 0 of the buffer 25 for the second memory group 23 Write data including d (28).

  Through the processing of steps 113 to 118 described above, reading of 47 pieces of data d (4) to d (50) is completed, and a product-sum operation result for the 47 pieces of data is obtained. Also, the data arrangement at this time is shown in FIG. 28, which is equal to the initial state of FIG.

  As a result of the processing in steps 101 to 118, the product-sum operation result of 47 pieces of data d (0) to d (46), data d (2) to d (48), and data d (4) to d (50) is obtained. Are sequentially obtained, and by repeating this, filtering processing by odd taps and 1/2 decimation can be performed.

  Note that the above operation example is an example, and other decimation processing and the like can be handled by appropriately changing the order of reading and writing with respect to the first memory group 22, the second memory group 23, and the buffer 25. Further, by controlling the read / write address only for the buffer 25 independently, the read / write common address can be used for the first memory group 22 and the second memory group 23, and the control can be easily performed.

  In each of the above-described embodiments, data is stored in descending order of addresses for each memory block of the first memory group 22, and data is stored in ascending order of addresses for each memory block of the second memory group 23. However, conversely, data may be stored in ascending order of addresses for each memory block of the first memory group 22, and data may be stored in descending order of addresses for each memory block of the second memory group 23. Good.

Configuration diagram of an embodiment of the present invention Operation explanatory diagram of the embodiment Operation explanatory diagram of the embodiment Operation explanatory diagram of the embodiment Operation explanatory diagram of the embodiment Operation explanatory diagram of the embodiment Configuration diagram for coefficient asymmetric type Configuration of another embodiment of the present invention Operation explanatory diagram of other embodiments Operation explanatory diagram of other embodiments Operation explanatory diagram of other embodiments Configuration of another embodiment of the present invention Operation explanatory diagram of decimation processing of another embodiment Operation explanatory diagram of odd tap processing of other embodiment Operation explanatory diagram of odd tap processing of other embodiment Operation explanatory diagram of odd tap processing of other embodiment Operation explanatory diagram of odd tap processing of other embodiment Operation explanatory diagram of odd tap processing of other embodiment Operation explanatory diagram of odd tap processing and decimation processing of other embodiment Operation explanatory diagram of odd tap processing and decimation processing of other embodiment Operation explanatory diagram of decimation processing when the number of addresses of the memory block is 6 Operation explanatory diagram of decimation processing when the number of addresses of the memory block is 6 Operation explanatory diagram of decimation processing when the number of addresses of the memory block is 6 Operation explanatory diagram of decimation processing when the number of addresses of the memory block is 6 Explanatory diagram of odd tap and decimation process when the number of addresses of the memory block is 6 Explanatory diagram of odd tap and decimation process when the number of addresses of the memory block is 6 Explanatory diagram of odd tap and decimation process when the number of addresses of the memory block is 6 Explanatory diagram of odd tap and decimation process when the number of addresses of the memory block is 6 Basic configuration of FIR type digital filter

Explanation of symbols

  20, 50, 60, 70... FIR digital filter, 21... Data storage unit, 22... First memory group, 22a to 22d... Memory block, 23. Memory block, 24... Latch circuit, 25... Buffer, 26... Data switch, 30... Controller, 30 a... Data reading means, 30 b ... First data writing means, 30 c. Write means, 30d... Buffer control means, 40... Product-sum operation unit, 41... Coefficient memory, 42... Coefficient selection means, 43a to 43d ... adder, 44a to 44h ... multiplier, 45 ... ... Sum calculator

Claims (7)

Data storage unit (21) for storing the latest plural N data (N is an integer equal to 2 × m × p or 2 × m × p−1 for plural m and integer p) input in time series And a product-sum operation unit (40) that multiplies a predetermined number of N data stored in the data storage unit by a predetermined coefficient, and calculates and outputs the sum,
Wherein the data storage unit,
Memory blocks (22a to 22d) consisting of dual-port RAMs with an address number m that can independently read and write data are connected in series in p stages, receive new data, and count from the newest of the N consecutive data. A first memory group (22) for storing m × p data,
Memory blocks (23a to 23d) consisting of dual-port RAMs with the number of addresses m that can independently read and write data are connected in p stages in series, receive data read from the first memory group, and receive the continuous N A second memory group (23) for storing m × p data counted from the oldest of the data,
A state in which data is stored in descending order in each memory block of one of the first memory group and the second memory group and data is stored in ascending order in each memory block of the other memory group is an initial state From the initial state, the first memory group and the second memory group are instructed to read while sequentially changing the addresses, and the consecutive N data are sequentially read in 2p divided into m times, Data reading means (30a) for outputting to the product-sum operation unit;
Each time data reading by the data reading means is performed a predetermined number of times, each memory block of the first memory group is instructed to write to the address of the oldest stored data, and each data at the address is transferred to the subsequent stage. And first data writing means (30b) for writing new data to the memory block in the first stage,
Each time the data reading by the data reading means is performed a predetermined number of times, the memory block of the second memory group is instructed to write the read data to the address, and each data at the address is written to the subsequent stage. And a second data writing means (30c) for writing data read from the first memory group at the time of data writing by the first data writing means to the first-stage memory block,
Said data reading means, said first data writing means and the second data writing means, so that at the stage of the writing from an initial state of the m new data has been completed to switch the address to return to the initial state Composed of
The first data writing means immediately after the data reading means instructs to read by designating the address of the oldest data among the data stored in each memory block of the first memory group. It is configured to instruct writing to the corresponding address of each memory block of the memory group,
The second data writing means is configured such that each of the memories in the second memory group immediately after the data reading means designates an address of data stored in each memory block of the second memory group and instructs reading. It is configured to instruct to write data to the address of the block,
further,
A latch circuit (24) is provided between the first memory group and the second memory group;
The first data writing means writes the data read from the last memory block to the latch circuit when instructing to write to each memory block of the first memory group,
The second data writing means is configured to write the data stored in the latch circuit to the first-stage memory block when instructing writing to each memory block of the second memory group. FIR type digital filter characterized by the above. Data storage unit (21) for storing the latest plural N data (N is an integer equal to 2 × m × p or 2 × m × p−1 for plural m and integer p) input in time series And a product-sum operation unit (40) that multiplies a predetermined number of N data stored in the data storage unit by a predetermined coefficient, and calculates and outputs the sum,
The data storage unit
Memory blocks (22a to 22d) consisting of dual-port RAMs with the number of addresses m that can independently read and write data are connected in p stages in series, receive new data, and count from the newest of the N consecutive data. A first memory group (22) for storing m × p data,
Memory blocks (23a to 23d) consisting of dual-port RAMs with the number of addresses m that can independently read and write data are connected in p stages in series, receive data read from the first memory group, and receive the continuous N A second memory group (23) for storing m × p data counted from the oldest of the data,
A state in which data is stored in descending order in each memory block of one of the first memory group and the second memory group and data is stored in ascending order in each memory block of the other memory group is an initial state From the initial state, the first memory group and the second memory group are instructed to read while sequentially changing the addresses, and the consecutive N data are sequentially read in 2p divided into m times, Data reading means (30a) for outputting to the product-sum operation unit;
Each time data reading by the data reading means is performed a predetermined number of times, each memory block of the first memory group is instructed to write to the address of the oldest stored data, and each data at the address is transferred to the subsequent stage. And first data writing means (30b) for writing new data to the memory block in the first stage,
Each time the data reading by the data reading means is performed a predetermined number of times, the memory block of the second memory group is instructed to write the read data to the address, and each data at the address is written to the subsequent stage. And a second data writing means (30c) for writing data read from the first memory group at the time of data writing by the first data writing means to the first-stage memory block,
The data reading means, the first data writing means, and the second data writing means switch addresses so as to return to the initial state when m new data has been written from the initial state. Composed of
The first data writing means immediately after the data reading means instructs to read by designating the address of the oldest data among the data stored in each memory block of the first memory group. It is configured to instruct writing to the corresponding address of each memory block of the memory group,
The second data writing means is configured such that each of the memories in the second memory group immediately after the data reading means designates an address of data stored in each memory block of the second memory group and instructs reading. It is configured to instruct to write data to the address of the block,
further,
A buffer (25) comprising a dual port RAM having the same number of addresses m as the memory block, storing data read from the first memory group, and outputting the stored data to the second memory group;
A data switch (26) for selecting any of the data output from the last stage and at least the previous memory block among the memory blocks of the first memory group and inputting the selected data to the buffer;
When data is written by the first data writing means, data corresponding to an address specified for each memory block of the first memory group is selected by the data switch and input to the buffer, and the address is input to the buffer. When the data is written by the second data writing means, m new data from the data in the first memory block at the write target address is read from the buffer and the first memory is written. Buffer control means (30d) for input to the block, and
By the data reading means, the first data writing means, the second data writing means, and the buffer control means, the even tap type filter processing, the odd tap type filter processing, and the filter processing obtained by adding decimation processing thereto. F IR digital filter you characterized in that either configured to accommodate. Of the data in the last memory block of the first memory group, the data in the last memory block in the first memory group and the data in the first memory block in the second memory group do not overlap. The state in which the oldest data is replaced with m older data is stored in the buffer as the initial state, and when the new data has been written, the initial state is restored and the time series continues. The even-number tap 1 / m decimation type filter processing is performed by controlling the read address of the buffer and the switch so that one product-sum operation result of 2 × m × p data is obtained. The FIR type digital filter according to claim 2. The oldest data of the last memory block of the first memory group and the newest data of the first memory block of the second memory group are common, and the last memory block and the buffer of the first memory group The initial state is the state where the stored contents are the same, and when the writing of m new data is completed, the initial state is restored, and the product-sum operation of 2 × m × p−1 data continuous in time series 3. The FIR digital filter according to claim 2, wherein odd tap type filter processing is performed by controlling the read address of the buffer and the switch so that m results are obtained . The oldest data in the last memory block of the first memory group and the newest data in the first memory block of the second memory group are common, and the data of the memory block in the last memory block of the first memory group Among them, the state in which the data obtained by replacing the oldest data with m new data is stored in the buffer is set as an initial state, and when the writing of m new data is completed, the initial state is restored, and time series Odd tap 1 / m decimation type filter processing is performed by controlling the read address and the switch of the buffer so that one product-sum operation result of 2 × m × p−1 continuous data is obtained. The FIR type digital filter according to claim 2 . The product-sum operation unit
A coefficient memory (41) for storing coefficients for multiplying the continuous N pieces of data;
Coefficient selection means (42) for selecting, from the coefficient memory, coefficients corresponding to the data read by the data reading means from the first memory group and the second memory group, respectively.
2. The product-sum operation is performed using the data read by the data reading means in increments of 2p and the coefficients selected by the coefficient selection means. FIR type digital filter in any one of -5. In the coefficient memory, among the consecutive N pieces of data stored in the first memory group and the second memory group, each of the sets of data in which the rank counted from the newest and the rank counted from the oldest is the same. The coefficient of
The data reading means is configured to read data having a common coefficient from the first memory group and the second memory group by p pieces,
The product-sum operation unit adds data having common coefficients to each other by p adders (43a to 43d), and outputs the addition results to p multipliers (44a to 44d), respectively. 7. The FIR type digital filter according to claim 6, wherein the sum of the multiplication results of the p multipliers is obtained by a sum calculator (45).

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