JP4287217B2 - Method for manufacturing nonvolatile memory having local SONOS structure - Google Patents

Description

  The present invention relates to a method for manufacturing a nonvolatile memory device, and more particularly, to a method for manufacturing a nonvolatile memory device having a local SONOS structure.

  Semiconductor memory devices used for storing data are generally classified into volatile and nonvolatile memory devices. The volatile memory device loses the stored data if the power supply is interrupted, but the nonvolatile memory device maintains the stored data even if the power supply is interrupted. Thus, the power supply is not always available, such as mobile phone systems, memory cards for storing music and / or video data, and other application devices, which are sometimes interrupted or require low power usage. In this situation, non-volatile memory devices are widely used.

  Generally, a nonvolatile memory device has a stacked gate structure in which a gate insulating film, a floating gate electrode, an inter-gate insulating film, and a control gate electrode are sequentially stacked on a channel region of a cell transistor. In some cases, the structure of the nonvolatile memory device includes a silicon film in which a channel region is formed, an oxide film in which a tunneling layer is formed, a nitride film used as a charge trap layer, an oxide film used as a shielding layer, and a control. It includes a silicon film used as a gate electrode. Such a film is called a SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) structure. Recently, a local SONOS structure in which a nitride film used as a charge trap layer overlaps only a part of a silicon film used as a control gate electrode has been proposed. It is already known that the nonvolatile memory element having the local SONOS structure exhibits improved operational characteristics by adjusting the overlapping length of the charge trap layer and the control gate electrode.

  1 to 4 are cross-sectional views illustrating a conventional method for manufacturing a nonvolatile memory device having a local SONOS structure.

  As shown in FIG. 1, an ONO film 110 is formed on the silicon substrate 100, and a first photoresist film pattern 121 is formed on the ONO film 110. The ONO film 110 has a structure in which a first oxide film 112, a nitride film 114, and a second oxide film 116 are sequentially stacked. The first photoresist film pattern 121 has an opening that exposes a partial surface of the second oxide film 116. Next, an exposed portion of the second oxide film 116, the nitride film 114, and the first oxide film 112 is sequentially removed by performing an etching process using the first photoresist film pattern 121 as an etching mask. As a result, as shown in FIG. 2, a partial surface 101 of the silicon substrate 100 is exposed, and ONO film patterns 110 ′ are formed on both sides of the exposed surface 101. After performing the etching process, the first photoresist film pattern 121 is removed.

  Next, as shown in FIG. 3, an oxidation process is performed to form a third oxide film 130 as a gate insulating film on the exposed surface (101 in FIG. 2) of the silicon substrate 100. Then, a polysilicon film 140 and a second photoresist film pattern 122 are sequentially formed on the ONO film pattern 110 ′ and the third oxide film 130.

  Next, an etching process using the second photoresist film pattern 122 as an etching mask is performed to sequentially remove the exposed portions of the polysilicon film 140 and the ONO film pattern 110 '. After the etching process, the second photoresist film pattern 122 is removed. As a result, as shown in FIG. 4, a polysilicon film pattern 142 is formed as a control gate insulating film. On both sides of the polysilicon film pattern 142, the polysilicon film pattern 142 is aligned with the etch of the polysilicon film pattern 142. Then, a tunneling layer 112, a charge trap layer 114, and a shielding layer 116 are sequentially stacked. The overlapping length of the charge trap layer 114 and the polysilicon film pattern 142 is represented as “A”.

  Next, an ion implantation process using the polysilicon film pattern 142 and a predetermined mask film pattern (not shown) as an ion implantation mask is performed to form a source region 162 and a drain region 164 in certain regions on the silicon substrate 100, respectively. .

As described above, according to the conventional method of manufacturing a nonvolatile memory device, “A”, which is the overlap length of the charge trap layer 114 and the polysilicon film pattern 142, is the first photoresist film pattern (FIG. 1). 121) and the second photoresist film pattern (122 in FIG. 3). Accordingly, misalignment inevitably occurs in the photolithography process due to an increase in the degree of integration of elements, and this misalignment results in the length “A” being irregular at each specific position. As described above, the irregular length of “A” makes the characteristics of the memory cell non-uniform and ultimately weakens the reliability of the element.
JP 2002-73960 A

  The technical problem to be solved by the present invention is to provide a method for manufacturing a nonvolatile memory device having a local SONOS structure that can determine the overlap length between the charge trap layer and the control gate electrode without being affected by the photolithography process. Is to provide.

  In order to achieve the above object, a method of manufacturing a non-volatile memory device according to an embodiment of the present invention provides a first oxide film pattern, a nitride film pattern, and a first oxide film pattern while exposing a partial surface of the semiconductor substrate on a semiconductor substrate. Forming a vertical structure in which two oxide film patterns are sequentially stacked, exposing a partial surface of the nitride film pattern by the second oxide film pattern; and on the exposed surfaces of the vertical structure and the semiconductor substrate. Forming a third oxide film, forming a polysilicon film on the third oxide film, and performing a planarization process until the second oxide film pattern is exposed. Forming a control gate electrode, and performing an etching process using the control gate electrode as an etching mask until a part of the surface of the semiconductor substrate is exposed. An ONO film in which a tunneling layer made of the first oxide film pattern, a charge trap layer made of the nitride film pattern, and a shielding layer made of the third oxide film are sequentially stacked under the control gate electrode; And a step of forming a source region and a drain region by performing an ion implantation process on the conductor substrate exposed by the control gate electrode. And

  Forming the vertical structure includes sequentially forming a first oxide film, a nitride film and a second oxide film on the semiconductor substrate; and patterning the second oxide film to form a part of the nitride film. Performing a step of forming a second oxide film pattern exposing the surface, a step of forming an intermediate film on the exposed surface of the nitride film and the second oxide film pattern, and an isotropic etching process for the intermediate film Forming a spacer film on a side surface of the second oxide film pattern, and performing an etching process on the nitride film using the second oxide film pattern and the spacer film as an etching mask to perform a partial surface of the first oxide film Forming a nitride film pattern that exposes a portion, removing the spacer to expose a portion of the nitride film pattern, and using the nitride film pattern as an etching mask to form the first acid. Performing an etching process on the film to form a first oxide film pattern; and forming a third oxide film on the exposed surface of the semiconductor substrate, the exposed surface of the nitride film pattern, and the second oxide film pattern. It is desirable to include.

  In this case, the intermediate film is preferably a polysilicon film.

  It is desirable to use an etch-back process as an isotropic etching process for the intermediate film.

  The etching process for the first oxide film is preferably performed using a wet etching method.

  In this embodiment, the third oxide film is preferably formed by a chemical vapor deposition process. In this case, the method may further include a step of performing a thermal oxidation process after the chemical vapor deposition process to thicken the third oxide film.

  The planarization process is preferably performed using a chemical mechanical polishing method.

  According to another aspect of the present invention, a method of manufacturing a non-volatile memory device includes a pair of vertical structures spaced apart from each other while exposing a part of a surface of a semiconductor substrate. Each vertical structure has a structure in which a first oxide film pattern, a nitride film pattern, and a second oxide film pattern are sequentially stacked, and one of the nitride film patterns is formed by the second oxide film pattern. A step of having a structure in which a part surface is exposed; a step of forming a third oxide film on the exposed surface of the vertical structure and the semiconductor substrate; and a step of forming a polysilicon film on the third oxide film. Performing a planarization process until the second oxide film pattern is exposed to form a polysilicon film pattern, and an etching process using the control gate electrode as an etching mask. A part of the substrate is exposed until a part of the surface is exposed, and a pair of ONO films and the third oxide film spaced apart from each other are disposed under the polysilicon film pattern, and each ONO film is formed from the first oxide film pattern. A tunneling layer, a charge trap layer made of the nitride film pattern, and a shielding layer made of the third oxide film, and a part of the polysilicon film pattern on the polysilicon film pattern. A step of forming a mask film pattern that exposes a surface, and an etching process for the polysilicon film pattern and the third oxide film are sequentially performed using the mask film pattern as an etching mask. A first control gate electrode and a second control gate electrode disposed to be spaced apart from each other; Forming a first gate insulating film and a second gate insulating film made of an oxide film and disposed below the first control gate electrode and the second control gate electrode; and the first control gate electrode and the second control gate A source region, a drain region, and an impurity region are formed by performing an ion implantation process on the semiconductor substrate exposed by the gate electrode, and the source region is adjacent to the charge trap layer below the first control gate electrode. The drain region is formed in a semiconductor substrate adjacent to the charge trap layer below the second control gate electrode, and the impurity region is formed in the semiconductor substrate between the first and second control gate electrodes. A stage.

  Forming the pair of vertical structures includes sequentially forming a first oxide film, a nitride film and a second oxide film on the semiconductor substrate; and patterning the second oxide film to form the nitride film. Forming a pair of second oxide film patterns exposing a central portion; forming an intermediate film on the exposed surface of the nitride film and the second oxide film pattern; and isotropic etching of the intermediate film Performing a process to form a spacer film on a side surface of the second oxide film pattern, and performing an etching process on the nitride film using the second oxide film pattern and the spacer film as an etching mask to form a center of the first oxide film Forming a pair of nitride patterns that expose portions, exposing the portions of the nitride patterns by removing the spacers, and using the nitride patterns as an etching mask Performing an etching process on the first oxide film to form a first oxide film pattern exposing a central portion of the semiconductor substrate; an exposed surface of the semiconductor substrate; an exposed surface of the nitride film pattern; and the second oxide film Forming a third oxide film on the pattern.

  In this case, the intermediate film is preferably a polysilicon film.

  It is desirable to use an etch-back process as an isotropic etching process for the intermediate film.

  The etching process for the first oxide film is preferably performed using a wet etching method.

  In this embodiment, the third oxide film is preferably formed by a chemical vapor deposition process. In this case, the method may further include performing a thermal oxidation process after the chemical vapor deposition process to thicken the third oxide film.

  The planarization process is preferably performed using a chemical mechanical polishing method.

  According to the method for manufacturing a non-volatile memory device having a local SONOS structure according to the present invention, the length of the charge trap layer overlapping the control gate electrode is simply determined by the thickness of the polysilicon film without the photolithography process. Since it is determined uniformly in every region, the uniformity of element characteristics is improved. Further, by adjusting the thickness of the polysilicon film, a desired overlapping length of the control gate electrode and the charge trap layer can be easily formed.

  Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the embodiments of the present invention can be modified in various other forms, and the scope of the present invention should not be construed as being limited by the embodiments described below.

  5 to 11 are cross-sectional views illustrating a method for manufacturing a nonvolatile memory device having a local SONOS structure according to the first embodiment of the present invention.

Referring to FIG. 5, an ONO film 210 is formed on a silicon substrate (semiconductor substrate) 200. The ONO film 210 has a structure in which a first oxide film 211, a nitride film 213, and a second oxide film 215 are sequentially stacked. As an example, the first oxide film 211 can be formed by thermally oxidizing the silicon substrate 200. In some cases, the thermal oxidation may be performed in an atmosphere containing nitrogen, for example, an atmosphere of N ₂ O gas or NO gas. In this case, the first oxide film 211 contains oxynitride. The nitride film 213 and the second oxide film 215 are formed by using a low-pressure chemical vapor deposition (LP-CVD) method. In some cases, the nitride film 213 may be formed by performing a nitriding process on the first oxide film 211. The second oxide film 211 is formed to be substantially thicker than a normal thickness.

  Next, referring to FIG. 6, the second oxide film 211 is patterned to form a second oxide film pattern 215 '. The central portion of the nitride film 213 is exposed by the second oxide film pattern 215 '. In order to form the second oxide film pattern 215 ', a mask film pattern (not shown) is formed on the second oxide film (215 in FIG. 5). Then, an etching process is performed until a partial surface of the nitride film 213 is exposed using the mask film pattern as an etching mask, and the exposed second oxide film 215 is removed.

  After forming the second oxide film pattern 215 ′, a first polysilicon film 220 (intermediate film) is formed so that the exposed surfaces of the second oxide film pattern 215 ′ and the exposed nitride film 213 are completely covered. To do. At this time, the thickness d of the first polysilicon film 220 is an important factor for determining the overlapping length of the subsequent charge trap layer and the control gate electrode. Accordingly, the thickness d of the first polysilicon film 220 is determined so that a desired charge trap layer and control gate electrode overlap length can be obtained.

  Referring to FIG. 7, isotropic etching of the first polysilicon film (220 in FIG. 6) is performed until the upper surface of the second oxide film pattern 215 'is exposed. As a result, a polysilicon film spacer 220 ′ is formed on the side surface of the second oxide film pattern 215 ′ and a partial surface of the nitride film (213 in FIG. 6). In the isotropic etching, an etch back etching method can be used.

  After the polysilicon film spacer 220 'is formed, a part of the nitride film (213 in FIG. 1) is exposed in addition to the upper surface of the second oxide film pattern 215'. Therefore, the exposed surface of the nitride film 213 is removed to form a nitride film pattern 213 '. At this time, the second oxide film pattern 215 ′ and the first polysilicon film spacer 220 ′ are used as a mask film for removing the exposed surface of the nitride film 213. The nitride pattern 213 'is covered with a second oxide pattern 215' and a first polysilicon film spacer 220 '. A part of the surface of the first oxide film 211 is exposed between the first polysilicon film spacers 220 '. Thereafter, an etching process for removing the first polysilicon film spacer 220 'is performed.

  Referring to FIG. 8, an etching process using the nitride film pattern 213 'as an etching mask is performed to remove an exposed portion of the first oxide film (211 in FIG. 7). Thus, the first oxide film pattern 211 ′ is formed in alignment with the etch of the nitride film pattern 213 ′ while exposing a part of the surface of the silicon substrate 200, that is, a portion where the gate insulating film is formed. Since a part of the surface of the silicon substrate 200 is exposed by the etching process, a dry etching method using plasma may be used in the etching process, but in this case, the silicon substrate 200 is damaged by the plasma. It is desirable to use wet etching methods whenever possible.

  Next, an oxide film forming step is performed to form a third oxide film 230 so that the exposed portion of the silicon substrate 200 is completely covered. In this process, not only the upper surface of the second oxide film pattern 215 ′ but also the exposed surface of the nitride film pattern 213 ′ is covered with the third oxide film 230. The oxide film forming step can be performed using a chemical vapor deposition (CVD) method.

  After the third oxide film 230 is formed by the chemical vapor deposition method, the third oxide film 230 is cured by performing normal annealing. However, thermal oxidation may be performed instead of annealing in order to form the thicker third oxide film 230. When thermal oxidation is performed instead of annealing, the third oxide film 230 is hardened and a thicker third oxide film 230 can be obtained at the same time.

  Referring to FIG. 9, a second polysilicon film 240 is formed on the third oxide film 230. The second polysilicon film 240 can be formed using a CVD method. As an example, during the CVD process for forming the second polysilicon film 240, the phosphine gas is mixed by about 10% of the volume of the source gas to be doped as phosphorus of an n-type impurity (phosphorus). . As a result, the second polysilicon film 240 having higher conductivity than the undoped polysilicon film can be obtained.

  Referring to FIG. 10, a planarization process is performed to remove a part of the second polysilicon film 240 in FIG. 9 so that the second oxide film pattern 215 'is exposed. The planarization process is performed by using chemical mechanical polishing (CMP). The planarization process may be performed until the second oxide film pattern 215 'is exposed, and may be performed until the third oxide film 230 on the second oxide film pattern 215' is exposed. When the planarization process is completed, the control gate electrode 242 made of the second polysilicon film pattern is formed.

  Referring to FIG. 11, the second oxide film pattern (215 ′ in FIG. 10) and the third oxide film (FIG. 10) exposed by the control gate electrode 242 are formed by performing an etching process using the control gate electrode 242 as an etching mask. 230) is removed.

  As a result, a part of the surface of the nitride film pattern 213 ′ is exposed, and an etching process for removing the exposed portion of the nitride film pattern 213 ′ is then performed. If the nitride film pattern 213 'is removed, a partial surface of the first oxide film pattern 211' is exposed. Similarly, an exposed portion of the first oxide film pattern 211 ′ is removed by performing an etching process to expose a part of the silicon substrate 200.

  When all the etching processes are completed, the tunneling layer 212 made of the first oxide film, the charge trap layer 214 made of the nitride film, and the shielding layer 234 made of the third oxide film are formed between the silicon substrate 200 and the control gate electrode 242. Sequentially stacked vertical structures 210 ′ are formed in alignment with the etch of the control gate electrode 242. A gate insulating layer 232 made of a third oxide layer is formed between the silicon substrate 200 and the control gate electrode 242 between the vertical structures 210 ′.

  On the other hand, a metal silicide film (not shown) may be formed on the control gate electrode 242 in order to reduce the current resistance of the gate line. In this case, the metal silicide film may be a tungsten silicide (WSi) film, a cobalt silicide (CoSi) film, or a titanium silicide (TiSi) film. When the etching process is completed, an ion implantation process using the control gate electrode 242 and a predetermined mask film pattern (not shown) as an ion implantation mask is performed to form a source region in a certain region on the silicon substrate 200. 252 and drain region 254 are formed.

  12 and 13 are cross-sectional views illustrating a method for manufacturing a nonvolatile memory device having a local SONOS structure according to a second embodiment of the present invention. Specifically, the present embodiment relates to a method for manufacturing a nonvolatile memory device having a local SONOS structure capable of 1-bit operation.

  Referring to FIG. 12, the method for manufacturing a non-volatile memory device according to the present invention includes the same steps as described with reference to FIGS. Further, the process is the same up to the stage before forming the source region (252 in FIG. 11) and the drain region (254 in FIG. 11) at the stage described with reference to FIG. Therefore, a duplicate description is omitted, and a mask film pattern (not shown) is formed on the control gate electrode (242 in FIG. 11) if it is described from the subsequent stage.

  This mask film pattern has an opening that exposes the central portion of the control gate electrode 242. An exposed portion of the control gate electrode 242 is removed by performing an etching process using this mask film pattern as an etching mask. As a result, a part of the surface of the gate insulating film (232 in FIG. 11) is exposed.

  Subsequently, the etching process is advanced to remove the exposed portion of the gate insulating film 232 so that a part of the surface of the silicon substrate 200 is exposed. Next, the mask film pattern is removed. As a result, the first control gate electrode 242a and the second control gate electrode 242b are formed so as to be spaced apart from each other at a constant interval. A first gate insulating film 232a below the first control gate electrode 242a and a second gate insulating film 232b below the second control gate electrode 242b are also formed. Then, the silicon substrate 200 between the first control gate electrode 242a and the second control gate electrode 242b is exposed.

  As shown in FIG. 12, an ion implantation process using the first control gate electrode 242a, the second control gate electrode 242b, and a predetermined mask film pattern (not shown) as an ion implantation mask is performed. A source region 252, a drain region 254, and an impurity region 256 are formed in the certain region.

  The source region 252 is formed on the silicon substrate 200 adjacent to the charge trap layer 214 below the first control gate electrode 242a. The drain region 254 is formed in the silicon substrate 200 adjacent to the charge trap layer 214 below the second control gate electrode 242b. The impurity region 256 is formed in the silicon substrate 200 between the first control gate electrode 242a and the second control gate electrode 242b.

  The present invention has been described in detail with reference to preferred embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made by those skilled in the art within the technical idea of the present invention.

  The present invention relates to a local SONOS nonvolatile memory device among nonvolatile memory devices, and can be used in all fields where the nonvolatile memory device is used.

It is sectional drawing shown in order to demonstrate the manufacturing method of the non-volatile memory element which has the conventional local SONOS structure. It is sectional drawing shown in order to demonstrate the manufacturing method of the non-volatile memory element which has the conventional local SONOS structure. It is sectional drawing shown in order to demonstrate the manufacturing method of the non-volatile memory element which has the conventional local SONOS structure. It is sectional drawing shown in order to demonstrate the manufacturing method of the non-volatile memory element which has the conventional local SONOS structure. 3 is a cross-sectional view illustrating a method for manufacturing a nonvolatile memory device having a local SONOS structure according to a first embodiment of the present invention. FIG. 3 is a cross-sectional view illustrating a method for manufacturing a nonvolatile memory device having a local SONOS structure according to a first embodiment of the present invention. FIG. 3 is a cross-sectional view illustrating a method for manufacturing a nonvolatile memory device having a local SONOS structure according to a first embodiment of the present invention. FIG. 3 is a cross-sectional view illustrating a method for manufacturing a nonvolatile memory device having a local SONOS structure according to a first embodiment of the present invention. FIG. 3 is a cross-sectional view illustrating a method for manufacturing a nonvolatile memory device having a local SONOS structure according to a first embodiment of the present invention. FIG. 3 is a cross-sectional view illustrating a method for manufacturing a nonvolatile memory device having a local SONOS structure according to a first embodiment of the present invention. FIG. 3 is a cross-sectional view illustrating a method for manufacturing a nonvolatile memory device having a local SONOS structure according to a first embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a method for manufacturing a nonvolatile memory device having a local SONOS structure according to a second embodiment of the present invention. 6 is a cross-sectional view illustrating a method for manufacturing a nonvolatile memory device having a local SONOS structure according to a second embodiment of the present invention.

Explanation of symbols

200 ... silicon substrate,
210 ... vertical structure,
211, 211 '... the first oxide film pattern,
212 ... Tunneling layer,
213, 213 '... nitride film pattern,
214 ... charge trapping layer,
215, 215 '... oxide film pattern,
220 ... polysilicon film spacer,
230 ... third oxide film,
232 ... a gate insulating film,
232a ... gate insulating film,
232b ... gate insulating film,
232 ... a gate insulating film,
234 ... shielding layer,
240 ... polysilicon film,
242, 242a, 242b ... control gate electrode,
252 ... Source region,
254 ... drain region,
256: Impurity region.

Claims (14)

Sequentially forming a first oxide film, a nitride film and a second oxide film on a semiconductor substrate;
Patterning the second oxide film to form a second oxide film pattern exposing a partial surface of the nitride film;
Forming an intermediate film on the exposed surface of the nitride film and the second oxide film pattern;
Performing an isotropic etching process on the intermediate film to form a spacer film on a side surface of the second oxide film pattern;
Performing an etching process on the nitride film using the second oxide film pattern and the spacer film as an etching mask to form a nitride film pattern exposing a part of the first oxide film;
Removing the spacer to expose a portion of the nitride pattern;
Performing an etching process on the first oxide film using the nitride film pattern as an etching mask to form a first oxide film pattern;
Forming a third oxide film on the exposed surface of the semiconductor substrate, the exposed surface of the nitride film pattern, and the second oxide film pattern;
Forming a polysilicon film on the third oxide film;
Performing a planarization process until the second oxide film pattern is exposed to form a control gate electrode made of the polysilicon film pattern;
An etching process using the control gate electrode as an etching mask is performed until a part of the surface of the semiconductor substrate is exposed, and a tunneling layer made of the first oxide film pattern and the nitride film pattern are formed below the control gate electrode. An ONO film in which a charge trap layer and a shielding layer made of the third oxide film are sequentially stacked, and a gate insulating film made of the third oxide film,
Forming a source region and a drain region by performing an ion implantation process on the semiconductor substrate exposed by the control gate electrode. The method of claim 1 , wherein the intermediate film is a polysilicon film. 3. The method of manufacturing a nonvolatile memory element according to claim 1 , wherein an etch-back process is used as an isotropic etching process for the intermediate film. The method of manufacturing a nonvolatile memory element according to claim 1, wherein the etching process for the first oxide film is performed using a wet etching method. The method of manufacturing a nonvolatile memory element according to claim 1, wherein the third oxide film is formed by a chemical vapor deposition process. 6. The method of claim 5 , further comprising performing a thermal oxidation process after the chemical vapor deposition process to thicken the third oxide film. The method of manufacturing a nonvolatile memory element according to claim 1, wherein the planarization step is performed using a chemical mechanical polishing method.
Sequentially forming a first oxide film, a nitride film and a second oxide film on a semiconductor substrate;
Patterning the second oxide film to form a pair of second oxide film patterns exposing a central portion of the nitride film;
Forming an intermediate film on the exposed surface of the nitride film and the second oxide film pattern;
Performing an isotropic etching process on the intermediate film to form a spacer film on a side surface of the second oxide film pattern;
Performing a process of etching the nitride film using the second oxide film pattern and the spacer film as an etching mask to form a pair of nitride film patterns exposing a central portion of the first oxide film;
Removing the spacer to expose a portion of the nitride pattern;
Performing an etching process on the first oxide film using the nitride film pattern as an etching mask to form a first oxide film pattern exposing a central portion of the semiconductor substrate;
Forming a third oxide film on the exposed surface of the semiconductor substrate, the exposed surface of the nitride film pattern, and the second oxide film pattern;
Forming a polysilicon film on the third oxide film;
Performing a planarization process until the second oxide film pattern is exposed to form a polysilicon film pattern;
An etching process using the control gate electrode as an etching mask is performed until a partial surface of the semiconductor substrate is exposed, and a pair of ONO films and the third oxide film separated from each other below the polysilicon film pattern are formed. Each ONO film has a structure in which a tunneling layer made of a first oxide film pattern, a charge trap layer made of the nitride film pattern, and a shielding layer made of the third oxide film are sequentially stacked;
Forming a mask film pattern exposing a part of the surface of the polysilicon film pattern on the polysilicon film pattern;
A first control gate electrode made of the polysilicon film pattern and spaced apart from each other by sequentially performing an etching process on the polysilicon film pattern and the third oxide film using the mask film pattern as an etching mask. Forming a first control gate electrode and a second control gate electrode, and a first gate insulating film and a second gate insulating film formed of the third oxide film and disposed below the first control gate electrode and the second control gate electrode. When,
A source region, a drain region, and an impurity region are formed by performing an ion implantation process on the semiconductor substrate exposed by the first control gate electrode and the second control gate electrode, and the source region is formed on the first control gate electrode. The drain region is formed on a semiconductor substrate adjacent to a lower charge trap layer, the drain region is formed on a semiconductor substrate adjacent to a lower charge trap layer of the second control gate electrode, and the impurity region is formed on the first and second impurity regions. And forming the semiconductor substrate between the control gate electrodes on a semiconductor substrate. 9. The method of manufacturing a nonvolatile memory device according to claim 8 , wherein the intermediate film is a polysilicon film. 10. The method of manufacturing a nonvolatile memory element according to claim 8, wherein an etch-back process is used as an isotropic etching process for the intermediate film. 11. The method of manufacturing a nonvolatile memory element according to claim 8, wherein the etching process for the first oxide film is performed using a wet etching method. The method of manufacturing a nonvolatile memory element according to claim 8, wherein the third oxide film is formed by a chemical vapor deposition process. The method of claim 12 , further comprising performing a thermal oxidation process after the chemical vapor deposition process to thicken the third oxide film. The method of manufacturing a nonvolatile memory device according to claim 8, wherein the planarization step is performed using a chemical mechanical polishing method.

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