JP4286091B2 - Solid-state imaging device - Google Patents

Description

  The present invention relates to a solid-state image pickup device applied to, for example, an electronic camera, and more particularly to a solid-state image pickup device that can simultaneously read out a plurality of types of signals according to applications.

  In recent years, the number of pixels of digital still cameras has increased, and the number of mounted image sensors has millions of pixels. As the number of pixels increases, it takes longer to read out one frame of signal. . When such a high-pixel image sensor is used, when attempting to capture a moving image to be recorded or displayed in a viewfinder, the number of frames per unit time (seconds) is small and the image quality of the moving image cannot be tolerated. . In order to improve this, it is possible to improve the image quality of moving images by reducing the number of pixels per frame and increasing the number of frames per second by thinning out the signal reading operation from the image sensor. ing.

  As an AF method for capturing a moving image, a hill-climbing method using an image sensor is generally used. In this method, the determination of in-focus is performed using the high-frequency component of the imaging signal. Therefore, there is a problem that AF accuracy is lowered when moving images are picked up by thinning out image pickup signals.

Here, as a technique for improving the accuracy of AF, for example, in Patent Document 1, a part of two-dimensionally arranged pixel units is configured to output an AF signal, and a signal suitable for AF is obtained. A technique related to an XY address type solid-state imaging device that improves the accuracy by obtaining is disclosed. This technology is a solid-state imaging device in which photoelectric conversion cells that convert an optical image formed by an optical system into an electrical signal are two-dimensionally arranged, and a part of the photoelectric conversion cell group receives an image signal. A signal other than that for forming, that is, a signal for distance measurement is output.
JP 2000-156823 A

  However, in the technique according to Patent Document 1, although the AF accuracy is improved, an AF pixel different from the image forming pixel is arranged in a part of the pixel portion. Therefore, in the image formation, the signal of the AF pixel is interpolated. Processing is required, which increases the load on the image processing unit.

  The present invention has been made in view of the above problems, and the object of the present invention is to realize high-speed reading with improved frame rate and low power consumption while maintaining a simple configuration, and further to applications. An object of the present invention is to provide a solid-state imaging device capable of simultaneously reading out a plurality of types of signals in accordance with one frame.

  In order to solve the above-described problem, in the first aspect of the present invention, a vertical conversion circuit that selects a photoelectric conversion unit composed of a plurality of pixels arranged two-dimensionally and a pixel row to be read by the photoelectric conversion unit. A transfer switch connected to the output signal line of each pixel and driven and controlled by a transfer signal; a line memory for storing a pixel signal transferred from the pixel via the transfer switch; and a horizontal selection signal is output. A horizontal scanning circuit; a horizontal selection switch that is driven and controlled by the horizontal selection signal; and a plurality of output channels that read pixel signals through the horizontal selection switch, and controls the vertical scanning circuit and the horizontal scanning circuit. Provides a solid-state imaging device that simultaneously reads out the central pixel continuous signal and the readout of the thinned-out signal of the entire region in one frame. It is. According to this aspect, high-speed reading with improved frame rate and low power consumption can be realized while maintaining a simple configuration, and a plurality of types of signals can be read simultaneously in one frame depending on the application. Is possible.

  According to a second aspect of the present invention, in the first aspect, the pixel row selected in the readout of the central continuous signal and the pixel row selected in the readout of the thinned-out signal of the entire region are common, and For each selected pixel row, there is provided a solid-state imaging device further characterized by reading out a central pixel signal as a central continuous signal and reading out a pixel signal thinned out by a predetermined pixel as a whole region thinning signal. . According to this aspect, it is possible to simultaneously read out a plurality of types of signals according to applications in one frame.

  According to a third aspect of the present invention, unlike the first aspect, the pixel row selected in the readout of the central portion continuous signal and the pixel row selected in the readout of the thinned-out signal of the entire region differ from the central portion continuous signal. There is provided a solid-state imaging device further characterized by preventing mixing of pixel signals on the output signal line by shifting the timing at which the transfer switch is turned on between reading out and reading out the entire area. According to this aspect, mixing of pixel signals on the output signal line can be prevented.

  In the fourth aspect of the present invention, a photoelectric conversion unit composed of a plurality of pixels arranged two-dimensionally, a vertical scanning circuit for selecting a pixel row to be read by the photoelectric conversion unit, and an output signal of each pixel The first and second transfer switches connected to one end and the other end of the line, respectively, and driven and controlled by first and second transfer signals, and transferred from the pixel via the first and second transfer switches. First and second line memories that respectively store the pixel signals to be processed, first and second horizontal scanning circuits that respectively output the first and second horizontal selection signals, and the first and second horizontal scanning circuits. First and second horizontal selection switches that are driven and controlled by a selection signal, and first and second output channels that read out pixel signals via the first and second horizontal selection switches, respectively. First by the first horizontal selection signal The readout of the continuous signal at the center of the pixel by controlling the drive of the horizontal selection switch and the readout of the thinning signal for the entire area of the pixel by controlling the driving of the second horizontal selection switch by the second horizontal selection signal are as follows. A solid-state imaging device is provided which is performed simultaneously in the frames. According to this aspect, high-speed reading with improved frame rate and low power consumption can be realized while maintaining a simple configuration, and a plurality of types of signals can be read simultaneously in one frame depending on the application. Is possible.

  According to a fifth aspect of the present invention, in the fourth aspect, the pixel row selected in the readout of the central continuous signal and the pixel row selected in the readout of the thinned-out signal of the entire region are common, and For each selected pixel row, there is provided a solid-state imaging device further characterized by reading out a central pixel signal as a central continuous signal and reading out a pixel signal thinned out by a predetermined pixel as a whole region thinning signal. . According to this aspect, it is possible to simultaneously read out a plurality of types of signals corresponding to applications from a plurality of output channels in one frame.

  In a sixth aspect of the present invention, in the fourth aspect, the central row continuous signal is different from the pixel row selected in the readout of the central continuous signal and the pixel row selected in the readout of the thinned-out signal of the entire region. It is further characterized in that the read timing is made different by shifting the timing at which the first and second transfer switches are turned on between read-out of all the pixels and read-out of the entire region, thereby preventing pixel signals from being mixed on the output signal line. A solid-state imaging device is provided. According to this aspect, mixing of pixel signals on the output signal line can be prevented.

  According to the present invention, while maintaining a simple configuration, high-speed reading with improved frame rate and low power consumption are realized, and furthermore, a plurality of types of signals according to applications can be read simultaneously in one frame. A possible solid-state imaging device can be provided.

  Embodiments of the present invention will be described below with reference to the drawings.

  The solid-state imaging device according to the embodiment of the present invention reads out a plurality of types of signals according to applications at the same time. For example, when applied to an electronic camera or the like, for example, thinning-out readout of the entire pixel for image display in the finder mode and continuous readout of the center of the pixel for arithmetic processing such as AF are simultaneously performed in one frame. It is characterized by doing.

  First, FIG. 1 shows the configuration of a solid-state imaging device common to the first to fourth embodiments of the present invention and will be described in detail. However, in the third and fourth embodiments, although the details will be described later, the configuration as shown in FIG. 10 is adopted as the vertical scanning circuit 30.

  In FIG. 1, symbols P11 to Pmn (m and n are natural numbers) indicate m × n pixels arranged in a two-dimensional matrix (matrix arrangement).

  The solid-state image sensor (photoelectric conversion unit) 1 includes these plural pixels P11 to Pmn.

  The vertical scanning circuit 30 sequentially scans the lines 40-1 to 40-n, and includes a plurality of units 30-1 to 30-n corresponding to the lines 40-1 to 40-n.

  The horizontal scanning circuits 10 and 20 are for sequentially reading out the electrical signals derived from the pixels P11 to Pmn to the output signal lines 50-1 to 50-m in the horizontal direction for each pixel.

  The horizontal scanning circuits 10 and 20 include a plurality of units 10-1 to 10-m and 20-1 to 20-m corresponding to the output signal lines 50-1 to 50-m.

  In addition, although lines other than lines 40-1 to 40-n and output signal lines 50-1 to 50-m are connected to the pixels P11 to Pmn, illustration is omitted here.

  At one end of the output signal lines 50-1 to 50-m on the horizontal scanning circuit 10 side, transistors 13-1 to 13-m, line memories 12-1 to 12-m, and transistors 11-1 to 11- One set of m is arranged as shown in the figure.

  On the other hand, the other ends of the output signal lines 50-1 to 50-m on the horizontal scanning circuit 20 side are transistors 23-1 to 23-m, line memories 22-1 to 22-m, and transistors 21-2 to 21-21. As shown in the figure, one set of -m is provided.

  The transistors 13-1 to 13-m and 23-1 to 23-m transfer the signals of the pixel rows selected by the vertical scanning circuit 30 to the line memories 12-1 to 12-m and 22-1 to 22-m. And is configured to be on / off controlled by control clocks CKT1 and CKT2 (hereinafter referred to as transistors 13-1 to 13-m, 23-1). ˜23-m are referred to as “transfer switches”).

  Further, the line memories 12-1 to 12-m and 22-1 to 22-m are pixels transferred from the pixels P11 to Pmn via the transfer switches 13-1 to 13-m and 23-1 to 23-m. It consists of a capacitive element for temporarily storing signals. The transistors 11-1 to 11-m and 21-1 to 21-m serve as horizontal selection switches for selecting the pixel signals stored in the line memories 12-1 to 12-m and 22-1 to 22-m. It plays the role of

  The transistors 11-1 to 11-m and 21-1 to 21-m are configured to be turned on / off by the output signals of the horizontal scanning circuits 10 and 20 (hereinafter, the transistors 11-1 to 11-1). 11-m, 21-1 to 21-m are referred to as “horizontal selection switches”).

  In addition, an output channel CH1 for reading out pixel signals via the horizontal selection switches 11-1 to 11-m, and an output channel CH2 for reading out pixel signals via the horizontal selection switches 21-1 to 21-m. It has.

  The transfer signal described in the claims corresponds to the clocks CKT1 and CKT2, the transfer switch corresponds to the transfer switches 13-1 to 13-m, 23-1 to 23-m, etc., and the line memory refers to the line memory. 12-1 to 12-m, 22-1 to 22-m, etc., the horizontal scanning circuit corresponds to the horizontal scanning circuits 10, 20, etc., and the plurality of output channels correspond to CH1, CH2, etc. The first and second transfer signals described in the claims correspond to the clocks CKT1 and CKT2, and the first and second transfer switches are the transfer switches 13-1 to 13-m and 23-1 to 23, respectively. The first and second line memories correspond to the line memories 12-1 to 12-m, 22-1 to 22-m, etc., and the first and second horizontal scanning circuits It corresponds to the horizontal scanning circuits 10 and 20, etc., and the first and second output channels correspond to CH1, CH2, etc.

  Here, FIG. 2 shows a configuration example of each of the pixels P11 to Pmn, FIG. 3 shows a timing chart relating to the state of each signal, and the configuration and operation will be described in more detail.

  First, as shown in FIG. 2, each of the pixels P11 to Pmn includes a photodiode (hereinafter referred to as PD) 60, a transistor Tr1 for resetting the PD 60, a transistor Tr2 for amplifying the signal of the PD 60, A transistor Tr3 for reading the amplified signal to the vertical signal line is connected as shown in the figure. The current source 61 is provided for each column of the pixels P11 to Pmn, and the current source 61 and the transistor Tr2 constitute a follower amplifier. In addition, VDD is a power source. Of course, various types can be adopted as the pixels P11 to Pmn.

  In such a configuration, as shown in the timing chart of FIG. 3, when the pixel selection signal Vs1 becomes “H” level in synchronization with the fall of the vertical synchronization signal VD, the selection transistor Tr3 is turned on. . Next, when the pixel reset signal Vr1 becomes “H” level in synchronization with the fall of the pixel selection signal Vs1, the resetting transistor Tr1 is turned on and the charge of the PD 60 is reset. That is, the potential of the node N becomes the potential of the PD 60, but when reset is entered, the PD 60 is reset to the power supply level. Thereafter, when light is incident on the PD 60, it is discharged with the generated charges, and its level gradually decreases. When the pixel selection signal Vs1 becomes “H” level in the next frame, the potential of the PD 60 is read out to the vertical signal line. Note that if the pixel reset signal Vr1 is set to the “H” level again before the pixel selection signal becomes the “H” level in the next frame, the charge is reset, and the accumulation operation, that is, the shutter operation is performed again from that timing. become. The signal change in this case is indicated by a broken line in FIG.

  In the first to fourth embodiments of the present invention, it is possible to sequentially read out all the pixel pixels P11 to Pmn by the above-described configuration and operation, and to read them out by thinning them out.

  Hereinafter, with reference to the timing chart of FIG. 4, the sequential reading of all the pixels P11 to Pmn of the solid-state imaging device according to the first to fourth embodiments having the above-described configuration will be described.

  First, prior to the description of the operation, the meaning of each symbol used in FIG. 4 is defined. In FIG. 4, VD means a vertical synchronizing signal, and HD means a horizontal synchronizing signal. CKT1 means a transfer signal for controlling on / off of the transfer switches 12-1 to 12-m. CKT2 means a transfer signal for controlling on / off of the transfer switches 22-1 to 22-m.

  V 1 to Vn mean row selection signals output from the vertical scanning circuit 30. H1-1 to H1-m mean horizontal selection signals output from the units 10-1 to 10-m of the horizontal scanning circuit 10 and controlling the horizontal selection switches 11-1 to 11-m. H2-1 to H2-m mean horizontal selection signals that are output from the units 20-1 to 20-m of the horizontal scanning circuit 20 and control the horizontal selection switches 21-1 to 21-m. In addition to the above, CH1 and CH2 also mean pixel signals output from each output channel.

  When the row selection signal V1 becomes “H” level during the horizontal blanking period T1, the pixels P11 to Pm1 in the first row are selected. During this time, the transfer signals CKT1 and CKT2 are at the “H” level. Therefore, the pixel signals of the pixels P11 to Pm1 in the first row are stored in the line memories 12-1 to 12-m and 22-1 to 22-m. Thereafter, the horizontal scanning circuits 10 and 20 are operated within the horizontal effective period T2. In the horizontal scanning circuit 10, horizontal selection signals H 1-1, H 1-3,..., H 1-are sequentially from only odd-numbered horizontal scanning circuit units 10-1, 10-3,. (M-1) is output, and in synchronization with the output, the pixels P11, P31, ... stored in the odd-numbered line memories 12-1, 12-3, ..., 12- (m-1). , P (m−1) 1 pixel signals are sequentially output from the output channel CH1. The horizontal scanning circuit 20 outputs horizontal selection signals H2-2, H2-4,..., H2-m in order from only the even-numbered horizontal scanning circuit units 20-2, 20-4,. The pixel signals of the pixels P21, P41,..., Pm1 stored in the even-numbered line memories 22-2, 22-4,. Is output.

  Subsequently, when the row selection signal V2 becomes “H” level during the next horizontal blanking period T3, the pixels P12 to Pm2 in the second row are selected. During this time, the transfer signals CKT1 and CKT2 are at the “H” level. Accordingly, the pixel signals of the selected pixels P12 to Pm2 are stored in the line memories 12-1 to 12-m. Thereafter, the horizontal scanning circuits 10 and 20 are operated within the horizontal effective period T4. In the horizontal scanning circuit 10, only the odd-numbered horizontal scanning circuit units 10-1, 10-3,..., 10- (m−1) are sequentially selected, and the horizontal selection signals H1-1, H1-3, H1- (m -1) is output, and the pixels P12, P32, ... stored in the odd-numbered line memories 12-1, 12-3, ..., 12- (m-1) in synchronization with the output. , P (m−1) 2 pixel signals are sequentially output from the output channel CH1. Further, in the horizontal scanning circuit 20, horizontal selection signals H2-2, H2-4,..., H2- are sequentially arranged only from the even-numbered horizontal scanning circuit units 20-2, 20-4,. m is output, and the pixel signals of the pixels P22, P42... Pm2 stored in the even-numbered line memories 22-2, 22-4,. Will be output.

  Thereafter, as described above, the pixels from the third row to the n-th row are selected during the horizontal blanking period, and the odd-numbered column pixel signal among the pixel signals is output channel CH1 during the horizontal effective period. And even column pixel signals are output from the output channel CH2. Note that the operation timing of the horizontal scanning circuit 20 described above is 180 degrees out of phase with the operation timing of the horizontal scanning circuit 10. Therefore, when the pixel signals output from the output channels CH1 and CH2 are mixed later, the processing can be reliably performed.

  Here, the case where all the pixel signals are output using both the output channels CH1 and CH2 is shown, but it is also possible to read out all the pixel signals using only one of them.

  Hereinafter, the characteristic operations of the first to fourth embodiments will be described in detail on the premise of the configuration and operation of the solid-state imaging device as described above.

(First embodiment)
Hereinafter, the solid-state imaging device according to the first embodiment of the present invention will be described in detail with reference to FIGS. 5 to 7. 5 shows an example of the readout pattern of the thinned signal for all areas, FIG. 6 shows an example of the readout pattern of the central continuous signal, and FIG. 7 is for explaining the timing of reading out these signals simultaneously in one frame. It is a timing chart.

  In the solid-state imaging device according to the first embodiment, readout of the central continuous signal and readout of the thinned-out signal of the entire area are simultaneously performed as shown in FIGS. At this time, the row selected for reading the central continuous signal and the row selected for reading all the region thinning signals are common (in this example, the first, fourth and seventh rows are selected in order). Further, for each row, only the central pixel signal (7 to 12 columns in this example) is read as the central continuous signal, and the pixels thinned out by two pixels (in this example, 1, 4 in this example) , 7, 10, 13, 16) are read out.

  Hereinafter, a characteristic readout operation by the solid-state imaging device according to the first embodiment will be described in more detail with reference to the timing chart of FIG.

  First, prior to the description of the operation, the meaning content of each symbol used in FIG. 7 is defined.

  In FIG. 7, VD means a vertical synchronization signal. HD means a horizontal synchronization signal. CKT1 and 2 represent transfer signals for controlling on / off of the transfer switches 12-1 to 12-m and 22-1 to 22-m. V1 to Vn (here, n = 9) mean row selection signals output from the vertical scanning circuit 30. In addition to the above, CH1 and CH2 also mean pixel signals output from each output channel.

  When the operation is started, the vertical scanning circuit 30 first scans the first row along the arrangement direction of the units 30-1, 30-2,..., 30-n. That is, when the row selection signal V1 output from the vertical scanning circuit 30 becomes “H” level within the horizontal blanking period (horizontal synchronization signal HD is “L” level), the pixels P11 to Pm1 in the first row are changed. Selected.

  During this time, since the clocks CKT1 and CKT2 input to the transfer switches 13-1 to 13-m and 233-1 to 23-m are at the “H” level, the pixel signals of the selected pixels P11 to Pm1 are stored in the line memory. 12-1 to 12-m and 22-1 to 22-m.

  Thereafter, 10-1, 10-4, 10-7, 10-10, 10-13, and 10 among the units of the horizontal scanning circuit 10 within the horizontal effective period (period in which the horizontal synchronization signal HD is at "H" level). −16 outputs a horizontal selection signal, and the pixel signals of the pixels in the first, fourth, seventh, tenth, thirteenth and sixteenth columns selected from the pixels P11 to m1 in the first row are the horizontal selection switches 11-1 and 11-1. 11-4, 11-7, 11-10, 11-13, and 11-16 to be output from the output channel CH1. At the same time, a horizontal selection signal is output from 20-7 to 20-12 among the units of the horizontal scanning circuit 20 within the horizontal effective period (period in which the horizontal synchronization signal HD is at "H" level), and the first row Pixel signals of pixels in the 7th to 12th columns selected from the pixels P11 to m1 are output from the output channel CH2 via the horizontal selection switches 21-7 to 21-12.

  Thereafter, similarly, the pixels in the 4th and 7th rows are sequentially selected during the horizontal blanking period, and the selected columns (1, 4, 7, 10, 13, 16) for each row during the horizontal effective period. As shown in FIG. 5 and FIG. 6, readout is performed at the same time.

  According to the first embodiment described above, in the case of a high pixel, if a pixel signal is output at a time, there is a problem in the frame rate. By simultaneously reading out signals (for example, for AF) from different output channels in one frame, an output corresponding to the application can be easily obtained.

(Second Embodiment)
Hereinafter, the solid-state imaging device according to the second embodiment of the present invention will be described in detail with reference to FIGS. FIG. 8 shows an example of the reading pattern of the central continuous signal, and FIG. 9 is a timing chart for explaining in detail the timing of simultaneously reading the signals shown in FIGS. Hereinafter, FIG. 5 will be referred to as appropriate.

  The solid-state imaging device according to the second embodiment is characterized in that the reading of the central continuous signal and the reading of the thinned-out signal of the entire area are simultaneously performed in one frame as shown in FIG. At that time, in reading the central part continuous signal, the central part (9th and 10th rows) is read without thinning out in the vertical direction.

  Hereinafter, a characteristic readout operation by the solid-state imaging device according to the second embodiment will be described in more detail with reference to the timing chart of FIG.

  First, prior to the description of the operation, the meaning content of each symbol used in FIG. 9 is defined.

  In FIG. 9, VD means a vertical synchronizing signal. HD1 means a horizontal synchronizing signal for the whole area thinning signal, and HD2 means a horizontal synchronizing signal for the central continuous signal. CKT1 and 2 mean transfer signals for controlling on / off of the transfer switches 12-1 to 12-m and 22-1 to 22-m. V1 to Vn (here, n = 9) mean row selection signals output from the vertical scanning circuit 30. In addition to the above, CH1 and CH2 also mean pixel signals output from each output channel.

  When the operation is started, the vertical scanning circuit 30 first scans the first row along the arrangement direction of the units 30-1, 30-2,..., 30-n. That is, when the row selection signal V1 output from the vertical scanning circuit 30 becomes “H” level within the period T1, the pixels P11 to Pm1 in the first row are selected.

  During this time, since the clocks CKT1 and CKT2 input to the transfer switches 13-1 to 13-m and 233-1 to 23-m are at the “H” level, the pixel signals of the selected pixels P11 to Pm1 are stored in the line memory. 12-1 to 12-m and 22-1 to 22-m.

  Thereafter, 10-1, 10-4, 10-7, 10-10, 10-13 among the units of the horizontal scanning circuit 10 within the horizontal effective period (HD1 is “H” level period) in the thinning signal for all areas. The horizontal selection signal is output from 10-16, and the pixel signals of the pixels in the first, fourth, seventh, tenth, thirteenth, and sixteenth columns selected from the pixels P11 to m1 in the first row are the horizontal selection switch 11-1. , 11-4, 11-7, 11-10, 11-13, and 11-16, and output from the output channel CH1. On the other hand, in the horizontal scanning circuit 20, horizontal selection signals are output from 20-9 and 20-10 of each unit, and the pixel signals of the pixels in the 9th and 10th columns selected from the pixels P11 to m1 in the first row. Is output from the output channel CH2 via the horizontal selection switches 21-9 and 21-10.

  Next, the vertical scanning circuit 30 scans the second row along the arrangement direction of the units 30-1, 30-2,..., 30-n. That is, when the row selection signal V2 output from the vertical scanning circuit 30 becomes “H” level within the period T2, the pixels P12 to Pm2 in the second row are selected.

  During this time, since the clock CKT1 input to the transfer switches 13-1 to 13-m and 23-1 to 23-m is at the “L” level and CKT2 is at the “H” level, the pixels of the selected pixels P12 to Pm2 The signal is stored only in the line memories 22-1 to 22-m. Thereafter, a horizontal selection signal is output from 20-9 and 20-10 of each unit of the horizontal scanning circuit 20, and pixel signals of the pixels in the ninth and tenth columns selected from the pixels P12 to m2 in the second row are output. It is output from the output channel CH2 via the horizontal selection switches 21-9 to 21-10.

  For the third row, similarly to the second row, the pixel signals of the ninth and tenth rows are read out only from the output channel CH2. For the fourth and subsequent rows, the same operations as those for the first to third rows are repeated. Therefore, for the fourth and seventh rows, the pixel signals in the first, fourth, seventh, tenth, thirteenth and sixteenth columns from the output channel CH1 are output. The pixel signals of the ninth and tenth columns are read out from the output channel CH2. For the fifth, sixth, eighth, and ninth rows, the pixel signals in the ninth and tenth columns are read out only from the output channel CH2, and readout as shown in FIGS.

  According to the second embodiment described above, a certain degree of resolution can be achieved in both the horizontal and vertical directions. Further, in the case of a high pixel, if a pixel signal is output at a time, there is a problem in the frame rate. However, according to this embodiment, readout of a thinned signal in all areas (for example, for display) and continuous signal at the center Can be obtained easily (for example, for AF) by simultaneously reading from different output channels in one frame.

(Third embodiment)
Hereinafter, a solid-state imaging device according to the third embodiment of the present invention will be described in detail with reference to FIGS. 10 shows an example of the configuration of the vertical scanning circuit 30 employed by the solid-state imaging device according to the third embodiment, FIG. 11 shows an example of a central continuous signal readout pattern, and FIG. 12 is a timing chart for explaining in detail timings for simultaneously reading out signals as shown in FIGS. 5 and 11 in one frame. Hereinafter, FIG. 5 will be referred to as appropriate.

  In the solid-state imaging device according to the third embodiment, reading of the central continuous signal and reading of the thinned-out signal of the entire region are simultaneously performed in one frame as shown in FIG.

  Here, the vertical scanning circuit 30 shown in FIG. 10 selects and outputs either V1-1, V1-2,... Vn-1 or Vn-2 as the row selection signals V1 to Vn. , ..., 30-n. For example, the unit 30-1 includes subunits 30-1-1 and 30-1-2 and an OR circuit 30-1-3, and the output V1-1 or the subunit 30-1 of the subunit 30-1-1. -2 output V1-2 is selected by the OR circuit 30-1-3 and output as the row selection signal V1.

  Hereinafter, a characteristic readout operation by the solid-state imaging device according to the third embodiment will be described in more detail with reference to the timing chart of FIG.

  First, prior to explanation of the operation, the meaning content of each symbol used in FIG. 12 is defined. In FIG. 12, VD means a vertical synchronization signal. HD means a horizontal synchronization signal. CKT1 and 2 represent transfer signals for controlling on / off of the transfer switches 12-1 to 12-m and 22-1 to 22-m. V1 to Vn (here, n = 9) mean row selection signals output from the vertical scanning circuit 30. In addition to the above, CH1 and CH2 also mean pixel signals output from each output channel.

  When the operation is started, the vertical scanning circuit 30 first scans the first row along the arrangement direction of the units 30-1, 30-2,..., 30-n. That is, when the row selection signal V1 output from the vertical scanning circuit 30 becomes “H” level within the horizontal blanking period (horizontal synchronization signal HD is “L” level), the pixels P11 to Pm1 in the first row are selected. Is done.

  During this time, since the clock CKT1 input to the transfer switches 13-1 to 13-m is at “H” level, the pixel signals of the selected pixels P11 to Pm1 are stored in the line memories 12-1 to 12-m. Will be. Thereafter, 10-1, 10-4, 10-7, 10-10, 10-13, and 10 among the units of the horizontal scanning circuit 10 within the horizontal effective period (period in which the horizontal synchronization signal HD is at "H" level). The horizontal selection signal is output from −16, and the pixel signals of the pixels in the first, fourth, seventh, tenth, thirteenth and sixteenth columns selected from the pixels P11 to m1 in the first row are the horizontal selection switches 11-1 and 11. It is output from the output channel CH1 via −4, 11-7, 11-10, 11-13, and 11-16.

  Further, the vertical scanning circuit 30 scans the fourth row along the arrangement direction of the units 30-1, 30-2,..., 30-n within the same horizontal blanking period. That is, when the row selection signal V4 output from the vertical scanning circuit 30 becomes “H” level, the pixels P14 to Pm4 in the fourth row are selected. During this time, since the clock CKT2 input to the transfer switches 23-1 to 23-m is at “H” level, the pixel signals of the selected pixels P14 to Pm4 are stored in the line memories 22-1 to 22-m. The

  Thereafter, a horizontal selection signal is output from 20-7 to 20-12 among the units of the horizontal scanning circuit 20 within the horizontal effective period (period in which the horizontal synchronization signal HD is at “H” level), and the pixel P14 in the fourth row. The pixel signals of the pixels in the seventh to twelfth columns selected from ˜m4 are output from the output channel CH2 via the horizontal selection switches 21-7 to 21-12.

  In the third embodiment, in order to prevent the pixel signals of the vertical signal lines from being mixed, as described above, the timing of reading the central portion continuous signal and the reading of the thinned-out signal of all the regions (transfer signals CKT1, CKT2 One of the characteristics is that the “H” level) is shifted. Thereafter, similarly, the pixel signals in the 4th and 5th rows and the 7th and 6th rows are read out simultaneously from CH1 and CH2, respectively, so that the readout as shown in FIGS. At the same time.

  In this embodiment, since the same row is selected at different times for the whole region thinning signal and the central continuous signal (fourth row), the storage time may differ from other rows for that row. In that case, the entire row accumulation time can be made uniform using an electronic shutter.

  According to the third embodiment described above, a certain degree of resolution can be achieved in both the horizontal and vertical directions. Further, in the case of a high pixel, if a pixel signal is output at a time, there is a problem in the frame rate. However, according to this embodiment, readout of a thinned signal in all areas (for example, for display) and continuous signal at the center By simultaneously reading out (for example, for AF) in one frame, an output corresponding to the application can be easily obtained.

(Fourth embodiment)
Hereinafter, a solid-state imaging device according to the fourth embodiment of the present invention will be described in detail with reference to FIGS. FIG. 13 shows an example of the reading pattern of the central continuous signal, and FIG. 14 is a timing chart for explaining in detail the timing of simultaneously reading the signals shown in FIGS. Hereinafter, FIG. 5 will be referred to as appropriate.

  Also in the fourth embodiment, the configuration of FIG. 10 is adopted as the vertical scanning circuit 30.

  In the solid-state imaging device according to the fourth embodiment, reading of the central continuous signal and reading of the thinned-out signal of the entire region are simultaneously performed in one frame as shown in FIG.

  Hereinafter, a characteristic readout operation by the solid-state imaging device according to the fourth embodiment will be described in more detail with reference to the timing chart of FIG.

  First, prior to explanation of the operation, the meaning of each symbol used in FIG. 14 is defined. In FIG. 14, VD means a vertical synchronizing signal. HD means a horizontal synchronization signal. CKT1 and 2 represent transfer signals for controlling on / off of the transfer switches 12-1 to 12-m and 22-1 to 22-m. V1 to Vn (here, n = 9) mean row selection signals output from the vertical scanning circuit 30. In addition to the above, CH1 and CH2 also mean pixel signals output from each output channel.

  When the operation is started, the vertical scanning circuit 30 first scans the first row along the arrangement direction of the units 30-1, 30-2,..., 30-n. That is, when the row selection signal V1 output from the vertical scanning circuit 30 becomes “H” level within the horizontal blanking period (horizontal synchronization signal HD is “L” level), the pixels P11 to Pm1 in the first row are selected. Is done.

  During this time, since the clock CKT1 input to the transfer switches 13-1 to 13-m is at “H” level, the pixel signals of the selected pixels P11 to Pm1 are stored in the line memories 12-1 to 12-m. Will be. Thereafter, 10-1, 10-4, 10-7, 10-10, 10-13, and 10 among the units of the horizontal scanning circuit 10 within the horizontal effective period (period in which the horizontal synchronization signal HD is at "H" level). The horizontal selection signal is output from −16, and the pixel signals of the pixels in the first, fourth, seventh, tenth, thirteenth and sixteenth columns selected from the pixels P11 to m1 in the first row are the horizontal selection switches 11-1 and 11. It is output from the output channel CH1 via −4, 11-7, 11-10, 11-13, and 11-16.

  Subsequently, the vertical scanning circuit 30 scans the third row along the arrangement direction of the units 30-1, 30-2,..., 30-n within the same horizontal blanking period. That is, when the row selection signal V3 output from the vertical scanning circuit 30 becomes “H” level, the pixels P13 to Pm3 in the third row are selected. During this time, since the clock CKT2 input to the transfer switches 23-1 to 23-m is at “H” level, the pixel signals of the selected pixels P13 to Pm3 are stored in the line memories 22-1 to 22-m. The

  Thereafter, a horizontal selection signal is output from 20-7 to 20-12 among the units of the horizontal scanning circuit 20 within a horizontal effective period (period in which the horizontal synchronization signal HD is at "H" level), and the pixel P13 in the third row. The pixel signals of the pixels in the seventh to twelfth columns selected from ˜m3 are output from the output channel CH2 via the horizontal selection switches 21-7 to 21-12.

  In the fourth embodiment, in order to prevent the pixel signals of the vertical signal lines from being mixed, as described above, the timing between the readout of the central continuous signal and the readout of the thinned-out signal in all the regions (transfer signals CKT1, CKT2 One of the characteristics is that the “H” level is shifted). Thereafter, the 4th and 5th rows and the 7th and 6th rows are selected during the same horizontal blanking period, and these pixel signals are simultaneously read out from CH1 and CH2 during the horizontal effective period. Thus, readout as shown in FIGS. 5 and 13 is simultaneously performed in one frame.

  In this embodiment, since the lines to be selected are different between the whole area thinning signal and the central continuous signal, there is no phenomenon that the lines having different accumulation times described in the third embodiment are generated.

  According to the fourth embodiment described above, a certain degree of resolution can be achieved in both the horizontal and vertical directions. Further, in the case of a high pixel, if a pixel signal is output at a time, there is a problem in the frame rate. However, according to this embodiment, readout of a thinned signal in all areas (for example, for display) and continuous signal at the center By repeating the reading (for example, for AF) alternately for each frame, an output corresponding to the application can be easily obtained.

  As described above, the embodiments of the present invention have been described. However, the present invention is not limited to such as providing FPN cancellation that is normally performed in a MOS type solid-state imaging device, or mixing readout of thinned-out signals in all areas to suppress false signals. Without being limited to the above, various improvements and changes can be made without departing from the spirit of the invention.

  In the above embodiment of the present invention, the operation that can perform the thinning scanning of the horizontal scanning circuit and the vertical scanning circuit has been described. However, in order to perform such an operation, a decoder circuit is used or a shift to the scanning circuit is performed. A device using a register can be realized, for example, by the thinning scanning method described in JP-A-9-163245, and of course, all pixels can be read out sequentially by performing sequential scanning. It is.

  Here, FIG. 15 illustrates a configuration example of a shift register used in a scanning circuit for performing sequential scanning and thinning scanning.

  Here, 1/3 thinning scanning will be described as an example.

  In FIG. 15, the one-stage shift register unit 300 is composed of a first shift register unit 100 and a second shift register unit 200 that are composed of subunits 101 and 102. The input ends of the first and second shift register units 100 and 200 are connected in common. The output terminal of the first shift register unit 100 is connected to the input terminal of the next-stage shift register unit, and the output terminal of the second shift register unit 200 is the input of the subunit 102 that is two stages behind. Connected to the end. The subunits 101 and 102 of the first shift register unit are driven by drive pulses φ1-1 and φ1-2, respectively, and the second shift register unit 200 is driven by a drive pulse φ2.

  In the shift register having such a configuration, a drive signal is given to the drive pulses φ1-1 and φ1-2, and the drive pulse φ2 is set in a state in which the second shift register unit 200 is not operated, so that the shift register starts. When the pulse φST is input, the input signal is shifted in the shift register as shown by the one-dot chain line in FIG. 16, so signals are output from the shift register in the order of SRout1, SRout2, SRout3,. Can be done.

  On the other hand, in this shift register, a drive signal is given to the drive pulses φ1-2 and φ2, and the drive pulse φ1-1 is set in a state in which the subunit 101 is inoperative. Since the input signal is shifted in the shift register as shown by a one-dot chain line in FIG. 17, the signals are output from the shift register in the order of Srout3, Srout6,...

  As described above, by using the shift register having the configuration as shown in FIG. 15 in the scanning circuit and controlling the drive pulse, it is possible to switch between the sequential scanning and the thinning scanning. Since switching between sequential scanning and thinning scanning can be performed by driving pulse control, switching between sequential scanning and thinning scanning can be performed during scanning by changing the driving pulse during scanning. The effective pixel region can also be scanned by performing thinning scanning.

The block diagram of the solid-state imaging device common to the 1st thru | or 4th embodiment of this invention. The figure which shows the structural example of each pixel P11-Pmn of FIG. The timing chart of each signal regarding the structure of FIG. 6 is a timing chart regarding sequential reading of all the pixels P11 to Pmn of the solid-state imaging device according to the first to fourth embodiments of the present invention. FIG. 3 is a diagram illustrating an example of a readout pattern of a whole area thinning signal by the solid-state imaging device according to the first embodiment of the present invention. FIG. 3 is a diagram showing an example of a readout pattern of a central continuous signal by the solid-state imaging device according to the first embodiment of the present invention. 5 is a timing chart for explaining in more detail a characteristic readout operation by the solid-state imaging device according to the first embodiment of the present invention. The figure which shows the example of a read-out pattern of the center part continuous signal by the solid-state imaging device which concerns on the 2nd Embodiment of this invention. 9 is a timing chart for explaining in more detail a characteristic readout operation by the solid-state imaging device according to the second embodiment of the present invention. It is a figure which shows the structural example of the vertical scanning circuit 30 which the solid-state imaging device which concerns on the 3rd, 4th embodiment of this invention employ | adopts. The figure which shows the example of a read-out pattern of the center part continuous signal by the solid-state imaging device which concerns on the 3rd Embodiment of this invention. 10 is a timing chart for explaining in more detail a characteristic readout operation by the solid-state imaging device according to the third embodiment of the present invention. The figure which shows the example of a read-out pattern of the center part continuous signal by the solid-state imaging device which concerns on the 4th Embodiment of this invention. 10 is a timing chart for explaining in more detail a characteristic readout operation by the solid-state imaging device according to the fourth embodiment of the present invention. FIG. 5 is a diagram illustrating a configuration example of a shift register applicable as a scanning circuit that performs sequential scanning and thinning scanning in the solid-state imaging device according to the first to fourth embodiments of the present invention. FIG. 15 is a conceptual diagram illustrating sequential scanning with the configuration of FIG. 14. The conceptual diagram explaining the thinning scanning by the structure of FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Solid-state image sensor, P11-Pmn ... Pixel, 10 ... Horizontal scanning circuit, 11-1 to 11-m ... Horizontal selection switch, 12-1 to 12-m ... Line memory 13-1 to 13-m... Transfer switch, 20... Horizontal scanning circuit, 21-1 to 21-m... Horizontal selection switch, 22-1 to 22-m. -1 to 23-m... Transfer switch, 30... Vertical scanning circuit.

Claims (6)

A photoelectric conversion unit composed of a plurality of pixels arranged two-dimensionally;
A vertical scanning circuit for selecting a pixel row to be read by the photoelectric conversion unit;
A transfer switch connected to the output signal line of each of the pixels and driven and controlled by a transfer signal;
A line memory for storing pixel signals transferred from the pixels via the transfer switch;
A horizontal scanning circuit for outputting a horizontal selection signal;
A horizontal selection switch driven and controlled by the horizontal selection signal;
A plurality of output channels for reading out pixel signals via the horizontal selection switch;
A solid-state imaging device that simultaneously reads out a central pixel continuous signal and reads out a pixel thinning signal in one frame under the control of the vertical scanning circuit and the horizontal scanning circuit. The pixel row selected in the readout of the central portion continuous signal and the pixel row selected in the readout of the entire region thinning signal are common, and for each selected pixel row, the central portion is used as the central portion continuous signal. The solid-state imaging device according to claim 1, further comprising: reading out a pixel signal of a predetermined number of pixels, and reading out a pixel signal thinned out by a predetermined number of pixels as a whole region thinning signal. Unlike the pixel row selected in the central continuous signal readout and the pixel row selected in the readout of the whole area thinned signal, the timing at which the transfer switch becomes conductive between the central continuous signal readout and the whole area thinned readout is set. The solid-state imaging device according to claim 1, further comprising preventing pixel signals from being mixed on the output signal line by shifting the pixel signals. A photoelectric conversion unit composed of a plurality of pixels arranged in two dimensions, a vertical scanning circuit for selecting a pixel row to be read by the photoelectric conversion unit, and one end and the other end of the output signal line of each pixel, respectively. The first and second transfer switches that are driven and controlled by the first and second transfer signals, respectively, and the pixel signals transferred from the pixels via the first and second transfer switches are stored. First and second line memories, first and second horizontal scanning circuits that output first and second horizontal selection signals, respectively, and first and second horizontal selection signals that are driven and controlled by the first and second horizontal selection signals, respectively. 1 and a second horizontal selection switch, and first and second output channels for reading out pixel signals via the first and second horizontal selection switches,
Pixels by reading out the central continuous signal of the pixel by driving and controlling the first horizontal selection switch by the first horizontal selection signal and driving and controlling the second horizontal selection switch by the second horizontal selection signal The solid-state imaging device is characterized in that the readout of the entire region thinning signal is simultaneously performed in one frame. The pixel row selected in the readout of the central portion continuous signal and the pixel row selected in the readout of the entire region thinning signal are common, and for each selected pixel row, the central portion is used as the central portion continuous signal. 5. The solid-state imaging device according to claim 4, further comprising: reading out a pixel signal of a predetermined number of pixels, and reading out a pixel signal thinned out by a predetermined number of pixels as a whole region thinning signal. Unlike the pixel row selected in the readout of the central continuous signal and the pixel row selected in the readout of the whole region thinning signal, the first and second transfers are performed in the central portion continuous signal readout and the whole region thinning readout. The solid-state imaging device according to claim 4, further comprising: changing a timing of reading by changing a timing at which the switch is turned on to prevent mixing of pixel signals on the output signal line.

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