JP4275346B2 - Method for manufacturing semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device capable of preventing etching damage of a silicon-based semiconductor film by a resist stripping solution. The present invention also relates to a resist stripping apparatus used in the manufacturing method. In this specification, the semiconductor device refers to all semiconductor devices configured by a thin film transistor (hereinafter abbreviated as TFT), for example, an active matrix type liquid crystal display device or an organic EL (Electro-luminescence). Abbreviation) includes a semiconductor display device such as a display device in its category.
[0002]
[Prior art]
In recent years, an active matrix type liquid crystal display device in which a circuit is constituted by TFTs on a transparent insulating substrate such as a glass substrate has been mass-produced. Particularly, an active matrix type organic EL display device has recently attracted attention as a next generation semiconductor display device. ing. Conventionally, an amorphous silicon film has been applied to an active layer (island-like semiconductor layer) of a TFT which is a constituent element of these semiconductor display devices, but recently, a polycrystalline silicon film having a large field effect mobility. Has come to apply. Semiconductor display devices composed of polycrystalline silicon films have the advantage of being able to integrate not only pixel transistors but also drive circuits, which are peripheral circuits, and therefore, vigorous research has been carried out by companies involved in the development of semiconductor display devices. ing.
[0003]
In the manufacturing process of such a semiconductor display device, a dry etching process or an impurity ion doping process is performed using the resist pattern as a mask, and an ashing process or a resist stripping process is used to remove the resist pattern after these processes are completed. The resist removal process which consists of is performed.
[0004]
The resist pattern on the substrate is subjected to a plasma treatment such as dry etching or a doping treatment of impurity ions, thereby reacting a polymer constituting the resist with an etching gas or reacting with a doping impurity, and further crosslinking between the polymers. As the reaction proceeds, an altered layer that is difficult to remove is formed on the surface of the resist pattern. The altered layer has ashing resistance and tends to have a long ashing time, and an ashing rate is improved by adding a certain amount of nitrogen or hydrogen to oxygen as an ashing gas. In addition, CF is added to oxygen as an ashing gas. _Four It is known that the ashing speed can be improved by adding a halogen gas such as, but there is a problem that the base substrate is damaged in terms of the selection ratio between the resist pattern and the base substrate, so the application process is limited. It is used.
[0005]
Although the ashing speed is improved in this way, it is difficult to reliably remove the resist pattern with a desired throughput only by the ashing process. Pattern removal processing is performed. In the resist stripping step, the substrate after the ashing treatment is immersed in a processing tank filled with a resist stripping solution at a predetermined temperature (about 60 to 90 ° C.) for about 10 minutes, so that the resist stripping solution dissolves. This is used to dissolve and remove the resist pattern. In the resist stripping step, there are a batch processing method for processing a plurality of substrates at once and a single wafer processing method for sequentially processing the substrates one by one. The single wafer processing method is advantageous in reducing the area efficiency of the processing apparatus or reducing the consumption of the resist stripping solution, and is therefore used in the case of a relatively large substrate.
[0006]
By the way, in a manufacturing process of a semiconductor display device, an island-shaped semiconductor layer which is a constituent region of a source region, a drain region, or a channel region is formed using a silicon-based semiconductor film such as amorphous silicon or polycrystalline silicon. A semiconductor layer made of a silicon-based semiconductor film is patterned by dry etching. In the resist stripping process after the semiconductor layer is formed, an exposed portion of the semiconductor layer is formed by an etching process depending on the process, and the semiconductor layer and the organic resist stripping solution are in direct contact with the exposed portion. There is a case. When the semiconductor layer and the resist stripping solution are in direct contact, depending on the resist stripping solution, the resist stripping solution may contain about several percent of moisture due to the hygroscopic action of the resist stripping solution. The peeling liquid becomes strongly alkaline, and a semiconductor layer made of a silicon-based semiconductor film is damaged by etching, and in an extreme case, a phenomenon that the semiconductor layer disappears by etching is a serious problem. Etching damage in this specification refers to a phenomenon in which a silicon-based semiconductor film that should remain is etched by a resist stripping solution, and the remaining film thickness becomes thinner than a desired remaining film thickness.
[0007]
Against this background, various countermeasure technologies have been published by related industries from the viewpoint of improving the process of resist stripping solution materials and semiconductor display devices as countermeasures for the problem, and the main countermeasure technologies are summarized below. Describe.
[0008]
First, as a countermeasure technique relating to the material of the resist stripping solution, for example, JP 2000-241991 A discloses stripping for a photoresist containing alkanolamines, saccharides, a water-soluble organic solvent, benzotriazole or a derivative thereof, and water. A liquid composition and a photoresist stripping method using the stripping liquid composition ”are disclosed. JP-A-2001-183849 discloses “hydroxylamines, aromatic hydroxy compounds and benzotriazole or derivatives thereof, and amines having an acid dissociation constant (pKa) in an aqueous solution at 25 ° C. of 7.5 to 13, And a photoresist stripping composition comprising a water-soluble organic solvent and / or water, and a photoresist stripping method using the stripping composition ”. Further, JP 2001-188363 A discloses a photoresist stripping solution containing a nitrogen-containing organic hydroxy compound, a water-soluble organic solvent, water and a specific benzotriazole compound, and a photoresist stripping method using the stripping solution. Is disclosed. JP-A-2001-209190 discloses "primary, secondary or tertiary alkylamine or primary, secondary or tertiary alkanolamine, polar organic solvent, water, 2,3,6-trimethylphenol or A photoresist stripping composition mainly comprising one or a mixture of 2,4-di-tert-butylphenol and a method of using the photoresist stripping composition is disclosed.
[0009]
Further, as a countermeasure technique for process improvement of a semiconductor display device, Japanese Patent Laid-Open No. 2001-308342 discloses that “a surface oxide layer is formed on a surface of a semiconductor film formed on a substrate by bringing ozone-containing water into contact therewith”. A step of forming a mask having a predetermined pattern on the semiconductor film, a step of performing any treatment selected from etching and doping of impurity ions using the mask, and at least an exposed surface of the semiconductor film And a step of removing the mask in a state in which the surface oxide layer is formed.
[0010]
[Problems to be solved by the invention]
15A and 15B are a cross-sectional view and a plan view showing the structure of an n-channel TFT which is a constituent element of the semiconductor display device. In FIG. 15, a base film 702 made of a silicon oxynitride film having a predetermined thickness is deposited on a glass substrate 701, and an n-channel TFT is formed on the base film 702. The n-channel TFT includes a semiconductor layer 703 made of a silicon-based semiconductor film having a predetermined thickness, a gate insulating film 704 made of a silicon oxide film having a predetermined thickness, and a refractory metal film having a predetermined thickness (specifically, A gate electrode 705 made of a (W film) is formed so as to be laminated in order from the glass substrate 701 side. The semiconductor layer 703 made of a silicon-based semiconductor film has a channel region 706 that is a substantially intrinsic region located directly below the gate electrode 705 and an n-type conductivity type that is located on both sides of the channel region 706. A source region (n + region) 707 and a drain region (n + region) 708 are arranged. Further, on the surface of the TFT, a first interlayer insulating film 709 having a predetermined thickness made of an inorganic film and a second interlayer insulating film 710 made of an organic resin film such as an acrylic resin film are laminated thereon, and these Contact holes 711a and 712a are formed so as to penetrate the stacked film and reach the source region (n + region) 707 and the drain region (n + region) 708, respectively. Conductive metal wirings 711b and 712b are patterned so as to bury the contact holes 711a and 712a. The first interlayer insulating film 709 is formed on the entire surface after forming the gate electrode 705 on the semiconductor layer 703 made of a silicon-based semiconductor film with the gate insulating film 704 interposed therebetween. And the like, a silicon nitride film or a silicon oxynitride film, which is an inorganic film having a predetermined thickness, is preferable. On the other hand, the second interlayer insulating film 710 is preferably an organic resin film such as an acrylic resin film which is advantageous in terms of flatness and translucency (see FIG. 15).
[0011]
In the process of forming the contact holes 711a and 712a of the n-channel TFT as shown in FIG. 15, the resist pattern and the underlying organic resin film are removed in the process of removing unnecessary resist patterns after the dry etching process. Since the selection ratio with the second interlayer insulating film 710 cannot be secured, it is impossible to apply the ashing process. Accordingly, the resist is removed only by the resist stripping process using the organic resist stripping solution. However, since the silicon-based semiconductor film is exposed at the bottoms of the contact holes 711a and 712a, the silicon-based semiconductor film and the resist stripping solution are removed. In some cases, the silicon-based semiconductor film is directly contacted, and etching damage of the silicon-based semiconductor film occurs from the contact portion. When etching damage of the silicon-based semiconductor film occurs at the bottoms of the contact holes 711a and 712a, the silicon-based semiconductor film in the source region (n + region) 707 and the drain region (n + region) 708 near the bottoms of the contact holes 711a and 712a. Since the film thickness fluctuates, it becomes a cause of variation in contact resistance, and finally affects variation in the electrical characteristics of the TFT. In addition, if the silicon-based semiconductor film disappears at the bottom of the contact holes 711a and 712a, the yield of the semiconductor device is affected. As described above, the etching damage and etching loss of the silicon-based semiconductor film at the bottoms of the contact holes 711a and 712a greatly affect the electrical characteristics and the yield of the semiconductor device, which is a serious process problem.
[0012]
As a countermeasure technique against etching damage of a silicon-based semiconductor film, for example, a silicon-based material is disclosed in Japanese Patent Laid-Open Nos. 2000-241991, 2001-183849, 2001-188363, 2001-209190, and the like. Although organic resist stripping solutions effective for preventing etching damage to semiconductor films have been disclosed, it is possible to take measures against etching damage to silicon-based semiconductor films, but there are often problems with the essential resist stripping properties. It is recognized that there is no resist stripper that satisfies both the stripping performance and the etching damage prevention performance of the silicon-based semiconductor film. Therefore, from the viewpoint of improving the process of the semiconductor device, it is required to take measures to prevent etching damage of the silicon-based semiconductor film.
[0013]
An object of the present invention is to solve the above-described problems of the prior art. More specifically, an object of the present invention is to provide a method for manufacturing a semiconductor device capable of preventing etching damage of a silicon-based semiconductor film by a resist stripping solution, and a resist stripping apparatus used in the manufacturing method. .
[0014]
[Means for solving the problems]
In order to solve the above problems, an invention relating to a manufacturing method of a semiconductor device and an invention relating to a resist stripping apparatus used in the manufacturing method are conceivable.
[0015]
[Invention relating to a method for manufacturing a semiconductor device]
The configuration of the present invention includes a first step of forming a silicon-based semiconductor film on the surface of a substrate, and a second step of forming a semiconductor layer to be an active layer of a thin film transistor by patterning the silicon-based semiconductor film, A third step of depositing a gate insulating film so as to cover the semiconductor layer; a fourth step of depositing a gate electrode film on the gate insulating film; and patterning the gate electrode film to form a gate electrode A sixth step of forming a source region and a drain region in the semiconductor layer corresponding to the outside of the gate electrode by doping an impurity element of one conductivity type, and a step of forming the gate electrode A seventh step of depositing a first interlayer insulating film so as to cover; an eighth step of depositing a second interlayer insulating film on the first interlayer insulating film; and the second interlayer insulating. Resist pattern on film Forming a contact hole by dry-etching the laminated film composed of the gate insulating film, the first interlayer insulating film and the second interlayer insulating film using the resist pattern as a mask In the method for manufacturing a semiconductor device comprising the tenth step of performing and an eleventh step of stripping the resist pattern with an organic resist stripper, the eleventh step includes the contact hole as a pretreatment. A protective film for the resist stripping solution is formed on the exposed surface of the silicon-based semiconductor film at the bottom of the substrate.
[0016]
Another configuration of the present invention includes a first step of forming a silicon-based semiconductor film on the surface of the substrate, a second step of performing an etching process using the resist pattern as a mask, and a pre-processing of the silicon-based semiconductor film. And a third step of forming a protective film against an organic resist stripping solution on the exposed surface and stripping the resist pattern with the resist stripping solution. In other words, a first step of forming a silicon-based semiconductor film on the surface of the substrate, a second step of performing an etching process using the resist pattern as a mask, and stripping the resist pattern with an organic resist stripping solution In the method of manufacturing a semiconductor device including the third step, the third step includes forming a protective film against the resist stripping solution on the exposed surface of the silicon-based semiconductor film as a pretreatment. It is a feature.
[0017]
In the invention having the above structure, the substrate includes not only a glass substrate or a quartz substrate whose semiconductor device fabrication surface is a flat surface, but also a glass body or a quartz body whose fabrication surface is a curved surface, and further a film-like structure. This category also includes other plastic substrates. The silicon-based semiconductor film includes an amorphous semiconductor film containing silicon, a polycrystalline semiconductor film containing silicon obtained by heat-treating an amorphous semiconductor film containing silicon, or a catalytic element having a crystallization promoting action. A typical example is a crystalline semiconductor film containing silicon obtained by heat treatment after addition of silicon, but any thin film containing semiconductor characteristics containing silicon may be used. Note that in this specification, technical terms such as an amorphous semiconductor film containing silicon, a polycrystalline semiconductor film containing silicon, and a crystalline semiconductor film containing silicon are used separately. Clarify the definition. The amorphous semiconductor film containing silicon is a semiconductor film containing silicon in an amorphous state having semiconductor characteristics, and naturally includes an amorphous silicon film. All included. For example, Si _x Ge _1-x An amorphous film made of a compound of silicon and germanium described in the form (0 <X <1) is also included. In addition, a crystalline semiconductor film containing silicon is a crystalline semiconductor film obtained by adding a catalytic element having a crystallization promoting action to an amorphous semiconductor film containing silicon. Compared with a crystalline semiconductor film, crystal grains are oriented in the same direction and have high field-effect mobility. It is described as a semiconductor film.
[0018]
In the invention having the above structure, as the first interlayer insulating film, a silicon nitride film or a silicon oxynitride film having a thickness of 50 to 300 nm, preferably 100 to 200 nm, is deposited by plasma CVD. ing. The first interlayer insulating film is formed for the purpose of hydrogenating the active layer of the TFT by hydrogen present in the film during the heat treatment after deposition and for blocking alkali metals such as moisture and Na element from the upper layer film. Has been. Further, as the second interlayer insulating film, an organic resin film having a film thickness of 0.7 to 3 μm, preferably 1 to 2 μm, is applied by spin coating, and then baked at a predetermined temperature. It is filming. The second interlayer insulating film is formed for the purpose of reducing the electric capacity of the interlayer film and planarizing the substrate, and is made of an acrylic resin film, a polyimide resin film, or a BCB (benzocyclobutene) resin film as a material. In particular, an acrylic resin film is a preferred example of the organic resin film in terms of transparency.
[0019]
In the step of forming a contact hole in the laminated film of the interlayer insulating film having such a structure (that is, the first interlayer insulating film and the second interlayer insulating film) and the gate insulating film made of the silicon oxide film as the base film. In this case, the ashing process cannot be applied when removing the unnecessary resist pattern after the dry etching process. The reason is that in the ashing process, the selection ratio cannot be ensured between the resist pattern and the second interlayer insulating film made of the underlying organic resin film. For this reason, the removal process of the said resist pattern will be performed only by the resist stripping process by an organic type resist stripping solution.
[0020]
In the invention having the above-described configuration, an organic resist stripping solution is generally used as the resist stripping solution, and there is no particular limitation on the material as long as it is an organic resist stripping solution. Since the object of the invention is to prevent etching damage of the silicon-based semiconductor film due to the formation of a protective film, it exhibits strong alkalinity due to water mixing into the resist stripping solution and has an etching effect on the silicon-based semiconductor film. The present invention is effective in the case of using a resist stripping solution. In this respect, the resist stripping solution is mainly a resist stripping solution that exhibits strong alkalinity due to water mixing into the resist stripping solution and has an etching action on the silicon-based semiconductor film. The resist stripping step using the resist stripping solution includes a resist stripping solution treatment step using a resist stripping solution held at a predetermined temperature (about 60 to 90 ° C.) and isopropyl alcohol (hereinafter referred to as IPA for cleaning the resist stripping solution). And an IPA treatment step and a water washing step. Although the IPA treatment step can be omitted as long as there is no harmful effect, it prevents the formation of a mixture of a resist stripping solution and pure water at the time of washing in the vicinity of the surface of the substrate. In general, it is preferable to introduce an IPA treatment step because it works to prevent etching damage to the silicon-based semiconductor film and metal wiring exposed on the surface of the substrate.
[0021]
In the invention having the above-described configuration, the protective film for protecting the exposed portion of the silicon-based semiconductor film needs to be resistant to erosion to the resist stripping solution that has become strongly alkaline due to the hygroscopic action of the resist stripping solution. A silicon oxide film with a film thickness of about 0.5 to 5 nm is preferable in terms of simplicity of the film formation method, but is not limited to a silicon oxide film, and a silicon oxynitride film with a film thickness of about 0.5 to 5 nm A silicon nitride film is also applicable. The silicon oxide film can be easily formed by a cleaning process using ozone-containing water or hydrogen peroxide solution, or can be easily formed by irradiating ultraviolet rays in an atmosphere containing oxygen to generate ozone. In addition, since the silicon oxynitride film directly oxynitrides the exposed surface of the silicon-based semiconductor film, it is difficult to form the film, but basically a reactive gas containing nitrogen atoms and oxygen atoms is used. The oxynitriding treatment can be applied by plasma treatment in an atmosphere, for example, a nitrogen oxide atmosphere. The silicon nitride film can be similarly nitrided by plasma treatment in a reactive gas atmosphere containing nitrogen atoms and no oxygen atoms, for example, in an ammonia gas atmosphere.
[0022]
According to the invention configured as described above, in the resist stripping step after etching, the silicon oxide film or silicon oxynitride film having a film thickness of about 0.5 to 5 nm is formed before the stripping treatment with the resist stripping solution. A protective film made of a silicon nitride film can be formed on the bottom of the contact hole that is the exposed portion of the silicon-based semiconductor film. Since these protective films are formed by oxidizing, oxynitriding or nitriding the surface of the silicon-based semiconductor film at the bottom of the contact hole, they are selectively formed on the exposed portions of the silicon-based semiconductor film. . Further, it has been found that these protective films have an overwhelmingly higher resistance to erosion against strong alkali than silicon based semiconductor films. Therefore, the present invention can surely prevent the etching damage or disappearance of the silicon-based semiconductor film at the bottom of the contact hole due to the organic resist stripping solution, and can stabilize the electrical characteristics and yield of the semiconductor device. It is effective for improvement.
[0023]
[Invention relating to resist stripping apparatus]
The structure of the present invention comprises a film forming means for forming a protective film against a resist removing solution on the surface of a substrate and a resist removing solution treatment for removing the resist pattern formed on the surface of the substrate with the resist removing solution. And a means. In this case, the apparatus includes a (IPA treatment means) washing means for washing the resist stripping solution adhering to the surface of the substrate and a drying means for drying the substrate. Yes. The reason why the IPA processing means is described in parentheses is that, in some cases, a configuration in which the processing means is omitted is also applicable.
[0024]
In the configuration of the above invention, the resist stripping solution processing means and the water washing means (and the IPA processing means) may be configured as a batch processing type processing tank for collectively processing a plurality of substrates. Alternatively, a single-wafer processing type continuous processing tank or a spin processing unit for sequentially processing the substrates one by one may be used. In addition, the drying means may be configured by a spin drying unit or IPA vapor drying unit that is a batch processing type drying unit, or may be configured by a spin drying unit or an air knife drying unit that is a single wafer processing type drying unit. You may do it. In addition, each processing means of the resist stripping apparatus is configured by a batch processing method or a single wafer processing method. However, for the convenience of substrate processing, mixed processing for each of the batch processing method and the single wafer processing method is avoided. Is preferred. That is, it is preferable from the standpoint of the apparatus configuration that the processing means of the resist stripping apparatus are unified by the batch processing method or unified by the single wafer processing method.
[0025]
In the configuration of the above invention, examples of the film forming means include a silicon oxide film forming part, a silicon oxynitride film forming part, and a silicon nitride film forming part. As a silicon oxide film forming unit, an ozone-containing water treatment unit for treating a substrate with ozone-containing water, a hydrogen peroxide solution treatment unit for treating a substrate with hydrogen peroxide solution, or an atmosphere containing oxygen In the above, an ultraviolet irradiation processing unit for performing ultraviolet irradiation processing on the substrate is representative, but other configurations may be used. In any processing section, a silicon oxide film having a thickness of about 0.5 to 5 nm can be formed on the exposed surface of the silicon-based semiconductor film by a simple method. Note that either the batch processing method or the single wafer processing method may be applied to the ozone-containing water processing unit, the hydrogen peroxide solution processing, and the ultraviolet irradiation processing unit, which are specific processing units of the silicon oxide film forming unit. On the other hand, the silicon oxynitride film forming unit, which is another film forming means, is composed of a plasma processing unit that performs plasma processing on a substrate in an atmosphere of a reactive gas containing nitrogen atoms and oxygen atoms, for example, an atmosphere of nitrogen oxides. In addition, the silicon nitride film forming unit is configured by a plasma processing unit that performs plasma processing on a substrate in an atmosphere of a reactive gas containing nitrogen atoms but not oxygen atoms, for example, in an atmosphere of ammonia gas. By performing plasma processing in these plasma processing units, the surface of the exposed silicon-based semiconductor film can be subjected to oxynitriding or nitriding, and a silicon oxynitride film or silicon nitride film having a thickness of about 0.5 to 5 nm Can be formed.
[0026]
The device configuration of the silicon oxynitride film forming unit and the plasma processing unit of the silicon nitride film forming unit may be a batch processing method or a single wafer processing method, and either processing method may be adopted. It is necessary to unify with the processing method of other processing means.
[0027]
According to the invention configured as described above, it is possible to perform the protective film forming step before the resist stripping and the resist stripping step in a continuous process, and the silicon-based semiconductor film by the resist stripping solution in the resist stripping step Etching damage can be reliably prevented. The resist stripping apparatus capable of continuous processing is also effective in terms of processing capability in the resist stripping process.
[0028]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be specifically described with reference to FIGS.
[0029]
Embodiment 1
In the present embodiment, a case where the resist stripping process of the present invention is applied to a contact hole forming process which is a TFT manufacturing process will be described with reference to FIGS. 1 and 2 are process cross-sectional views showing a TFT manufacturing process, FIG. 3 is a process cross-sectional view showing a process for forming a polycrystalline silicon film, and FIG. 4 is a crystalline silicon film obtained using a catalytic element. It is process sectional drawing which shows this film-forming process.
[0030]
First, a silicon-based semiconductor film 102 having a thickness of 20 to 200 nm, preferably 30 to 70 nm, is formed on the glass substrate 101 by a plasma CVD method or a low pressure CVD method. In this embodiment, the silicon-based semiconductor film 102 with a film thickness of 50 nm is formed by the plasma CVD method. A natural oxide film having a thickness of 5 nm or less (not shown) is formed on the surface of the silicon-based semiconductor film 102 when the silicon-based semiconductor film 102 is formed (see FIG. 1A).
[0031]
Here, the category of the silicon-based semiconductor film 102 includes an amorphous semiconductor film containing silicon and a polycrystalline semiconductor film containing silicon obtained by heat-treating an amorphous semiconductor film containing silicon, as already described. Since a crystalline semiconductor film containing silicon obtained by adding a catalytic element having a promoting action for crystallization and then heat-treating is included, a method for forming each silicon-based semiconductor film 102 is described in detail with reference to FIGS. It describes. In this embodiment, an amorphous silicon film containing silicon includes an amorphous silicon film, a polycrystalline semiconductor film containing silicon, a polycrystalline silicon film, and a crystalline semiconductor film containing silicon. A quality silicon film is described.
[0032]
As shown in FIG. 3, the polycrystalline silicon film 102f is formed by depositing an amorphous silicon film 102b having a predetermined thickness (for example, 53 nm) on a glass substrate 102a by a plasma CVD method or a low pressure CVD method. The natural oxide film 102c adhering to the substrate is removed by dilute hydrofluoric acid cleaning, and then a polycrystalline silicon film 102f is formed through a thermal crystallization process (polycrystalline silicon film 102d) and a laser crystallization process in a furnace. To do. On the other hand, as shown in FIG. 4, a crystalline silicon film 102m obtained by using a catalytic element is obtained by applying an amorphous silicon film 102h having a predetermined film thickness (for example, 53 nm) on a glass substrate 102g by plasma CVD or low pressure CVD. The natural oxide film 102i deposited by the method is removed by dilute hydrofluoric acid cleaning, and a clean silicon oxide film 102j having a thickness of about 0.5 to 5 nm is removed by ozone-containing water treatment. A film is formed on the crystalline silicon film 102h. Thereafter, a solution containing a catalytic element having a promoting action of crystallization (hereinafter abbreviated as a catalytic element solution) is added to the entire surface of the amorphous silicon film 102h (strictly, the silicon oxide film 102j) by spin addition. A catalytic element-containing layer 102k is uniformly attached to the surface of the oxide film 102j, and then a crystalline silicon film 102m is formed through thermal crystallization processing (crystalline silicon film 102l) and laser crystallization processing in a furnace. To do. Here, the crystalline silicon film 102m is characterized in that the crystal grains are oriented in substantially the same direction as compared with the normal polycrystalline silicon film 102f and has high field effect mobility. However, it is described separately from the polycrystalline semiconductor film 102f. In addition, the amorphous silicon films 102b and 102h, which are starting materials for the polycrystalline silicon film 102f and the crystalline silicon film 102m, are amorphous silicon films in which no fine crystallized regions exist (see FIG. 3-4).
[0033]
A natural oxide film (not shown) is formed on the surface of the silicon-based semiconductor film 102 as described above, and the natural oxide film (not shown) is removed by dilute hydrofluoric acid treatment. Thereafter, a silicon oxide film 103 having a thickness of about 0.5 to 5 nm is formed on the surface of the silicon-based semiconductor film 102 by treatment with ozone-containing water. The silicon oxide film 103 maintains the cleanliness of the surface of the silicon-based semiconductor film 102 in order to improve the adhesion of the resist pattern to be formed next, to improve the hydrophobicity of the silicon-based semiconductor film 102 and to prevent contamination. In this case, the film is formed for the purpose of reducing the interface state, but it also has a function of preventing etching damage from the organic resist stripping solution. In this embodiment, the silicon oxide film 103 having a film thickness of about 0.5 to 5 nm is formed by treatment with ozone-containing water, but it may be treated with hydrogen peroxide water or an atmosphere containing oxygen. It is also possible to generate ozone by irradiating ultraviolet rays therein and oxidize the surface of the silicon-based semiconductor film 102 by an oxidizing action by ozone. Thereafter, a resist pattern 104 having a predetermined dimension is formed by a normal photolithography process (see FIG. 1-B).
[0034]
Next, using the resist pattern 104 as a mask, the silicon semiconductor film 102 and the silicon oxide film 103 which is the surface layer film are dry-etched to form an island-shaped semiconductor layer 105 made of the silicon semiconductor film 102 with a thickness of 50 nm. To do. The semiconductor layer 105 is an island-shaped region that becomes an active layer of the TFT, and is a region where a source region and a drain region of the TFT are formed later. When forming the semiconductor layer 105, an RIE type dry etching apparatus is used, and CF, which is an etching gas, is used. _Four And O ₂ Since the dry etching process is performed under an etching condition with a gas flow ratio of 50:45, a resist pattern receding phenomenon occurs during the dry etching process, and the semiconductor layer 105 that is an etched film is tapered and etched. A forward tapered shape is formed on the side wall. The sidewall portion of the forward-tapered semiconductor layer 105 contains oxygen in the etching gas, so that there is almost no adhesion of the sidewall protective polymer during dry etching, and the surface of the silicon-based semiconductor film is exposed (or (Some silicon oxide films may also be formed). Note that the reason for taper-etching the semiconductor layer 105 is to improve the coverage with a step portion of a gate insulating film or a gate electrode film formed in a later process (see FIG. 1C).
[0035]
Next, in order to remove the resist pattern (not shown) after the dry etching, an ashing process that is an oxygen plasma process is performed. The ashing process employs a half ashing method in which about half of the resist pattern is ashed. For this reason, the resist pattern (not shown) after the ashing process is thinned by about half, and the resist pattern shape is deformed. During this ashing process, a silicon-based semiconductor film is exposed on the side wall portion of the semiconductor layer 105 having a forward taper shape, and thus a silicon oxide film 106 having a thickness of about 0.5 to 5 nm is formed. The The silicon oxide film 106 has a function of preventing etching damage from the resist stripping solution during the resist stripping solution process in the next step (see FIG. 1-C).
[0036]
Next, in order to completely remove the remaining resist pattern (not shown), a resist stripping process using an organic resist stripper is performed. The resist stripping process includes a resist stripping solution process, an IPA cleaning process, a water cleaning process, and a drying process. The resist remover treatment is a treatment for completely removing the resist pattern by treating with a resist remover kept at a temperature of about 60 to 90 ° C. for a predetermined time (about 10 minutes). After the resist remover treatment, the resist remover adhering to the substrate surface is replaced with IPA by performing an IPA cleaning treatment. The IPA cleaning process can be omitted only if it is omitted and there is no harmful effect. However, the IPA cleaning process has an effect of preventing generation of a mixed solution of a resist stripping solution and pure water at the time of washing in the vicinity of the substrate surface. In order to prevent the etching damage to the silicon-based semiconductor film and the metal wiring exposed on the substrate, it is generally preferable to introduce the IPA cleaning process. After the IPA cleaning treatment, a water washing treatment for a predetermined time is performed to thoroughly wash the IPA and resist stripping solution adhering to the substrate, and finally the substrate is dried. In the resist stripping step, since the silicon-based semiconductor film is not exposed, a protective film for resist stripping solution is basically formed on the exposed surface of the silicon-based semiconductor film, which is a specific matter of the present invention. No processing is required (see FIG. 1-C).
[0037]
Next, the substrate is washed with dilute hydrofluoric acid for a predetermined time, so that the silicon oxide film 103 having a film thickness of about 0.5 to 5 nm formed on the surface and side wall portion of the semiconductor layer 105 made of a silicon-based semiconductor film. , 106 are removed. Thereafter, a gate insulating film 107 made of a silicon oxide film or a silicon oxynitride film having a thickness of 30 to 200 nm, preferably 80 to 130 nm is deposited by plasma CVD or low pressure CVD so as to cover the semiconductor layer 105. . In this embodiment, a gate insulating film 107 made of a silicon oxide film having a thickness of 100 nm is deposited by plasma CVD. It is known that the thickness of the gate insulating film 107 needs to be 80 nm or more in order to avoid stress from the upper gate electrode film formed in a later process. (See FIG. 1-D).
[0038]
Next, in order to deposit an electrode material for the gate electrode, an aluminum alloy film having a film thickness of 200 to 600 nm, preferably 300 to 500 nm, or a laminated film of a refractory metal and a refractory metal compound is formed by sputtering. accumulate. Examples of the aluminum-based alloy film include alloys containing about 1 to 3% of copper (Cu), scandium (Sc), neodymium (Nd), etc. in the main component aluminum (Al). Examples of the laminated film with the metal compound include a W film / TaN film. In this embodiment, an aluminum alloy film having a copper content of 0.5% is deposited with a thickness of 40 nm. The aluminum-based alloy film deposited here has a characteristic of low electric resistance because the specific resistance value of aluminum is 2.5 to 3.55 μΩcm in the temperature range of 0 to 100 ° C. For this reason, in a semiconductor display device constituted by TFTs, it is effective in suppressing signal delay of the gate wiring (see FIG. 1-E).
[0039]
Next, a resist pattern (not shown) having a predetermined dimension is formed by a normal photolithography process, and then a gate electrode film made of an aluminum-based alloy film having a thickness of 40 nm is dried using the resist pattern (not shown) as a mask. Etching is performed to form a gate electrode 108 having a predetermined size. In the dry etching process, an RIE type dry etching apparatus is applied, and at the time of the dry etching process, the gate insulating film 107 made of a silicon oxide film is reduced to some extent in relation to the selection ratio. It is deformed to 109 shape. Thereafter, an ashing process and a resist stripping process are performed in order to remove an unnecessary resist pattern (not shown). The ashing process and the resist stripping process are basically the same as the already described process for forming the semiconductor layer 105 (see FIG. 1-E).
[0040]
Next, using a doping apparatus, a high dose n-type impurity composed of P (ie, phosphorus) element is doped using the gate electrode 108 as a mask. By the doping process, high-concentration impurity regions (n + regions) 110 and 111 of n-type impurities functioning as a source region and a drain region are formed in the semiconductor layer 105 corresponding to the region outside the gate electrode 108. At this time, in the formation of the n-type impurity high-concentration impurity regions (n + regions) 110 and 111, doping is performed through the gate insulating film 109 which is an upper layer film by a so-called through doping method. As doping conditions, phosphine (PH _Three ) 3-20% dilution of phosphine (PH _Three ) / Hydrogen (H ₂ ) At an acceleration voltage of 30 to 90 kV and a dose of 6 × 10 ¹⁴ ~ 1.5 × 10 ¹⁶ atoms / cm ² In this embodiment, phosphine (PH _Three ) 5% diluted phosphine (PH _Three ) / Hydrogen (H ₂ ), Acceleration voltage 65 kV, dose amount 3 × 10 ¹⁵ atoms / cm ² (See FIG. 1-E).
[0041]
Next, a first interlayer insulating film 113 made of a silicon nitride film or silicon oxynitride film having a thickness of 50 to 300 nm, preferably 100 to 200 nm is deposited. In this embodiment, a first interlayer insulating film 113 made of a silicon nitride film having a thickness of 150 nm is deposited by plasma CVD. Thereafter, in order to thermally activate the n-type impurity (P element) doped in the semiconductor layer 105, a heat activation process is performed at 600 ° C. for 12 hours in a furnace. The thermal activation process may be performed before the deposition of the first interlayer insulating film 113, but an aluminum-based alloy film having a low electrical resistance is used for the gate electrode, and the heat resistance of the gate electrode material is low. Since it is weak, it is preferably performed after the first interlayer insulating film 113 is deposited. Subsequent to the thermal activation treatment, hydrogenation treatment at 410 ° C. for 1 hour is performed in a nitrogen atmosphere containing 3% hydrogen (see FIG. 1-F) in order to terminate dangling bonds in the semiconductor layer 113.
[0042]
Next, a second interlayer insulating film 114 made of a transparent organic resin film having a thickness of 0.7 to 3 μm, preferably 1 to 2 μm is formed on the first interlayer insulating film 113. In the present embodiment, the second interlayer insulating film 114 made of an acrylic resin film having a thickness of 1.6 μm is formed. The acrylic resin film is formed by applying an acrylic resin film by a spin coating method, performing pre-baking, and then performing a heat treatment in an oven baking furnace. Thereafter, a resist pattern 115a for forming a contact hole is formed by a normal photolithography process (see FIG. 2-A).
[0043]
Next, dry etching is performed using the resist pattern 115a as a mask, and the second interlayer insulating film 114 made of an acrylic resin film, the first interlayer insulating film 113 made of a silicon oxynitride film, and the lower silicon oxide film A contact hole 116 having a predetermined size is formed so as to penetrate the gate insulating film 109 formed. The dry etching process uses an RIE type dry etching apparatus, and CF _Four The acrylic resin film as the second interlayer insulating film 114 is etched by oxygen plasma treatment with the addition of CHF, and then CHF _Three The silicon oxynitride film that is the first interlayer insulating film 113 and the silicon oxide film that is the gate insulating film 109 are etched by plasma treatment. Note that after the dry etching process, the surface of the silicon-based semiconductor film that is the semiconductor layer 105 is exposed at the bottom of the contact hole 116. Further, the resist pattern 115a that has become a mask for the dry etching process is deformed into the shape of the resist pattern 115b in which the film thickness has greatly decreased (see FIG. 2-B).
[0044]
Next, in order to remove the resist pattern 115b after the dry etching, a resist stripping process using an organic resist stripper is performed. The resist pattern removing process usually includes an ashing process and a resist stripping process. However, if the ashing process is applied in the removing process, the acrylic resin film as the second interlayer insulating film 114 is also removed by ashing at the same time. In the removal process, the resist pattern 115b is removed only by the resist peeling process. Therefore, no silicon oxide film is formed on the surface of the silicon-based semiconductor film exposed at the bottom of the contact hole 116 by ashing. For this reason, at the time of resist stripping treatment, the silicon-based semiconductor film exposed at the bottom of the contact hole 116 is in direct contact with the resist stripping solution. It is necessary to form a protective film against the resist stripping solution. As the protective film, erosion resistance to the resist stripping solution that has become strongly alkaline due to the hygroscopic action of the resist stripping solution is necessary. For example, a silicon oxide film having a thickness of about 0.5 to 5 nm is a typical example. In this embodiment, the silicon oxide film 117 having a thickness of about 0.5 to 5 nm is formed by treatment with ozone-containing water. Further, the silicon oxide film 117 having a thickness of about 0.5 to 5 nm may be formed by treatment with hydrogen peroxide water, or ozone is generated by irradiating ultraviolet rays in an atmosphere containing oxygen. The film may be formed by performing (see FIG. 2-C).
[0045]
As a protective film other than the silicon oxide film 117 having a thickness of about 0.5 to 5 nm, a silicon oxynitride film and a silicon nitride film having a thickness of about 0.5 to 5 nm are also candidates. Silicon oxynitride films and silicon nitride films are difficult to form because the surface of the exposed silicon-based semiconductor film is directly oxynitrided or nitrided. Oxynitriding treatment or nitriding treatment can be performed by plasma treatment in an atmosphere of a reactive gas. In the case of a silicon oxynitride film, oxynitridation can be performed by plasma treatment in an atmosphere of a reactive gas containing nitrogen atoms and oxygen atoms, for example, in an atmosphere of nitrogen oxides. In the case of a silicon nitride film, nitriding can be performed by plasma treatment in an atmosphere of a reactive gas containing nitrogen atoms and no oxygen atoms, for example, in an atmosphere of ammonia gas. At this time, the temperature of the plasma treatment is preferably higher in terms of film formation speed, but if it is too high, the resist pattern is altered and it is expected that the resist stripping solution treatment makes it difficult to remove. It is necessary to perform plasma treatment in the temperature range.
[0046]
After a protective film made of a silicon oxide film 117 having a thickness of about 0.5 to 5 nm is formed by the above method, a resist stripping solution treatment is performed to remove the resist pattern 115b after dry etching. The resist stripping solution treatment is a processing for completely removing the resist pattern 115b by performing a predetermined time (about 10 minutes) with a resist stripping solution kept at a temperature of about 60 to 90 ° C. The resist stripping solution used here is disclosed in, for example, JP 2000-241991, JP 2001-183849, JP 2001-188363, JP 2001-209190, and the like. A resist stripping solution with less etching damage to the silicon-based semiconductor film is preferable. However, resist stripping solutions with little etching damage to silicon-based semiconductor films often have problems in resist stripping performance, and resists that satisfy both resist stripping performance and etching damage-preventing performance to silicon-based semiconductor films. A stripping solution is preferred. After the resist remover treatment, the resist remover adhering to the substrate surface is replaced with IPA by performing an IPA cleaning treatment. The IPA cleaning process can be omitted only if it is omitted and there is no harmful effect. However, the IPA cleaning process has an effect of preventing generation of a mixed solution of a resist stripping solution and pure water at the time of washing in the vicinity of the substrate surface. In order to prevent the etching damage to the silicon-based semiconductor film and the metal wiring exposed on the substrate, it is generally preferable to introduce the IPA cleaning process. After the IPA cleaning process, a predetermined period of water washing process is performed to thoroughly clean the IPA and resist stripping solution adhering to the substrate, and finally the substrate is dried (see FIG. 2-D).
[0047]
As described above, it is possible to apply the resist stripping process of the present invention in the contact hole forming process in the manufacturing process of a TFT having a semiconductor layer made of a silicon-based semiconductor film. The present invention is to form a protective film against the resist stripping solution on the exposed surface of the silicon-based semiconductor film as a pretreatment of the resist stripping solution treatment. By applying the present invention, the resist stripping solution for the silicon-based semiconductor film is formed. It is possible to reliably prevent the etching damage due to. Therefore, application of the present invention is effective for stabilizing the electrical characteristics of the TFT and improving the yield of the semiconductor device.
[0048]
[Embodiment 2]
In the present embodiment, the resist stripping apparatus used in the resist stripping process of the first embodiment will be described with reference to FIGS. FIG. 5 is a plan view showing an overall outline of the resist stripping apparatus, and FIGS. 6 to 7 are side sectional views showing a specific configuration of a protective film forming unit constituting a characteristic part of the present invention.
[0049]
FIG. 5 is a plan view showing an overall outline of a resist stripping apparatus capable of continuously processing the resist stripping process of the present invention described in Embodiment 1, and is a sheet that can continuously process substrates to be processed one by one. A leaf processing type resist stripping apparatus 201 is shown. The resist stripping apparatus 201 includes a loader-side carrier 203 capable of storing a plurality of substrates to be processed 202 (usually storing about 20 substrates), a plurality of processing units 204 to 208 for processing the substrates to be processed 202, and processing. The unloader-side carrier 210 that can store the finished substrate 209 and a substrate transport unit (not shown) for transporting the substrate to be processed 202, and the substrate to be processed 202 stored in the loader-side carrier 203 is A substrate transport unit (not shown) is sequentially transported one by one in the direction indicated by an arrow (→) in the drawing, and is processed by each processing unit 204 to 208. Each of the processing units 204 to 208 of the resist stripping apparatus 201 includes a protective film deposition unit 204 for depositing a protective film against the resist stripping solution on the exposed surface of the silicon-based semiconductor film on the substrate 202 to be processed, A resist removing solution processing unit 205 for removing a resist pattern on the processing substrate 202; an IPA processing unit 206 for replacing and cleaning the resist removing solution adhering on the processing substrate 202 with IPA; A water washing unit 207 for washing the water 202 and a drying unit 208 for drying the substrate to be treated 202 after the water washing are configured (see FIG. 5).
[0050]
Regarding the resist stripping apparatus having such a configuration, the specific configuration of each processing unit will be described along the flow of processing. The protective film forming unit 204, which is the first processing unit, prevents the silicon-based semiconductor film exposed on the surface of the substrate to be processed 202 from coming into direct contact with the resist stripping solution. A processing unit for forming a protective film against the resist stripping solution. The protective film needs to be resistant to erosion to the resist stripping solution that has become strongly alkaline due to the hygroscopic action of the resist stripping solution. For example, a typical example is a silicon oxide film having a thickness of about 0.5 to 5 nm. . For this reason, as shown in FIG. 6, the apparatus configuration of the protective film forming unit 204 is spin addition in which a chemical solution that exerts an oxidizing action such as ozone-containing water or hydrogen peroxide water is spin-added onto the substrate 202 (307) to be processed. The apparatus configuration of the method 301 can be applied. As another device configuration, ozone is generated by irradiating ultraviolet rays in an oxygen-containing atmosphere as shown in FIG. 7, and the silicon-based semiconductor film on the substrate 202 (407) to be processed is oxidized by the ozone. It is good also as an apparatus structure of the ozone oxidation system 401 by the ultraviolet irradiation which oxidizes the surface (refer FIGS. 6-7).
[0051]
As shown in FIG. 6, the apparatus configuration of the spin addition method 301 specifically includes a processing cup 302, a spin chuck 304 supported by a rotation drive shaft 303 disposed in the processing cup 302, ozone-containing water, A chemical solution supply nozzle 305 for supplying a chemical solution having an oxidizing action such as hydrogen peroxide solution and a drain pipe 306 for discharging the chemical solution to the lower side of the processing cup 302 are provided. A chemical solution having an oxidizing action such as ozone-containing water or hydrogen peroxide solution is supplied to the substrate 202 (307) to be processed placed on the spin chuck 304, and the chemical solution is applied to the substrate 202 (307) to be processed. The substrate is held in a stacked state, and the substrate to be processed 202 (307) is spin-dried after a predetermined time has elapsed. Further, as shown in FIG. 7, the apparatus configuration of the ozone oxidation method 401 by ultraviolet irradiation specifically includes a processing chamber 402, a substrate mounting stage 403 disposed in the processing chamber 402, and a substrate mounting stage 403. An ultraviolet irradiation lamp 404 located above, a gas supply pipe 405 for supplying a gas containing oxygen to the processing chamber 402, and a power supply line 406 for supplying electric power to the ultraviolet irradiation lamp 404, are mounted on the substrate. Ultraviolet light is irradiated from an ultraviolet irradiation lamp 404 positioned above the substrate 202 (407) to be processed placed on the mounting stage 403, and at the same time, a gas containing oxygen is supplied into the processing chamber 402 from a gas supply pipe 405. When the ozone generated by the ultraviolet irradiation fills the processing chamber 402, silicon on the surface of the substrate 202 (407) to be processed Semiconductor film are configured to be surface oxidation (see Figure 6-7).
[0052]
In addition, as a protective film other than the silicon oxide film having a film thickness of about 0.5 to 5 nm, a silicon oxynitride film or a silicon nitride film having a film thickness of about 0.5 to 5 nm can be cited as candidates. The silicon oxynitride film or silicon nitride film is formed by directly oxynitriding or nitriding the exposed surface of the silicon-based semiconductor film. There is a protective film forming unit 204 to be processed. In the protective film forming unit 204, the surface of the silicon-based semiconductor film is subjected to an oxynitriding process by a plasma process in an atmosphere of a reactive gas containing nitrogen atoms and oxygen atoms, for example, in an atmosphere of nitrogen oxides, so Can be formed. Further, in the protective film forming unit 204, the surface of the silicon-based semiconductor film is nitrided by plasma treatment in an atmosphere of a reactive gas containing nitrogen atoms and no oxygen atoms, for example, in an atmosphere of ammonia gas, and silicon nitride It is possible to form a film.
[0053]
The next processing unit, a resist stripping solution processing unit 205, is a processing unit for removing an unnecessary resist pattern that has become a mask for etching or impurity doping on the substrate 202 to be processed. A resist stripping solution of a system is common. The IPA processing unit 206, which is the next processing unit, is a processing unit for replacing and cleaning the resist stripping solution adhering on the substrate 202 to be processed with IPA. In addition, a water washing unit 207, which is the next processing unit, is a processing unit for thoroughly cleaning the resist stripping solution and IPA adhering on the substrate to be processed 202 by water washing. In the resist stripping apparatus 201, these processing units 205 to 207 are configured as single-wafer processing type processing units. As a specific device configuration, a device configuration of a continuous processing tank and a device of a spin processing unit There is a configuration (see FIG. 5).
[0054]
Although not shown in particular, the apparatus configuration of the continuous processing tank in the resist stripping solution processing unit 205 and the IPA processing unit 206 is specifically that the substrate 202 to be processed is applied to the resist stripping solution or IPA filled in the continuous processing tank. It is constructed such that it is immersed while moving and is continuously processed for a predetermined time. In the resist stripping solution processing unit 205, a temperature increasing mechanism is attached to the continuous processing tank, and the resist stripping liquid filled in the continuous processing tank is maintained at a predetermined temperature of about 60 to 90 ° C. In this state, the substrate to be processed 202 is processed. The apparatus configuration of the continuous processing tank in the water washing unit 207 is divided into a plurality of independent processing tanks, and in each processing tank, each substrate 202 to be processed is independently QDR (Quick). -Abbreviated as Dump-Rinse). In addition, the apparatus structure of the continuous processing tank described above is only an example, and it cannot be overemphasized that another specific structure can also be considered (refer FIG. 5).
[0055]
Further, the apparatus configuration of the spin processing unit of the single wafer processing system in the resist stripping solution processing unit 205, the IPA processing unit 206, and the water washing unit 207 is the same as the apparatus configuration of FIG. Are the same. In the resist stripping solution processing unit 205, the resist stripping solution maintained at a predetermined temperature of about 60 to 90 ° C. is applied to the substrate 202 to be processed placed on the spin chuck from the chemical solution supply nozzle located above. The substrate is supplied and held for a predetermined time in a liquid accumulation state, and after a predetermined time, the resist stripping solution is scattered and removed around the substrate to be processed 202 by spin rotation of the substrate to be processed 202. In the IPA processing unit 206, IPA is supplied from the chemical solution supply nozzle located above onto the substrate to be processed 202 in the spin rotation state, and the resist stripping solution adhering to the substrate to be processed 202 is replaced and cleaned with IPA. The IPA of the substrate to be processed 202 is spin-dried after a predetermined time. In the water washing unit 207, pure water is supplied from the pure water supply nozzle located above onto the substrate to be processed 202 in the spin rotation state, and the resist stripping solution and IPA adhering to the substrate to be processed 202 are pure. The substrate 202 is washed with water and then the substrate to be processed 202 is spin-dried. In the case where the water washing unit 207 is configured by a spin processing unit, the substrate 202 to be processed is spin-dried after the water washing treatment, so that the drying unit 208 described later can be omitted (see FIG. 5).
[0056]
The drying unit 208, which is the next processing unit, is a processing unit for drying a small amount of water adhering to the substrate 202 to be processed, and is composed of a single wafer processing type air knife drying unit or a spin drying unit. . Since the spin drying unit has the same apparatus configuration as the washing unit 207 including the spin processing unit, the apparatus configuration of the air knife drying unit will be described here. Although not particularly illustrated, in the drying unit 208 including an air knife drying unit, air blow is supplied from the air knife nozzle to the surface of the substrate 202 to be processed, and moisture attached by the air blow is dried. (See FIG. 5).
[0057]
By the way, in the said embodiment, although the single-wafer processing type resist peeling apparatus was demonstrated concretely, the resist peeling apparatus of this invention is not limited to the said embodiment, The range which does not deviate from the summary Needless to say, various changes can be made. For example, although not particularly illustrated, a batch processing type resist stripping apparatus is naturally possible. In this case, the protective film forming unit is a batch processing type processing unit for forming a silicon oxide film having a film thickness of about 0.5 to 5 nm. For example, a chemical solution having an oxidizing action such as ozone-containing water or hydrogen peroxide water is used. An apparatus configuration in which a plurality of substrates to be processed are collectively processed in a filled processing tank, and ozone is generated by irradiating ultraviolet rays in an atmosphere containing oxygen, and a plurality of substrates to be processed by the oxidizing action of ozone. A device configuration in which the (strictly speaking, the surface of the silicon-based semiconductor film) is oxidized collectively is considered. In addition, a device configuration of a protective film forming unit composed of a batch processing type plasma processing unit for forming a silicon oxynitride film or a silicon nitride film with a thickness of about 0.5 to 5 nm is also conceivable, and a plurality of processed objects There is an apparatus configuration in which a plurality of substrates to be processed are subjected to plasma processing in a reactive gas atmosphere while the substrate is placed in a susceptor or a boat and inserted into a processing chamber. The reactive gas includes a reactive gas (for example, nitrogen oxide) containing nitrogen atoms and oxygen atoms, which is a reactive gas for forming a silicon oxynitride film, and a silicon nitride film. There is a reactive gas (for example, ammonia gas) that contains nitrogen atoms and does not contain oxygen atoms.
[0058]
In addition, as a resist stripping liquid processing unit, an IPA processing unit, and a water washing unit, which are processing units other than the protective film forming unit, from a processing tank filled with a corresponding processing liquid (resist stripping liquid or IPA or pure water), respectively. There is a batch processing type processing unit. The batch processing type drying unit includes a spin drying unit that spin-drys a plurality of substrates to be processed and an IPA vapor drying unit that collectively dries a plurality of substrates to be processed with IPA vapor.
[0059]
According to the single-wafer processing type or batch processing type resist stripping apparatus configured as described above, it is possible to perform the protective film forming process and the resist stripping liquid process before the resist stripping process in a continuous process. Etching damage to the silicon-based semiconductor film in the peeling process can be reliably prevented with high throughput. In the mass production process of semiconductor display devices composed of TFTs, the pinhole exposure of the silicon-based semiconductor film in the resist stripping process may occur unexpectedly due to some trouble. Even in this case, etching damage of the silicon-based semiconductor film can be reliably prevented with high throughput. For this reason, the resist stripping apparatus of the present invention is effective in stabilizing the electrical characteristics and improving the yield of TFTs in the mass production process of semiconductor display devices.
[0060]
[Embodiment 3]
In the present embodiment, the resist of the present invention is used in the manufacturing process of the active matrix type liquid crystal display device having both the GOLD structure TFT and the LDD structure TFT based on the process cross-sectional views showing the manufacturing process of the liquid crystal display device of FIGS. It describes about the case where a peeling apparatus is applied. In the liquid crystal display device of the present embodiment, a crystalline silicon film that is crystallized using a catalytic element is applied to a semiconductor layer that is an active layer of a TFT, and a pixel TFT having an LDD structure and an n-channel type having a GOLD structure. Alternatively, a case where a p-channel driver circuit is included is described as an example.
[0061]
First, a first silicon oxynitride film 502a having a thickness of 50 nm and a second silicon oxynitride film 502b having a thickness of 100 nm are deposited on the glass substrate 501 by plasma CVD, respectively. A base film 502 is formed. Note that the glass substrate 501 used here includes quartz glass, barium borosilicate glass, aluminoborosilicate glass, or the like. Next, an amorphous silicon film 503a having a thickness of 20 to 200 nm, preferably 30 to 70 nm, is deposited on the base film 502 (502a and 502b) by plasma CVD or low pressure CVD. In this embodiment, an amorphous silicon film 503a having a film thickness of 53 nm is deposited by plasma CVD. At this time, an extremely thin natural oxide film (not shown) is formed on the surface of the amorphous silicon film 503a due to the influence of oxygen in the air mixed in the processing atmosphere. In this embodiment, the amorphous silicon film 503a is deposited by the plasma CVD method, but may be deposited by the low pressure CVD method (see FIG. 8A).
[0062]
By the way, when the amorphous silicon film 503a is deposited, there is a possibility that carbon, oxygen, and nitrogen existing in the air are mixed. It is empirically known that mixing of these impurity gases causes deterioration of the characteristics of the finally obtained TFT, and the mixing of the impurity gases acts as a crystallization inhibiting factor. Therefore, mixing of the impurity gas should be thoroughly eliminated. Specifically, in the case of carbon and nitrogen, both are 5E17 atoms / cm. ^Three Below, in the case of oxygen, 1E18 atoms / cm ^Three It is preferable to control the following (see FIG. 8A).
[0063]
Next, the natural oxide film (not shown) formed on the surface of the amorphous silicon film 503a is removed by washing the substrate with diluted hydrofluoric acid for a predetermined time. Thereafter, a clean ultrathin silicon oxide film (not shown) having a film thickness of about 0.5 to 5 nm is formed on the surface of the amorphous silicon film 503a by performing treatment for a predetermined time with ozone-containing water. . In the present embodiment, the silicon oxide film (not shown) is formed by treatment with ozone-containing water, but may be formed by treatment with hydrogen peroxide solution. The silicon oxide film (not shown) is applied to the amorphous silicon film 503a in order to uniformly deposit Ni element when a Ni (nickel) element aqueous solution as a catalytic element solution is added later by a spin addition method. A film is formed for the purpose of improving wettability (see FIG. 8A).
[0064]
Next, an Ni element aqueous solution that is a catalyst element solution having a promoting action of crystallization is added to the entire surface of the amorphous silicon film 503a (strictly speaking, an extremely thin silicon oxide film) by a spin addition method. In this embodiment, nickel acetate, which is a Ni compound, dissolved in pure water and adjusted to a concentration of 10 ppm in terms of weight is used as the Ni element aqueous solution, and the amorphous silicon film 503a (strictly speaking, extremely A Ni-containing layer (not shown) is uniformly deposited on the entire surface of the thin silicon oxide film (see FIG. 8A).
[0065]
Next, in order to control the hydrogen content in the amorphous silicon film 503a to 5 atom% or less, a dehydrogenation process of the hydrogen contained in the amorphous silicon film 503a is performed. The dehydrogenation treatment is performed by heat treatment at 450 ° C. for 1 hour in a nitrogen atmosphere using a furnace. Thereafter, heat treatment is performed at 550 ° C. for 4 hours in a furnace to promote crystallization of the amorphous silicon film 503a, and a crystalline silicon film 503b having a thickness of 50 nm is formed. Subsequently, in order to further improve the crystallinity of the obtained crystalline silicon film 503b, crystallization is performed by irradiation with a pulse oscillation type KrF excimer laser (wavelength 248 nm). In this specification, a polycrystalline silicon film that is crystallized using Ni element as a catalytic element is referred to as a crystalline silicon film in order to distinguish it from a normal polycrystalline silicon film. Here, the reason why it is referred to as crystalline rather than polycrystalline is that the crystal grains are oriented in the same direction and have high field-effect mobility compared to a normal polycrystalline silicon film. Therefore, it is intended to be distinguished from a polycrystalline silicon film (see FIG. 8A).
[0066]
Next, pre-channel dope cleaning is performed for a predetermined time by dilute hydrofluoric acid cleaning and ozone-containing water cleaning, and a clean ultrathin silicon oxide film having a thickness of about 0.5 to 5 nm is formed on the surface of the crystalline silicon film 503b (FIG. (Not shown) is formed again. The silicon oxide film (not shown) is subjected to hydrogen ions (diborane (B) as an ion source during the channel doping process. ₂ H ₆ ) And hydrogen) to prevent the crystalline silicon film 503b from being etched. Thereafter, in order to control the threshold voltages of the n-channel TFT and the p-channel TFT, a channel doping process which is a first doping process is performed using a doping apparatus. The channel doping process is performed by doping the entire surface of the substrate with a B (ie, boron) element which is a p-type impurity having a low dose. As a doping condition at this time, diborane (B ₂ H ₆ ) Diborane (B ₂ H ₆ ) / Hydrogen (H ₂ ) At an acceleration voltage of 5 to 30 kV and a dose of 8 × 10 ¹³ ~ 2x10 ¹⁵ atoms / cm ² In this embodiment, the B concentration in the crystalline silicon film 503b is 1 × 10 5. ¹⁷ atoms / cm ^Three Diborane (B ₂ H ₆ ) Diborane (B ₂ H ₆ ) / Hydrogen (H ₂ ), Acceleration voltage 15 kV, dose amount 4 × 10 ¹⁴ atoms / cm ² The element B is doped under the following doping conditions (see FIG. 8B).
[0067]
Next, the silicon oxide film (not shown) is removed by treating the ultrathin silicon oxide film (not shown) formed as a pretreatment for channel doping with dilute hydrofluoric acid. Thereafter, by performing treatment for a predetermined time with ozone-containing water, ultrathin silicon oxide films 504a to 508a having a film thickness of about 0.5 to 5 nm are formed again on the surface of the crystalline silicon film 503b. The silicon oxide films 504a to 508a are used to improve the adhesion of a resist pattern to be formed next, to improve the hydrophobicity of the crystalline silicon film 503b, to prevent contamination, and to clean the surface of the crystalline silicon film 503b. However, it also has a function of preventing etching damage from the organic resist stripping solution. In this embodiment, the silicon oxide films 504a to 508a having a film thickness of about 0.5 to 5 nm are formed by treatment with ozone-containing water, but may be treated with hydrogen peroxide water or oxygen. The surface of the crystalline silicon film 503b may be oxidized by generating ozone by irradiating ultraviolet rays in an atmosphere including the same and oxidizing the ozone. Thereafter, a resist pattern (not shown) having a predetermined dimension is formed by a normal photolithography process (see FIG. 8B).
[0068]
Next, using the resist pattern (not shown) as a mask, the crystalline silicon film 503b and the silicon oxide films 504a to 508a which are the surface layer films thereof are dry-etched to form an island shape made of a crystalline silicon film 503b having a thickness of 50 nm. The semiconductor layers 504 to 508 are formed. The semiconductor layers 504 to 508 are island-shaped regions that become the active layers of the TFTs, and are regions where the source and drain regions of the TFT are formed later. In the dry etching process, an RIE type dry etching apparatus is used and CF, which is an etching gas, is used. _Four And O ₂ A dry etching process is performed under an etching condition with a gas flow ratio of 50:45, and a taper etching process is performed according to the resist receding method. For this reason, although not shown for convenience, a forward taper shape is formed on the side walls of the semiconductor layers 504 to 508 which are films to be etched (indicated in a rectangular shape for convenience). Further, since the sidewall portion of the forward taper shape contains oxygen in the etching gas, there is almost no adhesion of the sidewall protective polymer during dry etching, and the surface of the crystalline silicon film 503b is exposed (or some silicon). An oxide film can also be formed). Note that the reason why the semiconductor layers 504 to 508 are formed in a forward tapered shape is to improve the coverage with a step portion of a gate insulating film or a gate electrode film formed in a later process (see FIG. 8B). ).
[0069]
Next, in order to remove the resist pattern (not shown) after the dry etching, an ashing process that is an oxygen plasma process is performed. The ashing process employs a half ashing method in which about half of the resist pattern is ashed. For this reason, the resist pattern (not shown) after the ashing process is thinned by about half, and the resist pattern shape is deformed. At the time of this ashing process, the crystalline silicon film 503b is exposed on the side wall portions of the semiconductor layers 504 to 508 having a forward taper shape, so that the silicon oxide films 504b to 504b having a thickness of about 0.5 to 5 nm are exposed. 508b is formed. The silicon oxide films 504b to 508b have a function of preventing etching damage from the resist stripping solution during the next step of stripping the resist stripping solution (see FIG. 8B).
[0070]
Next, in order to completely remove the remaining resist pattern (not shown), a resist stripping process is performed using the resist stripping apparatus of the present invention. The resist stripping apparatus of the present invention can perform a protective film forming process before the resist stripping process. In the resist stripping process, the surface of the semiconductor layers 504 to 508 made of the crystalline silicon film 503b. Since the silicon oxide films 504a to 508a and 504b to 508b having a film thickness of about 0.5 to 5 nm are already formed on the side surfaces, a protective film formation process for the semiconductor layers 504 to 508 is unnecessary. In this case, the processing program of the resist stripping apparatus is changed to a program without a protective film forming process, so that it is possible to further increase the throughput of the resist stripping process. Therefore, the specific process of the resist stripping process by the resist stripping apparatus in this case is processed by a continuous process including a resist stripping solution process, an IPA cleaning process, a water cleaning process, and a drying process. Although the IPA cleaning process is continuously performed after the resist stripping solution process, the IPA cleaning process can be omitted only when there is no harmful effect even if the IPA cleaning process is omitted. However, the IPA cleaning treatment has an effect of preventing the formation of a mixed solution of the resist stripping solution and pure water at the time of washing in the vicinity of the substrate surface, and the function of preventing the resist stripping solution from becoming strongly alkaline due to the mixing of moisture. For this reason, it is generally preferable to introduce an IPA cleaning process (see FIG. 8B).
[0071]
Next, by cleaning the substrate with dilute hydrofluoric acid for a predetermined time, silicon having a film thickness of about 0.5 to 5 nm formed on the surfaces and side walls of the semiconductor layers 504 to 508 made of the crystalline silicon film 503b. The oxide films 504a to 508a and 504b to 508b are removed. After that, a gate insulating film 509 made of a silicon oxide film or a silicon oxynitride film having a thickness of 30 to 200 nm, preferably 80 to 130 nm is formed by plasma CVD or low pressure CVD so as to cover the semiconductor layers 504 to 508. accumulate. In this embodiment, a gate insulating film 509 made of a silicon oxide film having a thickness of 100 nm is deposited by plasma CVD. It is known that the thickness of the gate insulating film 509 needs to be 80 nm or more in order to avoid stress from the upper gate electrode film formed in a later step. (See FIG. 9-A).
[0072]
Next, in order to deposit an electrode material for the gate electrode, an aluminum alloy film having a film thickness of 200 to 600 nm, preferably 300 to 600 nm, or a laminated film of a refractory metal and a refractory metal nitride is formed by sputtering. To deposit. In this embodiment, a TaN film having a thickness of 30 nm is deposited as the first layer gate electrode film 510, and then a W film having a thickness of 370 nm is deposited as the second layer gate electrode film 511. The film thickness of the TaN film as the first layer gate electrode film 510 is controlled by controlling the remaining film thickness in the tapered region during dry etching, and is doped with an impurity element by passing through the TaN film by a through doping method. It is set in consideration of both doping characteristics. Further, it is known that the film thickness of the W film as the second-layer gate electrode film 511 needs to be 340 nm or more in order to prevent channeling phenomenon of the W film when doping the impurity element. This is set in consideration of this point (see FIG. 9A).
[0073]
Next, a normal photolithography process is performed to form a resist pattern (not shown) having a predetermined size for forming a gate electrode, a storage capacitor electrode, a source wiring, and the like on the metal laminated film. Thereafter, using a resist pattern (not shown) as a mask, a metal laminated film comprising a first layer gate electrode film 510 made of a TaN film having a thickness of 30 nm and a second layer gate electrode film 511 made of a W film having a thickness of 370 nm. Is dry-etched. By the dry etching process, a gate electrode having a predetermined size composed of the first layer gate electrodes 512c to 515c and the second layer gate electrodes 512b to 515b is formed, and at the same time, the first layer storage capacitor electrode 516c and the second layer storage capacitor electrode A storage capacitor electrode having a predetermined dimension composed of 516b and a source wiring electrode having a predetermined dimension composed of the first layer source wiring electrode 517c and the second layer source wiring electrode 517b are formed. In the dry etching process, the second layer electrodes 512b to 517b (a general term for electrodes composed of the second layer gate electrodes 512b to 515b, the second layer storage capacitor electrode 516b, and the second layer source wiring electrode 517b) The dimensions in the channel direction are shorter than those of the first layer electrodes 512c to 517c (the generic term for the first layer gate electrodes 512c to 515c, the first layer storage capacitor electrode 516c, and the first layer source wiring electrode 517c). . In addition, the first layer electrodes 512c to 517c corresponding to the exposed regions from the second layer electrodes 512b to 517b are formed in a tapered shape that is gradually thinned toward the end. Note that the developed resist pattern (not shown) has the shape of resist patterns 512a to 517a due to film reduction during dry etching, and the gate insulating film 509 has the shape of the gate insulating film 518 due to film reduction during dry etching. It is deformed (see FIG. 9-B).
[0074]
Next, in order to remove the resist patterns 512a to 517a after the dry etching, an ashing process by a half ashing method is performed. After ashing and removing the resist patterns 512a to 517a to about half by the ashing treatment, a resist stripping process is performed using the resist stripping apparatus of the present invention in order to completely remove the remaining resist pattern (not shown). The resist stripping apparatus of the present invention can perform a protective film forming process before the resist stripping process. In the resist stripping process, the gate insulating film 518 is coated so as to cover the semiconductor layers 504 to 508. Therefore, the semiconductor layers 504 to 508 and the resist stripping solution cannot usually come into direct contact with each other, and the protective film is not required to be formed. In this case, the processing program of the resist stripping apparatus is changed to a program without a protective film forming process, so that it is possible to further increase the throughput of the resist stripping process. Therefore, the specific process of the resist stripping process by the resist stripping apparatus in this case is a continuous process including a resist stripping liquid process, an IPA cleaning process, a water washing process, and a drying process. Although the IPA cleaning process is continuously performed after the resist stripping solution process, the IPA cleaning process can be omitted only when there is no harmful effect even if the IPA cleaning process is omitted. However, the IPA cleaning treatment has an effect of preventing the formation of a mixed solution of the resist stripping solution and pure water at the time of washing in the vicinity of the substrate surface, and the function of preventing strong alkalinity of the resist stripping solution due to mixing of moisture. Therefore, it is generally preferable to introduce an IPA cleaning process (see FIG. 10-A).
[0075]
Next, using a doping apparatus, a low dose n-type impurity composed of P element, which is the second doping process, is doped using the first layer electrodes 512c to 516c as a mask. By the second doping process, low-concentration impurity regions (n−− regions) 519 to 523 of n-type impurities are formed in the semiconductor layers 504 to 508 corresponding to the regions outside the first layer electrodes 512c to 516c. At this time, in the formation of the low-concentration impurity regions (n−− regions) 519 to 523, doping is performed through the gate insulating film 518 which is an upper layer film by a so-called through doping method. As doping conditions, phosphine (PH _Three ) 3-20% dilution of phosphine (PH _Three ) / Hydrogen (H ₂ ) At an acceleration voltage of 30 to 90 kV and a dose of 6 × 10 ¹² ~ 1.5 × 10 ¹⁴ atoms / cm ² In this embodiment, phosphine (PH _Three ) 5% diluted phosphine (PH _Three ) / Hydrogen (H ₂ ), Acceleration voltage 50 kV, dose amount 3 × 10 ¹³ atoms / cm ² (See FIG. 10-B).
[0076]
Next, resist patterns 524 to 525 which are masks for doping impurities are formed by a normal photolithography process. The resist patterns 524 to 525 are formed in a manufacturing region of the p-channel TFT 602 which is the GOLD structure driving circuit 606 and the pixel TFT 604 having the LDD structure, and the n-channel TFTs 601 and 603 which are the GOLD structure driving circuit 606 and the storage capacitor. It is not formed in the manufacturing region 605. At this time, in the manufacturing region of the p-channel TFT 602 having the GOLD structure, the resist pattern 524 is formed so that the end portion of the resist pattern 524 is located outside the semiconductor layer 505, that is, completely covering the semiconductor layer 505. The In the region where the pixel TFT 604 having the LDD structure is formed, the end portion of the resist pattern 525 is located inside the semiconductor layer 507 and outside the first layer gate electrode 515c by a predetermined distance, that is, the first layer. The gate electrode 515c is formed so as to be positioned on the outer side by an amount corresponding to the Loff region (details will be described in a later step) (see FIG. 11A).
[0077]
Next, a high dose n-type impurity composed of a P element, which is the third doping process, is doped using a doping apparatus. At this time, in the manufacturing region of the n-channel TFTs 601 and 603 which are the drive circuit 606 having the GOLD structure, the semiconductor layers 504 and 506 corresponding to the outside of the first layer gate electrodes 512c and 514c already have n-type impurities. Low-concentration impurity regions (n−− regions) 519 and 521 are formed, and n-type impurity high-concentration impurity regions (n + regions) 526 and 528 are formed thereon, and at the same time, the first-layer gate electrode 512c. , 514c, n-type impurity low-concentration impurity regions (n− regions) 527 and 529 are formed in the semiconductor layers 504 and 506 corresponding to the exposed regions from the second-layer gate electrodes 512b and 514b. The high-concentration impurity regions (n + regions) 526 and 528 formed in this manner have a function as a source region or drain region of the GOLD structure, and the low-concentration impurity regions (n− regions) 527 and 529 have a GOLD structure. It has a function as an electric field relaxation region which is a Lov region (an electric field relaxation region overlapping with the gate electrode). Similarly, a high concentration impurity region (n + region) 532 and a low concentration impurity region (n− region) 533 of an n-type impurity are also formed in the manufacturing region of the storage capacitor 605. The n-type impurity high-concentration impurity region (n + region) 532 and the low-concentration impurity region (n− region) 533 formed here are regions for forming the storage capacitor 605 instead of the TFT. It functions as one side of the electrode (see FIG. 11-A).
[0078]
On the other hand, in the manufacturing region of the pixel TFT 604 having the LDD structure, a high concentration impurity region (n + region) 530 of an n-type impurity is formed in the semiconductor layer 507 corresponding to the outside of the resist pattern 525 by the third doping process. Is done. In the semiconductor layer 507, a low-concentration impurity region (n−− region) 522 of an n-type impurity is already formed. However, with the formation of the high-concentration impurity region (n + region) 530, the low-concentration impurity region ( The n−− region) 522 is divided into a high concentration impurity region (n + region) 530 and a low concentration impurity region (n−− region) 531 formed as a result. The high-concentration impurity region (n + region) 530 thus formed functions as a source region or a drain region of the LDD structure, and the low-concentration impurity region (n−− region) 531 is a Loff region (LDD structure). It has a function as an electric field relaxation region which is an electric field relaxation region that does not overlap with the gate electrode. As doping conditions, phosphine (PH _Three ) 3-20% dilution of phosphine (PH _Three ) / Hydrogen (H ₂ ) At an acceleration voltage of 30 to 90 kV and a dose of 6 × 10 ¹⁴ ~ 1.5 × 10 ¹⁶ atoms / cm ² In this embodiment, phosphine (PH _Three ) 5% diluted phosphine (PH _Three ) / Hydrogen (H ₂ ), Acceleration voltage 65 kV, dose amount 3 × 10 ¹⁵ atoms / cm ² (See FIG. 11-A).
[0079]
The high-concentration impurity regions (n + regions) 526, 528, 530, and 532 and the low-concentration impurity regions (n− regions) 527, 529, and 533 are formed by a so-called through doping method in which doping is performed through an upper layer film. The through doping method is a doping method in which impurities are doped into the target material layer through the upper layer film, and has a feature that the impurity concentration of the target material layer can be changed depending on the film quality and film thickness of the upper layer film. Therefore, although the impurity is doped under the same doping conditions, the high-concentration impurity regions (n + regions) 526, 528, 530, and 532 are formed in the region where the upper layer film is configured by the gate insulating film 518 having a small ion blocking ability. And a low-concentration impurity region (n−region) in a region constituted by a laminated film of first layer electrodes (TaN films) 512c, 514c, 516c and a gate insulating film 518 having a high ion blocking ability. 527, 529, and 533 can be formed simultaneously (see FIG. 11A).
[0080]
Note that, in the manufacturing region of the n-channel TFTs 601 and 603 which are the drive circuit 606 having the GOLD structure, the high-concentration impurity regions (n + regions) 526 and 528 and the low-concentration impurity regions (n− regions) 527 and 529 are used. With the formation of the TFT, the channel region of the TFT is defined in a region of the semiconductor layers 504 and 506 that overlaps with the second layer gate electrodes 512b and 514b. Similarly, a channel region of the TFT is defined in a region where the LDT structure pixel TFT 604 is formed, in a region overlapping with the first layer gate electrode 515c in the semiconductor layer 507 (FIG. 11-). A).
[0081]
Next, in order to remove the resist patterns 524 to 525 after the doping process, an ashing process by a half ashing method is performed. After ashing and removing the resist patterns 524 to 525 to about half by the ashing treatment, a resist stripping process is performed using the resist stripping apparatus of the present invention in order to completely remove the remaining resist pattern (not shown). Note that the details of the resist stripping step are the same as those in the resist stripping step without the protective film forming process after the dry etching process, and therefore the description thereof is omitted here. Thereafter, resist patterns 534 to 536 which are masks for doping impurities are formed by a normal photolithography process. At this time, the resist patterns 534 to 536 are formed so as to open manufacturing regions of the p-channel TFT 602 and the storage capacitor 605 which are the drive circuits 606 having the GOLD structure (see FIG. 11B).
[0082]
Next, using a doping apparatus, a high dose p-type impurity composed of B element, which is the fourth doping process, is doped by a through doping method. By the fourth doping process, in the manufacturing region of the p-channel TFT 602 which is the drive circuit 606 having the GOLD structure, the semiconductor layer 505 corresponding to the outside of the first layer gate electrode 513c has a high concentration of p-type impurities. Impurity region (p + region) 537 is formed. Further, a low-concentration impurity region (p− region) 538 of a p-type impurity is simultaneously formed in the semiconductor layer 505 corresponding to the exposed region of the first layer gate electrode 513c from the second layer gate electrode 513b. The high concentration impurity region (p ⁺ (Region) 537 has a function as a source region or drain region of the GOLD structure, and a low concentration impurity region (p− region) 538 is a Lov region of the GOLD structure (an electric field relaxation region overlapping with the gate electrode). It has a function as an electric field relaxation region. On the other hand, also in the manufacturing region of the storage capacitor 605, a high concentration impurity region (p + region) 539 and a low concentration impurity region (p− region) 540 functioning as one side of the capacitor forming electrode are formed. (See FIG. 11-B).
[0083]
By the way, a low-concentration impurity region (n−− region) 520 of an n-type impurity is already formed in the high-concentration impurity region (p + region) 537 of the p-type impurity in the manufacturing region of the p-channel TFT 602. Since p-type impurities having a concentration higher than that of n-type impurities are doped, a high-concentration impurity region (p + region) 537 having a p-type conductivity as a whole is formed. In the storage region of the storage capacitor 605, the n-type impurity high-concentration impurity region (n + region) 532 and the low-concentration impurity region (n− region) 533 are already formed. Since p-type impurities having a concentration higher than that are doped, a high-concentration impurity region (p + region) 539 and a low-concentration impurity region (p− region) 540 having a p-type conductivity as a whole are formed. Note that the high-concentration impurity regions (p + regions) 537 and 539 and the low-concentration impurity regions (p− regions) 538 and 540 of the p-type impurity have the same film quality and film thickness as the n-type impurity region. It is formed at the same time by the through dope method using the difference. In addition, as doping conditions at this time, diborane (B ₂ H ₆ ) Diborane (B ₂ H ₆ ) / Hydrogen (H ₂ ) At an acceleration voltage of 60 to 100 kV and a dose of 4 × 10 ¹⁵ ~ 1x10 ¹⁷ atoms / cm ² In this embodiment, diborane (B ₂ H ₆ ) Diborane (B ₂ H ₆ ) / Hydrogen (H ₂ ), Acceleration voltage 80 kV, dose amount 2 × 10 ¹⁶ atoms / cm ² (See FIG. 11-B).
[0084]
Next, in order to remove the resist patterns 534 to 536 after the doping process, an ashing process by a half ashing method is performed. After the resist patterns 534 to 536 are ashed and removed by about half by the ashing process, a resist stripping process is performed using the resist stripping apparatus of the present invention in order to completely remove the remaining resist pattern (not shown). Note that the details of the resist stripping step are the same as those in the resist stripping step without the protective film forming process after the dry etching process, and therefore the description thereof is omitted here. Thereafter, a first interlayer insulating film 541 made of a silicon oxynitride film or a silicon nitride film having a thickness of 50 to 300 nm, preferably 100 to 200 nm is deposited by plasma CVD. In the present embodiment, a first interlayer insulating film 541 made of a silicon nitride film having a thickness of 150 nm is deposited by plasma CVD. Thereafter, a heat treatment is performed at 600 ° C. for 12 hours in a furnace for thermal activation of the n-type impurity (P element) or the p-type impurity (B element) doped in the semiconductor layers 504 to 508. The heat treatment is performed for thermal activation treatment of n-type or p-type impurities, and the purpose is to getter the catalytic element (Ni element) present in the channel region located directly under the gate electrode with the impurities. Also serves. Note that the thermal activation treatment may be performed before the deposition of the first interlayer insulating film 541. However, if the heat resistance of the wiring material such as the gate electrode is weak, it is performed after the deposition of the first interlayer insulating film 541. Is preferred. Following the heat treatment, a hydrogenation treatment at 410 ° C. for 1 hour is performed in a nitrogen atmosphere containing 3% hydrogen in order to terminate dangling bonds in the semiconductor layers 504 to 508 (see FIG. 12A).
[0085]
Next, a second interlayer insulating film 542 made of an acrylic resin film having a thickness of 0.7 to 3 μm, preferably 1 to 2 μm is formed on the first interlayer insulating film 541. In the present embodiment, a second interlayer insulating film 542 made of an acrylic resin film having a thickness of 1.6 μm is formed. The acrylic resin film is formed by applying an acrylic resin film by a spin coating method and then performing a heat treatment in an oven baking furnace. Thereafter, a resist pattern 543a for forming a contact hole with a predetermined dimension is formed on the second interlayer insulating film 542 made of an acrylic resin film by a normal photolithography process (see FIG. 12-B).
[0086]
Next, using the resist pattern 543a as a mask, the laminated film of the second interlayer insulating film 542 made of an acrylic resin film, the first interlayer insulating film 541 made of a silicon nitride film, and the gate insulating film 518 made of a silicon oxide film is dried. Etching process. By the dry etching process, a contact hole 544 having a predetermined size is formed so as to penetrate the second interlayer insulating film 542, the first interlayer insulating film 541, and the gate insulating film 518. At this time, in the dry etching process, oxygen and CF _Four The acrylic resin film, which is the second interlayer insulating film 542, is etched by dry etching under a gas mixture condition with a gas flow ratio of 19: 1, and oxygen and CF _Four The silicon nitride film which is the first interlayer insulating film 541 is etched by dry etching under a gas mixture condition with a gas flow ratio of 1: 1, and CHF _Three The silicon oxide film which is the gate insulating film 518 is etched by dry etching using gas. In this way, in the final stage of the dry etching process, CHF _Three Since the gas plasma is applied, a high etching ratio dry etching process is realized for the semiconductor layers 504 to 508 made of the crystalline silicon film 503b existing at the bottom of the contact hole 544. Further, after dry etching, the resist pattern 543a contains oxygen (strictly speaking, 5% CF). _Four Containing) As a result of the significant reduction in film thickness caused by the plasma treatment, the resist pattern 543b is deformed. Note that the contact hole 544 includes n-type impurity high-concentration impurity regions (n + regions) 526, 528, and 530, p-type impurity high-concentration impurity regions (p + regions) 537 and 539, and a source wiring functioning as a source wiring. It is formed so as to be connected to the electrode 517bc (consisting of the first layer source wiring electrode 517c and the second layer source wiring electrode 517b) (see FIG. 13-A).
[0087]
Next, in order to remove the unnecessary resist pattern 543b after the dry etching process, a resist stripping process is performed using the resist stripping apparatus of the present invention. Here, since an organic acrylic resin film is applied to the second interlayer insulating film 542, the ashing process cannot be introduced into the resist removing process, and the resist pattern removing process is performed only by the resist stripping process. ing. The resist stripping apparatus of the present invention is capable of forming a protective film made of a silicon oxide film having a thickness of about 0.5 to 5 nm before the resist stripping solution treatment. In the resist stripping process, Then, the resist stripping process is processed under the processing conditions including the protective film forming process. The resist stripping process by the resist stripping apparatus includes a protective film forming process before the resist stripping process, a resist stripping process, an IPA cleaning process, a water cleaning process, and a drying process. The protective film before the resist stripping process It is possible to perform the ultra-thin silicon oxide film forming process and the resist stripping liquid process with a film thickness of about 0.5 to 5 nm in a continuous process. Accordingly, before the resist stripping solution treatment, a film thickness of 0.5 to 5 nm which is a protective film 545 against the resist stripping solution is formed on the surface of the semiconductor layers 504 to 508 made of the crystalline silicon film 503b exposed at the bottom of the contact hole 544. An extremely thin silicon oxide film can be formed, and etching damage to the crystalline silicon film 503b by the resist stripping solution can be reliably prevented with high throughput. The resist stripping solution used here is disclosed in, for example, JP 2000-241991, JP 2001-183849, JP 2001-188363, JP 2001-209190, and the like. A resist stripping solution with less etching damage to such a crystalline silicon film is preferred. However, the resist stripping solution with little etching damage to the crystalline silicon film often has a problem in the resist stripping performance, and the resist that satisfies both the resist stripping performance and the etching damage prevention performance to the silicon-based semiconductor film. A stripping solution is suitable, and it is preferable to apply the resist stripping solution. Further, the IPA cleaning process is continuously performed after the resist stripping solution process, but the IPA cleaning process can be omitted only if there is no harmful effect even if the IPA cleaning process is omitted. However, the IPA cleaning process has an effect of preventing the formation of a mixed solution of a resist stripping solution and pure water at the time of washing in the vicinity of the substrate surface, and the crystalline silicon film or metal wiring exposed on the substrate is not affected. In general, it is preferable to introduce an IPA cleaning treatment (see FIG. 13-B) because it advantageously acts to prevent etching damage.
[0088]
Next, dilute hydrofluoric acid treatment is performed as pre-sputter cleaning, and the protective film (silicon oxide film) 545 on the surface of the crystalline silicon film 503b exposed at the bottom of the contact hole 544 is removed. Thereafter, a metal laminated film composed of a three-layer film of Ti (100 nm) / Al (350 nm) / Ti (100 nm) is deposited by sputtering. In the metal laminated film, the first Ti film having a thickness of 100 nm is deposited for the purpose of reducing the contact resistance and preventing mutual diffusion of silicon and aluminum, and the third layer having a thickness of 100 nm. The Ti film is deposited for the purpose of preventing hillocks on the aluminum wiring surface. After depositing the metal laminated film, a resist pattern (not shown) for wiring formation having a predetermined dimension is formed on the metal laminated film by a normal photolithography process (see FIG. 14A).
[0089]
Next, by performing a dry etching process using a chlorine-based etching gas, metal laminate film wirings 546 to 551 having predetermined dimensions, connection electrodes 552, 554, 555, and a gate wiring 553 are formed simultaneously. The metal laminated film wirings 546 to 551 are formed so as to be electrically connected to the high concentration impurity regions (n + regions) 526 and 528 and the high concentration impurity region (p + region) 537 of the drive circuit 606. The connection electrode 552 is formed so as to electrically connect the high-concentration impurity region (n + region) 530 of the pixel TFT 604 and the second-layer source wiring electrode 517b functioning as a source wiring. The connection electrode 554 is formed so as to be electrically connected to the high concentration impurity region (n + region) 530 of the pixel TFT 604, and the connection electrode 555 is connected to the high concentration impurity region (p + region) 539 of the storage capacitor 605. It is formed so as to be electrically connected. The gate wiring 553 is formed so as to electrically connect a plurality of second layer gate electrodes 515b of the pixel TFT 604. After the dry etching process, in order to remove an unnecessary resist pattern (not shown), a resist stripping process is performed using the resist stripping apparatus of the present invention. Here, since an organic acrylic resin film is applied to the second interlayer insulating film 542, the ashing process cannot be introduced into the resist removing process, and the resist pattern removing process is performed only by the resist stripping process. ing. Note that the details of the resist stripping step are the same as the resist stripping step after the dry etching process described above, so the description is omitted here (see FIG. 14A).
[0090]
Next, an ITO (Indium-Ti-Oxide) film, which is a transparent conductive film having a thickness of 80 to 130 nm, preferably 100 to 120 nm, is deposited by sputtering. In this embodiment, an ITO film having a thickness of 110 nm is deposited by sputtering. Thereafter, a resist pattern (not shown) for pixel electrodes having a predetermined dimension is formed by a normal photolithography process. Thereafter, a wet etching process is performed using an etching solution having a trade name “ITO-04N” manufactured by Kanto Chemical Co., Inc. By the wet etching process, the pixel electrode 556 having a predetermined size made of an ITO film is formed so as to be connected to the connection electrodes 554 and 555. The pixel electrode 556 is electrically connected to a high-concentration impurity region (n + region) 530 functioning as a source region or a drain region of the pixel TFT 604 through the connection electrode 554, and further retained through the connection electrode 555. The high-concentration impurity region (p + region) 539 of the capacitor 605 is also electrically connected. After the wet etching process, a resist stripping process is performed using the resist stripping apparatus of the present invention in order to remove an unnecessary resist pattern (not shown). Here, since an organic acrylic resin film is applied to the second interlayer insulating film 542, an ashing process cannot be introduced into the resist removal process, and a resist pattern (not shown) can be formed only by the resist stripping process. The removal process is performed. The details of the resist stripping step are the same as those of the resist stripping step without the protective film forming process after the dry etching process described above, and the description is omitted here (see FIG. 14-B).
[0091]
As described above, by applying the resist stripping device of the present invention to the resist stripping process of the active matrix liquid crystal display device, the etching damage of the semiconductor layer made of the crystalline silicon film due to the resist stripping solution can be reliably prevented with high throughput. Is possible. Depending on the resist stripping process, there is a process where the crystalline silicon film cannot be exposed at all, and the processing program of the resist stripping apparatus can be changed to a program without a protective film forming process. As described above, the resist peeling apparatus of the present invention can easily change the presence or absence of the protective film formation process by the program setting in the resist peeling process, and etch the semiconductor layer made of the crystalline silicon film while maintaining high throughput. It is possible to reliably prevent damage. In this embodiment, the manufacturing method of the active matrix type liquid crystal display device has been specifically described, but it goes without saying that the present invention can also be applied to a manufacturing method of an active matrix type organic EL display device.
[0092]
[Embodiment 4]
In this embodiment, a specific example of an electronic device incorporating a semiconductor display device manufactured by applying the resist stripping process or the resist stripping apparatus of the present invention will be described. Examples of the semiconductor display device include an active matrix liquid crystal display device, an EL display device, and the like, which are applied to display portions of various electronic devices. Here, specific examples of electronic devices in which the semiconductor display device is applied to the display portion will be described with reference to FIGS.
[0093]
Electronic devices in which the semiconductor display device is applied to the display unit include a video camera, a digital camera, a projector (rear type or front type), a head mounted display (goggles type display), a game machine, a car navigation system, a personal computer, Examples thereof include portable information terminals (mobile computers, mobile phones, electronic books, etc.).
[0094]
FIG. 16A illustrates a personal computer including a main body 1001, a video input unit 1002, a display device 1003, and a keyboard 1004. The semiconductor display device of the present invention can be applied to the display device 1003 and other circuits.
[0095]
FIG. 16B illustrates a video camera, which includes a main body 1101, a display device 1102, an audio input unit 1103, an operation switch 1104, a battery 1105, and an image receiving unit 1106. The semiconductor display device of the present invention can be applied to the display device 1102 and other circuits.
[0096]
FIG. 16C illustrates a mobile computer, which includes a main body 1201, a camera unit 1202, an image receiving unit 1203, an operation switch 1204, and a display device 1205. The semiconductor display device of the present invention can be applied to the display device 1205 and other circuits.
[0097]
FIG. 16D shows a goggle type display, which is composed of a main body 1301, a display device 1302, and an arm portion 1303. The semiconductor display device of the present invention can be applied to the display device 1302 and other circuits.
[0098]
FIG. 16E shows a player used as a recording medium (hereinafter abbreviated as a recording medium) on which a program is recorded, and includes a main body 1401, a display device 1402, a speaker unit 1403, a recording medium 1404, and an operation switch 1405. This apparatus uses a DVD, a CD, or the like as a recording medium, and can be used for music appreciation, games, or the Internet. The semiconductor display device of the present invention can be applied to the display device 1402 and other circuits.
[0099]
FIG. 16F shows a mobile phone, which includes a display panel 1501, an operation panel 1502, a connection unit 1503, a display unit 1504, an audio output unit 1505, an operation key 1506, a power switch 1507, an audio input unit 1508, and an antenna 1509. Composed. The display panel 1501 and the operation panel 1502 are connected by a connection unit 1503. An angle θ between the surface of the display panel 1501 on which the display unit 1504 is installed and the surface of the operation panel 1502 on which the operation key 1506 is installed can be arbitrarily changed in the connection unit 1503. Note that the semiconductor display device of the present invention can be applied to the display portion 1504 (see FIG. 16).
[0100]
FIG. 17A shows a front type projector, which includes a light source optical system and display device 1601 and a screen 1602. The semiconductor display device of the present invention can be applied to the display device 1601 and other circuits.
[0101]
FIG. 17B shows a rear projector, which includes a main body 1701, a light source optical system and display device 1702, mirrors 1703 to 1704, and a screen 1705. The semiconductor display device of the present invention can be applied to the display device 1702 and other circuits.
[0102]
17C is a diagram showing an example of the structure of the light source optical system and display device 1601 shown in FIG. 17A and the light source optical system and display device 1702 shown in FIG. 17B. is there. The light source optical system and display devices 1601 and 1702 include a light source optical system 1801, mirrors 1802 and 1804 to 1806, a dichroic mirror 1803, an optical system 1807, a display device 1808, a retardation plate 1809, and a projection optical system 1810. The projection optical system 1810 is composed of a plurality of optical lenses provided with a projection lens. This configuration is called a three-plate type because three display devices 1808 are used. Further, in the optical path indicated by the arrow in the figure, an optical lens, a film having a polarizing function, a film for adjusting a phase difference, an IR film, or the like may be appropriately disposed.
[0103]
FIG. 17D is a diagram showing an example of the structure of the light source optical system 1801 in FIG. 17C. In this embodiment, the light source optical system 1801 includes a reflector 1811, a light source 1812, lens arrays 1813 to 1814, a polarization conversion element 1815, and a condenser lens 1816. Needless to say, the light source optical system 1801 shown in the figure is merely an example, and is not limited to this configuration. For example, the light source optical system 1801 may be appropriately provided with an optical lens, a film having a polarization function, a film for adjusting a phase difference, an IR film, or the like (see FIG. 17).
[0104]
FIG. 18-A shows an example of a single plate type. The light source optical system and display device shown in FIG. 1 includes a light source optical system 1901, a display device 1902, a projection optical system 1903, and a retardation plate 1904. The projection optical system 1903 is composed of a plurality of optical lenses provided with a projection lens. The light source optical system and the display device shown in the figure can be applied to the light source optical system and the display devices 1601 and 1702 in FIGS. 17A and 17B. The light source optical system 1901 may use the light source optical system shown in FIG. Note that a color filter (not shown) is attached to the display device 1902 so that the display image is colored.
[0105]
The light source optical system and display device shown in FIG. 18-B is an application example of FIG. 18-A, and instead of providing a color filter, an RGB rotating color filter disc 1905 is applied to color the display image. Yes. The light source optical system and the display device shown in the figure can be applied to the light source optical system and the display devices 1601 and 1702 in FIGS. 17A and 17B.
[0106]
The light source optical system and display device shown in FIG. 18-C are called a color filterless single plate type. In this method, a microlens array 1915 is attached to a display device 1916, and a dichroic mirror (green) 1912, a dichroic mirror (red) 1913, and a dichroic mirror (blue) 1914 are applied to color a display image. The projection optical system 1917 includes a plurality of optical lenses provided with a projection lens. The light source optical system and the display device shown in the figure can be applied to the light source optical system and the display devices 1601 and 1702 in FIGS. 17A and 17B. Further, as the light source optical system 1911, an optical system using a coupling lens and a collimator lens in addition to the light source may be applied (see FIG. 18).
[0107]
As described above, the present invention can be applied to various electronic devices incorporating a semiconductor display device such as an active matrix liquid crystal display device and an EL display device, which has an extremely wide application range.
[0108]
【The invention's effect】
The effects of the present invention are listed below. The first effect is that etching damage to the silicon-based semiconductor film of the TFT due to the resist stripping solution can be surely prevented in the resist stripping step. The second effect is that the etching damage of the silicon-based semiconductor film of the TFT can be surely prevented, which is effective in stabilizing the electrical characteristics of the TFT and improving the yield of the semiconductor device. The third effect is that by applying the resist stripping apparatus of the present invention, it is possible to increase the throughput of the resist stripping process while maintaining the first and second effects.
[Brief description of the drawings]
FIG. 1 is a process cross-sectional view illustrating a manufacturing process of a TFT.
FIG. 2 is a process cross-sectional view illustrating a manufacturing process of a TFT.
FIG. 3 is a process cross-sectional view illustrating a process for forming a polycrystalline silicon film.
FIG. 4 is a process cross-sectional view showing a film formation process of a crystalline silicon film obtained using a catalytic element.
FIG. 5 is a plan view showing an overall outline of a resist stripping apparatus.
FIG. 6 is a side sectional view showing a specific configuration of a protective film forming unit.
FIG. 7 is a side sectional view showing a specific configuration of a protective film forming unit.
FIG. 8 is a process cross-sectional view illustrating a manufacturing process of an active matrix liquid crystal display device.
FIG. 9 is a process cross-sectional view illustrating a manufacturing process of an active matrix liquid crystal display device.
FIG. 10 is a process cross-sectional view illustrating a manufacturing process of an active matrix liquid crystal display device.
FIG. 11 is a process cross-sectional view illustrating a manufacturing process of an active matrix liquid crystal display device.
FIG. 12 is a process cross-sectional view illustrating a manufacturing process of an active matrix liquid crystal display device.
FIG. 13 is a process cross-sectional view illustrating a manufacturing process of an active matrix liquid crystal display device.
FIG. 14 is a process cross-sectional view illustrating a manufacturing process of an active matrix liquid crystal display device.
FIGS. 15A and 15B are a cross-sectional view and a plan view showing a structure of an n-channel TFT. FIGS.
FIG. 16 is a schematic diagram illustrating an example of an electronic device incorporating a semiconductor display device.
FIG. 17 is a schematic diagram illustrating an example of an electronic device incorporating a semiconductor display device.
FIG. 18 is a schematic diagram illustrating an example of an electronic device incorporating a semiconductor display device.

Claims (8)

A first step of forming a semiconductor film containing silicon on the surface of the substrate;
A second step of forming a first oxide film on the semiconductor film containing silicon;
A third step of forming a resist pattern on the semiconductor film containing silicon;
A fourth step of patterning the semiconductor film containing silicon to form an island-shaped semiconductor layer;
A fifth step of ashing the resist pattern and forming a second oxide film on a sidewall of the island-shaped semiconductor layer;
A sixth step of stripping the resist pattern with a resist stripper;
A seventh step of removing the first and second oxide films;
An eighth step of depositing a gate insulating film so as to cover the semiconductor layer;
A ninth step of depositing a gate electrode film on the gate insulating film;
A tenth step of patterning the gate electrode film to form a gate electrode;
An eleventh step of forming a source region and a drain region in the semiconductor layer corresponding to the outside of the gate electrode by doping an impurity element of one conductivity type;
A twelfth step of depositing a first interlayer insulating film so as to cover the gate electrode;
A thirteenth step of forming a second interlayer insulating film on the first interlayer insulating film;
A fourteenth step of forming a resist pattern on the second interlayer insulating film;
A fifteenth step of forming a contact hole by dry-etching a laminated film composed of the gate insulating film, the first interlayer insulating film, and the second interlayer insulating film using the resist pattern as a mask;
A sixteenth step of forming a protective film against an organic resist stripping solution on the exposed surface of the island-shaped semiconductor layer present at the bottom of the contact hole;
And a seventeenth step of stripping the resist pattern with the resist stripping solution.   The method for manufacturing a semiconductor device according to claim 1, wherein a silicon oxide film is formed as the protective film.   3. The method for manufacturing a semiconductor device according to claim 2, wherein the silicon oxide film is formed by treatment with ozone-containing water.   3. The method for manufacturing a semiconductor device according to claim 2, wherein the silicon oxide film is formed by treatment with a hydrogen peroxide solution. In any one of claims 1 to 4, wherein the first interlayer insulating film, a method for manufacturing a semiconductor device characterized by depositing a silicon oxynitride film or a silicon nitride film having a thickness of 50~300nm . In any one of claims 1 to 4, wherein the first interlayer insulating film, a method for manufacturing a semiconductor device characterized by depositing a silicon oxynitride film or a silicon nitride film having a thickness of 100~200nm . In any one of claims 1 to 6, wherein the second interlayer insulating film, a method for manufacturing a semiconductor device characterized by depositing an acrylic resin film with a thickness of 0.7～3Myuemu. In any one of claims 1 to 6, wherein the second interlayer insulating film, a method for manufacturing a semiconductor device characterized by depositing an acrylic resin film with a thickness of 1 to 2 [mu] m.

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