JP4272607B2 - SOI by oxidation of porous silicon - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor substrate structure, and more particularly to a method for manufacturing a silicon-on-insulator (SOI) substrate structure. The method of the present invention provides a very low cost SOI material that is attractive to the silicon integrated circuit (IC) industry. The SOI material provided by the method of the present invention can be expanded to 300 mm.

In today's microelectronic IC industry, semiconductor devices are miniaturized to the micron (10 ⁻⁶ m) or even nanometer (10 ⁻⁹ m) scale, which itself is the upper surface layer of a semiconductor substrate or wafer. Made on top. The bulk of the substrate under the top device layer has no purpose beyond becoming a physical support substrate or heat sink. In fact, the electrical and electronic coupling between this device layer and the bulk can be extremely detrimental in some cases.

  In SOI technology, the SOI layer and the bulk substrate layer are separated by a continuous insulating layer called a buried oxide film (BOX). This device layer (ie, SOI layer) separation or isolation can be achieved, for example, by reducing junction capacitance and junction leakage, increasing ionizing radiation resistance, electrical noise resistance and heat resistance, and CMOS latchup resistance. Important benefits, including gender etc., and performance improvements can be provided. However, formation of an SOI structure is not easy.

  Decades of research and development have shown that only a few methods are commercially feasible. One method, called BESOI (bond-and-etch-back SOI), oxidizes two Si wafers on the surface, bonds the oxidized surfaces, and then combines the two bonded wafers. One is etched to form a thin SOI device layer. In this prior art method and variations thereof, the wafer surface is oxidized before bonding, so that the buried oxide film can be made to any desired thickness. However, the main problems are the impurities at the bonded interface and the difficulty of realizing a thin and uniform Si overlayer by the etch-back method. The terms “Si overlayer” and “SOI layer” may be used interchangeably in this application.

  Another known method, called SIMOX (separation by oxygen implantation), implants a selected implantation amount of oxygen ions directly into a Si wafer, which is then continuously embedded in the oxygen atmosphere in an oxygen atmosphere. Annealing is performed at a high temperature that can be converted into an oxide film layer. The thickness of the buried oxide film layer in SIMOX is substantially determined by the amount of implanted oxygen and thermal oxidation conditions. Further, in SIMOX, the Si over layer is thinned to a desired thickness during thermal oxidation, and the surface oxide film is peeled off after the heat treatment.

Usually, in SIMOX, an oxygen implantation amount of about 3 × 10 ¹⁷ cm ^{−2 to} 5 × 10 ¹⁷ cm ⁻² is required to form a low-defect continuous buried oxide film that separates the substrate and the Si overlayer. is there. In order to facilitate the implantation of this high level of oxygen ions in a reasonable time, a high current (ion) implanter for SIMOX was specially constructed at an additional cost. As Si substrates scale up to larger wafer dimensions, the high cost of scaled up high current implanters and the implant process itself becomes a serious problem.

Porous Si is formed by electrolytic anodization in an HF-containing aqueous solution. An HF-resistant electrode such as platinum is negatively biased, and a low or high concentration p-doped Si substrate is positively biased. The porosity measured by the volume loss of the porous Si layer formed in the surface of the obtained Si wafer layer is proportional to the current and voltage, and inversely proportional to the HF concentration. The depth of the formed porous Si layer is proportional to the anodization time for a given dopant concentration. However, the actual structure of porous Si is a very complex function of dopant and defect type and concentration in addition to the above parameters. A characteristic common to porous Si materials is the huge surface area associated with dense pores. This surface area per unit volume is estimated to be 100-200 m ² / cm ³ . Due to the presence of this large surface area, porous Si is very likely to cause a chemical reaction with an atmospheric gas such as oxygen. It has been found that the oxidation rate of porous Si is an order of magnitude greater than that of bulk Si. For this reason, porous Si is a good candidate for oxide film separation.

  A well-known method called FIPOS (complete separation with porous silicon oxide) uses a patterning process followed by HF anodization to surround the shallow Si island and subsequently oxidizes the porous Si to completely separate it. Porous Si is formed by producing the Si island. Oxidized porous Si provides good separation, but is generally too thick and laterally non-uniform compared to Si islands. This non-uniformity causes the Si wafer to warp and many oxidation-induced defects are formed in the Si island.

  In view of the above disadvantages with prior art SOI substrate manufacturing methods, there is a continuing need to provide new and improved SOI substrate structure forming methods that are relatively simple and not costly.

  Accordingly, one object of the present invention is to provide a simple and cost-effective method of manufacturing a silicon-on-insulator (SOI) substrate structure.

  Another object of the present invention is to provide a method for manufacturing SOI substrate structures with reduced defect levels by reducing implantation damage and reducing oxidation-induced stresses and strains.

  Yet another object of the present invention is to provide a simple and cost effective method of manufacturing an SOI substrate structure that can be expanded to 300 mm.

  Yet another object of the present invention is to provide a method of manufacturing an SOI substrate structure that does not use wafer bonding and / or oxygen implantation.

  These and other objects and advantages can be realized by using a method in which an SOI substrate structure is made by oxidizing porous Si with a graded porosity. This graded porous Si comprises a relatively rough top layer and a fine porous layer embedded under the top layer. In the next oxidation step, this fine buried porous layer is converted into a buried oxide film, and the rough top layer is dissolved into the solid Si-containing overlayer by surface migration of Si atoms. Much of this Si top layer becomes a thermal oxide that can be easily removed, leaving only a thin Si overlayer on the buried oxide.

  When using the whole surface implantation in the method of the present invention, porous Si having a porosity gradient is spatially laterally uniform on the surface of the Si-containing substrate, and oxidation occurs uniformly from all regions of the surface. Therefore, the buried oxide film is uniform and the Si over layer is relatively free of stress.

  The method of the present invention provides several additional benefits over the SIMOX method described above. One such benefit is that no expensive high current injection device is used. A related benefit is that the damage associated with injection is reduced. Furthermore, the oxidation-induced stress and strain are small. This is because, during oxidation, porous Si has less volume expansion than bulk Si.

Specifically and broadly, the method of the present invention comprises:
Providing a porous Si-containing structure with a porosity gradient;
Oxidizing the graded porous Si-containing structure to form a silicon-on-insulator (SOI) with a uniform buried oxide layer and a Si-containing overlayer.

  In the present invention, porous Si with a gradient in porosity is first implanted with a dopant (p-type or n-type) into a Si-containing substrate and activated using an activation annealing step, and then implanted. The activated dopant region is formed by anodizing in an HF-containing solution.

  In one embodiment of the present invention, a short oxidation anneal step was used to create an intermediate SOI structure that includes a discontinuous oxide and a continuous oxide. An additional anneal may be performed to convert the two different oxides into a continuous single buried oxide region.

  In other embodiments, two different injection steps, dual injection, were used. One of the two implantation steps involves implanting an n-type or p-type dopant into the structure, and the other implantation step results in damage formation in the structure, and ions that are neutral to Si are structured. Injecting into. In this neutral ion implantation, an amorphous region may or may not be formed in the structure. The sequence of these two implantation steps can be (A) implanting an n-type or p-type dopant followed by neutral ions, or (B) implanting neutral ions followed by An n-type or p-type dopant can also be implanted.

  In yet another embodiment of the invention, the two injection steps are performed as described above, and the ranges of the injection peaks substantially overlap each other.

  The structure provided by the method of the present invention comprises an SOI substrate structure comprising a Si-containing overlayer of a desired thickness, a uniform buried oxide layer directly under the Si-containing overlayer, and a Si-containing substrate under the buried oxide film. It is. This Si-containing overlayer is almost defect-free and thin (thinner than about 100 nm). This buried oxide layer formed using the method of the present invention is uniform and has a thickness in the range of about 50-200 nm. The term “uniform” as used in the present invention means that the buried oxide layer has a continuous interface with the Si-containing overlayer and the Si-containing base substrate, and the thickness variation across the wafer is 20 times the total thickness of the buried oxide. % Is less than%.

  The present invention provides a simple and low cost method of SOI substrate structure with a uniform buried oxide layer under a Si-containing overlayer, and will now be described in more detail with reference to the accompanying drawings. explain. In the accompanying drawings, the same or corresponding components are denoted by the same reference numerals.

First, referring to the initial structure shown in FIG. 1, this initial structure includes a Si-containing substrate 10 in which a dopant region 12 is formed. As used herein, the term “Si-containing substrate” refers to a semiconductor material containing at least silicon. Illustrative examples of such Si-containing substrates include, but are not limited to, Si, SiGe, SiC, SiGeC, epi-Si / Si, epi-Si / SiC, epi-Si / SiGe, and within Included are silicon-on-insulator (SOI) or SiGe-on-insulator (SGOI), which can include any number of buried insulating (ie, continuous, non-continuous, or a combination of continuous and non-continuous) regions formed. This Si-containing substrate may be undoped or doped. The doping into the Si-containing substrate 10 may be a low concentration (dopant concentration: less than 1 × 10 ¹⁷ atoms / cm ³ ) or a high concentration (dopant concentration: 1 × 10 ¹⁷ atoms / cm ³ or more).

  More specific examples of the Si-containing substrate include a p + substrate, an n-doped substrate, a p-epi / p- substrate, a p-epi / n-substrate, a p + epi / p-substrate, a p + epi / n substrate, and an n-epi / A p-substrate, n + epi / p-substrate, p + SiGe / p-Si, or p +, p-SOI is included. In one embodiment using the doped Si-containing semiconductor substrate 10, the Si-containing semiconductor substrate 10 is preferably a p + substrate. When an epi layer is formed on the top surface of the substrate, the epi layer is formed using conventional epitaxial growth methods known to those skilled in the art.

This doped region 12 is either an n-type dopant region or a p-type dopant region formed in the Si-containing substrate 10 by ion implantation. In one embodiment, p-type dopants such as Ga, Al, B, BF ₂ are used. Of these p-type dopants, B and BF ₂ are particularly preferred.

During this step of the invention, the dopant concentration implanted can vary depending on the type of dopant implanted. For n-type dopants, the implanted dopant concentration is typically about 1 × 10 ¹⁷ to about 1 × 10 ²¹ atoms / cm ³ , and for p-type dopants, the implanted dopant concentration is generally about 1 × 10 ¹⁷ to about 1 × 10 ²¹ atoms / cm ³

According to the present invention, an n-type or p-type dopant is implanted into the Si-containing substrate 10 so that the dopant concentration peak is at a certain depth below the upper surface of the substrate. More specifically, the implantation conditions are sufficient to form a deep implantation region with a depth of about 250 to about 1500 nm as measured from the top surface of the substrate. In a preferred embodiment, implant region 12 can be formed using boron with an energy of about 100 keV to 500 keV and BF ₂ with an energy of about 500 keV to 2500 keV. The implantation amount of B and BF ₂ is about 5 × 10 ¹⁵ to about 5 × 10 ¹⁶ atoms / cm ² .

  In some embodiments of the present invention, neutral ions that cause damage in the Si-containing substrate 10 are used with the dopant implantation described above. In the present invention, the term “neutral ion” refers to any ion that does not interact with the Si-containing substrate 10. Illustrative examples of such neutral ions include, but are not limited to, Si, Ge, Ne, Bi, Sn, Xe, and the like. Preferably, Si is used as a neutral ion. This neutral ion causes damage formation that may help to form a porous Si region. The damaged region is formed above, below, or in the dopant region. The neutral ions can be implanted before or after the dopant implantation step. Depending on the implantation conditions and the neutral ions used, an amorphized region may be formed in the Si-containing substrate 10 by this implantation step. In one embodiment, the neutral ion peak is matched to the dopant ion implantation peak such that the two implantations overlap one another.

The conditions for this optional neutral ion implantation step can vary depending on the ions used and the desired depth of the ions. In a preferred embodiment, Si is implanted at an energy of about 200 keV to 500 keV below normal room temperature and an implant dose of about 1 × 10 ¹⁴ to about 1 × 10 ¹⁶ atoms / cm ² . The two implants, or dual implants, when used can form a single or double SOI structure depending on the conditions used during thermal oxidation.

  Next, the structure of FIG. 1 is annealed to activate the dopant in the dopant region 12 to form holes (for p-type dopants) and electrons (for n-type dopants). The structure after annealing is shown in FIG. In FIG. 2, reference numeral 14 denotes an activated dopant implantation region formed after annealing. In general, as the annealing temperature is increased, more dopant ions are activated and at the same time more dopant ions are diffused to broaden the implantation profile. According to the present invention, the annealing step must be performed at a temperature at which at least concentration peak dopant ions are almost activated. In the region around the concentration peak, the dopant ions are generally not fully activated, thus indicating that the Si lattice region remains somewhat mismatched due to implantation damage. In some cases, the carrier profile may include peaks and valleys due to the inert dopant.

The anneal used at this point of the invention can include furnace anneal, rapid thermal anneal, or spike anneal. When furnace annealing is used, the furnace annealing is generally performed at a temperature of 600 ° C. or more for about 15 minutes or more. Preferably, the furnace anneal is performed at a temperature of about 650 ° C. to about 800 ° C. for a time of about 15 to about 250 minutes. This furnace annealing is generally performed in the presence of a rare gas atmosphere and / or an oxidizing atmosphere gas including, for example, He, Ar, O ₂ , N ₂ and a mixed gas thereof.

When using rapid thermal annealing (RTA), the RTA is generally performed at a temperature of about 800 ° C. or higher for a time of about 5 minutes or less. Preferably, the RTA is performed at a temperature of about 900 ° C. to about 1050 ° C. for a time of about 5 to about 30 seconds. This rapid thermal annealing is generally performed in the presence of a rare gas atmosphere and / or an oxidizing atmosphere gas including He, Ar, O ₂ , N ₂ and a mixed gas thereof.

When performing the spike annealing, the spike annealing is generally performed at a temperature of about 900 ° C. or more for a time of about 1 second or less. Preferably, spike annealing is performed at a temperature of about 900 ° C. to about 1100 ° C. This spike annealing is generally performed in the presence of a rare gas atmosphere and / or an oxidizing atmosphere gas including, for example, He, Ar, O ₂ , N ₂ and a mixed gas thereof.

  Of the various annealing techniques described above, it is preferable to use furnace annealing. When the dopant is B and furnace annealing is used, it is preferable to perform the annealing at about 650 ° C. for 2-3 hours.

  Next, as shown in FIG. 3, the structure shown in FIG. 2 is subjected to an electrolytic anodization process that can convert the activated dopant region 14 into a porous region 16. The structure shown in FIG. 3 can be referred to as a gradient porous Si-containing structure. The porous Si region 16 has a structure that closely reflects the carrier and damage profile. That is, a region having a high residual injection damage and a low carrier concentration has a rough porous structure, and a region having a high carrier concentration has a fine porous structure. Therefore, this porous structure is not uniform and has a gradient.

  The fine porous region 16 b is mainly present at the lower part of the porous region 16, and the coarse porous region 16 a is mainly present at the upper part of the porous region 16. The fine porous region 16b has a higher density (that is, contains a smaller number of pores) than the coarse porous Si region 16a. Since coarse porous Si has a very large surface area, any type of surface reaction, including oxidation, should occur faster than fine porous Si.

  The anodization process is performed by immersing the structure shown in FIG. 2 in the HF-containing solution while also electrically biasing the structure against an electrode placed in the HF-containing solution. In such a process, this structure generally serves as the positive electrode of the battery, and another semiconductor material or metal such as Si is used as the negative electrode.

  In general, doped single crystal Si is converted to porous Si by HF anodization. The rate of formation and the nature of the porous Si so formed (porosity, microstructure) depend on the material properties, ie the doping type and concentration, and the reaction conditions of the anodization process itself (current density, bias, illuminance) , And additives in HF-containing solutions). Specifically, in the more highly doped region, porous Si is formed with significantly higher efficiency, and thus the activated dopant region 14 is efficiently converted to porous Si.

  Generally, the porous Si region 16 formed in the present invention has a porosity of about 0.01% or more. The depth of the porous Si region 16 is about 50 nm or more as measured from the top surface of the structure to the top surface of the porous Si.

  The term “HF-containing solution” means high concentration HF (49%), high concentration HF and acetic acid, a mixture of HF and water, a mixture of HF and methanol, a monohydric alcohol such as ethanol, propanol, or at least one of Contains HF mixed with surfactant. The amount of surfactant present in the HF solution is generally from about 1 to about 80% when 49% HF is used.

This anodization process, which converts the activated dopant region 14 into a graded porous Si region 16, is performed using a constant current source operating at a current density of about 0.05 to about 50 milliamps / cm ² . A light source can optionally be used for illumination of the sample. More preferably, the anodization process of the present invention is performed using a constant current source operating at a current density of about 0.1 to about 5 milliamps / cm ² .

  This anodization process is generally carried out at room temperature, or temperatures higher than room temperature can be used. Following the anodization process, the structure is generally rinsed with deionized water and dried.

  In an optional embodiment of the present invention, an optional cap layer 18 is formed on the Si-containing substrate 10 containing the porous region 16 at this point of the present invention. A structure comprising this optional cap layer 18 is shown, for example, in FIG. This optional cap layer 18 used in the present invention includes, for example, epitaxial Si (epi-Si), SiGe, amorphous Si (a: Si), single crystal or polycrystalline Si, or any combination thereof, Includes any Si-containing material. Of the various Si materials described above, it is preferable to use epi-Si or SiGe as the optional cap layer 18.

  The optional cap layer 18, when present, is about 1 to about 100 nm thick, more preferably about 1 to about 50 nm thick. The optional cap layer 18 is formed using known deposition methods including the epitaxial growth method described above.

  Next, regardless of the presence or absence of the optional cap layer 18, the structure including the porous Si region 16 formed in this manner is subjected to dry thermal oxidation at a temperature at which the porous Si region 16 is converted into the buried oxide region 20. Heat or anneal using the method. The structure thus obtained comprising the buried oxide region 20 and the Si-containing overlayer 22 is shown, for example, in FIG. Note that an oxide layer 24 is formed on layer 22 during this heating step. The surface oxide film layer, that is, the oxide film layer 24 is not always always used, but generally uses a conventional wet etching method using a chemical etchant such as HF which removes the oxide film with high selectivity compared to silicon. And removed from the structure after the heating step. FIG. 6 shows the structure after the surface oxide film layer 24 is removed.

  According to the present invention, the fine porous Si region is converted into a buried oxide region 20, and the coarse porous Si region is typically fused to single crystal Si and then fused to the Si-containing overlayer 22. The thicknesses of the buried oxide film and the Si-containing overlayer can be controlled to desired values by adjusting the thermal oxidation conditions.

  The thickness of this surface oxide film 24 formed after the heating step of the present invention may be about 10 to about 1000 nm, more typically about 20 to about 500 nm.

  Specifically, the heating step of the present invention is a dry thermal oxidation process performed at a temperature of about 650 ° C. to about 1350 ° C., more preferably at a temperature of about 1200 ° C. to about 1325 ° C. In some embodiments of the present invention, thermal oxidation can be performed at temperatures below 650 ° C., particularly when a fractured or discontinuous buried oxide and continuous oxide is desired. In general, for this embodiment of the invention, the fractured buried oxide film can be formed by performing thermal oxidation at a temperature of about 1250 ° C. to about 1325 ° C. When a structure including a fractured buried oxide film and a continuous oxide film is converted into a single buried oxide film structure, annealing can be further performed within the above general temperature range.

Furthermore, the heating step of the present invention is performed in an oxidizing atmosphere containing at least one oxygen-containing gas, such as O ₂ , NO, N ₂ O, ozone, air, or other similar oxygen-containing gas. The oxygen-containing gas may be mixed with each other (such as a mixed gas of O ₂ and NO), or may be diluted with a rare gas such as He, Ar, N ₂ , Xe, Kr, or Ne. When a dilute atmosphere is used, the dilute atmosphere contains about 0.5 to about 100% oxygen-containing gas with the remainder being up to 100% noble gas.

  This heating step can be carried out at a temperature of about 1250 ° C. to about 1325 ° C., usually for about 10 to about 1800 minutes, more preferably for about 60 to about 600 minutes. The heating step can be performed at a single target temperature or can be performed at various ramps and soak cycles using various ramp rates and soak times.

  In some embodiments of the invention, a pre-oxidation step is performed. This pre-oxidation step is performed in a wet oxygen atmosphere such as steam at a temperature of about 600 ° C. to about 1200 ° C., more preferably at a temperature of about 800 ° C. to about 1000 ° C. The pre-oxidation step is advantageous in that it converts porous Si to an oxide film at a faster rate before the porous Si coalesces into large Si grains.

In another embodiment of the present invention that implants excess dopant ions, post-oxidation thermal annealing may be used to reduce the level of dopant in the Si-containing overlayer in an atmospheric pressure or reduced pressure hydrogen atmosphere. it can. When performing such post-oxidation processes, this thermal annealing in a hydrogen atmosphere is performed at a temperature of about 900 ° C. to about 1200 ° C., more preferably at a temperature of about 1000 ° C. to about 1050 ° C. Examples of the hydrogen atmosphere include H ₂ , NH ₄ , or a mixed gas thereof including a mixed gas containing a rare gas or a mixed gas not containing a rare gas. The concentration of dopant ions in the Si-containing overlayer can be reduced by more than two orders of magnitude using the post-oxidation thermal anneal described above.

  According to the present invention, the thickness of the Si-containing overlayer 22 is about 1000 nm or less, more preferably about 100 to about 500 nm. Note that the Si-containing overlayer 22 formed in the present invention is substantially free of defects. The buried oxide layer 20 formed during the heating step has a thickness of about 100 to about 200 nm. The buried oxide layer 20 has a smooth and continuous interface with the Si-containing overlayer 22.

  As noted above, the surface oxide layer 24 can be stripped at this point in the present invention to provide, for example, the Si-on-insulator substrate material shown in FIG.

  In addition to the non-patterned structures in FIGS. 1-6 shown above, the present invention also contemplates forming patterned structures. This patterned structure and the method of forming it are shown, for example, in FIGS. Specifically, FIG. 7 shows the initial structure of this embodiment in which discrete and isolated islands of dopant regions 14 implanted and activated in the Si-containing substrate 10 are formed. The discrete and isolated islands of implanted and activated dopant regions 14 can be formed using a masked ion implantation technique.

  The structure of FIG. 8 is then subjected to the anodization process described above. As described above, in this anodic oxidation process, the porous Si region 16 is formed in the substrate. Next, although not shown, an optional cap layer can be formed on the structure.

  The structure is then subjected to the annealing step described above, with or without an optional cap layer, to obtain, for example, the structure shown in FIG. Note that reference numerals 10, 20, and 22 have the same meaning as described above, and the surface oxide layer 24 has been removed from this structure.

  10 and 11 illustrate another alternative embodiment of the present invention in which a double SOI layer is formed in the same structure. In providing the structure shown in FIG. 6, this double SOI layer is formed by first performing the above steps. After providing this structure, a Si-containing substrate 10 'containing implanted and activated dopant 14' is formed over the structure. FIG. 10 shows this structure. Next, the anodization and annealing steps are repeated to provide, for example, the structure shown in FIG. In FIG. 11, a second buried oxide film layer 20 'is formed, and a second Si-containing overlayer 22' is formed. The same process can be repeated many times to provide a multilayer SOI structure. The multilayer SOI layers may all be continuous, discontinuous, or exist as a combination thereof.

FIG. 12 shows an actual SEM image of a porous Si structure produced using the method of the present invention. This porous Si structure was prepared by implanting B at 220 keV using a dose of about 2 × 10 ¹⁶ cm ^{−2 in} a p− / p + Si substrate, followed by annealing at 650 ° C. for 2 hours 45 minutes. Is. The implanted and activated substrate was then anodized in HF (49%) within 1 minute to provide the porous Si shown in FIG. The structure shown in FIG. 12 comprises a sloped upper region made of fine porous Si with a distinct band corresponding to the peak region of the implanted B profile. Then, as explained above, this porous Si structure shown in FIG. 12 can be oxidized to an SOI structure.

FIG. 13 shows an SEM image of an SOI structure made of porous Si formed by B + implantation. The implantation conditions used to form this porous Si structure were as follows. B + implantation, implantation amount: 2 × 10 ¹⁶ atoms / cm ² , implantation energy: 220 keV. Anodization was performed using the conditions described above. The dopant activation step was performed at 650 ° C. for 2 hours 45 minutes before forming porous Si. The SOI structure includes the following four layers. (I) The uppermost Si layer extending from the surface to the fractured buried oxide film (box 1), (ii) the fractured buried oxide film layer (box 1), (iii) continuous with the fractured oxide film (box 1) Si layer sandwiched between the oxidized oxide films (BOX2), and (iv) a continuous buried oxide film (referred to as BOX2). Further oxidation is performed to consume the above layers (i) and (ii), thereby a single Si layer (above layer (iii)) over a continuous BOX layer (above layer (iv)) An SOI structure comprising

FIG. 14 shows an SEM of an engineered porous Si structure prepared using a dual injection method. Specifically, this dual injection method included the following steps. B + implantation: 220 keV, 2 × 10 ¹⁶ atoms / cm ² , Si + implantation: 220 keV, 2 × 10 ¹⁵ atoms / cm ² . Anodization was performed using the above conditions. Two bands of porous Si are present in the SEM micrograph. The first band corresponds to the peak region of the implanted Si + profile and the second band corresponds to the peak region of the implanted boron profile.

FIG. 15 shows an SEM of a double SOI structure formed by advanced processing of a porous Si structure by dual implantation. The following conditions were used in forming the structure shown in FIG. B +: 180 keV, 2 × 10 ¹⁶ atoms / cm ² , Si +: 220 keV, 2 × 10 ¹⁵ atoms / cm ² . As shown, this structure comprises two SOI layers and two BOX regions. BOX1 corresponds to the first band of porous Si in FIG. 14, and BOX2 corresponds to the second band of porous Si in FIG. Some of the surface Si in FIG. 14 was consumed by the annealing oxidation necessary to form a continuous buried oxide region.

FIG. 16 shows an SEM of a porous Si-containing structure that has been highly processed by dual implantation. This structure was formed using the following conditions when formed. B +: 160 keV, 2 × 10 ¹⁶ atoms / cm ² , Si +: 220 keV, 2 × 10 ¹⁵ atoms / cm ² . B + and Si + implantation conditions were selected such that the projected ranges of B + and Si + coincided with each other. Thus, the porous Si bands of FIG. 14 overlapped each other in this case, resulting in a single porous Si band with a single porous Si band but with a high density of pores.

FIG. 17 shows a single SOI SEM prepared by dual injection. This structure uses the following conditions: (B +: 150 keV, 2 × 10 ¹⁶ atoms / cm ² , Si +: 220 keV, 2 × 10 ¹⁵ atoms / cm ² ), followed by dopant activity as described above It was formed by performing annealing, porous Si formation and high temperature annealing. The position of the buried oxide film layer corresponds to the position of the high-density Si band in FIG.

  While the invention has been particularly shown and described with respect to preferred embodiments thereof, those skilled in the art will recognize that changes may be made to the above and other forms and details without departing from the scope and spirit of the invention. It will be understood. Accordingly, the present invention is not intended to be limited to that described and shown herein, but is intended to be included within the scope of the appended claims.

FIG. 3 is a pictorial diagram (seen in cross section) showing the basic processing steps of the present invention. FIG. 3 is a pictorial diagram (seen in cross section) showing the basic processing steps of the present invention. FIG. 3 is a pictorial diagram (seen in cross section) showing the basic processing steps of the present invention. FIG. 3 is a pictorial diagram (seen in cross section) showing the basic processing steps of the present invention. FIG. 3 is a pictorial diagram (seen in cross section) showing the basic processing steps of the present invention. FIG. 3 is a pictorial diagram (seen in cross section) showing the basic processing steps of the present invention. FIG. 6 is a pictorial view (seen in cross-section) showing an alternative embodiment of the present invention. FIG. 6 is a pictorial view (seen in cross-section) showing an alternative embodiment of the present invention. FIG. 6 is a pictorial view (seen in cross-section) showing an alternative embodiment of the present invention. FIG. 6 is a pictorial view (seen in cross-section) showing another alternative embodiment of the present invention. FIG. 6 is a pictorial view (seen in cross-section) showing another alternative embodiment of the present invention. It is a cross-sectional SEM image of the embedded porous Si structure of this invention. 2 is a cross-sectional SEM image of a structure in which a discontinuous, that is, damaged, oxide film and a continuous oxide film are formed in the SOI substrate structure of the present invention. 2 is a cross-sectional SEM image of a highly processed Si-containing structure of the present invention realized by using dual implantation. It is a cross-sectional SEM image of the double SOI substrate structure of the present invention prepared by advanced processing of porous Si by dual implantation. 2 is a cross-sectional SEM image of a highly processed Si-containing structure of the present invention realized by dual implantation. It is a cross-sectional SEM image of the SOI substrate structure of this invention by dual implantation.

Explanation of symbols

10 Si-containing substrate 10 'Si-containing substrate 12 Dopant region 14 Activated dopant region 14' Activated dopant region 16 Porous Si region 16a Fine porous Si region 16b Coarse porous Si region 18 Cap layer 20 Embedded oxide region 20 'Second buried oxide layer 22 Si-containing overlayer 22' Second Si-containing overlayer 24 Surface oxide film

Claims (28)

Comprising: providing a porous Si-containing structure with a gradient of porosity in the interior of the Si-containing substrate,
Implanting a dopant into the Si-containing substrate;
Activating the dopant in the Si-containing substrate to form an activated doped region;
Then subjecting the activated doped region to an anodization process;
Providing a porous Si-containing structure comprising an upper region made of porous Si having a higher porosity and a lower region made of porous Si having a lower porosity, and
Oxidizing the graded porous Si-containing structure to form a silicon-on-insulator (SOI) structure comprising a uniform buried oxide layer and a Si-containing overlayer.
A method for manufacturing a silicon-on-insulator substrate structure. The method of claim 1 , wherein the dopant is an n-type dopant or a p-type dopant. The method of claim 2 , wherein the dopant is a p-type dopant selected from the group consisting of Ga, Al, B, and BF ₂ . The method of claim 3 , wherein the p-type dopant is B, and the B is implanted with an energy of 100 keV to 500 keV and a dosage of 5 × 10 ^{15 to} 5 × 10 ¹⁶ atoms / cm ² . The method of claim 3 , wherein the p-type dopant is BF ₂ , and the BF ₂ is implanted with an energy of 500 keV to 2500 keV, and a dosage of 5 × 10 ^{15 to} 5 × 10 ¹⁶ atoms / cm ² . The method of claim 1 , wherein the activating step comprises an annealing step. The method of claim 6 , wherein the annealing step is selected from the group consisting of furnace annealing, rapid thermal annealing, and spike annealing. 8. The furnace annealing step according to claim 7 , wherein the annealing step is a furnace annealing step performed in the presence of a rare gas atmosphere, an oxidizing atmosphere, or a mixed atmosphere thereof at a temperature of 600 ° C. or more for 15 minutes or more. Method. The annealing step is a rapid thermal annealing (RTA) step performed in the presence of a rare gas atmosphere, an oxidizing atmosphere, or a mixed atmosphere thereof for 5 minutes or less at a temperature of 800 ° C or higher. 8. The method according to 7 . The annealing step is, for less than 1 second at 900 ° C. or higher, a rare gas atmosphere, a spike annealing step carried out in the presence of an oxidizing atmosphere or a mixed atmosphere thereof, according to claim 7 the method of. The method of claim 1 , wherein the anodizing process is performed in the presence of an HF-containing solution. The method of claim 11 , wherein the anodization process is performed using a constant current source at a current density of 0.05 to 50 milliamps / cm ² .   The method according to claim 1, wherein the porous Si-containing region has a porosity of 0.01% or more.   The method of claim 1, further comprising forming a cap layer on the Si-containing substrate after the providing step and before the oxidation. The method of claim 14 , wherein the cap layer comprises a Si-containing material.   The method of claim 1, wherein the oxidation is performed at a temperature of 650 ° C. to 1350 ° C.   The method according to claim 1, wherein a surface oxide film is formed on the Si-containing overlayer by the oxidation.   The method of claim 1, wherein the porous Si-containing region comprises discrete islands, and the buried oxide film of the SOI structure comprises discrete islands of thermal oxide film.   The method of claim 1, further comprising repeating the providing and oxidizing steps any number of times to form a multilayer Si-on-insulator material.   The method of claim 1, further comprising a pre-oxidation step including oxidation in a humid oxygen atmosphere prior to the oxidation. 21. The method of claim 20 , wherein the pre-oxidation step is performed at a temperature of 600 <0> C to 1200 <0> C.   The method of claim 1, further comprising a post-oxidation step comprising a thermal annealing step in a hydrogen atmosphere. The method of claim 22 , wherein the post-oxidation step is performed at a temperature of 900 ° C. to 1200 ° C.   The method of claim 2, further comprising a neutral ion implantation step into the Si-containing substrate before or after the dopant implantation step. 25. The method of claim 24 , wherein the neutral ion comprises Si, Ne, Sn, Bi, or Xe. 25. The method of claim 24 , wherein an amorphous region is formed in the Si-containing substrate by the neutral ion implantation step. The neutral ion is Si, and the implantation step is performed at a room temperature or a temperature below room temperature, an Si implantation amount of 1 × 10 ¹⁵ atoms / cm ² to 1 × 10 ¹⁶ atoms / cm ² , an implantation energy of 200 keV to 500 keV. 25. The method of claim 24 , wherein the method is performed using. The method of claim 1, further comprising subjecting the SOI structure to a post-oxidation thermal anneal performed in a hydrogen atmosphere .

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