JP4263005B2 - Solid-state imaging device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a solid-state image pickup device, and more particularly to a solid-state image pickup device in which a dynamic range is expanded using a nonlinear region of a solid-state image pickup element in a solid-state image pickup device used for an image input device such as a digital camera, a video camera, and an image scanner. It is.
[0002]
[Prior art]
In driving a conventional solid-state imaging device, first, an on-pulse is input to the gate of a reset switch (MOS transistor) to reset the floating diffusion region FD to a reference voltage. Next, an ON pulse is input to the gate of the transfer switch (MOS transistor) to reset the photoelectric conversion unit PD such as a photodiode. At this time, since the reset switch remains on, the charge of the photoelectric conversion unit PD is transferred to the floating diffusing unit (hereinafter referred to as “floating diffusion region” or “FD”). Then, the transfer switch is turned off to separate the photoelectric conversion unit PD and the floating diffusion region FD. Since all the charges remaining in the photoelectric conversion unit PD are transferred to the floating diffusion region FD, the n layer of the photoelectric conversion unit PD is completely depleted. As the transfer switch is turned off, accumulation of photoelectric charges in the photoelectric conversion unit PD starts.
[0003]
Subsequently, after the reset switch is turned off and charge is accumulated for a certain time, the transfer switch is turned on again to transfer the charge accumulated in the photoelectric conversion unit PD to the floating diffusion region FD. Then, after turning off the transfer switch, a selection pulse is input to the gate of the selection switch, and the signal amplified by the amplifying unit transistor is read out. The charge remaining in the photoelectric conversion unit PD is removed by performing the reset operation described above again. As a result, since the noise signal and the image signal can be output continuously, an image signal with reduced dark noise can be obtained by performing arithmetic processing in the subsequent noise cancellation circuit, and the saturation signal amplitude and dark signal can be obtained. The dynamic range defined by the time-to-noise ratio is expanded.
[0004]
However, in such a conventional solid-state imaging device, the saturation signal amplitude is limited by saturation variation, and only about 1/2 to 1/3 of the actual saturation signal is used as the saturation signal amplitude. For this reason, saturation variation has limited the dynamic range.
[0005]
In view of this, conventionally, there has been proposed a solid-state imaging device that expands a saturation signal amplitude and corrects a dynamic range by correcting saturation variation. In this conventional configuration, in order to suppress the saturation variation, a charge is reversely injected from the semiconductor substrate to obtain a saturation signal, and the saturation variation is corrected by calculating the saturation signal and the image signal thus obtained. By enlarging, an image signal with a wide dynamic range was acquired. Furthermore, the dynamic range with respect to the amount of incident light is further expanded using the nonlinear characteristics after saturation of the image signal (see, for example, Patent Document 1 and Patent Document 2).
[0006]
[Patent Document 1]
JP 2000-201300 A (FIGS. 1 to 8)
[Patent Document 2]
JP 2001-094880 A (FIGS. 1-8)
[0007]
[Problems to be solved by the invention]
However, in the solid-state imaging device having the above-described conventional configuration, in order to suppress the saturation variation, the charge is reversely injected from the semiconductor substrate to obtain the saturation signal, and the saturation variation is calculated by the calculation of the obtained saturation signal and the image signal. Since correction is performed, in the case of such a configuration example, the obtained saturation signal cannot be output in the same frame as the image signal data. Therefore, it is necessary to store the saturation signal data once in an external frame memory and perform arithmetic processing after obtaining the image signal data. Furthermore, since the nonlinear characteristics that the solid-state imaging device exhibits after saturation are determined by the semiconductor process conditions, there are variations from device to device, and there is another problem that the image cannot be adjusted according to the imaging conditions.
[0008]
The present invention has been made to solve the above-described problem, and an object of the present invention is to obtain an image signal that can continuously output an output signal from a pixel and a saturation signal and suppress saturation variation. It is another object of the present invention to provide a solid-state imaging device that can obtain an image signal with a wide dynamic range by using a nonlinear characteristic of a saturation characteristic.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, a solid-state imaging device according to the present invention includes a photoelectric conversion unit that captures an image signal and reads the image signal to the outside and converts the optical signal into a signal charge, and an on / off switch for signal charge transfer. Transfer switch means, and charge holding means for holding the signal charge transferred from the photoelectric conversion means. The solid-state imaging device further transfers reset power supply means for resetting the photoelectric conversion means and charge holding means, reset switch means for switching on / off the connection between the charge holding means and reset power supply means, and transfer to the charge holding means A signal amplifying switch means for amplifying the signal charge, and a selection switch means for reading out the signal charge amplified through the signal amplifying switch means to the outside as an image signal, A noise signal read after resetting the charge holding means, an image signal read after transferring signal charges from the photoelectric conversion means, and a second read after resetting the charge holding means after charging the photoelectric conversion means 4 types of output signals are read out, such as a noise signal and a saturation signal read out after the charge charged in the photoelectric conversion means is transferred to the charge holding means It is characterized by that.
[0010]
With the above configuration, the reset power supply 9 can be controlled from the outside, so that fixed pattern noise caused by variations in the photoelectric conversion unit PD of the solid-state imaging device can be reduced and the dynamic range can be expanded.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. In addition, the same code | symbol is attached | subjected to the element which is common in each figure, and the overlapping description is abbreviate | omitted.
[0012]
(Embodiment 1)
A solid-state imaging device according to Embodiment 1 of the present invention will be described below with reference to FIGS. FIG. 1 is a circuit diagram corresponding to one pixel of the solid-state imaging device according to Embodiment 1 of the present invention, FIG. 2 is a timing chart showing the drive timing, and FIGS. 3 and 4 incorporate the circuit of FIG. It is a figure which shows the potential profile at the time of operation | movement by the general | schematic cross-section structure of the manufactured semiconductor device.
[0013]
In the basic configuration shown in FIG. 1, reference numeral 1 denotes a photodiode section (hereinafter simply referred to as “PD”) that converts an optical signal into signal charges, and 2 denotes an on / off switch for transferring signal charges photoelectrically converted by PD1. The transfer transistor 7 is a floating diffusion portion (hereinafter simply referred to as “FD”) including a capacitor means for holding the signal charge transferred from the PD 1. The cathode of the PD 1 is connected to the FD 7 via the transfer transistor 2. It is connected to the. 3 is a reset transistor that switches on / off the connection between the FD 7 and the reset power source 9, 4 is a signal amplification transistor (source follower SF) for converting the signal charge transferred to the FD 7 into a voltage and reading the potential of the FD 7, 5 is a selection transistor for reading out an image signal to the outside, 6 is a vertical signal line for outputting the image signal read out through the signal amplification transistor 4 to the outside, 8 is a power source of PD1, 9 is a reset voltage Vrst A reset power source that determines the reset potential of PD1 and FD7, 10 is a source follower (SF) power source that determines the output characteristics of the signal amplification transistor 4, 11 is a control line for the transfer transistor 2, and 12 is a gate control pulse φtx for the transfer transistor 2. The control pulse generator to be generated, 13 is a reset power line connected to the reset power supply 9, and 14 is a reset. A reset control line for transmitting a reset control pulse φrst for controlling the gate transistor 3, 15 a read control line for transmitting a gate control pulse φsel of the selection transistor 5, and 19 an analog latch unit 19 for signal capacity and the like .
[0014]
In the solid-state imaging device of the present invention, the control pulse voltage φtx of the transfer transistor 2 can be changed, and the barrier voltage is adjusted by adjusting the off-voltage of the transfer transistor 2.
[0015]
The driving operation of the solid-state imaging device having the above configuration will be described below with reference to FIGS. First, in the PD reset period P1, the transfer transistor 2 and the reset transistor 3 are simultaneously turned on (φtx = high level ΔVg, φrst = high level) to reset PD1. In the potential profile at this time, as shown in FIG. 3A, since all the residual charges of PD1 are transferred to FD7, PD1 is completely depleted of charge. The PD potential at this time is called a depletion potential and is expressed by a voltage potential Vdep.
[0016]
Next, when the charge accumulation period Te is entered, as indicated by the hatched portion in FIG. 3B, the transfer transistor 2 and the reset transistor 3 are turned off, and signal charges corresponding to the amount of incident light are accumulated in PD1. In the FD reset period P2 in the charge accumulation period Te, as shown by the hatched portion in FIG. 3 (3), the reset transistor 3 is turned on, and the FD7 is supplied from the reset power supply 9 with the high level reset power supply potential Vrst1. Same potential.
[0017]
Thereafter, in the noise readout period P3, as shown in FIG. 3 (4), the reset transistor 3 is turned off, the potential of the FD 7 is amplified by the signal amplification transistor 4, and the selection transistor 5 is turned on. A readout signal is output from the vertical output line 6. A signal output from the vertical output line 6 at this time is a noise output (Vb1) that becomes a reference level. This noise output (Vb1) is a signal including a reset noise component generated when the FD 7 is reset and a fixed pattern noise caused by semiconductor manufacturing variations.
[0018]
Next, in the signal charge transfer period P4 after a lapse of a certain charge accumulation time Te from the period P1, as shown in FIG. 3 (5), by turning on the transfer transistor 2, the signal charge accumulated in PD1 is changed. Transferred to FD7. The potential of the FD 7 at this time is also read in the same manner as the noise output (Vb1) of the black level signal read in the previous noise reading period P3 (period P5).
[0019]
That is, the signal charge potential transferred from PD1 to FD7 is amplified by the signal amplification transistor 4 and turned on in the signal readout period P5, as shown in FIG. Output from the output line 6. The signal (voltage) output from the vertical output line 6 at this time becomes a signal component Vs1 depending on the amount of incident light. The difference (Vs1−Vb1) between the signal component (Vs1) and the noise output (Vb1) of the black level signal described above is obtained by a known difference calculation means (not shown), thereby suppressing reset noise components and fixed pattern noise. The output signal Vsig thus obtained is continuously obtained from the same pixel. The output signal Vsig thus obtained changes in proportion to the amount of light incident on the solid-state imaging device, and the relationship of the output signal Vsig with respect to the amount of incident light is shown in FIG.
[0020]
As shown in FIG. 5, in a region where the amount of light incident on the image sensor is low, that is, in a linear region where the PD 1 has not reached the accumulated charge saturation state, the output signal Vsig obtained from the image sensor changes linearly with respect to the amount of incident light. To do. As the signal charge accumulated in PD1 approaches the saturation charge number Qmax (maximum chargeable number of charges), a nonlinear response is exhibited. Therefore, the effective operation region of the solid-state imaging device is about ½ of the number of saturated charges Qmax as shown in FIG. Further, it is known that when the amount of incident light is further increased, the output signal Vsig responds nonlinearly to the amount of incident light (a broken line characteristic called “knee characteristic”).
[0021]
In this nonlinear region, the output signal Vsig of the solid-state imaging device is proportional to the logarithmic component of the incident light quantity. If such a region exhibiting nonlinear characteristics can also be used effectively, a wide dynamic range of at least 6 digits in the light amount range can be realized. However, in this saturation region, there is a variation in saturation charge due to variations in the capacitance Cpd of PD1 and the depletion voltage Vdep, so that fixed pattern noise increases from the vicinity of the amount of light showing saturation characteristics as shown in FIG. Therefore, in order to effectively use the non-linear region, it is necessary to remove noise components due to saturation charge variations.
[0022]
A circuit operation for removing a noise component due to such variation in the saturation region will be described below. Referring to FIGS. 2, 3 and 4 again, after reading the signal output Vs1 in the above-described period P5, in the PD saturation reset period P6, as shown in FIG. Is set to a voltage (for example, GND) of the power source (8) of PD1, preferably a reset potential Vrst2 (GND <Vrst2 <Vrst1) corresponding to the off voltage of the transfer transistor 2. After setting the reset power supply 9 to the reset potential Vrst2, the transfer transistor 2 and the reset transistor 3 are simultaneously turned on, whereby the PD1 can be reset to the saturation voltage having the same potential as the reset potential Vrst2.
[0023]
Next, both the transfer transistor 2 and the reset transistor 3 are turned off, and the potential of the reset power supply 9 is returned to the reset potential Vrst1 of the FD 7 reset in the FD reset period P2. Then, in the subsequent FD reset period P7, as shown in FIG. 3B (8), the reset transistor 3 is turned on, and the FD 7 is reset to the reset potential Vrst1 having the same potential as the reset power source 9.
[0024]
Thereafter, the potential of the FD 7 at this time is read in the same manner as the noise output (Vb1) of the black level signal read in the previous noise reading period P3. That is, the reset potential Vrst1 of the FD 7 is turned off by the reset transistor 3 and amplified by the signal amplification transistor 4 and turned on by the signal amplification transistor 4 as shown in FIG. 4 (9) in the subsequent signal (noise) readout period P8. As a result, the signal is output from the vertical output line 6. The signal (voltage) Vb2 output from the vertical output line 6 at this time is a noise output serving as a reference for the saturation level output.
[0025]
Next, in the saturated charge transfer period P9, as shown in FIG. 4 (10), the transfer transistor 2 is turned on to transfer the saturated charge accumulated in the PD1 to the FD7. The potential of the FD 7 at this time is also read in the same manner as the noise output (Vb1) read in the noise reading period P8.
[0026]
That is, the potential of the saturation charge transferred from PD1 to FD7 is amplified by the signal amplification transistor 4 and turned on by selecting the selection transistor 5 in the saturation readout period P10 as shown in FIG. Output from the output line 6. The signal (voltage) Vs2 output from the vertical output line 6 at this time is an image signal that depends on the saturation charge amount of the PD1. By taking the difference (Vs2−Vb2) between the image signal component (Vs2) and the noise level output (Vb2) described above, the saturated output signal Vsat in which the reset noise component and the fixed pattern noise are suppressed is continuously generated from the same pixel. can get.
[0027]
As described above, by driving the solid-state imaging device having the circuit configuration shown in FIG. 1 at the operation timing shown in FIG. 2, four types of output signals Vout from the vertical output line 6, that is, (1) first noise. Output Vb1 (linear and nonlinear region), (2) PD accumulated image output Vs1 (linear and nonlinear region), (3) second noise output Vb2 (saturated region), (4) PD saturated output Vs2 (saturated region), Can be obtained. As described above, in the solid-state imaging device according to the first embodiment, the saturation output signal Vsat (= Vs2−Vb2) of the PD1 of each pixel can be output for each pixel, and the output obtained in the signal readout period P5. Two types of signals can be obtained: the signal Vsig and the saturation output Vsat of PD1 of each pixel obtained in the saturation readout period P10.
[0028]
As a result, fixed pattern noise caused by pixel-to-pixel variations can be reduced even in the saturation region, as shown in FIG. 5, and therefore, the nonlinear region can be effectively used. The dynamic range can be expanded.
[0029]
Next, a method for correcting the variation in the saturation region as shown in FIG. 5 using the two output signals Vsig and Vsat will be described in more detail. As described above, two types of output signals Vsig and Vsat are obtained continuously from the same pixel. Accordingly, it is not necessary to provide an external storage device such as a memory other than the solid-state imaging device as in the prior art, and by providing an analog latch unit 19 such as a signal capacity inside the imaging element, the signal output Vsig and the saturation output Vsat are compared. Can be easily performed.
[0030]
In the case of a linear region where Vsig <Vsat, the signal output Vsig is directly used as the signal output VSIG. On the other hand, in the case of the saturation region where Vsig> Vsat, the signal output Vsig includes saturation variation. Therefore, the saturation variation is corrected by obtaining the difference (Vsig−Vsat) between both signals, and further, Vsat is used to correct the DC component. The average value (described as / Vsat) is obtained and added to the previously obtained difference (Vsig−Vsat). Therefore, the signal output VSIG is obtained by VSIG = Vsig−Vsat + / Vsat.
[0031]
FIG. 6 shows the relationship of the signal output VSIG with respect to the incident light amount and the relationship of the fixed pattern noise with respect to the incident light amount at this time. As can be seen from FIG. 6, the output response to the incident light can maintain the same response characteristics as the conventional one shown in FIG. 4, and the fixed pattern noise (FPN) can be further reduced compared to the conventional one. Therefore, it can be used as an operation region up to the saturation region of PD1 of the solid-state imaging device, and the dynamic range can be greatly expanded.
[0032]
In the preferred embodiment, the off-voltage of the transfer transistor 2 may be set slightly lower than the power supply 8 potential of the PD1 during the period in which the charge is accumulated in the PD1. Alternatively, the off voltage of the transfer transistor 2 may be set by adjusting the power supply (8) potential of the PD 1 according to the imaging target. As a result, the charge overflowed in PD1 is caused to flow out to FD 7 that accumulates the charge transferred from PD1, and the sensitivity characteristic of the solid-state imaging device can exhibit logarithmic characteristics in the saturation region.
[0033]
(Embodiment 2)
A second embodiment of the present invention will be described below with reference to FIGS. In the second embodiment, the operation principle of the response characteristic of the output signal with respect to the incident light amount shown in FIG. 5 described in the first embodiment will be described. As described in the first embodiment, by simultaneously turning on the transfer transistor 2 and the reset transistor 3, the PD1 can be reset by extracting the residual charge of the PD1 to the FD7.
[0034]
Next, PD1 starts charge accumulation from the state in which the transfer transistor 2 and the reset transistor 3 are turned off. FIG. 6A shows a potential profile of low illuminance in the dark at that time. At this time, the initial potential Vdep (depletion potential) of the PD 1 is determined by the implantation dose amount and implantation energy in the PD implantation step in the manufacturing process of the solid-state imaging device. Light incident on PD1 is photoelectrically converted in the depletion layer of PD1. The maximum amount of charge Qmax that can be stored in PD1 is determined by the barrier voltage Vbr formed when the transfer transistor 2 is gated and the potential of the power supply 8 of PD1. In the solid-state imaging device of the present invention, since the control pulse voltage φtx of the transfer transistor 2 can be changed, the barrier voltage Vbr can be adjusted by adjusting the off voltage of the transistor 2.
[0035]
When the amount of incident light on the solid-state imaging device shifts from low illuminance that does not saturate PD1 to intermediate illuminance, the generated photocurrent (photocharge) is a linear region proportional to the amount of incident light, and therefore the initial potential Vdep ( The change amount Vpd from the depletion potential is determined by the following equation (1) (see IEEE Trans. Electron. Devices, vol. 42, pp. 652-655).
Vpd = −Iph × Te / Cpd (1)
Where Iph is the photocurrent, Te is the charge accumulation time, and Cpd is the capacitance of PD1.
[0036]
The potential profile at this time is shown in FIG. As the accumulated charge amount of PD1 increases, the barrier voltage Vbr decreases by an amount corresponding to the PD potential change amount Vpd. At this time, the leak current Iex flowing into the FD 7 beyond the potential barrier of the transfer transistor 2 is expressed by the following equation (2).
Iex = Io × exp (−β · Vpd) (2)
However, Io is a constant and β is q / kT.
[0037]
As can be seen from this equation (2), in the high illuminance / saturation region where PD1 is almost saturated as the change amount Vpd increases, the barrier voltage Vbr decreases and approaches 0 (˜0), and the leakage current Iex is Increases rapidly. The potential profile at this time is shown in FIG. 6 (3). The photocurrent Iph and the leak current Iex are almost equal and satisfy the relationship Iph≈Iex, and the potential change amount Vpd of PD1 is expressed by the following formula (3).
Vpd = −logIex / β + logIo / β (3)
As can be seen from the equations (1) and (3), when the relationship between the accumulated charge number Qpd of PD1 and the saturated charge number Qmax is Qpd <Qmax, the response characteristic of the fixed imaging element is linear, and when Qpd≈Qmax, The response of the fixed image sensor shows logarithmic characteristics. These response characteristics are shown in FIG.
[0038]
As shown in FIG. 9, a “knee characteristic” appears in which the response characteristic is bent near the saturation of PD1. In the solid-state imaging device of the present invention, the barrier voltage Vbr can be adjusted by adjusting the off-voltage of the transfer transistor 2, so that the position of the break point where the linear characteristic is switched to the logarithmic characteristic can be adjusted. In the example shown in FIG. 8, the barrier voltage Vbr is changed in three ways of 0.8 V, 1.0 V, and 1.2 V by adjusting the off voltage of the transfer transistor 2.
[0039]
The potential profile shown in FIG. 8 shows an example in which the barrier voltage Vbr of the transfer transistor 2 is set smaller than that shown in FIG. In this case, as shown in FIG. 8 (2), in the signal charge accumulation period of intermediate illuminance, the PD1 is almost saturated only by a slight increase in the amount of change Vpd, and the barrier voltage Vbr decreases. As a result, the leakage current Iex increases rapidly. Since other operations are the same as those in FIG. 7, detailed description thereof is omitted.
[0040]
FIG. 10 shows the characteristics of the logarithmic region with the vertical axis as a linear scale for easy understanding of the logarithmic characteristics of FIG. As apparent from FIG. 10, by changing the barrier voltage Vbr, the sensitivity characteristic of the solid-state imaging device can be changed, and the contrast of the image to be imaged can be adjusted. For example, the dynamic range can be expanded by increasing the logarithmic region by lowering the barrier voltage Vbr. In addition, the contrast in the low illuminance region can be improved by increasing the linear region.
[0041]
(Embodiment 3)
A solid-state imaging device according to Embodiment 3 of the present invention will be described below with reference to FIG. FIG. 11 is a circuit diagram showing a basic configuration of a solid-state imaging apparatus according to Embodiment 3 of the present invention. The basic configuration and operation principle are the same as those of the first embodiment, and the difference is that in the first embodiment shown in FIG. 1, the PD 1 is charged to the saturation voltage by the reset power source 9 via the reset transistor 3. In this embodiment, as shown in FIG. 11, a saturation reset transistor 16 for charging to a saturation voltage is connected between the cathode of PD1 and the reset power supply line 13, and a saturation reset control signal is transmitted from the saturation reset control line 17. May be input to the gate of the saturation reset transistor 16.
[0042]
With the above configuration, PD1 can be reset to the saturation voltage without passing through the transfer transistor 2, and the saturation voltage can be output with the gate voltage of the transfer transistor 2 kept constant, which is more accurate than in the first embodiment. A saturation signal can be output.
[0043]
(Embodiment 4)
A solid-state imaging device according to Embodiment 4 of the present invention will be described below with reference to FIG. FIG. 12 is a circuit diagram showing a basic configuration of a solid-state imaging apparatus according to Embodiment 4 of the present invention. The basic configuration and operation principle are the same as those of the first and third embodiments, and the difference is that in the first and third embodiments shown in FIGS. 1 and 11, the reset power supply line 13 from the reset power supply 9 is FD7 and PD1. The reset voltage Vrst1 is supplied to the FD7 and the saturation voltage Vrst2 is supplied to the PD1. However, in the present embodiment 4, as shown in FIG. 12, the saturation reset power supply line 18 is dedicated to supply the saturation voltage of the PD1. The configuration is provided.
[0044]
With the above configuration, the reset power of FD7 and PD1 can be supplied independently of each other, so that it is not necessary to change the potential of power supply lines 13 and 18, and a saturation signal is output with higher accuracy than in the first and third embodiments. be able to.
[0045]
【The invention's effect】
As described above, according to the present invention, an output signal from a pixel and a saturation signal can be continuously output, and an image signal in which saturation variation is suppressed is obtained, and dynamic characteristics are obtained by using a nonlinear characteristic of the saturation characteristic. A solid-state imaging device capable of obtaining an image signal with a wide range can be realized.
[Brief description of the drawings]
FIG. 1 is a circuit diagram corresponding to one pixel of a solid-state imaging device according to Embodiment 1 of the present invention.
FIG. 2 is a timing chart showing the operation of the circuit configuration of FIG.
3 is a diagram showing a first half of a potential profile during operation of the circuit configuration of FIG. 1. FIG.
4 is a diagram showing a second half of a potential profile during operation of the circuit configuration of FIG. 1;
5 is a graph showing the relationship between signal output and incident light amount for explaining an operation for correcting saturation region variation in the circuit configuration of FIG. 1; FIG.
6 is a graph showing the relationship between the signal output and the fixed pattern noise with respect to the amount of incident light for explaining the operation for correcting the saturation region variation of the circuit configuration of FIG. 1;
FIG. 7 is a diagram showing an example of a potential profile during operation of the solid-state imaging device according to Embodiment 2 of the present invention.
FIG. 8 is a diagram showing another example of a potential profile during operation of the solid-state imaging device according to Embodiment 2 of the present invention.
FIG. 9 is a graph showing response characteristics with respect to the amount of incident light of the solid-state imaging device according to Embodiment 2 of the present invention.
10 is a graph showing the characteristics of a logarithmic region with the vertical axis as a linear scale in the logarithmic characteristics of FIG.
FIG. 11 is a circuit diagram corresponding to one pixel of a solid-state imaging device according to Embodiment 3 of the present invention.
FIG. 12 is a circuit diagram corresponding to one pixel of a solid-state imaging device according to Embodiment 4 of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Photodiode PD, 2 Transfer transistor, 3 Reset transistor, 4 Signal amplification transistor, 4a, 4b Metal reflector, 5 Selection transistor, 6 Vertical signal line, 7 Floating diffusion area FD, 8 Power supply of PD1, 9 Reset power supply, 10 Source follower (SF) power supply, 11 control line, 11a substrate surface, 11b flat step portion, 12 control pulse generator, 13 reset power supply line, 14 reset control line, 15 readout control line, 16 saturation reset transistor, 17 saturation reset control Line, 18 saturation reset power line, 19 analog latch part

Claims (6)

In a solid-state imaging device that captures an image signal and reads it out,
Photoelectric conversion means for converting an optical signal into a signal charge;
Transfer switch means for switching on and off the transfer of the signal charge;
Charge holding means for holding the signal charge transferred from the photoelectric conversion means;
Reset power supply means for resetting the photoelectric conversion means and the charge holding means;
Reset switch means for switching on and off the connection between the charge holding means and the reset power supply means;
Signal amplification switch means for amplifying the signal charge transferred to the charge holding means;
Selection switch means for reading the signal charge amplified through the signal amplification switch means to the outside as an image signal ,
A noise signal read after resetting the charge holding means;
An image signal read out after transferring signal charges from the photoelectric conversion means;
A second noise signal read out after resetting the charge holding means after charging the photoelectric conversion means;
4. A solid-state image pickup device that reads out four types of output signals of a saturation signal that is read after the charge charged in the photoelectric conversion means is transferred to the charge holding means. By making the reset power supply means controllable from the outside, the reset potential of the photoelectric conversion means and the charge holding means can be changed,
The reset power supply means has a first reset voltage that is a reset potential of the charge holding means, and a second reset voltage that fills the photoelectric conversion means with charge and brings the photoelectric conversion means into a charge saturation state. The solid-state imaging device according to claim 1, wherein the kind of reset potential is set. 3. The solid-state imaging device according to claim 2, wherein the reset power supply unit supplies the voltage after setting the second reset voltage to fill and saturate the photoelectric conversion unit after the image signal is read. .   The solid-state imaging device according to claim 1, further comprising a control pulse generation unit capable of setting an off voltage of the transfer switch unit to an arbitrary voltage during a period in which charges are accumulated in the photoelectric conversion unit.   The solid-state imaging device according to claim 1, further comprising a second reset switch unit that resets the photoelectric conversion unit. The solid-state imaging device according to claim 5, wherein the second reset switch means is connected to a power source that supplies a saturation reset potential.

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