JP4251006B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device used in a high-frequency communication device represented by a mobile phone.
[0002]
[Prior art]
In recent mobile communication devices represented by mobile phones, GaAs field effect transistors or heterojunction bipolar transistors have been used, and have come to occupy an unwavering position. However, the development of high performance with new materials is also being actively promoted. Among them, a nitride-based III-V group compound semiconductor typified by GaN, that is, a group III whose general formula is represented by Al _x Ga _{1 -xy} In _y N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1) Nitride semiconductors are attracting much attention as next-generation compound semiconductor materials because they can achieve a sheet carrier concentration 10 times that of GaAs and have a high breakdown voltage.
[0003]
Of particular interest in group III nitride semiconductor devices are MODFETs (Modulation Doped Field Effect Transistors) using AlGaN / GaN heterojunctions. The biggest difference from GaAs MODFET is that the sheet carrier concentration 10 times that of GaAs MODFET can be realized without doping impurities in the AlGaN layer which is a Schottky layer. The carrier generation mechanism is that polarization due to the piezoelectric effect occurs in AlGaN due to stress between AlGaN / GaN, and as a result, two-dimensional electrons are accumulated at the AlGaN / GaN interface.
[0004]
For this reason, stress is a very important parameter, and the stress between AlGaN / GaN and the induced sheet carrier concentration have been intensively studied. For example, in Non-Patent Document 1, the sheet carrier concentration of a two-dimensional electron gas is quantitatively calculated from stress. FIG. 9 shows an example of a conventional AlGaN / GaN MODFET. This drawing shows a sketch from the top and a cross-sectional view of the MODFET. 101 is an InGaN layer, and 102 is an AlGaN layer, and a two-dimensional electron gas accumulates between InGaN / AlGaN. 103 is a gate electrode, and 104 is an ohmic electrode.
[0005]
[Non-Patent Document 1]
O. Ambacher et.al .; Journal of Applied Physics, Vol 85, No. (1999) p.3222-p.3233.
[0006]
[Problems to be solved by the invention]
In view of the carrier accumulation mechanism of the nitride-based field effect transistor, the stress around the gate electrode is very important. Nevertheless, in the prior art, only the stress between InGaN / AlGaN has been studied, and no attention has been paid to the stress generated around the gate electrode and the ohmic electrode. For this reason, there is an error in the prediction of the characteristics of the MODFET, and there is another problem that the characteristics vary.
[0007]
In view of the above problems, an object of the present invention is to provide a structure capable of accurately controlling the threshold characteristics of a field-effect transistor in consideration of the stress of a gate electrode and an ohmic electrode.
[0008]
The inventors of the present invention have clarified for the first time the superiority regarding the orientation of the gate electrode discussed in the present invention in a nitride-based field effect transistor. This has led to the present invention.
[0009]
[Means for Solving the Problems]
In order to solve the above problems, a semiconductor device according to the present invention is a field effect transistor comprising a group III nitride semiconductor layer formed on a substrate and having a gate electrode and an ohmic electrode formed thereon, wherein the gate The longitudinal direction of the electrode is formed in a specific direction.
[0010]
With this configuration, since the longitudinal direction of the gate electrode is formed in a specific direction, generation of piezoelectric charges due to stress on the gate electrode can be controlled.
[0011]
In the semiconductor device of the present invention, it is preferable that the specific direction is any of [11-20] direction, [2-1-10] direction, and [-12-10] direction. According to this preferable configuration, since the generation of piezoelectric charges due to the stress of the gate electrode is small, the temperature characteristics can be made insensitive.
[0012]
Here, for example, in [11-20], “-2” in “-2” means “bar”. The same applies to the other directions.
[0013]
In the semiconductor device of the present invention, it is preferable that the specific direction is any one of a [01-10] direction, a [10-10] direction, and a [1-100] direction. According to this preferred configuration, since the piezoelectric charge is often generated by the stress of the gate electrode, the threshold voltage can be made sensitive to temperature.
[0014]
The semiconductor device of the present invention has a plurality of field effect transistors made of a group III nitride semiconductor formed on a substrate and formed with a gate electrode and an ohmic electrode, of which the longitudinal direction of the gate electrode is [ 11-20] direction, [2-1-10] direction or [-12-10] direction field effect transistor, and the longitudinal direction of the gate electrode is [01-10] direction, [10- Field effect transistors that are in either the [10] direction or the [1-100] direction.
[0015]
With this configuration, since a gate orientation in which a large amount of piezoelectric charges are generated due to stress of the gate electrode and a orientation in which the gate electrode is small are mixed, a great degree of freedom can be given to circuit design by combining transistors having different temperature characteristics.
[0016]
The semiconductor device according to the present invention includes first and second group III nitride semiconductor layers formed on a substrate, a gate electrode is formed on the first group III nitride semiconductor layer, and an ohmic electrode is formed on the substrate. A field effect transistor formed on the second group III nitride semiconductor layer, wherein the longitudinal direction of the gate electrode is formed in a specific direction.
[0017]
With this configuration, since the longitudinal direction of the gate electrode is formed in a specific direction, the temperature characteristics can be controlled by controlling the generation of piezoelectric charges due to the stress of the gate electrode, and the second group III nitride semiconductor layer can be controlled. The controllability can be further improved by stress.
[0018]
In the semiconductor device of the present invention, it is preferable that the specific direction is any of [11-20] direction, [2-1-10] direction, and [-12-10] direction. According to this preferable configuration, since the generation of piezoelectric charges due to the stress of the gate electrode is small, the temperature characteristics can be made insensitive.
[0019]
In the semiconductor device of the present invention, it is preferable that the specific direction is any one of a [01-10] direction, a [10-10] direction, and a [1-100] direction. According to this preferred configuration, since the piezoelectric charge is often generated by the stress of the gate electrode, the threshold voltage can be made sensitive to temperature.
[0020]
The semiconductor device according to the present invention includes first and second group III nitride semiconductor layers formed on a substrate, a gate electrode is formed on the first group III nitride semiconductor layer, and an ohmic electrode is formed on the substrate. There are a plurality of field effect transistors formed on the second group III nitride semiconductor layer, of which the longitudinal direction of the gate electrode is the [11-20] direction, [2-1-10] direction or [-12] -10] direction field-effect transistor and the gate electrode has a longitudinal direction of [01-10] direction, [10-10] direction, or [1-100] direction. A transistor.
[0021]
With this configuration, since a gate orientation in which a large amount of piezoelectric charges are generated due to stress of the gate electrode and a orientation in which the gate electrode is small are mixed, a great degree of freedom can be given to circuit design by combining transistors having different temperature characteristics. Furthermore, the controllability of the piezoelectric charge can be further improved by the stress of the second group III nitride semiconductor layer due to the stress of the second group III nitride semiconductor layer.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0023]
A field effect transistor in which an AlN layer, a GaN layer, and an AlGaN layer are sequentially formed on a SiC substrate is configured so that the longitudinal direction of the gate electrode is directed to a specific direction. FIG. 7 shows a graph obtained as a result of the first measurement of the relationship between the longitudinal direction of the gate electrode and the threshold voltage. The threshold voltage shows gate orientation dependence, and it can be seen that the threshold voltage is the deepest in the [10-10] direction.
[0024]
Further, FIG. 8 shows the substrate temperature dependence of the threshold voltage for the field effect transistor. It can be seen that the temperature coefficient is also dependent on the gate direction. This makes it possible to align the threshold characteristics of the field effect transistors by making the amount of piezoelectric charge generated around the gate electrode or ohmic electrode constant.
[0025]
Further, the threshold voltage can be controlled by varying the stress around the gate electrode and the ohmic electrode.
[0026]
In this experiment, 4H—SiC was used as the substrate, but the same effect can be obtained with other substrates such as a 6H—SiC substrate and a sapphire substrate.
[0027]
Further, the combination of the group III nitride semiconductor layers constituting the field effect transistor is not limited to the InGaN layer / AlGaN layer, and the same effect can be obtained by other combinations.
[0028]
A semiconductor device having the above characteristics will be described in the following embodiments.
[0029]
In the following embodiments, as the substrate, a 4H—SiC substrate, a 6H—SiC substrate, a sapphire substrate, or the like can be used.
[0030]
(First embodiment)
In the semiconductor device according to the first embodiment, InGaN (mixed crystal ratio 0% to 100%) and AlGaN (mixed crystal ratio 0% to 100%) are sequentially formed on a substrate, and a gate electrode and an ohmic electrode are formed. A field-effect semiconductor device that is formed, wherein the longitudinal direction of the gate electrode is either the [11-20] direction, the [2-1-10] direction, or the [-12-10] direction. Since the generation of piezoelectric charges due to stress on the gate electrode is small, the temperature characteristics can be made insensitive.
[0031]
A top view and a cross-sectional structure diagram of this semiconductor device are specifically shown in FIG. In FIG. 1, 101 is an InGaN layer (mixed crystal ratio 0% to 100%), and a two-dimensional electron gas travels. Reference numeral 102 denotes an AlGaN layer that functions as a Schottky layer. 103 is a gate electrode, for example, PdSi / Au. 104 is an ohmic electrode, for example, Ti / Al. 105 is a gate electrode whose longitudinal direction is either the [11-20] direction or the [2-1-10] or [-12-10] direction.
[0032]
When the gate electrode is in this direction, the piezoelectric charge immediately below the gate electrode is small, so that the temperature fluctuation of the threshold voltage is small, so that stable temperature characteristics can be realized.
[0033]
(Second Embodiment)
In the semiconductor device according to the second embodiment, InGaN (mixed crystal ratio 0% to 100%) and AlGaN (mixed crystal ratio 0% to 100%) are sequentially formed on a substrate, and a gate electrode and an ohmic electrode are formed. A field effect transistor is formed, wherein the longitudinal direction of the gate electrode is either the [01-10] direction or the [10-10] or [1-100] direction, whereby the gate electrode The threshold voltage can be made sensitive to temperature because of the large amount of piezo electric charge generated by the stress.
[0034]
A top view and a cross-sectional structure diagram of this semiconductor device are specifically shown in FIG. In FIG. 2, 101 is an InGaN layer (mixed crystal ratio 0% to 100%), and a two-dimensional electron gas travels. Reference numeral 102 denotes an AlGaN layer that functions as a Schottky layer. 103 is a gate electrode, for example, PdSi / Au. 104 is an ohmic electrode, for example, Ti / Al. 105 is a gate electrode whose longitudinal direction is either the [01-10] direction or the [10-10] or [1-100] direction.
[0035]
When the gate electrode is in this direction, the piezoelectric charge immediately below the gate electrode is large, so that the temperature variation of the threshold voltage is large, so that a temperature sensitive characteristic can be realized.
[0036]
(Third embodiment)
In the semiconductor device according to the third embodiment, InGaN (mixed crystal ratio 0% to 100%) and AlGaN (mixed crystal ratio 0% to 100%) are sequentially formed on a substrate, and a gate electrode and an ohmic electrode are formed. A field effect type semiconductor device, wherein the longitudinal direction of the gate electrode is either the [11-20] direction or the [2-1-10] or [-12-10] direction. A semiconductor device comprising a transistor and a field effect transistor in which the longitudinal direction of the gate electrode is either the [01-10] direction or the [10-10] or [1-100] direction Since the gate orientation in which a large amount of piezoelectric charges are generated due to the stress of the gate electrode and the orientation in which there is a small amount are mixed, by combining transistors having different temperature characteristics, the circuit design has a large degree of freedom.
[0037]
A top view and a cross-sectional structure diagram of this semiconductor device are specifically shown in FIG. In FIG. 3, 101 is an InGaN layer (mixed crystal ratio 0% to 100%), and a two-dimensional electron gas travels. Reference numeral 102 denotes an AlGaN layer that functions as a Schottky layer. 103 is a gate electrode, for example, PdSi / Au. 104 is an ohmic electrode, for example, Ti / Al. 105 is a gate electrode, the field effect transistor whose longitudinal direction is either [11-20] direction or [2-1-10] or [-12-10] direction, and the longitudinal direction of the gate electrode is There are mixed field effect transistors in either the [01-10] direction or the [10-10] or [1-100] direction.
[0038]
When the gate electrode is in these directions, transistors having different characteristics can be mixed, which gives a great degree of freedom in circuit design. That is, it is possible to realize a circuit that actively uses this.
[0039]
(Fourth embodiment)
In the semiconductor device according to the fourth embodiment, InGaN (mixed crystal ratio 0% to 100%) and first AlGaN (mixed crystal ratio 0% to 100%) are sequentially formed on a substrate, and a gate electrode is formed. A field effect semiconductor device formed on the first AlGaN and having a second AlGaN and an ohmic electrode formed on a part of the first AlGaN, wherein the longitudinal direction of the gate electrode is [11-20] direction, [2-1-10] direction, or [-12-10] direction, a semiconductor device characterized by low generation of piezoelectric charges due to stress of the gate electrode It has the effect of making temperature characteristics insensitive. Further, the action can be further increased by the stress of the second AlGaN.
[0040]
A top view and a cross-sectional structure diagram of this semiconductor device are specifically shown in FIG. In FIG. 4, 401 is an InGaN layer (mixed crystal ratio 0% to 100%), and a two-dimensional electron gas travels. Reference numeral 402 denotes a first AlGaN layer that functions as a Schottky layer. Reference numeral 403 denotes a gate electrode, for example, PdSi / Au. Reference numeral 406 denotes a second AlGaN layer formed on a part of the first AlGaN layer, and an ohmic electrode 404 is formed thereon. For example, Ti / Al is used for the ohmic electrode 404. Reference numeral 405 denotes a gate electrode whose longitudinal direction is either the [11-20] direction or the [2-1-10] or [-12-10] direction.
[0041]
When the gate electrode is in this direction, the piezoelectric charge immediately below the gate electrode is small, so that the temperature fluctuation of the threshold voltage is small, so that stable temperature characteristics can be realized. Furthermore, the effect can be further enhanced by controlling the stress by the second AlGaN layer.
[0042]
(Fifth embodiment)
In the semiconductor device according to the fifth embodiment, InGaN (mixed crystal ratio 0% to 100%) and first AlGaN (mixed crystal ratio 0% to 100%) are sequentially formed on a substrate, and a gate electrode is formed. A field effect semiconductor device formed on the first AlGaN and having a second AlGaN and an ohmic electrode formed on a part of the first AlGaN, wherein the longitudinal direction of the gate electrode is [01-10] A semiconductor device characterized by being in one of [10-10] or [10-10] or [1-100] direction. Since the generation of piezoelectric charges due to stress of the gate electrode is large, the threshold voltage is Has the effect of making it temperature sensitive. Further, the action can be further increased by the stress of the second AlGaN.
[0043]
A top view and a cross-sectional structure diagram of this semiconductor device are specifically shown in FIG. In FIG. 5, 401 is an InGaN layer (mixed crystal ratio 0% to 100%), and a two-dimensional electron gas travels. Reference numeral 402 denotes a first AlGaN layer that functions as a Schottky layer. Reference numeral 403 denotes a gate electrode, for example, PdSi / Au. Reference numeral 406 denotes a second AlGaN layer formed on a part of the first AlGaN layer, and an ohmic electrode 404 is formed thereon. For example, Ti / Al is used for the ohmic electrode 404. Reference numeral 405 denotes a gate electrode whose longitudinal direction is either the [01-10] direction or the [10-10] or [1-100] direction.
[0044]
When the gate electrode is in this direction, the piezoelectric charge immediately below the gate electrode is large, so that the temperature variation of the threshold voltage is large, so that a temperature sensitive characteristic can be realized. Furthermore, the effect can be further enhanced by controlling the stress by the second AlGaN layer.
[0045]
(Sixth embodiment)
In the semiconductor device according to the sixth embodiment, InGaN (mixed crystal ratio 0% to 100%) and first AlGaN (mixed crystal ratio 0% to 100%) are sequentially formed on a substrate, and a gate electrode is formed. A field effect semiconductor device formed on the first AlGaN and having a second AlGaN and an ohmic electrode formed on a part of the first AlGaN, wherein the longitudinal direction of the gate electrode is [11-20] direction or [2-1-10] or [-12-10] field effect transistor, and the longitudinal direction of the gate electrode is [01-10] direction or [10- 10] or [1-100] direction field effect transistors are mixed, and the semiconductor device is characterized by a mixture of gate orientations that generate a large amount of piezoelectric charges due to stress on the gate electrode and those that have few orientations. Therefore, by combining transistors with different temperature characteristics, Has the effect of giving greater flexibility in circuit design. Further, the action can be further increased by the stress of the second AlGaN.
[0046]
FIG. 6 specifically shows a top view and a sectional view of this semiconductor device. In FIG. 6, 401 is an InGaN layer (mixed crystal ratio 0% to 100%), and a two-dimensional electron gas travels. Reference numeral 402 denotes a first AlGaN layer that functions as a Schottky layer. Reference numeral 403 denotes a gate electrode, for example, PdSi / Au. Reference numeral 406 denotes a second AlGaN layer formed on a part of the first AlGaN layer, and an ohmic electrode 404 is formed thereon. For example, Ti / Al is used for the ohmic electrode 404. 405 is a gate electrode, the field effect transistor whose longitudinal direction is either [11-20] direction or [2-1-10] or [01-10] direction, and the longitudinal direction of the gate electrode is [01 -10] direction or [10-10] direction or [1-100] direction field effect transistors are mixed.
[0047]
When the gate electrode is in this direction, a transistor with a large threshold voltage temperature variation and a small transistor can be mixed. This gives a great degree of freedom in circuit design. That is, it is possible to realize a circuit that actively uses this. Furthermore, the effect can be further enhanced by controlling the stress by the second AlGaN layer.
[0048]
In the above embodiment, the combination of the group III nitride semiconductor layers constituting the field effect transistor is not limited to the InGaN layer / AlGaN layer, but Al _x Ga _1-xy In _y N (0 ≦ x ≦ 1, 0 ≦ y The same effect can be obtained even with a combination of a plurality of AlGaInN layers obtained by selecting the values of x and y for ≦ 1).
[0049]
The above embodiment has been described by taking a field effect transistor as an example. However, the present invention is not limited to a field effect transistor, and the same applies to a semiconductor device using a field effect, that is, a field effect semiconductor device. An effect is obtained.
[0050]
【The invention's effect】
As described above, according to the present invention, in the AlGaN / InGaN field-effect transistor, the piezo effect is positively utilized to realize a transistor with uniform characteristics, or with a large or small temperature characteristic, and further to that. It can be mixed to increase the degree of freedom in circuit design.
[Brief description of the drawings]
FIG. 1 is a top view and a cross-sectional view showing a first embodiment of the present invention. FIG. 2 is a top view and a cross-sectional view showing a second embodiment of the present invention. FIG. 4 is a top view and cross-sectional view showing a fourth embodiment of the present invention. FIG. 5 is a top view and cross-sectional view showing a fifth embodiment of the present invention. FIG. 7 is a top view and a cross-sectional view showing a sixth embodiment of the invention. FIG. 7 is a view showing a gate electrode longitudinal direction of a threshold voltage. FIG. ] Top view and sectional view showing a conventional example [Explanation of symbols]
101 InGaN layer
102 AlGaN layer
103 Gate electrode
104 Ohmic electrode
105 Gate electrode
401 InGaN layer
402 First AlGaN layer
403 Gate electrode
404 ohmic electrode
405 Gate electrode
406 Second AlGaN layer

Claims (2)

A plurality of field effect transistors are formed of a group III nitride semiconductor having a (0001) plane as a main surface formed on a substrate, and a gate electrode and an ohmic electrode are formed.
Of which the gate electrode longitudinal direction [11-20] direction of the group III nitride semiconductor, and a field effect transistor is one of the [2-1-10] direction or [-12-10] direction,
[01-10] direction of the longitudinal direction of the gate electrode is the group III nitride semiconductor, characterized in that includes a field effect transistor is one of the [10-10] direction or [1-100] direction A semiconductor device. The gate electrode is the III Formed on a group nitride semiconductor, III Between the group nitride semiconductor and the ohmic electrode, there is a second III 2. The semiconductor device according to claim 1, wherein a group nitride semiconductor layer is formed.

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